1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // This file is provided under a dual BSD/GPLv2 license. When using or 4 // redistributing this file, you may do so under either license. 5 // 6 // Copyright(c) 2018 Intel Corporation. All rights reserved. 7 // 8 // Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com> 9 // Ranjani Sridharan <ranjani.sridharan@linux.intel.com> 10 // Rander Wang <rander.wang@intel.com> 11 // Keyon Jie <yang.jie@linux.intel.com> 12 // 13 14 /* 15 * Hardware interface for generic Intel audio DSP HDA IP 16 */ 17 18 #include <linux/module.h> 19 #include <sound/hdaudio_ext.h> 20 #include <sound/hda_register.h> 21 #include "../sof-audio.h" 22 #include "../ops.h" 23 #include "hda.h" 24 #include "hda-ipc.h" 25 26 static bool hda_enable_trace_D0I3_S0; 27 #if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG) 28 module_param_named(enable_trace_D0I3_S0, hda_enable_trace_D0I3_S0, bool, 0444); 29 MODULE_PARM_DESC(enable_trace_D0I3_S0, 30 "SOF HDA enable trace when the DSP is in D0I3 in S0"); 31 #endif 32 33 /* 34 * DSP Core control. 35 */ 36 37 static int hda_dsp_core_reset_enter(struct snd_sof_dev *sdev, unsigned int core_mask) 38 { 39 u32 adspcs; 40 u32 reset; 41 int ret; 42 43 /* set reset bits for cores */ 44 reset = HDA_DSP_ADSPCS_CRST_MASK(core_mask); 45 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR, 46 HDA_DSP_REG_ADSPCS, 47 reset, reset); 48 49 /* poll with timeout to check if operation successful */ 50 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, 51 HDA_DSP_REG_ADSPCS, adspcs, 52 ((adspcs & reset) == reset), 53 HDA_DSP_REG_POLL_INTERVAL_US, 54 HDA_DSP_RESET_TIMEOUT_US); 55 if (ret < 0) { 56 dev_err(sdev->dev, 57 "error: %s: timeout on HDA_DSP_REG_ADSPCS read\n", 58 __func__); 59 return ret; 60 } 61 62 /* has core entered reset ? */ 63 adspcs = snd_sof_dsp_read(sdev, HDA_DSP_BAR, 64 HDA_DSP_REG_ADSPCS); 65 if ((adspcs & HDA_DSP_ADSPCS_CRST_MASK(core_mask)) != 66 HDA_DSP_ADSPCS_CRST_MASK(core_mask)) { 67 dev_err(sdev->dev, 68 "error: reset enter failed: core_mask %x adspcs 0x%x\n", 69 core_mask, adspcs); 70 ret = -EIO; 71 } 72 73 return ret; 74 } 75 76 static int hda_dsp_core_reset_leave(struct snd_sof_dev *sdev, unsigned int core_mask) 77 { 78 unsigned int crst; 79 u32 adspcs; 80 int ret; 81 82 /* clear reset bits for cores */ 83 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR, 84 HDA_DSP_REG_ADSPCS, 85 HDA_DSP_ADSPCS_CRST_MASK(core_mask), 86 0); 87 88 /* poll with timeout to check if operation successful */ 89 crst = HDA_DSP_ADSPCS_CRST_MASK(core_mask); 90 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, 91 HDA_DSP_REG_ADSPCS, adspcs, 92 !(adspcs & crst), 93 HDA_DSP_REG_POLL_INTERVAL_US, 94 HDA_DSP_RESET_TIMEOUT_US); 95 96 if (ret < 0) { 97 dev_err(sdev->dev, 98 "error: %s: timeout on HDA_DSP_REG_ADSPCS read\n", 99 __func__); 100 return ret; 101 } 102 103 /* has core left reset ? */ 104 adspcs = snd_sof_dsp_read(sdev, HDA_DSP_BAR, 105 HDA_DSP_REG_ADSPCS); 106 if ((adspcs & HDA_DSP_ADSPCS_CRST_MASK(core_mask)) != 0) { 107 dev_err(sdev->dev, 108 "error: reset leave failed: core_mask %x adspcs 0x%x\n", 109 core_mask, adspcs); 110 ret = -EIO; 111 } 112 113 return ret; 114 } 115 116 static int hda_dsp_core_stall_reset(struct snd_sof_dev *sdev, unsigned int core_mask) 117 { 118 /* stall core */ 119 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR, 120 HDA_DSP_REG_ADSPCS, 121 HDA_DSP_ADSPCS_CSTALL_MASK(core_mask), 122 HDA_DSP_ADSPCS_CSTALL_MASK(core_mask)); 123 124 /* set reset state */ 125 return hda_dsp_core_reset_enter(sdev, core_mask); 126 } 127 128 static bool hda_dsp_core_is_enabled(struct snd_sof_dev *sdev, unsigned int core_mask) 129 { 130 int val; 131 bool is_enable; 132 133 val = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPCS); 134 135 #define MASK_IS_EQUAL(v, m, field) ({ \ 136 u32 _m = field(m); \ 137 ((v) & _m) == _m; \ 138 }) 139 140 is_enable = MASK_IS_EQUAL(val, core_mask, HDA_DSP_ADSPCS_CPA_MASK) && 141 MASK_IS_EQUAL(val, core_mask, HDA_DSP_ADSPCS_SPA_MASK) && 142 !(val & HDA_DSP_ADSPCS_CRST_MASK(core_mask)) && 143 !(val & HDA_DSP_ADSPCS_CSTALL_MASK(core_mask)); 144 145 #undef MASK_IS_EQUAL 146 147 dev_dbg(sdev->dev, "DSP core(s) enabled? %d : core_mask %x\n", 148 is_enable, core_mask); 149 150 return is_enable; 151 } 152 153 int hda_dsp_core_run(struct snd_sof_dev *sdev, unsigned int core_mask) 154 { 155 int ret; 156 157 /* leave reset state */ 158 ret = hda_dsp_core_reset_leave(sdev, core_mask); 159 if (ret < 0) 160 return ret; 161 162 /* run core */ 163 dev_dbg(sdev->dev, "unstall/run core: core_mask = %x\n", core_mask); 164 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR, 165 HDA_DSP_REG_ADSPCS, 166 HDA_DSP_ADSPCS_CSTALL_MASK(core_mask), 167 0); 168 169 /* is core now running ? */ 170 if (!hda_dsp_core_is_enabled(sdev, core_mask)) { 171 hda_dsp_core_stall_reset(sdev, core_mask); 172 dev_err(sdev->dev, "error: DSP start core failed: core_mask %x\n", 173 core_mask); 174 ret = -EIO; 175 } 176 177 return ret; 178 } 179 180 /* 181 * Power Management. 182 */ 183 184 static int hda_dsp_core_power_up(struct snd_sof_dev *sdev, unsigned int core_mask) 185 { 186 unsigned int cpa; 187 u32 adspcs; 188 int ret; 189 190 /* update bits */ 191 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPCS, 192 HDA_DSP_ADSPCS_SPA_MASK(core_mask), 193 HDA_DSP_ADSPCS_SPA_MASK(core_mask)); 194 195 /* poll with timeout to check if operation successful */ 196 cpa = HDA_DSP_ADSPCS_CPA_MASK(core_mask); 197 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, 198 HDA_DSP_REG_ADSPCS, adspcs, 199 (adspcs & cpa) == cpa, 200 HDA_DSP_REG_POLL_INTERVAL_US, 201 HDA_DSP_RESET_TIMEOUT_US); 202 if (ret < 0) { 203 dev_err(sdev->dev, 204 "error: %s: timeout on HDA_DSP_REG_ADSPCS read\n", 205 __func__); 206 return ret; 207 } 208 209 /* did core power up ? */ 210 adspcs = snd_sof_dsp_read(sdev, HDA_DSP_BAR, 211 HDA_DSP_REG_ADSPCS); 212 if ((adspcs & HDA_DSP_ADSPCS_CPA_MASK(core_mask)) != 213 HDA_DSP_ADSPCS_CPA_MASK(core_mask)) { 214 dev_err(sdev->dev, 215 "error: power up core failed core_mask %xadspcs 0x%x\n", 216 core_mask, adspcs); 217 ret = -EIO; 218 } 219 220 return ret; 221 } 222 223 static int hda_dsp_core_power_down(struct snd_sof_dev *sdev, unsigned int core_mask) 224 { 225 u32 adspcs; 226 int ret; 227 228 /* update bits */ 229 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR, 230 HDA_DSP_REG_ADSPCS, 231 HDA_DSP_ADSPCS_SPA_MASK(core_mask), 0); 232 233 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, 234 HDA_DSP_REG_ADSPCS, adspcs, 235 !(adspcs & HDA_DSP_ADSPCS_CPA_MASK(core_mask)), 236 HDA_DSP_REG_POLL_INTERVAL_US, 237 HDA_DSP_PD_TIMEOUT * USEC_PER_MSEC); 238 if (ret < 0) 239 dev_err(sdev->dev, 240 "error: %s: timeout on HDA_DSP_REG_ADSPCS read\n", 241 __func__); 242 243 return ret; 244 } 245 246 int hda_dsp_enable_core(struct snd_sof_dev *sdev, unsigned int core_mask) 247 { 248 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 249 const struct sof_intel_dsp_desc *chip = hda->desc; 250 int ret; 251 252 /* restrict core_mask to host managed cores mask */ 253 core_mask &= chip->host_managed_cores_mask; 254 255 /* return if core_mask is not valid or cores are already enabled */ 256 if (!core_mask || hda_dsp_core_is_enabled(sdev, core_mask)) 257 return 0; 258 259 /* power up */ 260 ret = hda_dsp_core_power_up(sdev, core_mask); 261 if (ret < 0) { 262 dev_err(sdev->dev, "error: dsp core power up failed: core_mask %x\n", 263 core_mask); 264 return ret; 265 } 266 267 return hda_dsp_core_run(sdev, core_mask); 268 } 269 270 int hda_dsp_core_reset_power_down(struct snd_sof_dev *sdev, 271 unsigned int core_mask) 272 { 273 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 274 const struct sof_intel_dsp_desc *chip = hda->desc; 275 int ret; 276 277 /* restrict core_mask to host managed cores mask */ 278 core_mask &= chip->host_managed_cores_mask; 279 280 /* return if core_mask is not valid */ 281 if (!core_mask) 282 return 0; 283 284 /* place core in reset prior to power down */ 285 ret = hda_dsp_core_stall_reset(sdev, core_mask); 286 if (ret < 0) { 287 dev_err(sdev->dev, "error: dsp core reset failed: core_mask %x\n", 288 core_mask); 289 return ret; 290 } 291 292 /* power down core */ 293 ret = hda_dsp_core_power_down(sdev, core_mask); 294 if (ret < 0) { 295 dev_err(sdev->dev, "error: dsp core power down fail mask %x: %d\n", 296 core_mask, ret); 297 return ret; 298 } 299 300 /* make sure we are in OFF state */ 301 if (hda_dsp_core_is_enabled(sdev, core_mask)) { 302 dev_err(sdev->dev, "error: dsp core disable fail mask %x: %d\n", 303 core_mask, ret); 304 ret = -EIO; 305 } 306 307 return ret; 308 } 309 310 void hda_dsp_ipc_int_enable(struct snd_sof_dev *sdev) 311 { 312 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 313 const struct sof_intel_dsp_desc *chip = hda->desc; 314 315 /* enable IPC DONE and BUSY interrupts */ 316 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl, 317 HDA_DSP_REG_HIPCCTL_DONE | HDA_DSP_REG_HIPCCTL_BUSY, 318 HDA_DSP_REG_HIPCCTL_DONE | HDA_DSP_REG_HIPCCTL_BUSY); 319 320 /* enable IPC interrupt */ 321 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIC, 322 HDA_DSP_ADSPIC_IPC, HDA_DSP_ADSPIC_IPC); 323 } 324 325 void hda_dsp_ipc_int_disable(struct snd_sof_dev *sdev) 326 { 327 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 328 const struct sof_intel_dsp_desc *chip = hda->desc; 329 330 /* disable IPC interrupt */ 331 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIC, 332 HDA_DSP_ADSPIC_IPC, 0); 333 334 /* disable IPC BUSY and DONE interrupt */ 335 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl, 336 HDA_DSP_REG_HIPCCTL_BUSY | HDA_DSP_REG_HIPCCTL_DONE, 0); 337 } 338 339 static int hda_dsp_wait_d0i3c_done(struct snd_sof_dev *sdev) 340 { 341 struct hdac_bus *bus = sof_to_bus(sdev); 342 int retry = HDA_DSP_REG_POLL_RETRY_COUNT; 343 344 while (snd_hdac_chip_readb(bus, VS_D0I3C) & SOF_HDA_VS_D0I3C_CIP) { 345 if (!retry--) 346 return -ETIMEDOUT; 347 usleep_range(10, 15); 348 } 349 350 return 0; 351 } 352 353 static int hda_dsp_send_pm_gate_ipc(struct snd_sof_dev *sdev, u32 flags) 354 { 355 struct sof_ipc_pm_gate pm_gate; 356 struct sof_ipc_reply reply; 357 358 memset(&pm_gate, 0, sizeof(pm_gate)); 359 360 /* configure pm_gate ipc message */ 361 pm_gate.hdr.size = sizeof(pm_gate); 362 pm_gate.hdr.cmd = SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_GATE; 363 pm_gate.flags = flags; 364 365 /* send pm_gate ipc to dsp */ 366 return sof_ipc_tx_message_no_pm(sdev->ipc, &pm_gate, sizeof(pm_gate), 367 &reply, sizeof(reply)); 368 } 369 370 static int hda_dsp_update_d0i3c_register(struct snd_sof_dev *sdev, u8 value) 371 { 372 struct hdac_bus *bus = sof_to_bus(sdev); 373 int ret; 374 375 /* Write to D0I3C after Command-In-Progress bit is cleared */ 376 ret = hda_dsp_wait_d0i3c_done(sdev); 377 if (ret < 0) { 378 dev_err(bus->dev, "CIP timeout before D0I3C update!\n"); 379 return ret; 380 } 381 382 /* Update D0I3C register */ 383 snd_hdac_chip_updateb(bus, VS_D0I3C, SOF_HDA_VS_D0I3C_I3, value); 384 385 /* Wait for cmd in progress to be cleared before exiting the function */ 386 ret = hda_dsp_wait_d0i3c_done(sdev); 387 if (ret < 0) { 388 dev_err(bus->dev, "CIP timeout after D0I3C update!\n"); 389 return ret; 390 } 391 392 dev_vdbg(bus->dev, "D0I3C updated, register = 0x%x\n", 393 snd_hdac_chip_readb(bus, VS_D0I3C)); 394 395 return 0; 396 } 397 398 static int hda_dsp_set_D0_state(struct snd_sof_dev *sdev, 399 const struct sof_dsp_power_state *target_state) 400 { 401 u32 flags = 0; 402 int ret; 403 u8 value = 0; 404 405 /* 406 * Sanity check for illegal state transitions 407 * The only allowed transitions are: 408 * 1. D3 -> D0I0 409 * 2. D0I0 -> D0I3 410 * 3. D0I3 -> D0I0 411 */ 412 switch (sdev->dsp_power_state.state) { 413 case SOF_DSP_PM_D0: 414 /* Follow the sequence below for D0 substate transitions */ 415 break; 416 case SOF_DSP_PM_D3: 417 /* Follow regular flow for D3 -> D0 transition */ 418 return 0; 419 default: 420 dev_err(sdev->dev, "error: transition from %d to %d not allowed\n", 421 sdev->dsp_power_state.state, target_state->state); 422 return -EINVAL; 423 } 424 425 /* Set flags and register value for D0 target substate */ 426 if (target_state->substate == SOF_HDA_DSP_PM_D0I3) { 427 value = SOF_HDA_VS_D0I3C_I3; 428 429 /* 430 * Trace DMA need to be disabled when the DSP enters 431 * D0I3 for S0Ix suspend, but it can be kept enabled 432 * when the DSP enters D0I3 while the system is in S0 433 * for debug purpose. 434 */ 435 if (!sdev->fw_trace_is_supported || 436 !hda_enable_trace_D0I3_S0 || 437 sdev->system_suspend_target != SOF_SUSPEND_NONE) 438 flags = HDA_PM_NO_DMA_TRACE; 439 } else { 440 /* prevent power gating in D0I0 */ 441 flags = HDA_PM_PPG; 442 } 443 444 /* update D0I3C register */ 445 ret = hda_dsp_update_d0i3c_register(sdev, value); 446 if (ret < 0) 447 return ret; 448 449 /* 450 * Notify the DSP of the state change. 451 * If this IPC fails, revert the D0I3C register update in order 452 * to prevent partial state change. 453 */ 454 ret = hda_dsp_send_pm_gate_ipc(sdev, flags); 455 if (ret < 0) { 456 dev_err(sdev->dev, 457 "error: PM_GATE ipc error %d\n", ret); 458 goto revert; 459 } 460 461 return ret; 462 463 revert: 464 /* fallback to the previous register value */ 465 value = value ? 0 : SOF_HDA_VS_D0I3C_I3; 466 467 /* 468 * This can fail but return the IPC error to signal that 469 * the state change failed. 470 */ 471 hda_dsp_update_d0i3c_register(sdev, value); 472 473 return ret; 474 } 475 476 /* helper to log DSP state */ 477 static void hda_dsp_state_log(struct snd_sof_dev *sdev) 478 { 479 switch (sdev->dsp_power_state.state) { 480 case SOF_DSP_PM_D0: 481 switch (sdev->dsp_power_state.substate) { 482 case SOF_HDA_DSP_PM_D0I0: 483 dev_dbg(sdev->dev, "Current DSP power state: D0I0\n"); 484 break; 485 case SOF_HDA_DSP_PM_D0I3: 486 dev_dbg(sdev->dev, "Current DSP power state: D0I3\n"); 487 break; 488 default: 489 dev_dbg(sdev->dev, "Unknown DSP D0 substate: %d\n", 490 sdev->dsp_power_state.substate); 491 break; 492 } 493 break; 494 case SOF_DSP_PM_D1: 495 dev_dbg(sdev->dev, "Current DSP power state: D1\n"); 496 break; 497 case SOF_DSP_PM_D2: 498 dev_dbg(sdev->dev, "Current DSP power state: D2\n"); 499 break; 500 case SOF_DSP_PM_D3: 501 dev_dbg(sdev->dev, "Current DSP power state: D3\n"); 502 break; 503 default: 504 dev_dbg(sdev->dev, "Unknown DSP power state: %d\n", 505 sdev->dsp_power_state.state); 506 break; 507 } 508 } 509 510 /* 511 * All DSP power state transitions are initiated by the driver. 512 * If the requested state change fails, the error is simply returned. 513 * Further state transitions are attempted only when the set_power_save() op 514 * is called again either because of a new IPC sent to the DSP or 515 * during system suspend/resume. 516 */ 517 int hda_dsp_set_power_state(struct snd_sof_dev *sdev, 518 const struct sof_dsp_power_state *target_state) 519 { 520 int ret = 0; 521 522 /* 523 * When the DSP is already in D0I3 and the target state is D0I3, 524 * it could be the case that the DSP is in D0I3 during S0 525 * and the system is suspending to S0Ix. Therefore, 526 * hda_dsp_set_D0_state() must be called to disable trace DMA 527 * by sending the PM_GATE IPC to the FW. 528 */ 529 if (target_state->substate == SOF_HDA_DSP_PM_D0I3 && 530 sdev->system_suspend_target == SOF_SUSPEND_S0IX) 531 goto set_state; 532 533 /* 534 * For all other cases, return without doing anything if 535 * the DSP is already in the target state. 536 */ 537 if (target_state->state == sdev->dsp_power_state.state && 538 target_state->substate == sdev->dsp_power_state.substate) 539 return 0; 540 541 set_state: 542 switch (target_state->state) { 543 case SOF_DSP_PM_D0: 544 ret = hda_dsp_set_D0_state(sdev, target_state); 545 break; 546 case SOF_DSP_PM_D3: 547 /* The only allowed transition is: D0I0 -> D3 */ 548 if (sdev->dsp_power_state.state == SOF_DSP_PM_D0 && 549 sdev->dsp_power_state.substate == SOF_HDA_DSP_PM_D0I0) 550 break; 551 552 dev_err(sdev->dev, 553 "error: transition from %d to %d not allowed\n", 554 sdev->dsp_power_state.state, target_state->state); 555 return -EINVAL; 556 default: 557 dev_err(sdev->dev, "error: target state unsupported %d\n", 558 target_state->state); 559 return -EINVAL; 560 } 561 if (ret < 0) { 562 dev_err(sdev->dev, 563 "failed to set requested target DSP state %d substate %d\n", 564 target_state->state, target_state->substate); 565 return ret; 566 } 567 568 sdev->dsp_power_state = *target_state; 569 hda_dsp_state_log(sdev); 570 return ret; 571 } 572 573 /* 574 * Audio DSP states may transform as below:- 575 * 576 * Opportunistic D0I3 in S0 577 * Runtime +---------------------+ Delayed D0i3 work timeout 578 * suspend | +--------------------+ 579 * +------------+ D0I0(active) | | 580 * | | <---------------+ | 581 * | +--------> | New IPC | | 582 * | |Runtime +--^--+---------^--+--+ (via mailbox) | | 583 * | |resume | | | | | | 584 * | | | | | | | | 585 * | | System| | | | | | 586 * | | resume| | S3/S0IX | | | | 587 * | | | | suspend | | S0IX | | 588 * | | | | | |suspend | | 589 * | | | | | | | | 590 * | | | | | | | | 591 * +-v---+-----------+--v-------+ | | +------+----v----+ 592 * | | | +-----------> | 593 * | D3 (suspended) | | | D0I3 | 594 * | | +--------------+ | 595 * | | System resume | | 596 * +----------------------------+ +----------------+ 597 * 598 * S0IX suspend: The DSP is in D0I3 if any D0I3-compatible streams 599 * ignored the suspend trigger. Otherwise the DSP 600 * is in D3. 601 */ 602 603 static int hda_suspend(struct snd_sof_dev *sdev, bool runtime_suspend) 604 { 605 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 606 const struct sof_intel_dsp_desc *chip = hda->desc; 607 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 608 struct hdac_bus *bus = sof_to_bus(sdev); 609 #endif 610 int ret, j; 611 612 hda_sdw_int_enable(sdev, false); 613 614 /* disable IPC interrupts */ 615 hda_dsp_ipc_int_disable(sdev); 616 617 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 618 hda_codec_jack_wake_enable(sdev, runtime_suspend); 619 620 /* power down all hda link */ 621 snd_hdac_ext_bus_link_power_down_all(bus); 622 #endif 623 624 /* power down DSP */ 625 ret = hda_dsp_core_reset_power_down(sdev, chip->host_managed_cores_mask); 626 if (ret < 0) { 627 dev_err(sdev->dev, 628 "error: failed to power down core during suspend\n"); 629 return ret; 630 } 631 632 /* reset ref counts for all cores */ 633 for (j = 0; j < chip->cores_num; j++) 634 sdev->dsp_core_ref_count[j] = 0; 635 636 /* disable ppcap interrupt */ 637 hda_dsp_ctrl_ppcap_enable(sdev, false); 638 hda_dsp_ctrl_ppcap_int_enable(sdev, false); 639 640 /* disable hda bus irq and streams */ 641 hda_dsp_ctrl_stop_chip(sdev); 642 643 /* disable LP retention mode */ 644 snd_sof_pci_update_bits(sdev, PCI_PGCTL, 645 PCI_PGCTL_LSRMD_MASK, PCI_PGCTL_LSRMD_MASK); 646 647 /* reset controller */ 648 ret = hda_dsp_ctrl_link_reset(sdev, true); 649 if (ret < 0) { 650 dev_err(sdev->dev, 651 "error: failed to reset controller during suspend\n"); 652 return ret; 653 } 654 655 /* display codec can powered off after link reset */ 656 hda_codec_i915_display_power(sdev, false); 657 658 return 0; 659 } 660 661 static int hda_resume(struct snd_sof_dev *sdev, bool runtime_resume) 662 { 663 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 664 struct hdac_bus *bus = sof_to_bus(sdev); 665 struct hdac_ext_link *hlink = NULL; 666 #endif 667 int ret; 668 669 /* display codec must be powered before link reset */ 670 hda_codec_i915_display_power(sdev, true); 671 672 /* 673 * clear TCSEL to clear playback on some HD Audio 674 * codecs. PCI TCSEL is defined in the Intel manuals. 675 */ 676 snd_sof_pci_update_bits(sdev, PCI_TCSEL, 0x07, 0); 677 678 /* reset and start hda controller */ 679 ret = hda_dsp_ctrl_init_chip(sdev, true); 680 if (ret < 0) { 681 dev_err(sdev->dev, 682 "error: failed to start controller after resume\n"); 683 goto cleanup; 684 } 685 686 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 687 /* check jack status */ 688 if (runtime_resume) { 689 hda_codec_jack_wake_enable(sdev, false); 690 if (sdev->system_suspend_target == SOF_SUSPEND_NONE) 691 hda_codec_jack_check(sdev); 692 } 693 694 /* turn off the links that were off before suspend */ 695 list_for_each_entry(hlink, &bus->hlink_list, list) { 696 if (!hlink->ref_count) 697 snd_hdac_ext_bus_link_power_down(hlink); 698 } 699 700 /* check dma status and clean up CORB/RIRB buffers */ 701 if (!bus->cmd_dma_state) 702 snd_hdac_bus_stop_cmd_io(bus); 703 #endif 704 705 /* enable ppcap interrupt */ 706 hda_dsp_ctrl_ppcap_enable(sdev, true); 707 hda_dsp_ctrl_ppcap_int_enable(sdev, true); 708 709 cleanup: 710 /* display codec can powered off after controller init */ 711 hda_codec_i915_display_power(sdev, false); 712 713 return 0; 714 } 715 716 int hda_dsp_resume(struct snd_sof_dev *sdev) 717 { 718 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 719 struct pci_dev *pci = to_pci_dev(sdev->dev); 720 const struct sof_dsp_power_state target_state = { 721 .state = SOF_DSP_PM_D0, 722 .substate = SOF_HDA_DSP_PM_D0I0, 723 }; 724 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 725 struct hdac_bus *bus = sof_to_bus(sdev); 726 struct hdac_ext_link *hlink = NULL; 727 #endif 728 int ret; 729 730 /* resume from D0I3 */ 731 if (sdev->dsp_power_state.state == SOF_DSP_PM_D0) { 732 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 733 /* power up links that were active before suspend */ 734 list_for_each_entry(hlink, &bus->hlink_list, list) { 735 if (hlink->ref_count) { 736 ret = snd_hdac_ext_bus_link_power_up(hlink); 737 if (ret < 0) { 738 dev_dbg(sdev->dev, 739 "error %d in %s: failed to power up links", 740 ret, __func__); 741 return ret; 742 } 743 } 744 } 745 746 /* set up CORB/RIRB buffers if was on before suspend */ 747 if (bus->cmd_dma_state) 748 snd_hdac_bus_init_cmd_io(bus); 749 #endif 750 751 /* Set DSP power state */ 752 ret = snd_sof_dsp_set_power_state(sdev, &target_state); 753 if (ret < 0) { 754 dev_err(sdev->dev, "error: setting dsp state %d substate %d\n", 755 target_state.state, target_state.substate); 756 return ret; 757 } 758 759 /* restore L1SEN bit */ 760 if (hda->l1_support_changed) 761 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, 762 HDA_VS_INTEL_EM2, 763 HDA_VS_INTEL_EM2_L1SEN, 0); 764 765 /* restore and disable the system wakeup */ 766 pci_restore_state(pci); 767 disable_irq_wake(pci->irq); 768 return 0; 769 } 770 771 /* init hda controller. DSP cores will be powered up during fw boot */ 772 ret = hda_resume(sdev, false); 773 if (ret < 0) 774 return ret; 775 776 return snd_sof_dsp_set_power_state(sdev, &target_state); 777 } 778 779 int hda_dsp_runtime_resume(struct snd_sof_dev *sdev) 780 { 781 const struct sof_dsp_power_state target_state = { 782 .state = SOF_DSP_PM_D0, 783 }; 784 int ret; 785 786 /* init hda controller. DSP cores will be powered up during fw boot */ 787 ret = hda_resume(sdev, true); 788 if (ret < 0) 789 return ret; 790 791 return snd_sof_dsp_set_power_state(sdev, &target_state); 792 } 793 794 int hda_dsp_runtime_idle(struct snd_sof_dev *sdev) 795 { 796 struct hdac_bus *hbus = sof_to_bus(sdev); 797 798 if (hbus->codec_powered) { 799 dev_dbg(sdev->dev, "some codecs still powered (%08X), not idle\n", 800 (unsigned int)hbus->codec_powered); 801 return -EBUSY; 802 } 803 804 return 0; 805 } 806 807 int hda_dsp_runtime_suspend(struct snd_sof_dev *sdev) 808 { 809 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 810 const struct sof_dsp_power_state target_state = { 811 .state = SOF_DSP_PM_D3, 812 }; 813 int ret; 814 815 /* cancel any attempt for DSP D0I3 */ 816 cancel_delayed_work_sync(&hda->d0i3_work); 817 818 /* stop hda controller and power dsp off */ 819 ret = hda_suspend(sdev, true); 820 if (ret < 0) 821 return ret; 822 823 return snd_sof_dsp_set_power_state(sdev, &target_state); 824 } 825 826 int hda_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state) 827 { 828 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 829 struct hdac_bus *bus = sof_to_bus(sdev); 830 struct pci_dev *pci = to_pci_dev(sdev->dev); 831 const struct sof_dsp_power_state target_dsp_state = { 832 .state = target_state, 833 .substate = target_state == SOF_DSP_PM_D0 ? 834 SOF_HDA_DSP_PM_D0I3 : 0, 835 }; 836 int ret; 837 838 /* cancel any attempt for DSP D0I3 */ 839 cancel_delayed_work_sync(&hda->d0i3_work); 840 841 if (target_state == SOF_DSP_PM_D0) { 842 /* Set DSP power state */ 843 ret = snd_sof_dsp_set_power_state(sdev, &target_dsp_state); 844 if (ret < 0) { 845 dev_err(sdev->dev, "error: setting dsp state %d substate %d\n", 846 target_dsp_state.state, 847 target_dsp_state.substate); 848 return ret; 849 } 850 851 /* enable L1SEN to make sure the system can enter S0Ix */ 852 hda->l1_support_changed = 853 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, 854 HDA_VS_INTEL_EM2, 855 HDA_VS_INTEL_EM2_L1SEN, 856 HDA_VS_INTEL_EM2_L1SEN); 857 858 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 859 /* stop the CORB/RIRB DMA if it is On */ 860 if (bus->cmd_dma_state) 861 snd_hdac_bus_stop_cmd_io(bus); 862 863 /* no link can be powered in s0ix state */ 864 ret = snd_hdac_ext_bus_link_power_down_all(bus); 865 if (ret < 0) { 866 dev_dbg(sdev->dev, 867 "error %d in %s: failed to power down links", 868 ret, __func__); 869 return ret; 870 } 871 #endif 872 873 /* enable the system waking up via IPC IRQ */ 874 enable_irq_wake(pci->irq); 875 pci_save_state(pci); 876 return 0; 877 } 878 879 /* stop hda controller and power dsp off */ 880 ret = hda_suspend(sdev, false); 881 if (ret < 0) { 882 dev_err(bus->dev, "error: suspending dsp\n"); 883 return ret; 884 } 885 886 return snd_sof_dsp_set_power_state(sdev, &target_dsp_state); 887 } 888 889 int hda_dsp_shutdown(struct snd_sof_dev *sdev) 890 { 891 sdev->system_suspend_target = SOF_SUSPEND_S3; 892 return snd_sof_suspend(sdev->dev); 893 } 894 895 int hda_dsp_set_hw_params_upon_resume(struct snd_sof_dev *sdev) 896 { 897 int ret; 898 899 /* make sure all DAI resources are freed */ 900 ret = hda_dsp_dais_suspend(sdev); 901 if (ret < 0) 902 dev_warn(sdev->dev, "%s: failure in hda_dsp_dais_suspend\n", __func__); 903 904 return ret; 905 } 906 907 void hda_dsp_d0i3_work(struct work_struct *work) 908 { 909 struct sof_intel_hda_dev *hdev = container_of(work, 910 struct sof_intel_hda_dev, 911 d0i3_work.work); 912 struct hdac_bus *bus = &hdev->hbus.core; 913 struct snd_sof_dev *sdev = dev_get_drvdata(bus->dev); 914 struct sof_dsp_power_state target_state = { 915 .state = SOF_DSP_PM_D0, 916 .substate = SOF_HDA_DSP_PM_D0I3, 917 }; 918 int ret; 919 920 /* DSP can enter D0I3 iff only D0I3-compatible streams are active */ 921 if (!snd_sof_dsp_only_d0i3_compatible_stream_active(sdev)) 922 /* remain in D0I0 */ 923 return; 924 925 /* This can fail but error cannot be propagated */ 926 ret = snd_sof_dsp_set_power_state(sdev, &target_state); 927 if (ret < 0) 928 dev_err_ratelimited(sdev->dev, 929 "error: failed to set DSP state %d substate %d\n", 930 target_state.state, target_state.substate); 931 } 932 933 int hda_dsp_core_get(struct snd_sof_dev *sdev, int core) 934 { 935 struct sof_ipc_pm_core_config pm_core_config = { 936 .hdr = { 937 .cmd = SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_CORE_ENABLE, 938 .size = sizeof(pm_core_config), 939 }, 940 .enable_mask = sdev->enabled_cores_mask | BIT(core), 941 }; 942 int ret, ret1; 943 944 /* power up core */ 945 ret = hda_dsp_enable_core(sdev, BIT(core)); 946 if (ret < 0) { 947 dev_err(sdev->dev, "failed to power up core %d with err: %d\n", 948 core, ret); 949 return ret; 950 } 951 952 /* No need to send IPC for primary core or if FW boot is not complete */ 953 if (sdev->fw_state != SOF_FW_BOOT_COMPLETE || core == SOF_DSP_PRIMARY_CORE) 954 return 0; 955 956 /* Now notify DSP for secondary cores */ 957 ret = sof_ipc_tx_message(sdev->ipc, &pm_core_config, sizeof(pm_core_config), 958 &pm_core_config, sizeof(pm_core_config)); 959 if (ret < 0) { 960 dev_err(sdev->dev, "failed to enable secondary core '%d' failed with %d\n", 961 core, ret); 962 goto power_down; 963 } 964 965 return ret; 966 967 power_down: 968 /* power down core if it is host managed and return the original error if this fails too */ 969 ret1 = hda_dsp_core_reset_power_down(sdev, BIT(core)); 970 if (ret1 < 0) 971 dev_err(sdev->dev, "failed to power down core: %d with err: %d\n", core, ret1); 972 973 return ret; 974 } 975