1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org> 4 * Copyright (c) 2022, Luca Weiss <luca.weiss@fairphone.com> 5 */ 6 7#include <dt-bindings/clock/qcom,gcc-sm6350.h> 8#include <dt-bindings/clock/qcom,rpmh.h> 9#include <dt-bindings/clock/qcom,sm6350-camcc.h> 10#include <dt-bindings/dma/qcom-gpi.h> 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/interconnect/qcom,icc.h> 13#include <dt-bindings/interconnect/qcom,osm-l3.h> 14#include <dt-bindings/interconnect/qcom,sm6350.h> 15#include <dt-bindings/interrupt-controller/arm-gic.h> 16#include <dt-bindings/mailbox/qcom-ipcc.h> 17#include <dt-bindings/phy/phy-qcom-qmp.h> 18#include <dt-bindings/power/qcom-rpmpd.h> 19#include <dt-bindings/soc/qcom,rpmh-rsc.h> 20 21/ { 22 interrupt-parent = <&intc>; 23 #address-cells = <2>; 24 #size-cells = <2>; 25 26 clocks { 27 xo_board: xo-board { 28 compatible = "fixed-clock"; 29 #clock-cells = <0>; 30 clock-frequency = <76800000>; 31 clock-output-names = "xo_board"; 32 }; 33 34 sleep_clk: sleep-clk { 35 compatible = "fixed-clock"; 36 clock-frequency = <32764>; 37 #clock-cells = <0>; 38 }; 39 }; 40 41 cpus { 42 #address-cells = <2>; 43 #size-cells = <0>; 44 45 CPU0: cpu@0 { 46 device_type = "cpu"; 47 compatible = "qcom,kryo560"; 48 reg = <0x0 0x0>; 49 clocks = <&cpufreq_hw 0>; 50 enable-method = "psci"; 51 capacity-dmips-mhz = <1024>; 52 dynamic-power-coefficient = <100>; 53 next-level-cache = <&L2_0>; 54 qcom,freq-domain = <&cpufreq_hw 0>; 55 operating-points-v2 = <&cpu0_opp_table>; 56 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 57 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 58 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 59 power-domains = <&CPU_PD0>; 60 power-domain-names = "psci"; 61 #cooling-cells = <2>; 62 L2_0: l2-cache { 63 compatible = "cache"; 64 cache-level = <2>; 65 next-level-cache = <&L3_0>; 66 L3_0: l3-cache { 67 compatible = "cache"; 68 cache-level = <3>; 69 }; 70 }; 71 }; 72 73 CPU1: cpu@100 { 74 device_type = "cpu"; 75 compatible = "qcom,kryo560"; 76 reg = <0x0 0x100>; 77 clocks = <&cpufreq_hw 0>; 78 enable-method = "psci"; 79 capacity-dmips-mhz = <1024>; 80 dynamic-power-coefficient = <100>; 81 next-level-cache = <&L2_100>; 82 qcom,freq-domain = <&cpufreq_hw 0>; 83 operating-points-v2 = <&cpu0_opp_table>; 84 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 85 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 86 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 87 power-domains = <&CPU_PD1>; 88 power-domain-names = "psci"; 89 #cooling-cells = <2>; 90 L2_100: l2-cache { 91 compatible = "cache"; 92 cache-level = <2>; 93 next-level-cache = <&L3_0>; 94 }; 95 }; 96 97 CPU2: cpu@200 { 98 device_type = "cpu"; 99 compatible = "qcom,kryo560"; 100 reg = <0x0 0x200>; 101 clocks = <&cpufreq_hw 0>; 102 enable-method = "psci"; 103 capacity-dmips-mhz = <1024>; 104 dynamic-power-coefficient = <100>; 105 next-level-cache = <&L2_200>; 106 qcom,freq-domain = <&cpufreq_hw 0>; 107 operating-points-v2 = <&cpu0_opp_table>; 108 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 109 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 110 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 111 power-domains = <&CPU_PD2>; 112 power-domain-names = "psci"; 113 #cooling-cells = <2>; 114 L2_200: l2-cache { 115 compatible = "cache"; 116 cache-level = <2>; 117 next-level-cache = <&L3_0>; 118 }; 119 }; 120 121 CPU3: cpu@300 { 122 device_type = "cpu"; 123 compatible = "qcom,kryo560"; 124 reg = <0x0 0x300>; 125 clocks = <&cpufreq_hw 0>; 126 enable-method = "psci"; 127 capacity-dmips-mhz = <1024>; 128 dynamic-power-coefficient = <100>; 129 next-level-cache = <&L2_300>; 130 qcom,freq-domain = <&cpufreq_hw 0>; 131 operating-points-v2 = <&cpu0_opp_table>; 132 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 133 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 134 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 135 power-domains = <&CPU_PD3>; 136 power-domain-names = "psci"; 137 #cooling-cells = <2>; 138 L2_300: l2-cache { 139 compatible = "cache"; 140 cache-level = <2>; 141 next-level-cache = <&L3_0>; 142 }; 143 }; 144 145 CPU4: cpu@400 { 146 device_type = "cpu"; 147 compatible = "qcom,kryo560"; 148 reg = <0x0 0x400>; 149 clocks = <&cpufreq_hw 0>; 150 enable-method = "psci"; 151 capacity-dmips-mhz = <1024>; 152 dynamic-power-coefficient = <100>; 153 next-level-cache = <&L2_400>; 154 qcom,freq-domain = <&cpufreq_hw 0>; 155 operating-points-v2 = <&cpu0_opp_table>; 156 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 157 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 158 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 159 power-domains = <&CPU_PD4>; 160 power-domain-names = "psci"; 161 #cooling-cells = <2>; 162 L2_400: l2-cache { 163 compatible = "cache"; 164 cache-level = <2>; 165 next-level-cache = <&L3_0>; 166 }; 167 }; 168 169 CPU5: cpu@500 { 170 device_type = "cpu"; 171 compatible = "qcom,kryo560"; 172 reg = <0x0 0x500>; 173 clocks = <&cpufreq_hw 0>; 174 enable-method = "psci"; 175 capacity-dmips-mhz = <1024>; 176 dynamic-power-coefficient = <100>; 177 next-level-cache = <&L2_500>; 178 qcom,freq-domain = <&cpufreq_hw 0>; 179 operating-points-v2 = <&cpu0_opp_table>; 180 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 181 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 182 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 183 power-domains = <&CPU_PD5>; 184 power-domain-names = "psci"; 185 #cooling-cells = <2>; 186 L2_500: l2-cache { 187 compatible = "cache"; 188 cache-level = <2>; 189 next-level-cache = <&L3_0>; 190 }; 191 }; 192 193 CPU6: cpu@600 { 194 device_type = "cpu"; 195 compatible = "qcom,kryo560"; 196 reg = <0x0 0x600>; 197 clocks = <&cpufreq_hw 1>; 198 enable-method = "psci"; 199 capacity-dmips-mhz = <1894>; 200 dynamic-power-coefficient = <703>; 201 next-level-cache = <&L2_600>; 202 qcom,freq-domain = <&cpufreq_hw 1>; 203 operating-points-v2 = <&cpu6_opp_table>; 204 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 205 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 206 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 207 power-domains = <&CPU_PD6>; 208 power-domain-names = "psci"; 209 #cooling-cells = <2>; 210 L2_600: l2-cache { 211 compatible = "cache"; 212 cache-level = <2>; 213 next-level-cache = <&L3_0>; 214 }; 215 }; 216 217 CPU7: cpu@700 { 218 device_type = "cpu"; 219 compatible = "qcom,kryo560"; 220 reg = <0x0 0x700>; 221 clocks = <&cpufreq_hw 1>; 222 enable-method = "psci"; 223 capacity-dmips-mhz = <1894>; 224 dynamic-power-coefficient = <703>; 225 next-level-cache = <&L2_700>; 226 qcom,freq-domain = <&cpufreq_hw 1>; 227 operating-points-v2 = <&cpu6_opp_table>; 228 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 229 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 230 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 231 power-domains = <&CPU_PD7>; 232 power-domain-names = "psci"; 233 #cooling-cells = <2>; 234 L2_700: l2-cache { 235 compatible = "cache"; 236 cache-level = <2>; 237 next-level-cache = <&L3_0>; 238 }; 239 }; 240 241 cpu-map { 242 cluster0 { 243 core0 { 244 cpu = <&CPU0>; 245 }; 246 247 core1 { 248 cpu = <&CPU1>; 249 }; 250 251 core2 { 252 cpu = <&CPU2>; 253 }; 254 255 core3 { 256 cpu = <&CPU3>; 257 }; 258 259 core4 { 260 cpu = <&CPU4>; 261 }; 262 263 core5 { 264 cpu = <&CPU5>; 265 }; 266 267 core6 { 268 cpu = <&CPU6>; 269 }; 270 271 core7 { 272 cpu = <&CPU7>; 273 }; 274 }; 275 }; 276 277 domain-idle-states { 278 CLUSTER_SLEEP_PC: cluster-sleep-0 { 279 compatible = "domain-idle-state"; 280 arm,psci-suspend-param = <0x41000044>; 281 entry-latency-us = <2752>; 282 exit-latency-us = <3048>; 283 min-residency-us = <6118>; 284 }; 285 286 CLUSTER_SLEEP_CX_RET: cluster-sleep-1 { 287 compatible = "domain-idle-state"; 288 arm,psci-suspend-param = <0x41001244>; 289 entry-latency-us = <3638>; 290 exit-latency-us = <4562>; 291 min-residency-us = <8467>; 292 }; 293 294 CLUSTER_AOSS_SLEEP: cluster-sleep-2 { 295 compatible = "domain-idle-state"; 296 arm,psci-suspend-param = <0x4100b244>; 297 entry-latency-us = <3263>; 298 exit-latency-us = <6562>; 299 min-residency-us = <9987>; 300 }; 301 }; 302 303 cpu_idle_states: idle-states { 304 entry-method = "psci"; 305 306 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 307 compatible = "arm,idle-state"; 308 idle-state-name = "little-power-collapse"; 309 arm,psci-suspend-param = <0x40000003>; 310 entry-latency-us = <549>; 311 exit-latency-us = <901>; 312 min-residency-us = <1774>; 313 local-timer-stop; 314 }; 315 316 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 317 compatible = "arm,idle-state"; 318 idle-state-name = "little-rail-power-collapse"; 319 arm,psci-suspend-param = <0x40000004>; 320 entry-latency-us = <702>; 321 exit-latency-us = <915>; 322 min-residency-us = <4001>; 323 local-timer-stop; 324 }; 325 326 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 327 compatible = "arm,idle-state"; 328 idle-state-name = "big-power-collapse"; 329 arm,psci-suspend-param = <0x40000003>; 330 entry-latency-us = <523>; 331 exit-latency-us = <1244>; 332 min-residency-us = <2207>; 333 local-timer-stop; 334 }; 335 336 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 337 compatible = "arm,idle-state"; 338 idle-state-name = "big-rail-power-collapse"; 339 arm,psci-suspend-param = <0x40000004>; 340 entry-latency-us = <526>; 341 exit-latency-us = <1854>; 342 min-residency-us = <5555>; 343 local-timer-stop; 344 }; 345 }; 346 }; 347 348 firmware { 349 scm: scm { 350 compatible = "qcom,scm-sm6350", "qcom,scm"; 351 #reset-cells = <1>; 352 }; 353 }; 354 355 memory@80000000 { 356 device_type = "memory"; 357 /* We expect the bootloader to fill in the size */ 358 reg = <0x0 0x80000000 0x0 0x0>; 359 }; 360 361 cpu0_opp_table: opp-table-cpu0 { 362 compatible = "operating-points-v2"; 363 opp-shared; 364 365 opp-300000000 { 366 opp-hz = /bits/ 64 <300000000>; 367 /* DDR: 4-wide, 2 channels, double data rate, L3: 16-wide, 2 channels */ 368 opp-peak-kBps = <(200000 * 4 * 2 * 2) (300000 * 16 * 2)>; 369 }; 370 371 opp-576000000 { 372 opp-hz = /bits/ 64 <576000000>; 373 opp-peak-kBps = <(547000 * 4 * 2 * 2) (556800 * 16 * 2)>; 374 }; 375 376 opp-768000000 { 377 opp-hz = /bits/ 64 <768000000>; 378 opp-peak-kBps = <(768000 * 4 * 2 * 2) (652800 * 16 * 2)>; 379 }; 380 381 opp-1017600000 { 382 opp-hz = /bits/ 64 <1017600000>; 383 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (940800 * 16 * 2)>; 384 }; 385 386 opp-1248000000 { 387 opp-hz = /bits/ 64 <1248000000>; 388 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1209600 * 16 * 2)>; 389 }; 390 391 opp-1324800000 { 392 opp-hz = /bits/ 64 <1324800000>; 393 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1286400 * 16 * 2)>; 394 }; 395 396 opp-1516800000 { 397 opp-hz = /bits/ 64 <1516800000>; 398 opp-peak-kBps = <(1353000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 399 }; 400 401 opp-1612800000 { 402 opp-hz = /bits/ 64 <1612800000>; 403 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 404 }; 405 406 opp-1708800000 { 407 opp-hz = /bits/ 64 <1708800000>; 408 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 409 }; 410 }; 411 412 cpu6_opp_table: opp-table-cpu6 { 413 compatible = "operating-points-v2"; 414 opp-shared; 415 416 opp-300000000 { 417 opp-hz = /bits/ 64 <300000000>; 418 opp-peak-kBps = <(200000 * 4 * 2 * 2) (300000 * 16 * 2)>; 419 }; 420 421 opp-787200000 { 422 opp-hz = /bits/ 64 <787200000>; 423 opp-peak-kBps = <(768000 * 4 * 2 * 2) (652800 * 16 * 2)>; 424 }; 425 426 opp-979200000 { 427 opp-hz = /bits/ 64 <979200000>; 428 opp-peak-kBps = <(768000 * 4 * 2 * 2) (940800 * 16 * 2)>; 429 }; 430 431 opp-1036800000 { 432 opp-hz = /bits/ 64 <1036800000>; 433 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (940800 * 16 * 2)>; 434 }; 435 436 opp-1248000000 { 437 opp-hz = /bits/ 64 <1248000000>; 438 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1209600 * 16 * 2)>; 439 }; 440 441 opp-1401600000 { 442 opp-hz = /bits/ 64 <1401600000>; 443 opp-peak-kBps = <(1353000 * 4 * 2 * 2) (1401600 * 16 * 2)>; 444 }; 445 446 opp-1555200000 { 447 opp-hz = /bits/ 64 <1555200000>; 448 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 449 }; 450 451 opp-1766400000 { 452 opp-hz = /bits/ 64 <1766400000>; 453 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 454 }; 455 456 opp-1900800000 { 457 opp-hz = /bits/ 64 <1900800000>; 458 opp-peak-kBps = <(1804000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 459 }; 460 461 opp-2073600000 { 462 opp-hz = /bits/ 64 <2073600000>; 463 opp-peak-kBps = <(2092000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 464 }; 465 }; 466 467 qup_opp_table: opp-table-qup { 468 compatible = "operating-points-v2"; 469 470 opp-75000000 { 471 opp-hz = /bits/ 64 <75000000>; 472 required-opps = <&rpmhpd_opp_low_svs>; 473 }; 474 475 opp-100000000 { 476 opp-hz = /bits/ 64 <100000000>; 477 required-opps = <&rpmhpd_opp_svs>; 478 }; 479 480 opp-128000000 { 481 opp-hz = /bits/ 64 <128000000>; 482 required-opps = <&rpmhpd_opp_nom>; 483 }; 484 }; 485 486 pmu { 487 compatible = "arm,armv8-pmuv3"; 488 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_LOW>; 489 }; 490 491 psci { 492 compatible = "arm,psci-1.0"; 493 method = "smc"; 494 495 CPU_PD0: power-domain-cpu0 { 496 #power-domain-cells = <0>; 497 power-domains = <&CLUSTER_PD>; 498 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 499 }; 500 501 CPU_PD1: power-domain-cpu1 { 502 #power-domain-cells = <0>; 503 power-domains = <&CLUSTER_PD>; 504 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 505 }; 506 507 CPU_PD2: power-domain-cpu2 { 508 #power-domain-cells = <0>; 509 power-domains = <&CLUSTER_PD>; 510 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 511 }; 512 513 CPU_PD3: power-domain-cpu3 { 514 #power-domain-cells = <0>; 515 power-domains = <&CLUSTER_PD>; 516 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 517 }; 518 519 CPU_PD4: power-domain-cpu4 { 520 #power-domain-cells = <0>; 521 power-domains = <&CLUSTER_PD>; 522 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 523 }; 524 525 CPU_PD5: power-domain-cpu5 { 526 #power-domain-cells = <0>; 527 power-domains = <&CLUSTER_PD>; 528 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 529 }; 530 531 CPU_PD6: power-domain-cpu6 { 532 #power-domain-cells = <0>; 533 power-domains = <&CLUSTER_PD>; 534 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 535 }; 536 537 CPU_PD7: power-domain-cpu7 { 538 #power-domain-cells = <0>; 539 power-domains = <&CLUSTER_PD>; 540 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 541 }; 542 543 CLUSTER_PD: power-domain-cpu-cluster0 { 544 #power-domain-cells = <0>; 545 domain-idle-states = <&CLUSTER_SLEEP_PC 546 &CLUSTER_SLEEP_CX_RET 547 &CLUSTER_AOSS_SLEEP>; 548 }; 549 }; 550 551 reserved_memory: reserved-memory { 552 #address-cells = <2>; 553 #size-cells = <2>; 554 ranges; 555 556 hyp_mem: memory@80000000 { 557 reg = <0 0x80000000 0 0x600000>; 558 no-map; 559 }; 560 561 xbl_aop_mem: memory@80700000 { 562 reg = <0 0x80700000 0 0x160000>; 563 no-map; 564 }; 565 566 cmd_db: memory@80860000 { 567 compatible = "qcom,cmd-db"; 568 reg = <0 0x80860000 0 0x20000>; 569 no-map; 570 }; 571 572 sec_apps_mem: memory@808ff000 { 573 reg = <0 0x808ff000 0 0x1000>; 574 no-map; 575 }; 576 577 smem_mem: memory@80900000 { 578 reg = <0 0x80900000 0 0x200000>; 579 no-map; 580 }; 581 582 cdsp_sec_mem: memory@80b00000 { 583 reg = <0 0x80b00000 0 0x1e00000>; 584 no-map; 585 }; 586 587 pil_camera_mem: memory@86000000 { 588 reg = <0 0x86000000 0 0x500000>; 589 no-map; 590 }; 591 592 pil_npu_mem: memory@86500000 { 593 reg = <0 0x86500000 0 0x500000>; 594 no-map; 595 }; 596 597 pil_video_mem: memory@86a00000 { 598 reg = <0 0x86a00000 0 0x500000>; 599 no-map; 600 }; 601 602 pil_cdsp_mem: memory@86f00000 { 603 reg = <0 0x86f00000 0 0x1e00000>; 604 no-map; 605 }; 606 607 pil_adsp_mem: memory@88d00000 { 608 reg = <0 0x88d00000 0 0x2800000>; 609 no-map; 610 }; 611 612 wlan_fw_mem: memory@8b500000 { 613 reg = <0 0x8b500000 0 0x200000>; 614 no-map; 615 }; 616 617 pil_ipa_fw_mem: memory@8b700000 { 618 reg = <0 0x8b700000 0 0x10000>; 619 no-map; 620 }; 621 622 pil_ipa_gsi_mem: memory@8b710000 { 623 reg = <0 0x8b710000 0 0x5400>; 624 no-map; 625 }; 626 627 pil_gpu_mem: memory@8b715400 { 628 reg = <0 0x8b715400 0 0x2000>; 629 no-map; 630 }; 631 632 pil_modem_mem: memory@8b800000 { 633 reg = <0 0x8b800000 0 0xf800000>; 634 no-map; 635 }; 636 637 cont_splash_memory: memory@a0000000 { 638 reg = <0 0xa0000000 0 0x2300000>; 639 no-map; 640 }; 641 642 dfps_data_memory: memory@a2300000 { 643 reg = <0 0xa2300000 0 0x100000>; 644 no-map; 645 }; 646 647 removed_region: memory@c0000000 { 648 reg = <0 0xc0000000 0 0x3900000>; 649 no-map; 650 }; 651 652 debug_region: memory@ffb00000 { 653 reg = <0 0xffb00000 0 0xc0000>; 654 no-map; 655 }; 656 657 last_log_region: memory@ffbc0000 { 658 reg = <0 0xffbc0000 0 0x40000>; 659 no-map; 660 }; 661 662 ramoops: ramoops@ffc00000 { 663 compatible = "ramoops"; 664 reg = <0 0xffc00000 0 0x100000>; 665 record-size = <0x1000>; 666 console-size = <0x40000>; 667 msg-size = <0x20000 0x20000>; 668 ecc-size = <16>; 669 no-map; 670 }; 671 672 cmdline_region: memory@ffd00000 { 673 reg = <0 0xffd00000 0 0x1000>; 674 no-map; 675 }; 676 }; 677 678 smem { 679 compatible = "qcom,smem"; 680 memory-region = <&smem_mem>; 681 hwlocks = <&tcsr_mutex 3>; 682 }; 683 684 smp2p-adsp { 685 compatible = "qcom,smp2p"; 686 qcom,smem = <443>, <429>; 687 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 688 IPCC_MPROC_SIGNAL_SMP2P 689 IRQ_TYPE_EDGE_RISING>; 690 mboxes = <&ipcc IPCC_CLIENT_LPASS 691 IPCC_MPROC_SIGNAL_SMP2P>; 692 693 qcom,local-pid = <0>; 694 qcom,remote-pid = <2>; 695 696 smp2p_adsp_out: master-kernel { 697 qcom,entry-name = "master-kernel"; 698 #qcom,smem-state-cells = <1>; 699 }; 700 701 smp2p_adsp_in: slave-kernel { 702 qcom,entry-name = "slave-kernel"; 703 interrupt-controller; 704 #interrupt-cells = <2>; 705 }; 706 }; 707 708 smp2p-cdsp { 709 compatible = "qcom,smp2p"; 710 qcom,smem = <94>, <432>; 711 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 712 IPCC_MPROC_SIGNAL_SMP2P 713 IRQ_TYPE_EDGE_RISING>; 714 mboxes = <&ipcc IPCC_CLIENT_CDSP 715 IPCC_MPROC_SIGNAL_SMP2P>; 716 717 qcom,local-pid = <0>; 718 qcom,remote-pid = <5>; 719 720 smp2p_cdsp_out: master-kernel { 721 qcom,entry-name = "master-kernel"; 722 #qcom,smem-state-cells = <1>; 723 }; 724 725 smp2p_cdsp_in: slave-kernel { 726 qcom,entry-name = "slave-kernel"; 727 interrupt-controller; 728 #interrupt-cells = <2>; 729 }; 730 }; 731 732 smp2p-mpss { 733 compatible = "qcom,smp2p"; 734 qcom,smem = <435>, <428>; 735 736 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 737 IPCC_MPROC_SIGNAL_SMP2P 738 IRQ_TYPE_EDGE_RISING>; 739 mboxes = <&ipcc IPCC_CLIENT_MPSS 740 IPCC_MPROC_SIGNAL_SMP2P>; 741 742 qcom,local-pid = <0>; 743 qcom,remote-pid = <1>; 744 745 modem_smp2p_out: master-kernel { 746 qcom,entry-name = "master-kernel"; 747 #qcom,smem-state-cells = <1>; 748 }; 749 750 modem_smp2p_in: slave-kernel { 751 qcom,entry-name = "slave-kernel"; 752 interrupt-controller; 753 #interrupt-cells = <2>; 754 }; 755 756 ipa_smp2p_out: ipa-ap-to-modem { 757 qcom,entry-name = "ipa"; 758 #qcom,smem-state-cells = <1>; 759 }; 760 761 ipa_smp2p_in: ipa-modem-to-ap { 762 qcom,entry-name = "ipa"; 763 interrupt-controller; 764 #interrupt-cells = <2>; 765 }; 766 }; 767 768 soc: soc@0 { 769 #address-cells = <2>; 770 #size-cells = <2>; 771 ranges = <0 0 0 0 0x10 0>; 772 dma-ranges = <0 0 0 0 0x10 0>; 773 compatible = "simple-bus"; 774 775 gcc: clock-controller@100000 { 776 compatible = "qcom,gcc-sm6350"; 777 reg = <0 0x00100000 0 0x1f0000>; 778 #clock-cells = <1>; 779 #reset-cells = <1>; 780 #power-domain-cells = <1>; 781 clock-names = "bi_tcxo", 782 "bi_tcxo_ao", 783 "sleep_clk"; 784 clocks = <&rpmhcc RPMH_CXO_CLK>, 785 <&rpmhcc RPMH_CXO_CLK_A>, 786 <&sleep_clk>; 787 }; 788 789 ipcc: mailbox@408000 { 790 compatible = "qcom,sm6350-ipcc", "qcom,ipcc"; 791 reg = <0 0x00408000 0 0x1000>; 792 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 793 interrupt-controller; 794 #interrupt-cells = <3>; 795 #mbox-cells = <2>; 796 }; 797 798 rng: rng@793000 { 799 compatible = "qcom,prng-ee"; 800 reg = <0 0x00793000 0 0x1000>; 801 clocks = <&gcc GCC_PRNG_AHB_CLK>; 802 clock-names = "core"; 803 }; 804 805 sdhc_1: mmc@7c4000 { 806 compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5"; 807 reg = <0 0x007c4000 0 0x1000>, 808 <0 0x007c5000 0 0x1000>, 809 <0 0x007c8000 0 0x8000>; 810 reg-names = "hc", "cqhci", "ice"; 811 812 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, 813 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>; 814 interrupt-names = "hc_irq", "pwr_irq"; 815 iommus = <&apps_smmu 0x60 0x0>; 816 817 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 818 <&gcc GCC_SDCC1_APPS_CLK>, 819 <&rpmhcc RPMH_CXO_CLK>; 820 clock-names = "iface", "core", "xo"; 821 resets = <&gcc GCC_SDCC1_BCR>; 822 qcom,dll-config = <0x000f642c>; 823 qcom,ddr-config = <0x80040868>; 824 power-domains = <&rpmhpd SM6350_CX>; 825 operating-points-v2 = <&sdhc1_opp_table>; 826 bus-width = <8>; 827 non-removable; 828 supports-cqe; 829 830 status = "disabled"; 831 832 sdhc1_opp_table: opp-table { 833 compatible = "operating-points-v2"; 834 835 opp-19200000 { 836 opp-hz = /bits/ 64 <19200000>; 837 required-opps = <&rpmhpd_opp_min_svs>; 838 }; 839 840 opp-100000000 { 841 opp-hz = /bits/ 64 <100000000>; 842 required-opps = <&rpmhpd_opp_low_svs>; 843 }; 844 845 opp-384000000 { 846 opp-hz = /bits/ 64 <384000000>; 847 required-opps = <&rpmhpd_opp_svs_l1>; 848 }; 849 }; 850 }; 851 852 gpi_dma0: dma-controller@800000 { 853 compatible = "qcom,sm6350-gpi-dma"; 854 reg = <0 0x00800000 0 0x60000>; 855 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 856 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 857 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 858 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 859 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 860 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 861 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 862 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 863 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 864 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>; 865 dma-channels = <10>; 866 dma-channel-mask = <0x1f>; 867 iommus = <&apps_smmu 0x56 0x0>; 868 #dma-cells = <3>; 869 status = "disabled"; 870 }; 871 872 qupv3_id_0: geniqup@8c0000 { 873 compatible = "qcom,geni-se-qup"; 874 reg = <0x0 0x008c0000 0x0 0x2000>; 875 clock-names = "m-ahb", "s-ahb"; 876 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 877 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 878 #address-cells = <2>; 879 #size-cells = <2>; 880 iommus = <&apps_smmu 0x43 0x0>; 881 ranges; 882 status = "disabled"; 883 884 i2c0: i2c@880000 { 885 compatible = "qcom,geni-i2c"; 886 reg = <0 0x00880000 0 0x4000>; 887 clock-names = "se"; 888 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 889 pinctrl-names = "default"; 890 pinctrl-0 = <&qup_i2c0_default>; 891 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 892 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 893 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 894 dma-names = "tx", "rx"; 895 #address-cells = <1>; 896 #size-cells = <0>; 897 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 898 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 899 <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>; 900 interconnect-names = "qup-core", "qup-config", "qup-memory"; 901 status = "disabled"; 902 }; 903 904 uart1: serial@884000 { 905 compatible = "qcom,geni-uart"; 906 reg = <0 0x00884000 0 0x4000>; 907 clock-names = "se"; 908 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 909 pinctrl-names = "default"; 910 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; 911 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 912 power-domains = <&rpmhpd SM6350_CX>; 913 operating-points-v2 = <&qup_opp_table>; 914 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 915 <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>; 916 interconnect-names = "qup-core", "qup-config"; 917 status = "disabled"; 918 }; 919 920 i2c2: i2c@888000 { 921 compatible = "qcom,geni-i2c"; 922 reg = <0 0x00888000 0 0x4000>; 923 clock-names = "se"; 924 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 925 pinctrl-names = "default"; 926 pinctrl-0 = <&qup_i2c2_default>; 927 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 928 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 929 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 930 dma-names = "tx", "rx"; 931 #address-cells = <1>; 932 #size-cells = <0>; 933 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 934 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 935 <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>; 936 interconnect-names = "qup-core", "qup-config", "qup-memory"; 937 status = "disabled"; 938 }; 939 }; 940 941 gpi_dma1: dma-controller@900000 { 942 compatible = "qcom,sm6350-gpi-dma"; 943 reg = <0 0x00900000 0 0x60000>; 944 interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH>, 945 <GIC_SPI 646 IRQ_TYPE_LEVEL_HIGH>, 946 <GIC_SPI 647 IRQ_TYPE_LEVEL_HIGH>, 947 <GIC_SPI 648 IRQ_TYPE_LEVEL_HIGH>, 948 <GIC_SPI 649 IRQ_TYPE_LEVEL_HIGH>, 949 <GIC_SPI 650 IRQ_TYPE_LEVEL_HIGH>, 950 <GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH>, 951 <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 952 <GIC_SPI 653 IRQ_TYPE_LEVEL_HIGH>, 953 <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH>; 954 dma-channels = <10>; 955 dma-channel-mask = <0x3f>; 956 iommus = <&apps_smmu 0x4d6 0x0>; 957 #dma-cells = <3>; 958 status = "disabled"; 959 }; 960 961 qupv3_id_1: geniqup@9c0000 { 962 compatible = "qcom,geni-se-qup"; 963 reg = <0x0 0x009c0000 0x0 0x2000>; 964 clock-names = "m-ahb", "s-ahb"; 965 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 966 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 967 #address-cells = <2>; 968 #size-cells = <2>; 969 iommus = <&apps_smmu 0x4c3 0x0>; 970 ranges; 971 status = "disabled"; 972 973 i2c6: i2c@980000 { 974 compatible = "qcom,geni-i2c"; 975 reg = <0 0x00980000 0 0x4000>; 976 clock-names = "se"; 977 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 978 pinctrl-names = "default"; 979 pinctrl-0 = <&qup_i2c6_default>; 980 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 981 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 982 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 983 dma-names = "tx", "rx"; 984 #address-cells = <1>; 985 #size-cells = <0>; 986 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 987 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 988 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; 989 interconnect-names = "qup-core", "qup-config", "qup-memory"; 990 status = "disabled"; 991 }; 992 993 i2c7: i2c@984000 { 994 compatible = "qcom,geni-i2c"; 995 reg = <0 0x00984000 0 0x4000>; 996 clock-names = "se"; 997 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 998 pinctrl-names = "default"; 999 pinctrl-0 = <&qup_i2c7_default>; 1000 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1001 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1002 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1003 dma-names = "tx", "rx"; 1004 #address-cells = <1>; 1005 #size-cells = <0>; 1006 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1007 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1008 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; 1009 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1010 status = "disabled"; 1011 }; 1012 1013 i2c8: i2c@988000 { 1014 compatible = "qcom,geni-i2c"; 1015 reg = <0 0x00988000 0 0x4000>; 1016 clock-names = "se"; 1017 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1018 pinctrl-names = "default"; 1019 pinctrl-0 = <&qup_i2c8_default>; 1020 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1021 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1022 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1023 dma-names = "tx", "rx"; 1024 #address-cells = <1>; 1025 #size-cells = <0>; 1026 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1027 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1028 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; 1029 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1030 status = "disabled"; 1031 }; 1032 1033 uart9: serial@98c000 { 1034 compatible = "qcom,geni-debug-uart"; 1035 reg = <0 0x0098c000 0 0x4000>; 1036 clock-names = "se"; 1037 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1038 pinctrl-names = "default"; 1039 pinctrl-0 = <&qup_uart9_default>; 1040 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1041 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1042 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1043 interconnect-names = "qup-core", "qup-config"; 1044 status = "disabled"; 1045 }; 1046 1047 i2c10: i2c@990000 { 1048 compatible = "qcom,geni-i2c"; 1049 reg = <0 0x00990000 0 0x4000>; 1050 clock-names = "se"; 1051 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1052 pinctrl-names = "default"; 1053 pinctrl-0 = <&qup_i2c10_default>; 1054 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1055 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1056 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1057 dma-names = "tx", "rx"; 1058 #address-cells = <1>; 1059 #size-cells = <0>; 1060 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1061 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1062 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; 1063 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1064 status = "disabled"; 1065 }; 1066 }; 1067 1068 config_noc: interconnect@1500000 { 1069 compatible = "qcom,sm6350-config-noc"; 1070 reg = <0 0x01500000 0 0x28000>; 1071 #interconnect-cells = <2>; 1072 qcom,bcm-voters = <&apps_bcm_voter>; 1073 }; 1074 1075 system_noc: interconnect@1620000 { 1076 compatible = "qcom,sm6350-system-noc"; 1077 reg = <0 0x01620000 0 0x17080>; 1078 #interconnect-cells = <2>; 1079 qcom,bcm-voters = <&apps_bcm_voter>; 1080 1081 clk_virt: interconnect-clk-virt { 1082 compatible = "qcom,sm6350-clk-virt"; 1083 #interconnect-cells = <2>; 1084 qcom,bcm-voters = <&apps_bcm_voter>; 1085 }; 1086 }; 1087 1088 aggre1_noc: interconnect@16e0000 { 1089 compatible = "qcom,sm6350-aggre1-noc"; 1090 reg = <0 0x016e0000 0 0x15080>; 1091 #interconnect-cells = <2>; 1092 qcom,bcm-voters = <&apps_bcm_voter>; 1093 }; 1094 1095 aggre2_noc: interconnect@1700000 { 1096 compatible = "qcom,sm6350-aggre2-noc"; 1097 reg = <0 0x01700000 0 0x1f880>; 1098 #interconnect-cells = <2>; 1099 qcom,bcm-voters = <&apps_bcm_voter>; 1100 1101 compute_noc: interconnect-compute-noc { 1102 compatible = "qcom,sm6350-compute-noc"; 1103 #interconnect-cells = <2>; 1104 qcom,bcm-voters = <&apps_bcm_voter>; 1105 }; 1106 }; 1107 1108 mmss_noc: interconnect@1740000 { 1109 compatible = "qcom,sm6350-mmss-noc"; 1110 reg = <0 0x01740000 0 0x1c100>; 1111 #interconnect-cells = <2>; 1112 qcom,bcm-voters = <&apps_bcm_voter>; 1113 }; 1114 1115 ufs_mem_hc: ufs@1d84000 { 1116 compatible = "qcom,sm6350-ufshc", "qcom,ufshc", 1117 "jedec,ufs-2.0"; 1118 reg = <0 0x01d84000 0 0x3000>, 1119 <0 0x01d90000 0 0x8000>; 1120 reg-names = "std", "ice"; 1121 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1122 phys = <&ufs_mem_phy_lanes>; 1123 phy-names = "ufsphy"; 1124 lanes-per-direction = <2>; 1125 #reset-cells = <1>; 1126 resets = <&gcc GCC_UFS_PHY_BCR>; 1127 reset-names = "rst"; 1128 1129 power-domains = <&gcc UFS_PHY_GDSC>; 1130 1131 iommus = <&apps_smmu 0x80 0x0>; 1132 1133 clock-names = "core_clk", 1134 "bus_aggr_clk", 1135 "iface_clk", 1136 "core_clk_unipro", 1137 "ref_clk", 1138 "tx_lane0_sync_clk", 1139 "rx_lane0_sync_clk", 1140 "rx_lane1_sync_clk", 1141 "ice_core_clk"; 1142 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 1143 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1144 <&gcc GCC_UFS_PHY_AHB_CLK>, 1145 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1146 <&rpmhcc RPMH_QLINK_CLK>, 1147 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1148 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1149 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 1150 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 1151 freq-table-hz = 1152 <50000000 200000000>, 1153 <0 0>, 1154 <0 0>, 1155 <37500000 150000000>, 1156 <75000000 300000000>, 1157 <0 0>, 1158 <0 0>, 1159 <0 0>, 1160 <0 0>; 1161 1162 status = "disabled"; 1163 }; 1164 1165 ufs_mem_phy: phy@1d87000 { 1166 compatible = "qcom,sm6350-qmp-ufs-phy"; 1167 reg = <0 0x01d87000 0 0x18c>; 1168 #address-cells = <2>; 1169 #size-cells = <2>; 1170 ranges; 1171 1172 clock-names = "ref", 1173 "ref_aux"; 1174 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, 1175 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 1176 1177 resets = <&ufs_mem_hc 0>; 1178 reset-names = "ufsphy"; 1179 1180 status = "disabled"; 1181 1182 ufs_mem_phy_lanes: phy@1d87400 { 1183 reg = <0 0x01d87400 0 0x128>, 1184 <0 0x01d87600 0 0x1fc>, 1185 <0 0x01d87c00 0 0x1dc>, 1186 <0 0x01d87800 0 0x128>, 1187 <0 0x01d87a00 0 0x1fc>; 1188 #phy-cells = <0>; 1189 }; 1190 }; 1191 1192 ipa: ipa@1e40000 { 1193 compatible = "qcom,sm6350-ipa"; 1194 1195 iommus = <&apps_smmu 0x440 0x0>, 1196 <&apps_smmu 0x442 0x0>; 1197 reg = <0 0x01e40000 0 0x8000>, 1198 <0 0x01e50000 0 0x3000>, 1199 <0 0x01e04000 0 0x23000>; 1200 reg-names = "ipa-reg", 1201 "ipa-shared", 1202 "gsi"; 1203 1204 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>, 1205 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1206 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1207 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1208 interrupt-names = "ipa", 1209 "gsi", 1210 "ipa-clock-query", 1211 "ipa-setup-ready"; 1212 1213 clocks = <&rpmhcc RPMH_IPA_CLK>; 1214 clock-names = "core"; 1215 1216 interconnects = <&aggre2_noc MASTER_IPA 0 &clk_virt SLAVE_EBI_CH0 0>, 1217 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_OCIMEM 0>, 1218 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_IPA_CFG 0>; 1219 interconnect-names = "memory", "imem", "config"; 1220 1221 qcom,smem-states = <&ipa_smp2p_out 0>, 1222 <&ipa_smp2p_out 1>; 1223 qcom,smem-state-names = "ipa-clock-enabled-valid", 1224 "ipa-clock-enabled"; 1225 1226 status = "disabled"; 1227 }; 1228 1229 tcsr_mutex: hwlock@1f40000 { 1230 compatible = "qcom,tcsr-mutex"; 1231 reg = <0x0 0x01f40000 0x0 0x40000>; 1232 #hwlock-cells = <1>; 1233 }; 1234 1235 adsp: remoteproc@3000000 { 1236 compatible = "qcom,sm6350-adsp-pas"; 1237 reg = <0 0x03000000 0 0x100>; 1238 1239 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 1240 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 1241 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 1242 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 1243 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 1244 interrupt-names = "wdog", "fatal", "ready", 1245 "handover", "stop-ack"; 1246 1247 clocks = <&rpmhcc RPMH_CXO_CLK>; 1248 clock-names = "xo"; 1249 1250 power-domains = <&rpmhpd SM6350_LCX>, 1251 <&rpmhpd SM6350_LMX>; 1252 power-domain-names = "lcx", "lmx"; 1253 1254 memory-region = <&pil_adsp_mem>; 1255 1256 qcom,qmp = <&aoss_qmp>; 1257 1258 qcom,smem-states = <&smp2p_adsp_out 0>; 1259 qcom,smem-state-names = "stop"; 1260 1261 status = "disabled"; 1262 1263 glink-edge { 1264 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 1265 IPCC_MPROC_SIGNAL_GLINK_QMP 1266 IRQ_TYPE_EDGE_RISING>; 1267 mboxes = <&ipcc IPCC_CLIENT_LPASS 1268 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1269 1270 label = "lpass"; 1271 qcom,remote-pid = <2>; 1272 1273 fastrpc { 1274 compatible = "qcom,fastrpc"; 1275 qcom,glink-channels = "fastrpcglink-apps-dsp"; 1276 label = "adsp"; 1277 #address-cells = <1>; 1278 #size-cells = <0>; 1279 1280 compute-cb@3 { 1281 compatible = "qcom,fastrpc-compute-cb"; 1282 reg = <3>; 1283 iommus = <&apps_smmu 0x1003 0x0>; 1284 }; 1285 1286 compute-cb@4 { 1287 compatible = "qcom,fastrpc-compute-cb"; 1288 reg = <4>; 1289 iommus = <&apps_smmu 0x1004 0x0>; 1290 }; 1291 1292 compute-cb@5 { 1293 compatible = "qcom,fastrpc-compute-cb"; 1294 reg = <5>; 1295 iommus = <&apps_smmu 0x1005 0x0>; 1296 qcom,nsessions = <5>; 1297 }; 1298 }; 1299 }; 1300 }; 1301 1302 mpss: remoteproc@4080000 { 1303 compatible = "qcom,sm6350-mpss-pas"; 1304 reg = <0x0 0x04080000 0x0 0x4040>; 1305 1306 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_EDGE_RISING>, 1307 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1308 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1309 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1310 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1311 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1312 interrupt-names = "wdog", "fatal", "ready", "handover", 1313 "stop-ack", "shutdown-ack"; 1314 1315 clocks = <&rpmhcc RPMH_CXO_CLK>; 1316 clock-names = "xo"; 1317 1318 power-domains = <&rpmhpd SM6350_CX>, 1319 <&rpmhpd SM6350_MSS>; 1320 power-domain-names = "cx", "mss"; 1321 1322 memory-region = <&pil_modem_mem>; 1323 1324 qcom,qmp = <&aoss_qmp>; 1325 1326 qcom,smem-states = <&modem_smp2p_out 0>; 1327 qcom,smem-state-names = "stop"; 1328 1329 status = "disabled"; 1330 1331 glink-edge { 1332 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 1333 IPCC_MPROC_SIGNAL_GLINK_QMP 1334 IRQ_TYPE_EDGE_RISING>; 1335 mboxes = <&ipcc IPCC_CLIENT_MPSS 1336 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1337 label = "modem"; 1338 qcom,remote-pid = <1>; 1339 }; 1340 }; 1341 1342 cdsp: remoteproc@8300000 { 1343 compatible = "qcom,sm6350-cdsp-pas"; 1344 reg = <0 0x08300000 0 0x10000>; 1345 1346 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, 1347 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 1348 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 1349 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 1350 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 1351 interrupt-names = "wdog", "fatal", "ready", 1352 "handover", "stop-ack"; 1353 1354 clocks = <&rpmhcc RPMH_CXO_CLK>; 1355 clock-names = "xo"; 1356 1357 power-domains = <&rpmhpd SM6350_CX>, 1358 <&rpmhpd SM6350_MX>; 1359 power-domain-names = "cx", "mx"; 1360 1361 memory-region = <&pil_cdsp_mem>; 1362 1363 qcom,qmp = <&aoss_qmp>; 1364 1365 qcom,smem-states = <&smp2p_cdsp_out 0>; 1366 qcom,smem-state-names = "stop"; 1367 1368 status = "disabled"; 1369 1370 glink-edge { 1371 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 1372 IPCC_MPROC_SIGNAL_GLINK_QMP 1373 IRQ_TYPE_EDGE_RISING>; 1374 mboxes = <&ipcc IPCC_CLIENT_CDSP 1375 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1376 1377 label = "cdsp"; 1378 qcom,remote-pid = <5>; 1379 1380 fastrpc { 1381 compatible = "qcom,fastrpc"; 1382 qcom,glink-channels = "fastrpcglink-apps-dsp"; 1383 label = "cdsp"; 1384 #address-cells = <1>; 1385 #size-cells = <0>; 1386 1387 compute-cb@1 { 1388 compatible = "qcom,fastrpc-compute-cb"; 1389 reg = <1>; 1390 iommus = <&apps_smmu 0x1401 0x20>; 1391 }; 1392 1393 compute-cb@2 { 1394 compatible = "qcom,fastrpc-compute-cb"; 1395 reg = <2>; 1396 iommus = <&apps_smmu 0x1402 0x20>; 1397 }; 1398 1399 compute-cb@3 { 1400 compatible = "qcom,fastrpc-compute-cb"; 1401 reg = <3>; 1402 iommus = <&apps_smmu 0x1403 0x20>; 1403 }; 1404 1405 compute-cb@4 { 1406 compatible = "qcom,fastrpc-compute-cb"; 1407 reg = <4>; 1408 iommus = <&apps_smmu 0x1404 0x20>; 1409 }; 1410 1411 compute-cb@5 { 1412 compatible = "qcom,fastrpc-compute-cb"; 1413 reg = <5>; 1414 iommus = <&apps_smmu 0x1405 0x20>; 1415 }; 1416 1417 compute-cb@6 { 1418 compatible = "qcom,fastrpc-compute-cb"; 1419 reg = <6>; 1420 iommus = <&apps_smmu 0x1406 0x20>; 1421 }; 1422 1423 compute-cb@7 { 1424 compatible = "qcom,fastrpc-compute-cb"; 1425 reg = <7>; 1426 iommus = <&apps_smmu 0x1407 0x20>; 1427 }; 1428 1429 compute-cb@8 { 1430 compatible = "qcom,fastrpc-compute-cb"; 1431 reg = <8>; 1432 iommus = <&apps_smmu 0x1408 0x20>; 1433 }; 1434 1435 /* note: secure cb9 in downstream */ 1436 }; 1437 }; 1438 }; 1439 1440 sdhc_2: mmc@8804000 { 1441 compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5"; 1442 reg = <0 0x08804000 0 0x1000>; 1443 1444 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 1445 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 1446 interrupt-names = "hc_irq", "pwr_irq"; 1447 iommus = <&apps_smmu 0x560 0x0>; 1448 1449 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1450 <&gcc GCC_SDCC2_APPS_CLK>, 1451 <&rpmhcc RPMH_CXO_CLK>; 1452 clock-names = "iface", "core", "xo"; 1453 resets = <&gcc GCC_SDCC2_BCR>; 1454 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &clk_virt SLAVE_EBI_CH0 0>, 1455 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_SDCC_2 0>; 1456 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 1457 1458 pinctrl-0 = <&sdc2_on_state>; 1459 pinctrl-1 = <&sdc2_off_state>; 1460 pinctrl-names = "default", "sleep"; 1461 1462 qcom,dll-config = <0x0007642c>; 1463 qcom,ddr-config = <0x80040868>; 1464 power-domains = <&rpmhpd SM6350_CX>; 1465 operating-points-v2 = <&sdhc2_opp_table>; 1466 bus-width = <4>; 1467 1468 status = "disabled"; 1469 1470 sdhc2_opp_table: opp-table { 1471 compatible = "operating-points-v2"; 1472 1473 opp-100000000 { 1474 opp-hz = /bits/ 64 <100000000>; 1475 required-opps = <&rpmhpd_opp_svs_l1>; 1476 opp-peak-kBps = <790000 131000>; 1477 opp-avg-kBps = <50000 50000>; 1478 }; 1479 1480 opp-202000000 { 1481 opp-hz = /bits/ 64 <202000000>; 1482 required-opps = <&rpmhpd_opp_nom>; 1483 opp-peak-kBps = <3190000 294000>; 1484 opp-avg-kBps = <261438 300000>; 1485 }; 1486 }; 1487 }; 1488 1489 usb_1_hsphy: phy@88e3000 { 1490 compatible = "qcom,sm6350-qusb2-phy", "qcom,qusb2-v2-phy"; 1491 reg = <0 0x088e3000 0 0x400>; 1492 status = "disabled"; 1493 #phy-cells = <0>; 1494 1495 clocks = <&xo_board>, <&rpmhcc RPMH_CXO_CLK>; 1496 clock-names = "cfg_ahb", "ref"; 1497 1498 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1499 }; 1500 1501 usb_1_qmpphy: phy@88e8000 { 1502 compatible = "qcom,sm6350-qmp-usb3-dp-phy"; 1503 reg = <0 0x088e8000 0 0x3000>; 1504 1505 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 1506 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 1507 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 1508 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 1509 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 1510 1511 power-domains = <&gcc USB30_PRIM_GDSC>; 1512 1513 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 1514 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 1515 reset-names = "phy", "common"; 1516 1517 #clock-cells = <1>; 1518 #phy-cells = <1>; 1519 1520 status = "disabled"; 1521 }; 1522 1523 dc_noc: interconnect@9160000 { 1524 compatible = "qcom,sm6350-dc-noc"; 1525 reg = <0 0x09160000 0 0x3200>; 1526 #interconnect-cells = <2>; 1527 qcom,bcm-voters = <&apps_bcm_voter>; 1528 }; 1529 1530 system-cache-controller@9200000 { 1531 compatible = "qcom,sm6350-llcc"; 1532 reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; 1533 reg-names = "llcc0_base", "llcc_broadcast_base"; 1534 }; 1535 1536 gem_noc: interconnect@9680000 { 1537 compatible = "qcom,sm6350-gem-noc"; 1538 reg = <0 0x09680000 0 0x3e200>; 1539 #interconnect-cells = <2>; 1540 qcom,bcm-voters = <&apps_bcm_voter>; 1541 }; 1542 1543 npu_noc: interconnect@9990000 { 1544 compatible = "qcom,sm6350-npu-noc"; 1545 reg = <0 0x09990000 0 0x1600>; 1546 #interconnect-cells = <2>; 1547 qcom,bcm-voters = <&apps_bcm_voter>; 1548 }; 1549 1550 usb_1: usb@a6f8800 { 1551 compatible = "qcom,sm6350-dwc3", "qcom,dwc3"; 1552 reg = <0 0x0a6f8800 0 0x400>; 1553 status = "disabled"; 1554 #address-cells = <2>; 1555 #size-cells = <2>; 1556 ranges; 1557 1558 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1559 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1560 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 1561 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1562 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 1563 clock-names = "cfg_noc", 1564 "core", 1565 "iface", 1566 "sleep", 1567 "mock_utmi"; 1568 1569 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1570 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, 1571 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 1572 <&pdc 14 IRQ_TYPE_EDGE_BOTH>; 1573 1574 interrupt-names = "hs_phy_irq", "ss_phy_irq", 1575 "dm_hs_phy_irq", "dp_hs_phy_irq"; 1576 1577 power-domains = <&gcc USB30_PRIM_GDSC>; 1578 1579 resets = <&gcc GCC_USB30_PRIM_BCR>; 1580 1581 interconnects = <&aggre2_noc MASTER_USB3 0 &clk_virt SLAVE_EBI_CH0 0>, 1582 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>; 1583 interconnect-names = "usb-ddr", "apps-usb"; 1584 1585 usb_1_dwc3: usb@a600000 { 1586 compatible = "snps,dwc3"; 1587 reg = <0 0x0a600000 0 0xcd00>; 1588 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 1589 iommus = <&apps_smmu 0x540 0x0>; 1590 snps,dis_u2_susphy_quirk; 1591 snps,dis_enblslpm_quirk; 1592 snps,has-lpm-erratum; 1593 snps,hird-threshold = /bits/ 8 <0x10>; 1594 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 1595 phy-names = "usb2-phy", "usb3-phy"; 1596 }; 1597 }; 1598 1599 cci0: cci@ac4a000 { 1600 compatible = "qcom,sm6350-cci", "qcom,msm8996-cci"; 1601 reg = <0 0x0ac4a000 0 0x1000>; 1602 interrupts = <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>; 1603 power-domains = <&camcc TITAN_TOP_GDSC>; 1604 1605 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 1606 <&camcc CAMCC_SOC_AHB_CLK>, 1607 <&camcc CAMCC_SLOW_AHB_CLK_SRC>, 1608 <&camcc CAMCC_CPAS_AHB_CLK>, 1609 <&camcc CAMCC_CCI_0_CLK>, 1610 <&camcc CAMCC_CCI_0_CLK_SRC>; 1611 clock-names = "camnoc_axi", 1612 "soc_ahb", 1613 "slow_ahb_src", 1614 "cpas_ahb", 1615 "cci", 1616 "cci_src"; 1617 1618 assigned-clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 1619 <&camcc CAMCC_CCI_0_CLK>; 1620 assigned-clock-rates = <80000000>, <37500000>; 1621 1622 pinctrl-0 = <&cci0_default &cci1_default>; 1623 pinctrl-1 = <&cci0_sleep &cci1_sleep>; 1624 pinctrl-names = "default", "sleep"; 1625 1626 #address-cells = <1>; 1627 #size-cells = <0>; 1628 1629 status = "disabled"; 1630 1631 cci0_i2c0: i2c-bus@0 { 1632 reg = <0>; 1633 clock-frequency = <1000000>; 1634 #address-cells = <1>; 1635 #size-cells = <0>; 1636 }; 1637 1638 cci0_i2c1: i2c-bus@1 { 1639 reg = <1>; 1640 clock-frequency = <1000000>; 1641 #address-cells = <1>; 1642 #size-cells = <0>; 1643 }; 1644 }; 1645 1646 cci1: cci@ac4b000 { 1647 compatible = "qcom,sm6350-cci", "qcom,msm8996-cci"; 1648 reg = <0 0x0ac4b000 0 0x1000>; 1649 interrupts = <GIC_SPI 462 IRQ_TYPE_EDGE_RISING>; 1650 power-domains = <&camcc TITAN_TOP_GDSC>; 1651 1652 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 1653 <&camcc CAMCC_SOC_AHB_CLK>, 1654 <&camcc CAMCC_SLOW_AHB_CLK_SRC>, 1655 <&camcc CAMCC_CPAS_AHB_CLK>, 1656 <&camcc CAMCC_CCI_1_CLK>, 1657 <&camcc CAMCC_CCI_1_CLK_SRC>; 1658 clock-names = "camnoc_axi", 1659 "soc_ahb", 1660 "slow_ahb_src", 1661 "cpas_ahb", 1662 "cci", 1663 "cci_src"; 1664 1665 assigned-clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 1666 <&camcc CAMCC_CCI_1_CLK>; 1667 assigned-clock-rates = <80000000>, <37500000>; 1668 1669 pinctrl-0 = <&cci2_default>; 1670 pinctrl-1 = <&cci2_sleep>; 1671 pinctrl-names = "default", "sleep"; 1672 1673 #address-cells = <1>; 1674 #size-cells = <0>; 1675 1676 status = "disabled"; 1677 1678 cci1_i2c0: i2c-bus@0 { 1679 reg = <0>; 1680 clock-frequency = <1000000>; 1681 #address-cells = <1>; 1682 #size-cells = <0>; 1683 }; 1684 1685 /* SM6350 seems to have cci1_i2c1 on gpio2 & gpio3 but unused downstream */ 1686 }; 1687 1688 camcc: clock-controller@ad00000 { 1689 compatible = "qcom,sm6350-camcc"; 1690 reg = <0 0x0ad00000 0 0x16000>; 1691 clocks = <&rpmhcc RPMH_CXO_CLK>; 1692 #clock-cells = <1>; 1693 #reset-cells = <1>; 1694 #power-domain-cells = <1>; 1695 }; 1696 1697 pdc: interrupt-controller@b220000 { 1698 compatible = "qcom,sm6350-pdc", "qcom,pdc"; 1699 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x64>; 1700 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 1701 <125 63 1>, <126 655 12>, <138 139 15>; 1702 #interrupt-cells = <2>; 1703 interrupt-parent = <&intc>; 1704 interrupt-controller; 1705 }; 1706 1707 tsens0: thermal-sensor@c263000 { 1708 compatible = "qcom,sm6350-tsens", "qcom,tsens-v2"; 1709 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 1710 <0 0x0c222000 0 0x8>; /* SROT */ 1711 #qcom,sensors = <16>; 1712 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 1713 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; 1714 interrupt-names = "uplow", "critical"; 1715 #thermal-sensor-cells = <1>; 1716 }; 1717 1718 tsens1: thermal-sensor@c265000 { 1719 compatible = "qcom,sm6350-tsens", "qcom,tsens-v2"; 1720 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 1721 <0 0x0c223000 0 0x8>; /* SROT */ 1722 #qcom,sensors = <16>; 1723 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 1724 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; 1725 interrupt-names = "uplow", "critical"; 1726 #thermal-sensor-cells = <1>; 1727 }; 1728 1729 aoss_qmp: power-management@c300000 { 1730 compatible = "qcom,sm6350-aoss-qmp", "qcom,aoss-qmp"; 1731 reg = <0 0x0c300000 0 0x1000>; 1732 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 1733 IRQ_TYPE_EDGE_RISING>; 1734 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 1735 1736 #clock-cells = <0>; 1737 }; 1738 1739 spmi_bus: spmi@c440000 { 1740 compatible = "qcom,spmi-pmic-arb"; 1741 reg = <0 0x0c440000 0 0x1100>, 1742 <0 0x0c600000 0 0x2000000>, 1743 <0 0x0e600000 0 0x100000>, 1744 <0 0x0e700000 0 0xa0000>, 1745 <0 0x0c40a000 0 0x26000>; 1746 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1747 interrupt-names = "periph_irq"; 1748 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 1749 qcom,ee = <0>; 1750 qcom,channel = <0>; 1751 #address-cells = <2>; 1752 #size-cells = <0>; 1753 interrupt-controller; 1754 #interrupt-cells = <4>; 1755 }; 1756 1757 tlmm: pinctrl@f100000 { 1758 compatible = "qcom,sm6350-tlmm"; 1759 reg = <0 0x0f100000 0 0x300000>; 1760 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 1761 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 1762 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 1763 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 1764 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 1765 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 1766 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 1767 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 1768 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; 1769 gpio-controller; 1770 #gpio-cells = <2>; 1771 interrupt-controller; 1772 #interrupt-cells = <2>; 1773 gpio-ranges = <&tlmm 0 0 157>; 1774 1775 cci0_default: cci0-default-state { 1776 pins = "gpio39", "gpio40"; 1777 function = "cci_i2c"; 1778 drive-strength = <2>; 1779 bias-pull-up; 1780 }; 1781 1782 cci0_sleep: cci0-sleep-state { 1783 pins = "gpio39", "gpio40"; 1784 function = "cci_i2c"; 1785 drive-strength = <2>; 1786 bias-pull-down; 1787 }; 1788 1789 cci1_default: cci1-default-state { 1790 pins = "gpio41", "gpio42"; 1791 function = "cci_i2c"; 1792 drive-strength = <2>; 1793 bias-pull-up; 1794 }; 1795 1796 cci1_sleep: cci1-sleep-state { 1797 pins = "gpio41", "gpio42"; 1798 function = "cci_i2c"; 1799 drive-strength = <2>; 1800 bias-pull-down; 1801 }; 1802 1803 cci2_default: cci2-default-state { 1804 pins = "gpio43", "gpio44"; 1805 function = "cci_i2c"; 1806 drive-strength = <2>; 1807 bias-pull-up; 1808 }; 1809 1810 cci2_sleep: cci2-sleep-state { 1811 pins = "gpio43", "gpio44"; 1812 function = "cci_i2c"; 1813 drive-strength = <2>; 1814 bias-pull-down; 1815 }; 1816 1817 sdc2_off_state: sdc2-off-state { 1818 clk-pins { 1819 pins = "sdc2_clk"; 1820 drive-strength = <2>; 1821 bias-disable; 1822 }; 1823 1824 cmd-pins { 1825 pins = "sdc2_cmd"; 1826 drive-strength = <2>; 1827 bias-pull-up; 1828 }; 1829 1830 data-pins { 1831 pins = "sdc2_data"; 1832 drive-strength = <2>; 1833 bias-pull-up; 1834 }; 1835 }; 1836 1837 sdc2_on_state: sdc2-on-state { 1838 clk-pins { 1839 pins = "sdc2_clk"; 1840 drive-strength = <16>; 1841 bias-disable; 1842 }; 1843 1844 cmd-pins { 1845 pins = "sdc2_cmd"; 1846 drive-strength = <10>; 1847 bias-pull-up; 1848 }; 1849 1850 data-pins { 1851 pins = "sdc2_data"; 1852 drive-strength = <10>; 1853 bias-pull-up; 1854 }; 1855 }; 1856 1857 qup_uart9_default: qup-uart9-default-state { 1858 pins = "gpio25", "gpio26"; 1859 function = "qup13_f2"; 1860 drive-strength = <2>; 1861 bias-disable; 1862 }; 1863 1864 qup_i2c0_default: qup-i2c0-default-state { 1865 pins = "gpio0", "gpio1"; 1866 function = "qup00"; 1867 drive-strength = <2>; 1868 bias-pull-up; 1869 }; 1870 1871 qup_i2c2_default: qup-i2c2-default-state { 1872 pins = "gpio45", "gpio46"; 1873 function = "qup02"; 1874 drive-strength = <2>; 1875 bias-pull-up; 1876 }; 1877 1878 qup_i2c6_default: qup-i2c6-default-state { 1879 pins = "gpio13", "gpio14"; 1880 function = "qup10"; 1881 drive-strength = <2>; 1882 bias-pull-up; 1883 }; 1884 1885 qup_i2c7_default: qup-i2c7-default-state { 1886 pins = "gpio27", "gpio28"; 1887 function = "qup11"; 1888 drive-strength = <2>; 1889 bias-pull-up; 1890 }; 1891 1892 qup_i2c8_default: qup-i2c8-default-state { 1893 pins = "gpio19", "gpio20"; 1894 function = "qup12"; 1895 drive-strength = <2>; 1896 bias-pull-up; 1897 }; 1898 1899 qup_i2c10_default: qup-i2c10-default-state { 1900 pins = "gpio4", "gpio5"; 1901 function = "qup14"; 1902 drive-strength = <2>; 1903 bias-pull-up; 1904 }; 1905 1906 qup_uart1_cts: qup-uart1-cts-default-state { 1907 pins = "gpio61"; 1908 function = "qup01"; 1909 drive-strength = <2>; 1910 bias-disable; 1911 }; 1912 1913 qup_uart1_rts: qup-uart1-rts-default-state { 1914 pins = "gpio62"; 1915 function = "qup01"; 1916 drive-strength = <2>; 1917 bias-pull-down; 1918 }; 1919 1920 qup_uart1_rx: qup-uart1-rx-default-state { 1921 pins = "gpio64"; 1922 function = "qup01"; 1923 drive-strength = <2>; 1924 bias-disable; 1925 }; 1926 1927 qup_uart1_tx: qup-uart1-tx-default-state { 1928 pins = "gpio63"; 1929 function = "qup01"; 1930 drive-strength = <2>; 1931 bias-pull-up; 1932 }; 1933 }; 1934 1935 apps_smmu: iommu@15000000 { 1936 compatible = "qcom,sm6350-smmu-500", "arm,mmu-500"; 1937 reg = <0 0x15000000 0 0x100000>; 1938 #iommu-cells = <2>; 1939 #global-interrupts = <1>; 1940 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 1941 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 1942 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1943 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1944 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1945 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1946 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1947 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1948 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1949 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1950 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1951 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1952 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1953 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1954 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1955 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1956 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1957 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1958 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1959 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1960 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1961 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1962 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1963 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1964 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1965 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 1966 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 1967 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 1968 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 1969 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 1970 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 1971 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 1972 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 1973 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 1974 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 1975 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 1976 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 1977 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 1978 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 1979 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 1980 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 1981 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 1982 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 1983 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 1984 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 1985 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 1986 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 1987 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 1988 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 1989 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 1990 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 1991 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1992 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1993 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1994 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 1995 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 1996 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1997 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1998 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1999 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 2000 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 2001 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 2002 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 2003 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 2004 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 2005 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 2006 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 2007 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 2008 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 2009 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 2010 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 2011 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 2012 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 2013 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 2014 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 2015 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 2016 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 2017 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 2018 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 2019 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 2020 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>; 2021 }; 2022 2023 intc: interrupt-controller@17a00000 { 2024 compatible = "arm,gic-v3"; 2025 #interrupt-cells = <3>; 2026 interrupt-controller; 2027 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 2028 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 2029 interrupts = <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>; 2030 }; 2031 2032 watchdog@17c10000 { 2033 compatible = "qcom,apss-wdt-sm6350", "qcom,kpss-wdt"; 2034 reg = <0 0x17c10000 0 0x1000>; 2035 clocks = <&sleep_clk>; 2036 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 2037 }; 2038 2039 timer@17c20000 { 2040 compatible = "arm,armv7-timer-mem"; 2041 reg = <0x0 0x17c20000 0x0 0x1000>; 2042 clock-frequency = <19200000>; 2043 #address-cells = <1>; 2044 #size-cells = <1>; 2045 ranges = <0 0 0 0x20000000>; 2046 2047 frame@17c21000 { 2048 frame-number = <0>; 2049 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2050 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 2051 reg = <0x17c21000 0x1000>, 2052 <0x17c22000 0x1000>; 2053 }; 2054 2055 frame@17c23000 { 2056 frame-number = <1>; 2057 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 2058 reg = <0x17c23000 0x1000>; 2059 status = "disabled"; 2060 }; 2061 2062 frame@17c25000 { 2063 frame-number = <2>; 2064 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2065 reg = <0x17c25000 0x1000>; 2066 status = "disabled"; 2067 }; 2068 2069 frame@17c27000 { 2070 frame-number = <3>; 2071 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2072 reg = <0x17c27000 0x1000>; 2073 status = "disabled"; 2074 }; 2075 2076 frame@17c29000 { 2077 frame-number = <4>; 2078 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2079 reg = <0x17c29000 0x1000>; 2080 status = "disabled"; 2081 }; 2082 2083 frame@17c2b000 { 2084 frame-number = <5>; 2085 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2086 reg = <0x17c2b000 0x1000>; 2087 status = "disabled"; 2088 }; 2089 2090 frame@17c2d000 { 2091 frame-number = <6>; 2092 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2093 reg = <0x17c2d000 0x1000>; 2094 status = "disabled"; 2095 }; 2096 }; 2097 2098 apps_rsc: rsc@18200000 { 2099 compatible = "qcom,rpmh-rsc"; 2100 label = "apps_rsc"; 2101 reg = <0x0 0x18200000 0x0 0x10000>, 2102 <0x0 0x18210000 0x0 0x10000>, 2103 <0x0 0x18220000 0x0 0x10000>; 2104 reg-names = "drv-0", "drv-1", "drv-2"; 2105 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 2106 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 2107 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 2108 qcom,tcs-offset = <0xd00>; 2109 qcom,drv-id = <2>; 2110 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 2111 <WAKE_TCS 3>, <CONTROL_TCS 1>; 2112 power-domains = <&CLUSTER_PD>; 2113 2114 rpmhcc: clock-controller { 2115 compatible = "qcom,sm6350-rpmh-clk"; 2116 #clock-cells = <1>; 2117 clock-names = "xo"; 2118 clocks = <&xo_board>; 2119 }; 2120 2121 rpmhpd: power-controller { 2122 compatible = "qcom,sm6350-rpmhpd"; 2123 #power-domain-cells = <1>; 2124 operating-points-v2 = <&rpmhpd_opp_table>; 2125 2126 rpmhpd_opp_table: opp-table { 2127 compatible = "operating-points-v2"; 2128 2129 rpmhpd_opp_ret: opp1 { 2130 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 2131 }; 2132 2133 rpmhpd_opp_min_svs: opp2 { 2134 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2135 }; 2136 2137 rpmhpd_opp_low_svs: opp3 { 2138 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2139 }; 2140 2141 rpmhpd_opp_svs: opp4 { 2142 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2143 }; 2144 2145 rpmhpd_opp_svs_l1: opp5 { 2146 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2147 }; 2148 2149 rpmhpd_opp_nom: opp6 { 2150 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2151 }; 2152 2153 rpmhpd_opp_nom_l1: opp7 { 2154 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2155 }; 2156 2157 rpmhpd_opp_nom_l2: opp8 { 2158 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 2159 }; 2160 2161 rpmhpd_opp_turbo: opp9 { 2162 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2163 }; 2164 2165 rpmhpd_opp_turbo_l1: opp10 { 2166 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2167 }; 2168 }; 2169 }; 2170 2171 apps_bcm_voter: bcm-voter { 2172 compatible = "qcom,bcm-voter"; 2173 }; 2174 }; 2175 2176 osm_l3: interconnect@18321000 { 2177 compatible = "qcom,sm6350-osm-l3", "qcom,osm-l3"; 2178 reg = <0x0 0x18321000 0x0 0x1000>; 2179 2180 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 2181 clock-names = "xo", "alternate"; 2182 2183 #interconnect-cells = <1>; 2184 }; 2185 2186 cpufreq_hw: cpufreq@18323000 { 2187 compatible = "qcom,sm6350-cpufreq-hw", "qcom,cpufreq-hw"; 2188 reg = <0 0x18323000 0 0x1000>, <0 0x18325800 0 0x1000>; 2189 reg-names = "freq-domain0", "freq-domain1"; 2190 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 2191 clock-names = "xo", "alternate"; 2192 2193 #freq-domain-cells = <1>; 2194 #clock-cells = <1>; 2195 }; 2196 2197 wifi: wifi@18800000 { 2198 compatible = "qcom,wcn3990-wifi"; 2199 reg = <0 0x18800000 0 0x800000>; 2200 reg-names = "membase"; 2201 memory-region = <&wlan_fw_mem>; 2202 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 2203 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 2204 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 2205 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 2206 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 2207 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 2208 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 2209 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 2210 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 2211 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 2212 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 2213 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 2214 iommus = <&apps_smmu 0x20 0x1>; 2215 qcom,msa-fixed-perm; 2216 status = "disabled"; 2217 }; 2218 }; 2219 2220 timer { 2221 compatible = "arm,armv8-timer"; 2222 clock-frequency = <19200000>; 2223 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2224 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2225 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2226 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 2227 }; 2228}; 2229