1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Samsung's ExynosAuto v9 SoC device tree source
4 *
5 * Copyright (c) 2021 Samsung Electronics Co., Ltd.
6 *
7 */
8
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10
11/ {
12	compatible = "samsung,exynosautov9";
13	#address-cells = <2>;
14	#size-cells = <1>;
15
16	interrupt-parent = <&gic>;
17
18	aliases {
19		pinctrl0 = &pinctrl_alive;
20		pinctrl1 = &pinctrl_aud;
21		pinctrl2 = &pinctrl_fsys0;
22		pinctrl3 = &pinctrl_fsys1;
23		pinctrl4 = &pinctrl_fsys2;
24		pinctrl5 = &pinctrl_peric0;
25		pinctrl6 = &pinctrl_peric1;
26	};
27
28	arm-pmu {
29		compatible = "arm,cortex-a76-pmu";
30		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
31			     <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
32			     <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
33			     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
34			     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
35			     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
36			     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
37			     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
38		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,
39				     <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
40	};
41
42	cpus {
43		#address-cells = <1>;
44		#size-cells = <0>;
45
46		cpu-map {
47			cluster0 {
48				core0 {
49					cpu = <&cpu0>;
50				};
51				core1 {
52					cpu = <&cpu1>;
53				};
54				core2 {
55					cpu = <&cpu2>;
56				};
57				core3 {
58					cpu = <&cpu3>;
59				};
60			};
61
62			cluster1 {
63				core0 {
64					cpu = <&cpu4>;
65				};
66				core1 {
67					cpu = <&cpu5>;
68				};
69				core2 {
70					cpu = <&cpu6>;
71				};
72				core3 {
73					cpu = <&cpu7>;
74				};
75			};
76		};
77
78		cpu0: cpu@0 {
79			device_type = "cpu";
80			compatible = "arm,cortex-a76";
81			reg = <0x0>;
82			enable-method = "psci";
83		};
84
85		cpu1: cpu@100 {
86			device_type = "cpu";
87			compatible = "arm,cortex-a76";
88			reg = <0x100>;
89			enable-method = "psci";
90		};
91
92		cpu2: cpu@200 {
93			device_type = "cpu";
94			compatible = "arm,cortex-a76";
95			reg = <0x200>;
96			enable-method = "psci";
97		};
98
99		cpu3: cpu@300 {
100			device_type = "cpu";
101			compatible = "arm,cortex-a76";
102			reg = <0x300>;
103			enable-method = "psci";
104		};
105
106		cpu4: cpu@10000 {
107			device_type = "cpu";
108			compatible = "arm,cortex-a76";
109			reg = <0x10000>;
110			enable-method = "psci";
111		};
112
113		cpu5: cpu@10100 {
114			device_type = "cpu";
115			compatible = "arm,cortex-a76";
116			reg = <0x10100>;
117			enable-method = "psci";
118		};
119
120		cpu6: cpu@10200 {
121			device_type = "cpu";
122			compatible = "arm,cortex-a76";
123			reg = <0x10200>;
124			enable-method = "psci";
125		};
126
127		cpu7: cpu@10300 {
128			device_type = "cpu";
129			compatible = "arm,cortex-a76";
130			reg = <0x10300>;
131			enable-method = "psci";
132		};
133	};
134
135	psci {
136		compatible = "arm,psci-1.0";
137		method = "smc";
138		cpu_suspend = <0xc4000001>;
139		cpu_off = <0x84000002>;
140		cpu_on = <0xc4000003>;
141	};
142
143	timer {
144		compatible = "arm,armv8-timer";
145		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
146			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
147			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
148			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
149	};
150
151	fixed-rate-clocks {
152		xtcxo: clock {
153			compatible = "fixed-clock";
154			#clock-cells = <0>;
155			clock-frequency = <26000000>;
156			clock-output-names = "oscclk";
157		};
158
159		/*
160		 * Keep the stub clock for serial driver, until proper clock
161		 * driver is implemented.
162		 */
163		uart_clock: uart-clock {
164			compatible = "fixed-clock";
165			#clock-cells = <0>;
166			clock-frequency = <133250000>;
167			clock-output-names = "uart";
168		};
169
170		/*
171		 * Keep the stub clock for ufs driver, until proper clock
172		 * driver is implemented.
173		 */
174		ufs_core_clock: ufs-core-clock {
175			compatible = "fixed-clock";
176			#clock-cells = <0>;
177			clock-frequency = <166562500>;
178		};
179	};
180
181	soc: soc@0 {
182		compatible = "simple-bus";
183		#address-cells = <1>;
184		#size-cells = <1>;
185		ranges = <0x0 0x0 0x0 0x20000000>;
186
187		gic: interrupt-controller@10101000 {
188			compatible = "arm,gic-400";
189			#interrupt-cells = <3>;
190			#address-cells = <0>;
191			interrupt-controller;
192			reg = <0x10101000 0x1000>,
193			      <0x10102000 0x2000>,
194			      <0x10104000 0x2000>,
195			      <0x10106000 0x2000>;
196			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
197						 IRQ_TYPE_LEVEL_HIGH)>;
198		};
199
200		pinctrl_alive: pinctrl@10450000 {
201			compatible = "samsung,exynosautov9-pinctrl";
202			reg = <0x10450000 0x1000>;
203
204			wakeup-interrupt-controller {
205				compatible = "samsung,exynos7-wakeup-eint";
206			};
207		};
208
209		pinctrl_aud: pinctrl@19c60000{
210			compatible = "samsung,exynosautov9-pinctrl";
211			reg = <0x19c60000 0x1000>;
212		};
213
214		pinctrl_fsys0: pinctrl@17740000 {
215			compatible = "samsung,exynosautov9-pinctrl";
216			reg = <0x17740000 0x1000>;
217			interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
218		};
219
220		pinctrl_fsys1: pinctrl@17060000 {
221			compatible = "samsung,exynosautov9-pinctrl";
222			reg = <0x17060000 0x1000>;
223			interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
224		};
225
226		pinctrl_fsys2: pinctrl@17c30000 {
227			compatible = "samsung,exynosautov9-pinctrl";
228			reg = <0x17c30000 0x1000>;
229			interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
230		};
231
232		pinctrl_peric0: pinctrl@10230000 {
233			compatible = "samsung,exynosautov9-pinctrl";
234			reg = <0x10230000 0x1000>;
235			interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>;
236		};
237
238		pinctrl_peric1: pinctrl@10830000 {
239			compatible = "samsung,exynosautov9-pinctrl";
240			reg = <0x10830000 0x1000>;
241			interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
242		};
243
244		pmu_system_controller: system-controller@10460000 {
245			compatible = "samsung,exynos7-pmu", "syscon";
246			reg = <0x10460000 0x10000>;
247		};
248
249		syscon_fsys2: syscon@17c20000 {
250			compatible = "samsung,exynosautov9-sysreg", "syscon";
251			reg = <0x17c20000 0x1000>;
252		};
253
254		/* USI: UART */
255		serial_0: uart@10300000 {
256			compatible = "samsung,exynos850-uart";
257			reg = <0x10300000 0x100>;
258			interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
259			pinctrl-names = "default";
260			pinctrl-0 = <&uart0_bus_dual>;
261			clocks = <&uart_clock>, <&uart_clock>;
262			clock-names = "uart", "clk_uart_baud0";
263			status = "disabled";
264		};
265
266		ufs_0_phy: ufs0-phy@17e04000 {
267			compatible = "samsung,exynosautov9-ufs-phy";
268			reg = <0x17e04000 0xc00>;
269			reg-names = "phy-pma";
270			samsung,pmu-syscon = <&pmu_system_controller>;
271			#phy-cells = <0>;
272			clocks = <&xtcxo>;
273			clock-names = "ref_clk";
274			status = "disabled";
275		};
276
277		ufs_0: ufs0@17e00000 {
278			compatible ="samsung,exynosautov9-ufs";
279
280			reg = <0x17e00000 0x100>,  /* 0: HCI standard */
281				<0x17e01100 0x410>,  /* 1: Vendor-specific */
282				<0x17e80000 0x8000>,  /* 2: UNIPRO */
283				<0x17dc0000 0x2200>;  /* 3: UFS protector */
284			reg-names = "hci", "vs_hci", "unipro", "ufsp";
285			interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
286			clocks = <&ufs_core_clock>,
287				<&ufs_core_clock>;
288			clock-names = "core_clk", "sclk_unipro_main";
289			freq-table-hz = <0 0>, <0 0>;
290			pinctrl-names = "default";
291			pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>;
292			phys = <&ufs_0_phy>;
293			phy-names = "ufs-phy";
294			samsung,sysreg = <&syscon_fsys2>;
295			samsung,ufs-shareability-reg-offset = <0x710>;
296			status = "disabled";
297		};
298	};
299};
300
301#include "exynosautov9-pinctrl.dtsi"
302