1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/sound/mediatek,mt8188-afe.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek AFE PCM controller for mt8188
8
9maintainers:
10  - Trevor Wu <trevor.wu@mediatek.com>
11
12properties:
13  compatible:
14    const: mediatek,mt8188-afe
15
16  reg:
17    maxItems: 1
18
19  interrupts:
20    maxItems: 1
21
22  resets:
23    maxItems: 1
24
25  reset-names:
26    const: audiosys
27
28  mediatek,topckgen:
29    $ref: /schemas/types.yaml#/definitions/phandle
30    description: The phandle of the mediatek topckgen controller
31
32  power-domains:
33    maxItems: 1
34
35  clocks:
36    items:
37      - description: 26M clock
38      - description: audio pll1 clock
39      - description: audio pll2 clock
40      - description: clock divider for i2si1_mck
41      - description: clock divider for i2si2_mck
42      - description: clock divider for i2so1_mck
43      - description: clock divider for i2so2_mck
44      - description: clock divider for dptx_mck
45      - description: a1sys hoping clock
46      - description: audio intbus clock
47      - description: audio hires clock
48      - description: audio local bus clock
49      - description: mux for dptx_mck
50      - description: mux for i2so1_mck
51      - description: mux for i2so2_mck
52      - description: mux for i2si1_mck
53      - description: mux for i2si2_mck
54      - description: audio 26m clock
55
56  clock-names:
57    items:
58      - const: clk26m
59      - const: apll1
60      - const: apll2
61      - const: apll12_div0
62      - const: apll12_div1
63      - const: apll12_div2
64      - const: apll12_div3
65      - const: apll12_div9
66      - const: a1sys_hp_sel
67      - const: aud_intbus_sel
68      - const: audio_h_sel
69      - const: audio_local_bus_sel
70      - const: dptx_m_sel
71      - const: i2so1_m_sel
72      - const: i2so2_m_sel
73      - const: i2si1_m_sel
74      - const: i2si2_m_sel
75      - const: adsp_audio_26m
76
77  mediatek,etdm-in1-cowork-source:
78    $ref: /schemas/types.yaml#/definitions/uint32
79    description:
80      etdm modules can share the same external clock pin. Specify
81      which etdm clock source is required by this etdm in module.
82    enum:
83      - 1 # etdm2_in
84      - 2 # etdm1_out
85      - 3 # etdm2_out
86
87  mediatek,etdm-in2-cowork-source:
88    $ref: /schemas/types.yaml#/definitions/uint32
89    description:
90      etdm modules can share the same external clock pin. Specify
91      which etdm clock source is required by this etdm in module.
92    enum:
93      - 0 # etdm1_in
94      - 2 # etdm1_out
95      - 3 # etdm2_out
96
97  mediatek,etdm-out1-cowork-source:
98    $ref: /schemas/types.yaml#/definitions/uint32
99    description:
100      etdm modules can share the same external clock pin. Specify
101      which etdm clock source is required by this etdm out module.
102    enum:
103      - 0 # etdm1_in
104      - 1 # etdm2_in
105      - 3 # etdm2_out
106
107  mediatek,etdm-out2-cowork-source:
108    $ref: /schemas/types.yaml#/definitions/uint32
109    description:
110      etdm modules can share the same external clock pin. Specify
111      which etdm clock source is required by this etdm out module.
112    enum:
113      - 0 # etdm1_in
114      - 1 # etdm2_in
115      - 2 # etdm1_out
116
117patternProperties:
118  "^mediatek,etdm-in[1-2]-chn-disabled$":
119    $ref: /schemas/types.yaml#/definitions/uint8-array
120    minItems: 1
121    maxItems: 16
122    description:
123      This is a list of channel IDs which should be disabled.
124      By default, all data received from ETDM pins will be outputed to
125      memory. etdm in supports disable_out in direct mode(w/o interconn),
126      so user can disable the specified channels by the property.
127    uniqueItems: true
128    items:
129      minimum: 0
130      maximum: 15
131
132  "^mediatek,etdm-in[1-2]-multi-pin-mode$":
133    type: boolean
134    description: if present, the etdm data mode is I2S.
135
136  "^mediatek,etdm-out[1-3]-multi-pin-mode$":
137    type: boolean
138    description: if present, the etdm data mode is I2S.
139
140required:
141  - compatible
142  - reg
143  - interrupts
144  - resets
145  - reset-names
146  - mediatek,topckgen
147  - power-domains
148  - clocks
149  - clock-names
150
151additionalProperties: false
152
153examples:
154  - |
155    #include <dt-bindings/interrupt-controller/arm-gic.h>
156    #include <dt-bindings/interrupt-controller/irq.h>
157
158    afe@10b10000 {
159        compatible = "mediatek,mt8188-afe";
160        reg = <0x10b10000 0x10000>;
161        interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>;
162        resets = <&watchdog 14>;
163        reset-names = "audiosys";
164        mediatek,topckgen = <&topckgen>;
165        power-domains = <&spm 13>; //MT8188_POWER_DOMAIN_AUDIO
166        mediatek,etdm-in2-cowork-source = <2>;
167        mediatek,etdm-out2-cowork-source = <0>;
168        mediatek,etdm-in1-multi-pin-mode;
169        mediatek,etdm-in1-chn-disabled = /bits/ 8 <0x0 0x2>;
170        clocks = <&clk26m>,
171                 <&apmixedsys 9>, //CLK_APMIXED_APLL1
172                 <&apmixedsys 10>, //CLK_APMIXED_APLL2
173                 <&topckgen 186>, //CLK_TOP_APLL12_CK_DIV0
174                 <&topckgen 187>, //CLK_TOP_APLL12_CK_DIV1
175                 <&topckgen 188>, //CLK_TOP_APLL12_CK_DIV2
176                 <&topckgen 189>, //CLK_TOP_APLL12_CK_DIV3
177                 <&topckgen 191>, //CLK_TOP_APLL12_CK_DIV9
178                 <&topckgen 83>, //CLK_TOP_A1SYS_HP
179                 <&topckgen 31>, //CLK_TOP_AUD_INTBUS
180                 <&topckgen 32>, //CLK_TOP_AUDIO_H
181                 <&topckgen 69>, //CLK_TOP_AUDIO_LOCAL_BUS
182                 <&topckgen 81>, //CLK_TOP_DPTX
183                 <&topckgen 77>, //CLK_TOP_I2SO1
184                 <&topckgen 78>, //CLK_TOP_I2SO2
185                 <&topckgen 79>, //CLK_TOP_I2SI1
186                 <&topckgen 80>, //CLK_TOP_I2SI2
187                 <&adsp_audio26m 0>; //CLK_AUDIODSP_AUDIO26M
188        clock-names = "clk26m",
189                      "apll1",
190                      "apll2",
191                      "apll12_div0",
192                      "apll12_div1",
193                      "apll12_div2",
194                      "apll12_div3",
195                      "apll12_div9",
196                      "a1sys_hp_sel",
197                      "aud_intbus_sel",
198                      "audio_h_sel",
199                      "audio_local_bus_sel",
200                      "dptx_m_sel",
201                      "i2so1_m_sel",
202                      "i2so2_m_sel",
203                      "i2si1_m_sel",
204                      "i2si2_m_sel",
205                      "adsp_audio_26m";
206    };
207
208...
209