1// SPDX-License-Identifier: GPL-2.0
2/dts-v1/;
3
4#include <dt-bindings/clock/qcom,gcc-msm8960.h>
5#include <dt-bindings/clock/qcom,lcc-msm8960.h>
6#include <dt-bindings/reset/qcom,gcc-msm8960.h>
7#include <dt-bindings/clock/qcom,mmcc-msm8960.h>
8#include <dt-bindings/clock/qcom,rpmcc.h>
9#include <dt-bindings/soc/qcom,gsbi.h>
10#include <dt-bindings/interrupt-controller/irq.h>
11#include <dt-bindings/interrupt-controller/arm-gic.h>
12/ {
13	#address-cells = <1>;
14	#size-cells = <1>;
15	model = "Qualcomm APQ8064";
16	compatible = "qcom,apq8064";
17	interrupt-parent = <&intc>;
18
19	reserved-memory {
20		#address-cells = <1>;
21		#size-cells = <1>;
22		ranges;
23
24		smem_region: smem@80000000 {
25			reg = <0x80000000 0x200000>;
26			no-map;
27		};
28
29		wcnss_mem: wcnss@8f000000 {
30			reg = <0x8f000000 0x700000>;
31			no-map;
32		};
33	};
34
35	cpus {
36		#address-cells = <1>;
37		#size-cells = <0>;
38
39		CPU0: cpu@0 {
40			compatible = "qcom,krait";
41			enable-method = "qcom,kpss-acc-v1";
42			device_type = "cpu";
43			reg = <0>;
44			next-level-cache = <&L2>;
45			qcom,acc = <&acc0>;
46			qcom,saw = <&saw0>;
47			cpu-idle-states = <&CPU_SPC>;
48		};
49
50		CPU1: cpu@1 {
51			compatible = "qcom,krait";
52			enable-method = "qcom,kpss-acc-v1";
53			device_type = "cpu";
54			reg = <1>;
55			next-level-cache = <&L2>;
56			qcom,acc = <&acc1>;
57			qcom,saw = <&saw1>;
58			cpu-idle-states = <&CPU_SPC>;
59		};
60
61		CPU2: cpu@2 {
62			compatible = "qcom,krait";
63			enable-method = "qcom,kpss-acc-v1";
64			device_type = "cpu";
65			reg = <2>;
66			next-level-cache = <&L2>;
67			qcom,acc = <&acc2>;
68			qcom,saw = <&saw2>;
69			cpu-idle-states = <&CPU_SPC>;
70		};
71
72		CPU3: cpu@3 {
73			compatible = "qcom,krait";
74			enable-method = "qcom,kpss-acc-v1";
75			device_type = "cpu";
76			reg = <3>;
77			next-level-cache = <&L2>;
78			qcom,acc = <&acc3>;
79			qcom,saw = <&saw3>;
80			cpu-idle-states = <&CPU_SPC>;
81		};
82
83		L2: l2-cache {
84			compatible = "cache";
85			cache-level = <2>;
86		};
87
88		idle-states {
89			CPU_SPC: spc {
90				compatible = "qcom,idle-state-spc",
91						"arm,idle-state";
92				entry-latency-us = <400>;
93				exit-latency-us = <900>;
94				min-residency-us = <3000>;
95			};
96		};
97	};
98
99	memory@0 {
100		device_type = "memory";
101		reg = <0x0 0x0>;
102	};
103
104	thermal-zones {
105		cpu0-thermal {
106			polling-delay-passive = <250>;
107			polling-delay = <1000>;
108
109			thermal-sensors = <&tsens 7>;
110			coefficients = <1199 0>;
111
112			trips {
113				cpu_alert0: trip0 {
114					temperature = <75000>;
115					hysteresis = <2000>;
116					type = "passive";
117				};
118				cpu_crit0: trip1 {
119					temperature = <110000>;
120					hysteresis = <2000>;
121					type = "critical";
122				};
123			};
124		};
125
126		cpu1-thermal {
127			polling-delay-passive = <250>;
128			polling-delay = <1000>;
129
130			thermal-sensors = <&tsens 8>;
131			coefficients = <1132 0>;
132
133			trips {
134				cpu_alert1: trip0 {
135					temperature = <75000>;
136					hysteresis = <2000>;
137					type = "passive";
138				};
139				cpu_crit1: trip1 {
140					temperature = <110000>;
141					hysteresis = <2000>;
142					type = "critical";
143				};
144			};
145		};
146
147		cpu2-thermal {
148			polling-delay-passive = <250>;
149			polling-delay = <1000>;
150
151			thermal-sensors = <&tsens 9>;
152			coefficients = <1199 0>;
153
154			trips {
155				cpu_alert2: trip0 {
156					temperature = <75000>;
157					hysteresis = <2000>;
158					type = "passive";
159				};
160				cpu_crit2: trip1 {
161					temperature = <110000>;
162					hysteresis = <2000>;
163					type = "critical";
164				};
165			};
166		};
167
168		cpu3-thermal {
169			polling-delay-passive = <250>;
170			polling-delay = <1000>;
171
172			thermal-sensors = <&tsens 10>;
173			coefficients = <1132 0>;
174
175			trips {
176				cpu_alert3: trip0 {
177					temperature = <75000>;
178					hysteresis = <2000>;
179					type = "passive";
180				};
181				cpu_crit3: trip1 {
182					temperature = <110000>;
183					hysteresis = <2000>;
184					type = "critical";
185				};
186			};
187		};
188	};
189
190	cpu-pmu {
191		compatible = "qcom,krait-pmu";
192		interrupts = <1 10 0x304>;
193	};
194
195	clocks {
196		cxo_board: cxo_board {
197			compatible = "fixed-clock";
198			#clock-cells = <0>;
199			clock-frequency = <19200000>;
200		};
201
202		pxo_board: pxo_board {
203			compatible = "fixed-clock";
204			#clock-cells = <0>;
205			clock-frequency = <27000000>;
206		};
207
208		sleep_clk: sleep_clk {
209			compatible = "fixed-clock";
210			#clock-cells = <0>;
211			clock-frequency = <32768>;
212		};
213	};
214
215	sfpb_mutex: hwmutex {
216		compatible = "qcom,sfpb-mutex";
217		syscon = <&sfpb_wrapper_mutex 0x604 0x4>;
218		#hwlock-cells = <1>;
219	};
220
221	smem {
222		compatible = "qcom,smem";
223		memory-region = <&smem_region>;
224
225		hwlocks = <&sfpb_mutex 3>;
226	};
227
228	smd {
229		compatible = "qcom,smd";
230
231		modem-edge {
232			interrupts = <0 37 IRQ_TYPE_EDGE_RISING>;
233
234			qcom,ipc = <&l2cc 8 3>;
235			qcom,smd-edge = <0>;
236
237			status = "disabled";
238		};
239
240		q6-edge {
241			interrupts = <0 90 IRQ_TYPE_EDGE_RISING>;
242
243			qcom,ipc = <&l2cc 8 15>;
244			qcom,smd-edge = <1>;
245
246			status = "disabled";
247		};
248
249		dsps-edge {
250			interrupts = <0 138 IRQ_TYPE_EDGE_RISING>;
251
252			qcom,ipc = <&sps_sic_non_secure 0x4080 0>;
253			qcom,smd-edge = <3>;
254
255			status = "disabled";
256		};
257
258		riva-edge {
259			interrupts = <0 198 IRQ_TYPE_EDGE_RISING>;
260
261			qcom,ipc = <&l2cc 8 25>;
262			qcom,smd-edge = <6>;
263
264			status = "disabled";
265		};
266	};
267
268	smsm {
269		compatible = "qcom,smsm";
270
271		#address-cells = <1>;
272		#size-cells = <0>;
273
274		qcom,ipc-1 = <&l2cc 8 4>;
275		qcom,ipc-2 = <&l2cc 8 14>;
276		qcom,ipc-3 = <&l2cc 8 23>;
277		qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>;
278
279		apps_smsm: apps@0 {
280			reg = <0>;
281			#qcom,smem-state-cells = <1>;
282		};
283
284		modem_smsm: modem@1 {
285			reg = <1>;
286			interrupts = <0 38 IRQ_TYPE_EDGE_RISING>;
287
288			interrupt-controller;
289			#interrupt-cells = <2>;
290		};
291
292		q6_smsm: q6@2 {
293			reg = <2>;
294			interrupts = <0 89 IRQ_TYPE_EDGE_RISING>;
295
296			interrupt-controller;
297			#interrupt-cells = <2>;
298		};
299
300		wcnss_smsm: wcnss@3 {
301			reg = <3>;
302			interrupts = <0 204 IRQ_TYPE_EDGE_RISING>;
303
304			interrupt-controller;
305			#interrupt-cells = <2>;
306		};
307
308		dsps_smsm: dsps@4 {
309			reg = <4>;
310			interrupts = <0 137 IRQ_TYPE_EDGE_RISING>;
311
312			interrupt-controller;
313			#interrupt-cells = <2>;
314		};
315	};
316
317	firmware {
318		scm {
319			compatible = "qcom,scm-apq8064", "qcom,scm";
320
321			clocks = <&rpmcc RPM_DAYTONA_FABRIC_CLK>;
322			clock-names = "core";
323		};
324	};
325
326
327	/*
328	 * These channels from the ADC are simply hardware monitors.
329	 * That is why the ADC is referred to as "HKADC" - HouseKeeping
330	 * ADC.
331	 */
332	iio-hwmon {
333		compatible = "iio-hwmon";
334		io-channels = <&xoadc 0x00 0x01>, /* Battery */
335			    <&xoadc 0x00 0x02>, /* DC in (charger) */
336			    <&xoadc 0x00 0x04>, /* VPH the main system voltage */
337			    <&xoadc 0x00 0x0b>, /* Die temperature */
338			    <&xoadc 0x00 0x0c>, /* Reference voltage 1.25V */
339			    <&xoadc 0x00 0x0d>, /* Reference voltage 0.625V */
340			    <&xoadc 0x00 0x0e>; /* Charger temperature */
341	};
342
343	soc: soc {
344		#address-cells = <1>;
345		#size-cells = <1>;
346		ranges;
347		compatible = "simple-bus";
348
349		tlmm_pinmux: pinctrl@800000 {
350			compatible = "qcom,apq8064-pinctrl";
351			reg = <0x800000 0x4000>;
352
353			gpio-controller;
354			gpio-ranges = <&tlmm_pinmux 0 0 90>;
355			#gpio-cells = <2>;
356			interrupt-controller;
357			#interrupt-cells = <2>;
358			interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
359
360			pinctrl-names = "default";
361			pinctrl-0 = <&ps_hold>;
362		};
363
364		sfpb_wrapper_mutex: syscon@1200000 {
365			compatible = "syscon";
366			reg = <0x01200000 0x8000>;
367		};
368
369		intc: interrupt-controller@2000000 {
370			compatible = "qcom,msm-qgic2";
371			interrupt-controller;
372			#interrupt-cells = <3>;
373			reg = <0x02000000 0x1000>,
374			      <0x02002000 0x1000>;
375		};
376
377		timer@200a000 {
378			compatible = "qcom,kpss-wdt-apq8064", "qcom,kpss-timer",
379				     "qcom,msm-timer";
380			interrupts = <1 1 0x301>,
381				     <1 2 0x301>,
382				     <1 3 0x301>;
383			reg = <0x0200a000 0x100>;
384			clock-frequency = <27000000>;
385			cpu-offset = <0x80000>;
386		};
387
388		acc0: clock-controller@2088000 {
389			compatible = "qcom,kpss-acc-v1";
390			reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
391			clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
392			clock-names = "pll8_vote", "pxo";
393			clock-output-names = "acpu0_aux";
394			#clock-cells = <0>;
395		};
396
397		acc1: clock-controller@2098000 {
398			compatible = "qcom,kpss-acc-v1";
399			reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
400			clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
401			clock-names = "pll8_vote", "pxo";
402			clock-output-names = "acpu1_aux";
403			#clock-cells = <0>;
404		};
405
406		acc2: clock-controller@20a8000 {
407			compatible = "qcom,kpss-acc-v1";
408			reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
409			clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
410			clock-names = "pll8_vote", "pxo";
411			clock-output-names = "acpu2_aux";
412			#clock-cells = <0>;
413		};
414
415		acc3: clock-controller@20b8000 {
416			compatible = "qcom,kpss-acc-v1";
417			reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
418			clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
419			clock-names = "pll8_vote", "pxo";
420			clock-output-names = "acpu3_aux";
421			#clock-cells = <0>;
422		};
423
424		saw0: power-controller@2089000 {
425			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
426			reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
427			regulator;
428		};
429
430		saw1: power-controller@2099000 {
431			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
432			reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
433			regulator;
434		};
435
436		saw2: power-controller@20a9000 {
437			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
438			reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
439			regulator;
440		};
441
442		saw3: power-controller@20b9000 {
443			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
444			reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
445			regulator;
446		};
447
448		sps_sic_non_secure: sps-sic-non-secure@12100000 {
449			compatible = "syscon";
450			reg = <0x12100000 0x10000>;
451		};
452
453		gsbi1: gsbi@12440000 {
454			status = "disabled";
455			compatible = "qcom,gsbi-v1.0.0";
456			cell-index = <1>;
457			reg = <0x12440000 0x100>;
458			clocks = <&gcc GSBI1_H_CLK>;
459			clock-names = "iface";
460			#address-cells = <1>;
461			#size-cells = <1>;
462			ranges;
463
464			syscon-tcsr = <&tcsr>;
465
466			gsbi1_serial: serial@12450000 {
467				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
468				reg = <0x12450000 0x100>,
469				      <0x12400000 0x03>;
470				interrupts = <0 193 IRQ_TYPE_LEVEL_HIGH>;
471				clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
472				clock-names = "core", "iface";
473				status = "disabled";
474			};
475
476			gsbi1_i2c: i2c@12460000 {
477				compatible = "qcom,i2c-qup-v1.1.1";
478				pinctrl-0 = <&i2c1_pins>;
479				pinctrl-1 = <&i2c1_pins_sleep>;
480				pinctrl-names = "default", "sleep";
481				reg = <0x12460000 0x1000>;
482				interrupts = <0 194 IRQ_TYPE_LEVEL_HIGH>;
483				clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
484				clock-names = "core", "iface";
485				#address-cells = <1>;
486				#size-cells = <0>;
487				status = "disabled";
488			};
489
490		};
491
492		gsbi2: gsbi@12480000 {
493			status = "disabled";
494			compatible = "qcom,gsbi-v1.0.0";
495			cell-index = <2>;
496			reg = <0x12480000 0x100>;
497			clocks = <&gcc GSBI2_H_CLK>;
498			clock-names = "iface";
499			#address-cells = <1>;
500			#size-cells = <1>;
501			ranges;
502
503			syscon-tcsr = <&tcsr>;
504
505			gsbi2_i2c: i2c@124a0000 {
506				compatible = "qcom,i2c-qup-v1.1.1";
507				reg = <0x124a0000 0x1000>;
508				pinctrl-0 = <&i2c2_pins>;
509				pinctrl-1 = <&i2c2_pins_sleep>;
510				pinctrl-names = "default", "sleep";
511				interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>;
512				clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
513				clock-names = "core", "iface";
514				#address-cells = <1>;
515				#size-cells = <0>;
516				status = "disabled";
517			};
518		};
519
520		gsbi3: gsbi@16200000 {
521			status = "disabled";
522			compatible = "qcom,gsbi-v1.0.0";
523			cell-index = <3>;
524			reg = <0x16200000 0x100>;
525			clocks = <&gcc GSBI3_H_CLK>;
526			clock-names = "iface";
527			#address-cells = <1>;
528			#size-cells = <1>;
529			ranges;
530			gsbi3_i2c: i2c@16280000 {
531				compatible = "qcom,i2c-qup-v1.1.1";
532				pinctrl-0 = <&i2c3_pins>;
533				pinctrl-1 = <&i2c3_pins_sleep>;
534				pinctrl-names = "default", "sleep";
535				reg = <0x16280000 0x1000>;
536				interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
537				clocks = <&gcc GSBI3_QUP_CLK>,
538					 <&gcc GSBI3_H_CLK>;
539				clock-names = "core", "iface";
540				#address-cells = <1>;
541				#size-cells = <0>;
542				status = "disabled";
543			};
544		};
545
546		gsbi4: gsbi@16300000 {
547			status = "disabled";
548			compatible = "qcom,gsbi-v1.0.0";
549			cell-index = <4>;
550			reg = <0x16300000 0x03>;
551			clocks = <&gcc GSBI4_H_CLK>;
552			clock-names = "iface";
553			#address-cells = <1>;
554			#size-cells = <1>;
555			ranges;
556
557			gsbi4_i2c: i2c@16380000 {
558				compatible = "qcom,i2c-qup-v1.1.1";
559				pinctrl-0 = <&i2c4_pins>;
560				pinctrl-1 = <&i2c4_pins_sleep>;
561				pinctrl-names = "default", "sleep";
562				reg = <0x16380000 0x1000>;
563				interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
564				clocks = <&gcc GSBI4_QUP_CLK>,
565					 <&gcc GSBI4_H_CLK>;
566				clock-names = "core", "iface";
567				status = "disabled";
568			};
569		};
570
571		gsbi5: gsbi@1a200000 {
572			status = "disabled";
573			compatible = "qcom,gsbi-v1.0.0";
574			cell-index = <5>;
575			reg = <0x1a200000 0x03>;
576			clocks = <&gcc GSBI5_H_CLK>;
577			clock-names = "iface";
578			#address-cells = <1>;
579			#size-cells = <1>;
580			ranges;
581
582			gsbi5_serial: serial@1a240000 {
583				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
584				reg = <0x1a240000 0x100>,
585				      <0x1a200000 0x03>;
586				interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
587				clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
588				clock-names = "core", "iface";
589				status = "disabled";
590			};
591
592			gsbi5_spi: spi@1a280000 {
593				compatible = "qcom,spi-qup-v1.1.1";
594				reg = <0x1a280000 0x1000>;
595				interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
596				pinctrl-0 = <&spi5_default>;
597				pinctrl-1 = <&spi5_sleep>;
598				pinctrl-names = "default", "sleep";
599				clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
600				clock-names = "core", "iface";
601				status = "disabled";
602				#address-cells = <1>;
603				#size-cells = <0>;
604			};
605		};
606
607		gsbi6: gsbi@16500000 {
608			status = "disabled";
609			compatible = "qcom,gsbi-v1.0.0";
610			cell-index = <6>;
611			reg = <0x16500000 0x03>;
612			clocks = <&gcc GSBI6_H_CLK>;
613			clock-names = "iface";
614			#address-cells = <1>;
615			#size-cells = <1>;
616			ranges;
617
618			gsbi6_serial: serial@16540000 {
619				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
620				reg = <0x16540000 0x100>,
621				      <0x16500000 0x03>;
622				interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
623				clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
624				clock-names = "core", "iface";
625				status = "disabled";
626			};
627
628			gsbi6_i2c: i2c@16580000 {
629				compatible = "qcom,i2c-qup-v1.1.1";
630				pinctrl-0 = <&i2c6_pins>;
631				pinctrl-1 = <&i2c6_pins_sleep>;
632				pinctrl-names = "default", "sleep";
633				reg = <0x16580000 0x1000>;
634				interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
635				clocks = <&gcc GSBI6_QUP_CLK>,
636					 <&gcc GSBI6_H_CLK>;
637				clock-names = "core", "iface";
638				status = "disabled";
639			};
640		};
641
642		gsbi7: gsbi@16600000 {
643			status = "disabled";
644			compatible = "qcom,gsbi-v1.0.0";
645			cell-index = <7>;
646			reg = <0x16600000 0x100>;
647			clocks = <&gcc GSBI7_H_CLK>;
648			clock-names = "iface";
649			#address-cells = <1>;
650			#size-cells = <1>;
651			ranges;
652			syscon-tcsr = <&tcsr>;
653
654			gsbi7_serial: serial@16640000 {
655				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
656				reg = <0x16640000 0x1000>,
657				      <0x16600000 0x1000>;
658				interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
659				clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
660				clock-names = "core", "iface";
661				status = "disabled";
662			};
663
664			gsbi7_i2c: i2c@16680000 {
665				compatible = "qcom,i2c-qup-v1.1.1";
666				pinctrl-0 = <&i2c7_pins>;
667				pinctrl-1 = <&i2c7_pins_sleep>;
668				pinctrl-names = "default", "sleep";
669				reg = <0x16680000 0x1000>;
670				interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
671				clocks = <&gcc GSBI7_QUP_CLK>,
672					 <&gcc GSBI7_H_CLK>;
673				clock-names = "core", "iface";
674				status = "disabled";
675			};
676		};
677
678		rng@1a500000 {
679			compatible = "qcom,prng";
680			reg = <0x1a500000 0x200>;
681			clocks = <&gcc PRNG_CLK>;
682			clock-names = "core";
683		};
684
685		ssbi@c00000 {
686			compatible = "qcom,ssbi";
687			reg = <0x00c00000 0x1000>;
688			qcom,controller-type = "pmic-arbiter";
689
690			pm8821: pmic {
691				compatible = "qcom,pm8821";
692				interrupt-parent = <&tlmm_pinmux>;
693				interrupts = <76 IRQ_TYPE_LEVEL_LOW>;
694				#interrupt-cells = <2>;
695				interrupt-controller;
696				#address-cells = <1>;
697				#size-cells = <0>;
698
699				pm8821_mpps: mpps@50 {
700					compatible = "qcom,pm8821-mpp", "qcom,ssbi-mpp";
701					reg = <0x50>;
702					interrupt-controller;
703					#interrupt-cells = <2>;
704					gpio-controller;
705					#gpio-cells = <2>;
706					gpio-ranges = <&pm8821_mpps 0 0 4>;
707				};
708			};
709		};
710
711		ssbi@500000 {
712			compatible = "qcom,ssbi";
713			reg = <0x00500000 0x1000>;
714			qcom,controller-type = "pmic-arbiter";
715
716			pmicintc: pmic {
717				compatible = "qcom,pm8921";
718				interrupt-parent = <&tlmm_pinmux>;
719				interrupts = <74 8>;
720				#interrupt-cells = <2>;
721				interrupt-controller;
722				#address-cells = <1>;
723				#size-cells = <0>;
724
725				pm8921_gpio: gpio@150 {
726
727					compatible = "qcom,pm8921-gpio",
728						     "qcom,ssbi-gpio";
729					reg = <0x150>;
730					interrupt-controller;
731					#interrupt-cells = <2>;
732					gpio-controller;
733					gpio-ranges = <&pm8921_gpio 0 0 44>;
734					#gpio-cells = <2>;
735
736				};
737
738				pm8921_mpps: mpps@50 {
739					compatible = "qcom,pm8921-mpp",
740						     "qcom,ssbi-mpp";
741					reg = <0x50>;
742					gpio-controller;
743					#gpio-cells = <2>;
744					gpio-ranges = <&pm8921_mpps 0 0 12>;
745					interrupt-controller;
746					#interrupt-cells = <2>;
747				};
748
749				rtc@11d {
750					compatible = "qcom,pm8921-rtc";
751					interrupt-parent = <&pmicintc>;
752					interrupts = <39 1>;
753					reg = <0x11d>;
754					allow-set-time;
755				};
756
757				pwrkey@1c {
758					compatible = "qcom,pm8921-pwrkey";
759					reg = <0x1c>;
760					interrupt-parent = <&pmicintc>;
761					interrupts = <50 1>, <51 1>;
762					debounce = <15625>;
763					pull-up;
764				};
765
766				xoadc: xoadc@197 {
767					compatible = "qcom,pm8921-adc";
768					reg = <197>;
769					interrupts-extended = <&pmicintc 78 IRQ_TYPE_EDGE_RISING>;
770					#address-cells = <2>;
771					#size-cells = <0>;
772					#io-channel-cells = <2>;
773
774					vcoin: adc-channel@0 {
775						reg = <0x00 0x00>;
776					};
777					vbat: adc-channel@1 {
778						reg = <0x00 0x01>;
779					};
780					dcin: adc-channel@2 {
781						reg = <0x00 0x02>;
782					};
783					vph_pwr: adc-channel@4 {
784						reg = <0x00 0x04>;
785					};
786					batt_therm: adc-channel@8 {
787						reg = <0x00 0x08>;
788					};
789					batt_id: adc-channel@9 {
790						reg = <0x00 0x09>;
791					};
792					usb_vbus: adc-channel@a {
793						reg = <0x00 0x0a>;
794					};
795					die_temp: adc-channel@b {
796						reg = <0x00 0x0b>;
797					};
798					ref_625mv: adc-channel@c {
799						reg = <0x00 0x0c>;
800					};
801					ref_1250mv: adc-channel@d {
802						reg = <0x00 0x0d>;
803					};
804					chg_temp: adc-channel@e {
805						reg = <0x00 0x0e>;
806					};
807					ref_muxoff: adc-channel@f {
808						reg = <0x00 0x0f>;
809					};
810				};
811			};
812		};
813
814		qfprom: qfprom@700000 {
815			compatible = "qcom,apq8064-qfprom", "qcom,qfprom";
816			reg = <0x00700000 0x1000>;
817			#address-cells = <1>;
818			#size-cells = <1>;
819			ranges;
820			tsens_calib: calib@404 {
821				reg = <0x404 0x10>;
822			};
823			tsens_backup: backup_calib@414 {
824				reg = <0x414 0x10>;
825			};
826		};
827
828		gcc: clock-controller@900000 {
829			compatible = "qcom,gcc-apq8064", "syscon";
830			reg = <0x00900000 0x4000>;
831			#clock-cells = <1>;
832			#power-domain-cells = <1>;
833			#reset-cells = <1>;
834			clocks = <&cxo_board>,
835				 <&pxo_board>,
836				 <&lcc PLL4>;
837			clock-names = "cxo", "pxo", "pll4";
838
839			tsens: thermal-sensor {
840				compatible = "qcom,msm8960-tsens";
841
842				nvmem-cells = <&tsens_calib>, <&tsens_backup>;
843				nvmem-cell-names = "calib", "calib_backup";
844				interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
845				interrupt-names = "uplow";
846
847				#qcom,sensors = <11>;
848				#thermal-sensor-cells = <1>;
849			};
850		};
851
852		lcc: clock-controller@28000000 {
853			compatible = "qcom,lcc-apq8064";
854			reg = <0x28000000 0x1000>;
855			#clock-cells = <1>;
856			#reset-cells = <1>;
857			clocks = <&pxo_board>,
858				 <&gcc PLL4_VOTE>,
859				 <0>,
860				 <0>, <0>,
861				 <0>, <0>,
862				 <0>;
863			clock-names = "pxo",
864				      "pll4_vote",
865				      "mi2s_codec_clk",
866				      "codec_i2s_mic_codec_clk",
867				      "spare_i2s_mic_codec_clk",
868				      "codec_i2s_spkr_codec_clk",
869				      "spare_i2s_spkr_codec_clk",
870				      "pcm_codec_clk";
871		};
872
873		mmcc: clock-controller@4000000 {
874			compatible = "qcom,mmcc-apq8064";
875			reg = <0x4000000 0x1000>;
876			#clock-cells = <1>;
877			#power-domain-cells = <1>;
878			#reset-cells = <1>;
879			clocks = <&pxo_board>,
880				 <&gcc PLL3>,
881				 <&gcc PLL8_VOTE>,
882				 <&dsi0_phy 1>,
883				 <&dsi0_phy 0>,
884				 <&dsi1_phy 1>,
885				 <&dsi1_phy 0>,
886				 <&hdmi_phy>;
887			clock-names = "pxo",
888				      "pll3",
889				      "pll8_vote",
890				      "dsi1pll",
891				      "dsi1pllbyte",
892				      "dsi2pll",
893				      "dsi2pllbyte",
894				      "hdmipll";
895		};
896
897		l2cc: clock-controller@2011000 {
898			compatible = "qcom,kpss-gcc-apq8064", "qcom,kpss-gcc", "syscon";
899			reg = <0x2011000 0x1000>;
900			clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
901			clock-names = "pll8_vote", "pxo";
902			#clock-cells = <0>;
903		};
904
905		rpm: rpm@108000 {
906			compatible = "qcom,rpm-apq8064";
907			reg = <0x108000 0x1000>;
908			qcom,ipc = <&l2cc 0x8 2>;
909
910			interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
911				     <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
912				     <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
913			interrupt-names = "ack", "err", "wakeup";
914
915			rpmcc: clock-controller {
916				compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc";
917				#clock-cells = <1>;
918				clocks = <&pxo_board>, <&cxo_board>;
919				clock-names = "pxo", "cxo";
920			};
921
922			regulators {
923				compatible = "qcom,rpm-pm8921-regulators";
924
925				pm8921_s1: s1 {};
926				pm8921_s2: s2 {};
927				pm8921_s3: s3 {};
928				pm8921_s4: s4 {};
929				pm8921_s7: s7 {};
930				pm8921_s8: s8 {};
931
932				pm8921_l1: l1 {};
933				pm8921_l2: l2 {};
934				pm8921_l3: l3 {};
935				pm8921_l4: l4 {};
936				pm8921_l5: l5 {};
937				pm8921_l6: l6 {};
938				pm8921_l7: l7 {};
939				pm8921_l8: l8 {};
940				pm8921_l9: l9 {};
941				pm8921_l10: l10 {};
942				pm8921_l11: l11 {};
943				pm8921_l12: l12 {};
944				pm8921_l14: l14 {};
945				pm8921_l15: l15 {};
946				pm8921_l16: l16 {};
947				pm8921_l17: l17 {};
948				pm8921_l18: l18 {};
949				pm8921_l21: l21 {};
950				pm8921_l22: l22 {};
951				pm8921_l23: l23 {};
952				pm8921_l24: l24 {};
953				pm8921_l25: l25 {};
954				pm8921_l26: l26 {};
955				pm8921_l27: l27 {};
956				pm8921_l28: l28 {};
957				pm8921_l29: l29 {};
958
959				pm8921_lvs1: lvs1 {};
960				pm8921_lvs2: lvs2 {};
961				pm8921_lvs3: lvs3 {};
962				pm8921_lvs4: lvs4 {};
963				pm8921_lvs5: lvs5 {};
964				pm8921_lvs6: lvs6 {};
965				pm8921_lvs7: lvs7 {};
966
967				pm8921_usb_switch: usb-switch {};
968
969				pm8921_hdmi_switch: hdmi-switch {
970					bias-pull-down;
971				};
972
973				pm8921_ncp: ncp {};
974			};
975		};
976
977		usb1: usb@12500000 {
978			compatible = "qcom,ci-hdrc";
979			reg = <0x12500000 0x200>,
980			      <0x12500200 0x200>;
981			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
982			clocks = <&gcc USB_HS1_XCVR_CLK>, <&gcc USB_HS1_H_CLK>;
983			clock-names = "core", "iface";
984			assigned-clocks = <&gcc USB_HS1_XCVR_CLK>;
985			assigned-clock-rates = <60000000>;
986			resets = <&gcc USB_HS1_RESET>;
987			reset-names = "core";
988			phy_type = "ulpi";
989			ahb-burst-config = <0>;
990			phys = <&usb_hs1_phy>;
991			phy-names = "usb-phy";
992			status = "disabled";
993			#reset-cells = <1>;
994
995			ulpi {
996				usb_hs1_phy: phy {
997					compatible = "qcom,usb-hs-phy-apq8064",
998						     "qcom,usb-hs-phy";
999					clocks = <&sleep_clk>, <&cxo_board>;
1000					clock-names = "sleep", "ref";
1001					resets = <&usb1 0>;
1002					reset-names = "por";
1003					#phy-cells = <0>;
1004				};
1005			};
1006		};
1007
1008		usb3: usb@12520000 {
1009			compatible = "qcom,ci-hdrc";
1010			reg = <0x12520000 0x200>,
1011			      <0x12520200 0x200>;
1012			interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
1013			clocks = <&gcc USB_HS3_XCVR_CLK>, <&gcc USB_HS3_H_CLK>;
1014			clock-names = "core", "iface";
1015			assigned-clocks = <&gcc USB_HS3_XCVR_CLK>;
1016			assigned-clock-rates = <60000000>;
1017			resets = <&gcc USB_HS3_RESET>;
1018			reset-names = "core";
1019			phy_type = "ulpi";
1020			ahb-burst-config = <0>;
1021			phys = <&usb_hs3_phy>;
1022			phy-names = "usb-phy";
1023			status = "disabled";
1024			#reset-cells = <1>;
1025
1026			ulpi {
1027				usb_hs3_phy: phy {
1028					compatible = "qcom,usb-hs-phy-apq8064",
1029						     "qcom,usb-hs-phy";
1030					#phy-cells = <0>;
1031					clocks = <&sleep_clk>, <&cxo_board>;
1032					clock-names = "sleep", "ref";
1033					resets = <&usb3 0>;
1034					reset-names = "por";
1035				};
1036			};
1037		};
1038
1039		usb4: usb@12530000 {
1040			compatible = "qcom,ci-hdrc";
1041			reg = <0x12530000 0x200>,
1042			      <0x12530200 0x200>;
1043			interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
1044			clocks = <&gcc USB_HS4_XCVR_CLK>, <&gcc USB_HS4_H_CLK>;
1045			clock-names = "core", "iface";
1046			assigned-clocks = <&gcc USB_HS4_XCVR_CLK>;
1047			assigned-clock-rates = <60000000>;
1048			resets = <&gcc USB_HS4_RESET>;
1049			reset-names = "core";
1050			phy_type = "ulpi";
1051			ahb-burst-config = <0>;
1052			phys = <&usb_hs4_phy>;
1053			phy-names = "usb-phy";
1054			status = "disabled";
1055			#reset-cells = <1>;
1056
1057			ulpi {
1058				usb_hs4_phy: phy {
1059					compatible = "qcom,usb-hs-phy-apq8064",
1060						     "qcom,usb-hs-phy";
1061					#phy-cells = <0>;
1062					clocks = <&sleep_clk>, <&cxo_board>;
1063					clock-names = "sleep", "ref";
1064					resets = <&usb4 0>;
1065					reset-names = "por";
1066				};
1067			};
1068		};
1069
1070		sata_phy0: phy@1b400000 {
1071			compatible = "qcom,apq8064-sata-phy";
1072			status = "disabled";
1073			reg = <0x1b400000 0x200>;
1074			reg-names = "phy_mem";
1075			clocks = <&gcc SATA_PHY_CFG_CLK>;
1076			clock-names = "cfg";
1077			#phy-cells = <0>;
1078		};
1079
1080		sata0: sata@29000000 {
1081			compatible = "qcom,apq8064-ahci", "generic-ahci";
1082			status	 = "disabled";
1083			reg	 = <0x29000000 0x180>;
1084			interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
1085
1086			clocks = <&gcc SFAB_SATA_S_H_CLK>,
1087				 <&gcc SATA_H_CLK>,
1088				 <&gcc SATA_A_CLK>,
1089				 <&gcc SATA_RXOOB_CLK>,
1090				 <&gcc SATA_PMALIVE_CLK>;
1091			clock-names = "slave_iface",
1092				      "iface",
1093				      "bus",
1094				      "rxoob",
1095				      "core_pmalive";
1096
1097			assigned-clocks = <&gcc SATA_RXOOB_CLK>,
1098					  <&gcc SATA_PMALIVE_CLK>;
1099			assigned-clock-rates = <100000000>, <100000000>;
1100
1101			phys = <&sata_phy0>;
1102			phy-names = "sata-phy";
1103			ports-implemented = <0x1>;
1104		};
1105
1106		sdcc3: mmc@12180000 {
1107			compatible = "arm,pl18x", "arm,primecell";
1108			arm,primecell-periphid = <0x00051180>;
1109			status = "disabled";
1110			reg = <0x12180000 0x2000>;
1111			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1112			clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
1113			clock-names = "mclk", "apb_pclk";
1114			bus-width = <4>;
1115			cap-sd-highspeed;
1116			cap-mmc-highspeed;
1117			max-frequency = <192000000>;
1118			no-1-8-v;
1119			dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
1120			dma-names = "tx", "rx";
1121		};
1122
1123		sdcc3bam: dma-controller@12182000 {
1124			compatible = "qcom,bam-v1.3.0";
1125			reg = <0x12182000 0x8000>;
1126			interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
1127			clocks = <&gcc SDC3_H_CLK>;
1128			clock-names = "bam_clk";
1129			#dma-cells = <1>;
1130			qcom,ee = <0>;
1131		};
1132
1133		sdcc4: mmc@121c0000 {
1134			compatible = "arm,pl18x", "arm,primecell";
1135			arm,primecell-periphid = <0x00051180>;
1136			status = "disabled";
1137			reg = <0x121c0000 0x2000>;
1138			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1139			clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
1140			clock-names = "mclk", "apb_pclk";
1141			bus-width = <4>;
1142			cap-sd-highspeed;
1143			cap-mmc-highspeed;
1144			max-frequency = <48000000>;
1145			dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
1146			dma-names = "tx", "rx";
1147			pinctrl-names = "default";
1148			pinctrl-0 = <&sdc4_gpios>;
1149		};
1150
1151		sdcc4bam: dma-controller@121c2000 {
1152			compatible = "qcom,bam-v1.3.0";
1153			reg = <0x121c2000 0x8000>;
1154			interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
1155			clocks = <&gcc SDC4_H_CLK>;
1156			clock-names = "bam_clk";
1157			#dma-cells = <1>;
1158			qcom,ee = <0>;
1159		};
1160
1161		sdcc1: mmc@12400000 {
1162			status = "disabled";
1163			compatible = "arm,pl18x", "arm,primecell";
1164			pinctrl-names = "default";
1165			pinctrl-0 = <&sdcc1_pins>;
1166			arm,primecell-periphid = <0x00051180>;
1167			reg = <0x12400000 0x2000>;
1168			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1169			clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
1170			clock-names = "mclk", "apb_pclk";
1171			bus-width = <8>;
1172			max-frequency = <96000000>;
1173			non-removable;
1174			cap-sd-highspeed;
1175			cap-mmc-highspeed;
1176			dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
1177			dma-names = "tx", "rx";
1178		};
1179
1180		sdcc1bam: dma-controller@12402000 {
1181			compatible = "qcom,bam-v1.3.0";
1182			reg = <0x12402000 0x8000>;
1183			interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
1184			clocks = <&gcc SDC1_H_CLK>;
1185			clock-names = "bam_clk";
1186			#dma-cells = <1>;
1187			qcom,ee = <0>;
1188		};
1189
1190		tcsr: syscon@1a400000 {
1191			compatible = "qcom,tcsr-apq8064", "syscon";
1192			reg = <0x1a400000 0x100>;
1193		};
1194
1195		gpu: adreno-3xx@4300000 {
1196			compatible = "qcom,adreno-320.2", "qcom,adreno";
1197			reg = <0x04300000 0x20000>;
1198			reg-names = "kgsl_3d0_reg_memory";
1199			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1200			interrupt-names = "kgsl_3d0_irq";
1201			clock-names =
1202			    "core",
1203			    "iface",
1204			    "mem",
1205			    "mem_iface";
1206			clocks =
1207			    <&mmcc GFX3D_CLK>,
1208			    <&mmcc GFX3D_AHB_CLK>,
1209			    <&mmcc GFX3D_AXI_CLK>,
1210			    <&mmcc MMSS_IMEM_AHB_CLK>;
1211
1212			iommus = <&gfx3d 0
1213				  &gfx3d 1
1214				  &gfx3d 2
1215				  &gfx3d 3
1216				  &gfx3d 4
1217				  &gfx3d 5
1218				  &gfx3d 6
1219				  &gfx3d 7
1220				  &gfx3d 8
1221				  &gfx3d 9
1222				  &gfx3d 10
1223				  &gfx3d 11
1224				  &gfx3d 12
1225				  &gfx3d 13
1226				  &gfx3d 14
1227				  &gfx3d 15
1228				  &gfx3d 16
1229				  &gfx3d 17
1230				  &gfx3d 18
1231				  &gfx3d 19
1232				  &gfx3d 20
1233				  &gfx3d 21
1234				  &gfx3d 22
1235				  &gfx3d 23
1236				  &gfx3d 24
1237				  &gfx3d 25
1238				  &gfx3d 26
1239				  &gfx3d 27
1240				  &gfx3d 28
1241				  &gfx3d 29
1242				  &gfx3d 30
1243				  &gfx3d 31
1244				  &gfx3d1 0
1245				  &gfx3d1 1
1246				  &gfx3d1 2
1247				  &gfx3d1 3
1248				  &gfx3d1 4
1249				  &gfx3d1 5
1250				  &gfx3d1 6
1251				  &gfx3d1 7
1252				  &gfx3d1 8
1253				  &gfx3d1 9
1254				  &gfx3d1 10
1255				  &gfx3d1 11
1256				  &gfx3d1 12
1257				  &gfx3d1 13
1258				  &gfx3d1 14
1259				  &gfx3d1 15
1260				  &gfx3d1 16
1261				  &gfx3d1 17
1262				  &gfx3d1 18
1263				  &gfx3d1 19
1264				  &gfx3d1 20
1265				  &gfx3d1 21
1266				  &gfx3d1 22
1267				  &gfx3d1 23
1268				  &gfx3d1 24
1269				  &gfx3d1 25
1270				  &gfx3d1 26
1271				  &gfx3d1 27
1272				  &gfx3d1 28
1273				  &gfx3d1 29
1274				  &gfx3d1 30
1275				  &gfx3d1 31>;
1276
1277			operating-points-v2 = <&gpu_opp_table>;
1278
1279			gpu_opp_table: opp-table {
1280				compatible = "operating-points-v2";
1281
1282				opp-450000000 {
1283					opp-hz = /bits/ 64 <450000000>;
1284				};
1285
1286				opp-27000000 {
1287					opp-hz = /bits/ 64 <27000000>;
1288				};
1289			};
1290		};
1291
1292		mmss_sfpb: syscon@5700000 {
1293			compatible = "syscon";
1294			reg = <0x5700000 0x70>;
1295		};
1296
1297		dsi0: dsi@4700000 {
1298			compatible = "qcom,apq8064-dsi-ctrl",
1299				     "qcom,mdss-dsi-ctrl";
1300			label = "MDSS DSI CTRL->0";
1301			#address-cells = <1>;
1302			#size-cells = <0>;
1303			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1304			reg = <0x04700000 0x200>;
1305			reg-names = "dsi_ctrl";
1306
1307			clocks = <&mmcc DSI_M_AHB_CLK>,
1308				<&mmcc DSI_S_AHB_CLK>,
1309				<&mmcc AMP_AHB_CLK>,
1310				<&mmcc DSI_CLK>,
1311				<&mmcc DSI1_BYTE_CLK>,
1312				<&mmcc DSI_PIXEL_CLK>,
1313				<&mmcc DSI1_ESC_CLK>;
1314			clock-names = "iface", "bus", "core_mmss",
1315					"src", "byte", "pixel",
1316					"core";
1317
1318			assigned-clocks = <&mmcc DSI1_BYTE_SRC>,
1319					<&mmcc DSI1_ESC_SRC>,
1320					<&mmcc DSI_SRC>,
1321					<&mmcc DSI_PIXEL_SRC>;
1322			assigned-clock-parents = <&dsi0_phy 0>,
1323						<&dsi0_phy 0>,
1324						<&dsi0_phy 1>,
1325						<&dsi0_phy 1>;
1326			syscon-sfpb = <&mmss_sfpb>;
1327			phys = <&dsi0_phy>;
1328			status = "disabled";
1329
1330			ports {
1331				#address-cells = <1>;
1332				#size-cells = <0>;
1333
1334				port@0 {
1335					reg = <0>;
1336					dsi0_in: endpoint {
1337					};
1338				};
1339
1340				port@1 {
1341					reg = <1>;
1342					dsi0_out: endpoint {
1343					};
1344				};
1345			};
1346		};
1347
1348
1349		dsi0_phy: phy@4700200 {
1350			compatible = "qcom,dsi-phy-28nm-8960";
1351			#clock-cells = <1>;
1352			#phy-cells = <0>;
1353
1354			reg = <0x04700200 0x100>,
1355				<0x04700300 0x200>,
1356				<0x04700500 0x5c>;
1357			reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator";
1358			clock-names = "iface", "ref";
1359			clocks = <&mmcc DSI_M_AHB_CLK>,
1360				 <&pxo_board>;
1361			status = "disabled";
1362		};
1363
1364		dsi1: dsi@5800000 {
1365			compatible = "qcom,mdss-dsi-ctrl";
1366			interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
1367			reg = <0x05800000 0x200>;
1368			reg-names = "dsi_ctrl";
1369
1370			clocks = <&mmcc DSI2_M_AHB_CLK>,
1371				 <&mmcc DSI2_S_AHB_CLK>,
1372				 <&mmcc AMP_AHB_CLK>,
1373				 <&mmcc DSI2_CLK>,
1374				 <&mmcc DSI2_BYTE_CLK>,
1375				 <&mmcc DSI2_PIXEL_CLK>,
1376				 <&mmcc DSI2_ESC_CLK>;
1377			clock-names = "iface",
1378				      "bus",
1379				      "core_mmss",
1380				      "src",
1381				      "byte",
1382				      "pixel",
1383				      "core";
1384
1385			assigned-clocks = <&mmcc DSI2_BYTE_SRC>,
1386					  <&mmcc DSI2_ESC_SRC>,
1387					  <&mmcc DSI2_SRC>,
1388					  <&mmcc DSI2_PIXEL_SRC>;
1389			assigned-clock-parents = <&dsi1_phy 0>,
1390						 <&dsi1_phy 0>,
1391						 <&dsi1_phy 1>,
1392						 <&dsi1_phy 1>;
1393
1394			syscon-sfpb = <&mmss_sfpb>;
1395			phys = <&dsi1_phy>;
1396
1397			#address-cells = <1>;
1398			#size-cells = <0>;
1399
1400			status = "disabled";
1401
1402			ports {
1403				#address-cells = <1>;
1404				#size-cells = <0>;
1405
1406				port@0 {
1407					reg = <0>;
1408					dsi1_in: endpoint {
1409					};
1410				};
1411
1412				port@1 {
1413					reg = <1>;
1414					dsi1_out: endpoint {
1415					};
1416				};
1417			};
1418		};
1419
1420
1421		dsi1_phy: dsi-phy@5800200 {
1422			compatible = "qcom,dsi-phy-28nm-8960";
1423			reg = <0x05800200 0x100>,
1424			      <0x05800300 0x200>,
1425			      <0x05800500 0x5c>;
1426			reg-names = "dsi_pll",
1427				    "dsi_phy",
1428				    "dsi_phy_regulator";
1429			clock-names = "iface",
1430				      "ref";
1431			clocks = <&mmcc DSI2_M_AHB_CLK>,
1432				 <&pxo_board>;
1433			#clock-cells = <1>;
1434			#phy-cells = <0>;
1435
1436			status = "disabled";
1437		};
1438
1439		mdp_port0: iommu@7500000 {
1440			compatible = "qcom,apq8064-iommu";
1441			#iommu-cells = <1>;
1442			clock-names =
1443			    "smmu_pclk",
1444			    "iommu_clk";
1445			clocks =
1446			    <&mmcc SMMU_AHB_CLK>,
1447			    <&mmcc MDP_AXI_CLK>;
1448			reg = <0x07500000 0x100000>;
1449			interrupts =
1450			    <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
1451			    <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
1452			qcom,ncb = <2>;
1453		};
1454
1455		mdp_port1: iommu@7600000 {
1456			compatible = "qcom,apq8064-iommu";
1457			#iommu-cells = <1>;
1458			clock-names =
1459			    "smmu_pclk",
1460			    "iommu_clk";
1461			clocks =
1462			    <&mmcc SMMU_AHB_CLK>,
1463			    <&mmcc MDP_AXI_CLK>;
1464			reg = <0x07600000 0x100000>;
1465			interrupts =
1466			    <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
1467			    <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1468			qcom,ncb = <2>;
1469		};
1470
1471		gfx3d: iommu@7c00000 {
1472			compatible = "qcom,apq8064-iommu";
1473			#iommu-cells = <1>;
1474			clock-names =
1475			    "smmu_pclk",
1476			    "iommu_clk";
1477			clocks =
1478			    <&mmcc SMMU_AHB_CLK>,
1479			    <&mmcc GFX3D_AXI_CLK>;
1480			reg = <0x07c00000 0x100000>;
1481			interrupts =
1482			    <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
1483			    <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1484			qcom,ncb = <3>;
1485		};
1486
1487		gfx3d1: iommu@7d00000 {
1488			compatible = "qcom,apq8064-iommu";
1489			#iommu-cells = <1>;
1490			clock-names =
1491			    "smmu_pclk",
1492			    "iommu_clk";
1493			clocks =
1494			    <&mmcc SMMU_AHB_CLK>,
1495			    <&mmcc GFX3D_AXI_CLK>;
1496			reg = <0x07d00000 0x100000>;
1497			interrupts =
1498			    <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
1499			    <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
1500			qcom,ncb = <3>;
1501		};
1502
1503		pcie: pci@1b500000 {
1504			compatible = "qcom,pcie-apq8064";
1505			reg = <0x1b500000 0x1000>,
1506			      <0x1b502000 0x80>,
1507			      <0x1b600000 0x100>,
1508			      <0x0ff00000 0x100000>;
1509			reg-names = "dbi", "elbi", "parf", "config";
1510			device_type = "pci";
1511			linux,pci-domain = <0>;
1512			bus-range = <0x00 0xff>;
1513			num-lanes = <1>;
1514			#address-cells = <3>;
1515			#size-cells = <2>;
1516			ranges = <0x81000000 0x0 0x00000000 0x0fe00000 0x0 0x00100000>, /* I/O */
1517				 <0x82000000 0x0 0x08000000 0x08000000 0x0 0x07e00000>; /* mem */
1518			interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
1519			interrupt-names = "msi";
1520			#interrupt-cells = <1>;
1521			interrupt-map-mask = <0 0 0 0x7>;
1522			interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1523					<0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1524					<0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1525					<0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1526			clocks = <&gcc PCIE_A_CLK>,
1527				 <&gcc PCIE_H_CLK>,
1528				 <&gcc PCIE_PHY_REF_CLK>;
1529			clock-names = "core", "iface", "phy";
1530			resets = <&gcc PCIE_ACLK_RESET>,
1531				 <&gcc PCIE_HCLK_RESET>,
1532				 <&gcc PCIE_POR_RESET>,
1533				 <&gcc PCIE_PCI_RESET>,
1534				 <&gcc PCIE_PHY_RESET>;
1535			reset-names = "axi", "ahb", "por", "pci", "phy";
1536			status = "disabled";
1537		};
1538
1539		hdmi: hdmi-tx@4a00000 {
1540			compatible = "qcom,hdmi-tx-8960";
1541			pinctrl-names = "default";
1542			pinctrl-0 = <&hdmi_pinctrl>;
1543			reg = <0x04a00000 0x2f0>;
1544			reg-names = "core_physical";
1545			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1546			clocks = <&mmcc HDMI_APP_CLK>,
1547				 <&mmcc HDMI_M_AHB_CLK>,
1548				 <&mmcc HDMI_S_AHB_CLK>;
1549			clock-names = "core",
1550				      "master_iface",
1551				      "slave_iface";
1552
1553			phys = <&hdmi_phy>;
1554
1555			status = "disabled";
1556
1557			ports {
1558				#address-cells = <1>;
1559				#size-cells = <0>;
1560
1561				port@0 {
1562					reg = <0>;
1563					hdmi_in: endpoint {
1564					};
1565				};
1566
1567				port@1 {
1568					reg = <1>;
1569					hdmi_out: endpoint {
1570					};
1571				};
1572			};
1573		};
1574
1575		hdmi_phy: phy@4a00400 {
1576			compatible = "qcom,hdmi-phy-8960";
1577			reg = <0x4a00400 0x60>,
1578			      <0x4a00500 0x100>;
1579			reg-names = "hdmi_phy",
1580				    "hdmi_pll";
1581
1582			clocks = <&mmcc HDMI_S_AHB_CLK>;
1583			clock-names = "slave_iface";
1584			#phy-cells = <0>;
1585			#clock-cells = <0>;
1586
1587			status = "disabled";
1588		};
1589
1590		mdp: display-controller@5100000 {
1591			compatible = "qcom,mdp4";
1592			reg = <0x05100000 0xf0000>;
1593			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1594			clocks = <&mmcc MDP_CLK>,
1595				 <&mmcc MDP_AHB_CLK>,
1596				 <&mmcc MDP_AXI_CLK>,
1597				 <&mmcc MDP_LUT_CLK>,
1598				 <&mmcc HDMI_TV_CLK>,
1599				 <&mmcc MDP_TV_CLK>;
1600			clock-names = "core_clk",
1601				      "iface_clk",
1602				      "bus_clk",
1603				      "lut_clk",
1604				      "hdmi_clk",
1605				      "tv_clk";
1606
1607			iommus = <&mdp_port0 0
1608				  &mdp_port0 2
1609				  &mdp_port1 0
1610				  &mdp_port1 2>;
1611
1612			ports {
1613				#address-cells = <1>;
1614				#size-cells = <0>;
1615
1616				port@0 {
1617					reg = <0>;
1618					mdp_lvds_out: endpoint {
1619					};
1620				};
1621
1622				port@1 {
1623					reg = <1>;
1624					mdp_dsi1_out: endpoint {
1625					};
1626				};
1627
1628				port@2 {
1629					reg = <2>;
1630					mdp_dsi2_out: endpoint {
1631					};
1632				};
1633
1634				port@3 {
1635					reg = <3>;
1636					mdp_dtv_out: endpoint {
1637					};
1638				};
1639			};
1640		};
1641
1642		riva: riva-pil@3200800 {
1643			compatible = "qcom,riva-pil";
1644
1645			reg = <0x03200800 0x1000>, <0x03202000 0x2000>, <0x03204000 0x100>;
1646			reg-names = "ccu", "dxe", "pmu";
1647
1648			interrupts-extended = <&intc GIC_SPI 199 IRQ_TYPE_EDGE_RISING>,
1649					      <&wcnss_smsm 6 IRQ_TYPE_EDGE_RISING>;
1650			interrupt-names = "wdog", "fatal";
1651
1652			memory-region = <&wcnss_mem>;
1653
1654			vddcx-supply = <&pm8921_s3>;
1655			vddmx-supply = <&pm8921_l24>;
1656			vddpx-supply = <&pm8921_s4>;
1657
1658			status = "disabled";
1659
1660			iris {
1661				compatible = "qcom,wcn3660";
1662
1663				clocks = <&cxo_board>;
1664				clock-names = "xo";
1665
1666				vddxo-supply = <&pm8921_l4>;
1667				vddrfa-supply = <&pm8921_s2>;
1668				vddpa-supply = <&pm8921_l10>;
1669				vdddig-supply = <&pm8921_lvs2>;
1670			};
1671
1672			smd-edge {
1673				interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>;
1674
1675				qcom,ipc = <&l2cc 8 25>;
1676				qcom,smd-edge = <6>;
1677
1678				label = "riva";
1679
1680				wcnss {
1681					compatible = "qcom,wcnss";
1682					qcom,smd-channels = "WCNSS_CTRL";
1683
1684					qcom,mmio = <&riva>;
1685
1686					bluetooth {
1687						compatible = "qcom,wcnss-bt";
1688					};
1689
1690					wifi {
1691						compatible = "qcom,wcnss-wlan";
1692
1693						interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
1694							     <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
1695						interrupt-names = "tx", "rx";
1696
1697						qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
1698						qcom,smem-state-names = "tx-enable", "tx-rings-empty";
1699					};
1700				};
1701			};
1702		};
1703
1704		etb@1a01000 {
1705			compatible = "arm,coresight-etb10", "arm,primecell";
1706			reg = <0x1a01000 0x1000>;
1707
1708			clocks = <&rpmcc RPM_QDSS_CLK>;
1709			clock-names = "apb_pclk";
1710
1711			in-ports {
1712				port {
1713					etb_in: endpoint {
1714						remote-endpoint = <&replicator_out0>;
1715					};
1716				};
1717			};
1718		};
1719
1720		tpiu@1a03000 {
1721			compatible = "arm,coresight-tpiu", "arm,primecell";
1722			reg = <0x1a03000 0x1000>;
1723
1724			clocks = <&rpmcc RPM_QDSS_CLK>;
1725			clock-names = "apb_pclk";
1726
1727			in-ports {
1728				port {
1729					tpiu_in: endpoint {
1730						remote-endpoint = <&replicator_out1>;
1731					};
1732				};
1733			};
1734		};
1735
1736		replicator {
1737			compatible = "arm,coresight-static-replicator";
1738
1739			clocks = <&rpmcc RPM_QDSS_CLK>;
1740			clock-names = "apb_pclk";
1741
1742			out-ports {
1743				#address-cells = <1>;
1744				#size-cells = <0>;
1745
1746				port@0 {
1747					reg = <0>;
1748					replicator_out0: endpoint {
1749						remote-endpoint = <&etb_in>;
1750					};
1751				};
1752				port@1 {
1753					reg = <1>;
1754					replicator_out1: endpoint {
1755						remote-endpoint = <&tpiu_in>;
1756					};
1757				};
1758			};
1759
1760			in-ports {
1761				port {
1762					replicator_in: endpoint {
1763						remote-endpoint = <&funnel_out>;
1764					};
1765				};
1766			};
1767		};
1768
1769		funnel@1a04000 {
1770			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1771			reg = <0x1a04000 0x1000>;
1772
1773			clocks = <&rpmcc RPM_QDSS_CLK>;
1774			clock-names = "apb_pclk";
1775
1776			in-ports {
1777				#address-cells = <1>;
1778				#size-cells = <0>;
1779
1780				/*
1781				 * Not described input ports:
1782				 * 2 - connected to STM component
1783				 * 3 - not-connected
1784				 * 6 - not-connected
1785				 * 7 - not-connected
1786				 */
1787				port@0 {
1788					reg = <0>;
1789					funnel_in0: endpoint {
1790						remote-endpoint = <&etm0_out>;
1791					};
1792				};
1793				port@1 {
1794					reg = <1>;
1795					funnel_in1: endpoint {
1796						remote-endpoint = <&etm1_out>;
1797					};
1798				};
1799				port@4 {
1800					reg = <4>;
1801					funnel_in4: endpoint {
1802						remote-endpoint = <&etm2_out>;
1803					};
1804				};
1805				port@5 {
1806					reg = <5>;
1807					funnel_in5: endpoint {
1808						remote-endpoint = <&etm3_out>;
1809					};
1810				};
1811			};
1812
1813			out-ports {
1814				port {
1815					funnel_out: endpoint {
1816						remote-endpoint = <&replicator_in>;
1817					};
1818				};
1819			};
1820		};
1821
1822		etm@1a1c000 {
1823			compatible = "arm,coresight-etm3x", "arm,primecell";
1824			reg = <0x1a1c000 0x1000>;
1825
1826			clocks = <&rpmcc RPM_QDSS_CLK>;
1827			clock-names = "apb_pclk";
1828
1829			cpu = <&CPU0>;
1830
1831			out-ports {
1832				port {
1833					etm0_out: endpoint {
1834						remote-endpoint = <&funnel_in0>;
1835					};
1836				};
1837			};
1838		};
1839
1840		etm@1a1d000 {
1841			compatible = "arm,coresight-etm3x", "arm,primecell";
1842			reg = <0x1a1d000 0x1000>;
1843
1844			clocks = <&rpmcc RPM_QDSS_CLK>;
1845			clock-names = "apb_pclk";
1846
1847			cpu = <&CPU1>;
1848
1849			out-ports {
1850				port {
1851					etm1_out: endpoint {
1852						remote-endpoint = <&funnel_in1>;
1853					};
1854				};
1855			};
1856		};
1857
1858		etm@1a1e000 {
1859			compatible = "arm,coresight-etm3x", "arm,primecell";
1860			reg = <0x1a1e000 0x1000>;
1861
1862			clocks = <&rpmcc RPM_QDSS_CLK>;
1863			clock-names = "apb_pclk";
1864
1865			cpu = <&CPU2>;
1866
1867			out-ports {
1868				port {
1869					etm2_out: endpoint {
1870						remote-endpoint = <&funnel_in4>;
1871					};
1872				};
1873			};
1874		};
1875
1876		etm@1a1f000 {
1877			compatible = "arm,coresight-etm3x", "arm,primecell";
1878			reg = <0x1a1f000 0x1000>;
1879
1880			clocks = <&rpmcc RPM_QDSS_CLK>;
1881			clock-names = "apb_pclk";
1882
1883			cpu = <&CPU3>;
1884
1885			out-ports {
1886				port {
1887					etm3_out: endpoint {
1888						remote-endpoint = <&funnel_in5>;
1889					};
1890				};
1891			};
1892		};
1893	};
1894};
1895#include "qcom-apq8064-pins.dtsi"
1896