| bb61c536 | 10-May-2018 |
Shawn Guo <shawn.guo@linaro.org> |
arm64: dts: hi3798cv200: enable emmc support for poplar board
It adds pinctrl device pinconf@8a21000, gpio-ranges for GPIO devices,
and then enables eMMC support for Hi3798CV200 Poplar board.
Signe
arm64: dts: hi3798cv200: enable emmc support for poplar board
It adds pinctrl device pinconf@8a21000, gpio-ranges for GPIO devices,
and then enables eMMC support for Hi3798CV200 Poplar board.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
show more ...
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| e83474c6 | 10-May-2018 |
Shawn Guo <shawn.guo@linaro.org> |
arm64: dts: hi3798cv200: enable usb2 support for poplar board
It adds usb2 phy devices, and enables ehci/ohci support for Hi3798CV200
Poplar board.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
S
arm64: dts: hi3798cv200: enable usb2 support for poplar board
It adds usb2 phy devices, and enables ehci/ohci support for Hi3798CV200
Poplar board.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
show more ...
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| d2a1606c | 30-Apr-2018 |
John Garry <john.garry@huawei.com> |
arm64: dts: hisi: Enable Hisi LPC node for hip07
The patch enables the HiSi LPC node for hip07, with
the IPMI child device.
Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Wei Xu <
arm64: dts: hisi: Enable Hisi LPC node for hip07
The patch enables the HiSi LPC node for hip07, with
the IPMI child device.
Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
show more ...
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| 291985c4 | 30-Apr-2018 |
John Garry <john.garry@huawei.com> |
arm64: dts: hisi: Enable Hisi LPC node for hip06
The patch enables the HiSi LPC node for hip06, with
IPMI and UART child devices.
Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: We
arm64: dts: hisi: Enable Hisi LPC node for hip06
The patch enables the HiSi LPC node for hip06, with
IPMI and UART child devices.
Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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| 8d93e94b | 14-May-2018 |
Tao Wang <jean.wangtao@linaro.org> |
arm64: dts: hi3660: Add thermal cooling management
Add nodes and properties for thermal cooling management support.
Signed-off-by: Tao Wang <jean.wangtao@linaro.org>
Signed-off-by: Leo Yan <leo.yan
arm64: dts: hi3660: Add thermal cooling management
Add nodes and properties for thermal cooling management support.
Signed-off-by: Tao Wang <jean.wangtao@linaro.org>
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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| dfeae9e5 | 14-May-2018 |
Leo Yan <leo.yan@linaro.org> |
arm64: dts: hi3660: Add CPU frequency scaling support
Add two CPU OPP tables, one table is corresponding to one cluster,
which allow CPU frequency scaling on hi3660 platforms.
Signed-off-by: Leo Ya
arm64: dts: hi3660: Add CPU frequency scaling support
Add two CPU OPP tables, one table is corresponding to one cluster,
which allow CPU frequency scaling on hi3660 platforms.
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
show more ...
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| 6e2c52b3 | 14-May-2018 |
Kaihua Zhong <zhongkaihua@huawei.com> |
arm64: dts: hi3660: Add stub clock node
Add stub clock node for hi3660 platform.
Reviewed-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Kaihua Zhong <zhongkaihua@huawei.com>
Signed-off-by: Leo Ya
arm64: dts: hi3660: Add stub clock node
Add stub clock node for hi3660 platform.
Reviewed-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Kaihua Zhong <zhongkaihua@huawei.com>
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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| 928c4a5c | 08-Jan-2018 |
Leo Yan <leo.yan@linaro.org> |
arm64: dts: Hi3660: Remove 'CPU_NAP' idle state
Thanks a lot for Vincent Guittot careful work to find bug for 'CPU_NAP'
idle state. At early time, the CPU CA73 CPU_NAP idle state has been
supported
arm64: dts: Hi3660: Remove 'CPU_NAP' idle state
Thanks a lot for Vincent Guittot careful work to find bug for 'CPU_NAP'
idle state. At early time, the CPU CA73 CPU_NAP idle state has been
supported on Hikey960. Later we found the system has the hang issue
and for resolving this issue Hisilicon released new MCU firmware, but
unfortunately the new MCU firmware has side effect and results in the
CA73 CPU cannot really enter CPU_NAP state and roll back to WFI state.
After discussion we cannot see the possibility to enable CA73 CPU_NAP
state anymore on Hikey960, based on this conclusion we should remove
this state from DT binding.
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Kevin Wang <jean.wangtao@linaro.org>
Cc: Vincent Guittot <vincent.guittot@linaro.org>
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Tested-by: Vincent Guittot <vincent.guittot@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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| 183879d8 | 09-Feb-2018 |
Viresh Kumar <viresh.kumar@linaro.org> |
ARM64: dts: hi6220: Remove "cooling-{min|max}-level" for CPU nodes
The "cooling-min-level" and "cooling-max-level" properties are not
parsed by any part of the kernel currently and the max cooling s
ARM64: dts: hi6220: Remove "cooling-{min|max}-level" for CPU nodes
The "cooling-min-level" and "cooling-max-level" properties are not
parsed by any part of the kernel currently and the max cooling state of
a CPU cooling device is found by referring to the cpufreq table instead.
Moreover, the entries are incorrect here as min level is 4 and the max
level is 0.
Remove the unused properties from the CPU nodes.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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| abd7d097 | 17-Jan-2018 |
oscardagrach <ryan@edited.us> |
arm64: dts: hikey: Enable HS200 mode on eMMC
According to the hi6220 datasheet, the MMC controller is JEDEC eMMC 4.5
compliant, in addition to supporting a clock of up to 150MHz. The Hikey
schematic
arm64: dts: hikey: Enable HS200 mode on eMMC
According to the hi6220 datasheet, the MMC controller is JEDEC eMMC 4.5
compliant, in addition to supporting a clock of up to 150MHz. The Hikey
schematic also indicates the device utilizes 1.8v signaling. Define these
parameters in the device tree to enable HS200 mode.
Signed-off-by: Ryan Grachek <ryan@edited.us>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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| 17f21343 | 14-Dec-2017 |
Shameerali Kolothum Thodi <shameerali.kolothum.thodi@huawei.com> |
arm64: dts: hisi: Disable hisilicon smmu node on hip06/hip07
The HiSilicon erratum 161010801 describes the limitation of
HiSilicon platforms hip06/hip07 to support the SMMUv3 mappings
for MSI transa
arm64: dts: hisi: Disable hisilicon smmu node on hip06/hip07
The HiSilicon erratum 161010801 describes the limitation of
HiSilicon platforms hip06/hip07 to support the SMMUv3 mappings
for MSI transactions.
PCIe controller on these platforms has to differentiate the
MSI payload against other DMA payload and has to modify the
MSI payload. This makes it difficult for these platforms to
have SMMU translation for MSI. In order to workaround this,
ARM SMMUv3 driver requires a quirk to treat the MSI regions
separately. Such a quirk is currently missing for DT based
systems and therefore we need to explicitly disable the
hip06/hip07 smmu entries in dts.
Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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| 9a9760de | 13-Dec-2017 |
Valentin Schneider <valentin.schneider@arm.com> |
arm64: dts: hisilicon: Add hi3660 cpu capacity-dmips-mhz information
The following dt entries are added:
cpus [0-3] (Cortex A53):
- capacity-dmips-mhz = <592>;
cpus [4-7] (Cortex A73):
- ca
arm64: dts: hisilicon: Add hi3660 cpu capacity-dmips-mhz information
The following dt entries are added:
cpus [0-3] (Cortex A53):
- capacity-dmips-mhz = <592>;
cpus [4-7] (Cortex A73):
- capacity-dmips-mhz = <1024>;
Those values were obtained by running dhrystone 2.1 on a
HiKey960 with the following procedure:
- Offline all CPUs but CPU0 (A53)
- Set CPU0 frequency to maximum
- Run Dhrystone 2.1 for 20 seconds
- Offline all CPUs but CPU4 (A73)
- set CPU4 frequency to maximum
- Run Dhrystone 2.1 for 20 seconds
The results are as follows:
A53: 129633887 loops
A73: 287034147 loops
By scaling those values so that the A73s use 1024, we end up with 462
for the A53s. However, they have different maximum frequencies:
1.844GHz for A53s and 2.362GHz for A73s. Thus, we can scale the A53
value to truly represent dmips per MHz, and we end up with 592.
The impact of this change can be verified on HiKey960:
$ cat /sys/devices/system/cpu/cpu*/cpufreq/scaling_cur_freq
1844000
1844000
1844000
1844000
2362000
2362000
2362000
2362000
$ cat /sys/devices/system/cpu/cpu*/cpu_capacity
462
462
462
462
1024
1024
1024
1024
Signed-off-by: Valentin Schneider <valentin.schneider@arm.com>
Reviewed-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
show more ...
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| e07642fa | 09-Nov-2017 |
Xu YiPing <xuyiping@hisilicon.com> |
arm64: dts: hi3660: improve pmu description
cortex-a73 pmu driver is supported now. hi3660 is 4*a73 + 4*a53, so it
should use "cortex-a73-pmu" and "cortex-a53-pmu" instead of "armpmu-v3",
then we ca
arm64: dts: hi3660: improve pmu description
cortex-a73 pmu driver is supported now. hi3660 is 4*a73 + 4*a53, so it
should use "cortex-a73-pmu" and "cortex-a53-pmu" instead of "armpmu-v3",
then we can use the a73 and a53 events in perf tool directly.
Signed-off-by: Xu YiPing <xuyiping@hisilicon.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
show more ...
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| b6fff603 | 06-Nov-2017 |
Amit Kucheria <amit.kucheria@linaro.org> |
arm64: dts: hisilicon: hi6220-hikey: Allow USR1 LED to notify kernel panic
Blink the LED on a kernel panic.
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Acked-by: Guodong Xu <guodong.xu@
arm64: dts: hisilicon: hi6220-hikey: Allow USR1 LED to notify kernel panic
Blink the LED on a kernel panic.
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Acked-by: Guodong Xu <guodong.xu@linaro.org>
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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