1 /* SuperH Ethernet device driver 2 * 3 * Copyright (C) 2014 Renesas Electronics Corporation 4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu 5 * Copyright (C) 2008-2014 Renesas Solutions Corp. 6 * Copyright (C) 2013-2017 Cogent Embedded, Inc. 7 * Copyright (C) 2014 Codethink Limited 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms and conditions of the GNU General Public License, 11 * version 2, as published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope it will be useful, but WITHOUT 14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 16 * more details. 17 * 18 * The full GNU General Public License is included in this distribution in 19 * the file called "COPYING". 20 */ 21 22 #include <linux/module.h> 23 #include <linux/kernel.h> 24 #include <linux/spinlock.h> 25 #include <linux/interrupt.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/etherdevice.h> 28 #include <linux/delay.h> 29 #include <linux/platform_device.h> 30 #include <linux/mdio-bitbang.h> 31 #include <linux/netdevice.h> 32 #include <linux/of.h> 33 #include <linux/of_device.h> 34 #include <linux/of_irq.h> 35 #include <linux/of_net.h> 36 #include <linux/phy.h> 37 #include <linux/cache.h> 38 #include <linux/io.h> 39 #include <linux/pm_runtime.h> 40 #include <linux/slab.h> 41 #include <linux/ethtool.h> 42 #include <linux/if_vlan.h> 43 #include <linux/sh_eth.h> 44 #include <linux/of_mdio.h> 45 46 #include "sh_eth.h" 47 48 #define SH_ETH_DEF_MSG_ENABLE \ 49 (NETIF_MSG_LINK | \ 50 NETIF_MSG_TIMER | \ 51 NETIF_MSG_RX_ERR| \ 52 NETIF_MSG_TX_ERR) 53 54 #define SH_ETH_OFFSET_INVALID ((u16)~0) 55 56 #define SH_ETH_OFFSET_DEFAULTS \ 57 [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID 58 59 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = { 60 SH_ETH_OFFSET_DEFAULTS, 61 62 [EDSR] = 0x0000, 63 [EDMR] = 0x0400, 64 [EDTRR] = 0x0408, 65 [EDRRR] = 0x0410, 66 [EESR] = 0x0428, 67 [EESIPR] = 0x0430, 68 [TDLAR] = 0x0010, 69 [TDFAR] = 0x0014, 70 [TDFXR] = 0x0018, 71 [TDFFR] = 0x001c, 72 [RDLAR] = 0x0030, 73 [RDFAR] = 0x0034, 74 [RDFXR] = 0x0038, 75 [RDFFR] = 0x003c, 76 [TRSCER] = 0x0438, 77 [RMFCR] = 0x0440, 78 [TFTR] = 0x0448, 79 [FDR] = 0x0450, 80 [RMCR] = 0x0458, 81 [RPADIR] = 0x0460, 82 [FCFTR] = 0x0468, 83 [CSMR] = 0x04E4, 84 85 [ECMR] = 0x0500, 86 [ECSR] = 0x0510, 87 [ECSIPR] = 0x0518, 88 [PIR] = 0x0520, 89 [PSR] = 0x0528, 90 [PIPR] = 0x052c, 91 [RFLR] = 0x0508, 92 [APR] = 0x0554, 93 [MPR] = 0x0558, 94 [PFTCR] = 0x055c, 95 [PFRCR] = 0x0560, 96 [TPAUSER] = 0x0564, 97 [GECMR] = 0x05b0, 98 [BCULR] = 0x05b4, 99 [MAHR] = 0x05c0, 100 [MALR] = 0x05c8, 101 [TROCR] = 0x0700, 102 [CDCR] = 0x0708, 103 [LCCR] = 0x0710, 104 [CEFCR] = 0x0740, 105 [FRECR] = 0x0748, 106 [TSFRCR] = 0x0750, 107 [TLFRCR] = 0x0758, 108 [RFCR] = 0x0760, 109 [CERCR] = 0x0768, 110 [CEECR] = 0x0770, 111 [MAFCR] = 0x0778, 112 [RMII_MII] = 0x0790, 113 114 [ARSTR] = 0x0000, 115 [TSU_CTRST] = 0x0004, 116 [TSU_FWEN0] = 0x0010, 117 [TSU_FWEN1] = 0x0014, 118 [TSU_FCM] = 0x0018, 119 [TSU_BSYSL0] = 0x0020, 120 [TSU_BSYSL1] = 0x0024, 121 [TSU_PRISL0] = 0x0028, 122 [TSU_PRISL1] = 0x002c, 123 [TSU_FWSL0] = 0x0030, 124 [TSU_FWSL1] = 0x0034, 125 [TSU_FWSLC] = 0x0038, 126 [TSU_QTAG0] = 0x0040, 127 [TSU_QTAG1] = 0x0044, 128 [TSU_FWSR] = 0x0050, 129 [TSU_FWINMK] = 0x0054, 130 [TSU_ADQT0] = 0x0048, 131 [TSU_ADQT1] = 0x004c, 132 [TSU_VTAG0] = 0x0058, 133 [TSU_VTAG1] = 0x005c, 134 [TSU_ADSBSY] = 0x0060, 135 [TSU_TEN] = 0x0064, 136 [TSU_POST1] = 0x0070, 137 [TSU_POST2] = 0x0074, 138 [TSU_POST3] = 0x0078, 139 [TSU_POST4] = 0x007c, 140 [TSU_ADRH0] = 0x0100, 141 142 [TXNLCR0] = 0x0080, 143 [TXALCR0] = 0x0084, 144 [RXNLCR0] = 0x0088, 145 [RXALCR0] = 0x008c, 146 [FWNLCR0] = 0x0090, 147 [FWALCR0] = 0x0094, 148 [TXNLCR1] = 0x00a0, 149 [TXALCR1] = 0x00a4, 150 [RXNLCR1] = 0x00a8, 151 [RXALCR1] = 0x00ac, 152 [FWNLCR1] = 0x00b0, 153 [FWALCR1] = 0x00b4, 154 }; 155 156 static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = { 157 SH_ETH_OFFSET_DEFAULTS, 158 159 [EDSR] = 0x0000, 160 [EDMR] = 0x0400, 161 [EDTRR] = 0x0408, 162 [EDRRR] = 0x0410, 163 [EESR] = 0x0428, 164 [EESIPR] = 0x0430, 165 [TDLAR] = 0x0010, 166 [TDFAR] = 0x0014, 167 [TDFXR] = 0x0018, 168 [TDFFR] = 0x001c, 169 [RDLAR] = 0x0030, 170 [RDFAR] = 0x0034, 171 [RDFXR] = 0x0038, 172 [RDFFR] = 0x003c, 173 [TRSCER] = 0x0438, 174 [RMFCR] = 0x0440, 175 [TFTR] = 0x0448, 176 [FDR] = 0x0450, 177 [RMCR] = 0x0458, 178 [RPADIR] = 0x0460, 179 [FCFTR] = 0x0468, 180 [CSMR] = 0x04E4, 181 182 [ECMR] = 0x0500, 183 [RFLR] = 0x0508, 184 [ECSR] = 0x0510, 185 [ECSIPR] = 0x0518, 186 [PIR] = 0x0520, 187 [APR] = 0x0554, 188 [MPR] = 0x0558, 189 [PFTCR] = 0x055c, 190 [PFRCR] = 0x0560, 191 [TPAUSER] = 0x0564, 192 [MAHR] = 0x05c0, 193 [MALR] = 0x05c8, 194 [CEFCR] = 0x0740, 195 [FRECR] = 0x0748, 196 [TSFRCR] = 0x0750, 197 [TLFRCR] = 0x0758, 198 [RFCR] = 0x0760, 199 [MAFCR] = 0x0778, 200 201 [ARSTR] = 0x0000, 202 [TSU_CTRST] = 0x0004, 203 [TSU_FWSLC] = 0x0038, 204 [TSU_VTAG0] = 0x0058, 205 [TSU_ADSBSY] = 0x0060, 206 [TSU_TEN] = 0x0064, 207 [TSU_POST1] = 0x0070, 208 [TSU_POST2] = 0x0074, 209 [TSU_POST3] = 0x0078, 210 [TSU_POST4] = 0x007c, 211 [TSU_ADRH0] = 0x0100, 212 213 [TXNLCR0] = 0x0080, 214 [TXALCR0] = 0x0084, 215 [RXNLCR0] = 0x0088, 216 [RXALCR0] = 0x008C, 217 }; 218 219 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = { 220 SH_ETH_OFFSET_DEFAULTS, 221 222 [ECMR] = 0x0300, 223 [RFLR] = 0x0308, 224 [ECSR] = 0x0310, 225 [ECSIPR] = 0x0318, 226 [PIR] = 0x0320, 227 [PSR] = 0x0328, 228 [RDMLR] = 0x0340, 229 [IPGR] = 0x0350, 230 [APR] = 0x0354, 231 [MPR] = 0x0358, 232 [RFCF] = 0x0360, 233 [TPAUSER] = 0x0364, 234 [TPAUSECR] = 0x0368, 235 [MAHR] = 0x03c0, 236 [MALR] = 0x03c8, 237 [TROCR] = 0x03d0, 238 [CDCR] = 0x03d4, 239 [LCCR] = 0x03d8, 240 [CNDCR] = 0x03dc, 241 [CEFCR] = 0x03e4, 242 [FRECR] = 0x03e8, 243 [TSFRCR] = 0x03ec, 244 [TLFRCR] = 0x03f0, 245 [RFCR] = 0x03f4, 246 [MAFCR] = 0x03f8, 247 248 [EDMR] = 0x0200, 249 [EDTRR] = 0x0208, 250 [EDRRR] = 0x0210, 251 [TDLAR] = 0x0218, 252 [RDLAR] = 0x0220, 253 [EESR] = 0x0228, 254 [EESIPR] = 0x0230, 255 [TRSCER] = 0x0238, 256 [RMFCR] = 0x0240, 257 [TFTR] = 0x0248, 258 [FDR] = 0x0250, 259 [RMCR] = 0x0258, 260 [TFUCR] = 0x0264, 261 [RFOCR] = 0x0268, 262 [RMIIMODE] = 0x026c, 263 [FCFTR] = 0x0270, 264 [TRIMD] = 0x027c, 265 }; 266 267 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = { 268 SH_ETH_OFFSET_DEFAULTS, 269 270 [ECMR] = 0x0100, 271 [RFLR] = 0x0108, 272 [ECSR] = 0x0110, 273 [ECSIPR] = 0x0118, 274 [PIR] = 0x0120, 275 [PSR] = 0x0128, 276 [RDMLR] = 0x0140, 277 [IPGR] = 0x0150, 278 [APR] = 0x0154, 279 [MPR] = 0x0158, 280 [TPAUSER] = 0x0164, 281 [RFCF] = 0x0160, 282 [TPAUSECR] = 0x0168, 283 [BCFRR] = 0x016c, 284 [MAHR] = 0x01c0, 285 [MALR] = 0x01c8, 286 [TROCR] = 0x01d0, 287 [CDCR] = 0x01d4, 288 [LCCR] = 0x01d8, 289 [CNDCR] = 0x01dc, 290 [CEFCR] = 0x01e4, 291 [FRECR] = 0x01e8, 292 [TSFRCR] = 0x01ec, 293 [TLFRCR] = 0x01f0, 294 [RFCR] = 0x01f4, 295 [MAFCR] = 0x01f8, 296 [RTRATE] = 0x01fc, 297 298 [EDMR] = 0x0000, 299 [EDTRR] = 0x0008, 300 [EDRRR] = 0x0010, 301 [TDLAR] = 0x0018, 302 [RDLAR] = 0x0020, 303 [EESR] = 0x0028, 304 [EESIPR] = 0x0030, 305 [TRSCER] = 0x0038, 306 [RMFCR] = 0x0040, 307 [TFTR] = 0x0048, 308 [FDR] = 0x0050, 309 [RMCR] = 0x0058, 310 [TFUCR] = 0x0064, 311 [RFOCR] = 0x0068, 312 [FCFTR] = 0x0070, 313 [RPADIR] = 0x0078, 314 [TRIMD] = 0x007c, 315 [RBWAR] = 0x00c8, 316 [RDFAR] = 0x00cc, 317 [TBRAR] = 0x00d4, 318 [TDFAR] = 0x00d8, 319 }; 320 321 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = { 322 SH_ETH_OFFSET_DEFAULTS, 323 324 [EDMR] = 0x0000, 325 [EDTRR] = 0x0004, 326 [EDRRR] = 0x0008, 327 [TDLAR] = 0x000c, 328 [RDLAR] = 0x0010, 329 [EESR] = 0x0014, 330 [EESIPR] = 0x0018, 331 [TRSCER] = 0x001c, 332 [RMFCR] = 0x0020, 333 [TFTR] = 0x0024, 334 [FDR] = 0x0028, 335 [RMCR] = 0x002c, 336 [EDOCR] = 0x0030, 337 [FCFTR] = 0x0034, 338 [RPADIR] = 0x0038, 339 [TRIMD] = 0x003c, 340 [RBWAR] = 0x0040, 341 [RDFAR] = 0x0044, 342 [TBRAR] = 0x004c, 343 [TDFAR] = 0x0050, 344 345 [ECMR] = 0x0160, 346 [ECSR] = 0x0164, 347 [ECSIPR] = 0x0168, 348 [PIR] = 0x016c, 349 [MAHR] = 0x0170, 350 [MALR] = 0x0174, 351 [RFLR] = 0x0178, 352 [PSR] = 0x017c, 353 [TROCR] = 0x0180, 354 [CDCR] = 0x0184, 355 [LCCR] = 0x0188, 356 [CNDCR] = 0x018c, 357 [CEFCR] = 0x0194, 358 [FRECR] = 0x0198, 359 [TSFRCR] = 0x019c, 360 [TLFRCR] = 0x01a0, 361 [RFCR] = 0x01a4, 362 [MAFCR] = 0x01a8, 363 [IPGR] = 0x01b4, 364 [APR] = 0x01b8, 365 [MPR] = 0x01bc, 366 [TPAUSER] = 0x01c4, 367 [BCFR] = 0x01cc, 368 369 [ARSTR] = 0x0000, 370 [TSU_CTRST] = 0x0004, 371 [TSU_FWEN0] = 0x0010, 372 [TSU_FWEN1] = 0x0014, 373 [TSU_FCM] = 0x0018, 374 [TSU_BSYSL0] = 0x0020, 375 [TSU_BSYSL1] = 0x0024, 376 [TSU_PRISL0] = 0x0028, 377 [TSU_PRISL1] = 0x002c, 378 [TSU_FWSL0] = 0x0030, 379 [TSU_FWSL1] = 0x0034, 380 [TSU_FWSLC] = 0x0038, 381 [TSU_QTAGM0] = 0x0040, 382 [TSU_QTAGM1] = 0x0044, 383 [TSU_ADQT0] = 0x0048, 384 [TSU_ADQT1] = 0x004c, 385 [TSU_FWSR] = 0x0050, 386 [TSU_FWINMK] = 0x0054, 387 [TSU_ADSBSY] = 0x0060, 388 [TSU_TEN] = 0x0064, 389 [TSU_POST1] = 0x0070, 390 [TSU_POST2] = 0x0074, 391 [TSU_POST3] = 0x0078, 392 [TSU_POST4] = 0x007c, 393 394 [TXNLCR0] = 0x0080, 395 [TXALCR0] = 0x0084, 396 [RXNLCR0] = 0x0088, 397 [RXALCR0] = 0x008c, 398 [FWNLCR0] = 0x0090, 399 [FWALCR0] = 0x0094, 400 [TXNLCR1] = 0x00a0, 401 [TXALCR1] = 0x00a4, 402 [RXNLCR1] = 0x00a8, 403 [RXALCR1] = 0x00ac, 404 [FWNLCR1] = 0x00b0, 405 [FWALCR1] = 0x00b4, 406 407 [TSU_ADRH0] = 0x0100, 408 }; 409 410 static void sh_eth_rcv_snd_disable(struct net_device *ndev); 411 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev); 412 413 static void sh_eth_write(struct net_device *ndev, u32 data, int enum_index) 414 { 415 struct sh_eth_private *mdp = netdev_priv(ndev); 416 u16 offset = mdp->reg_offset[enum_index]; 417 418 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID)) 419 return; 420 421 iowrite32(data, mdp->addr + offset); 422 } 423 424 static u32 sh_eth_read(struct net_device *ndev, int enum_index) 425 { 426 struct sh_eth_private *mdp = netdev_priv(ndev); 427 u16 offset = mdp->reg_offset[enum_index]; 428 429 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID)) 430 return ~0U; 431 432 return ioread32(mdp->addr + offset); 433 } 434 435 static void sh_eth_modify(struct net_device *ndev, int enum_index, u32 clear, 436 u32 set) 437 { 438 sh_eth_write(ndev, (sh_eth_read(ndev, enum_index) & ~clear) | set, 439 enum_index); 440 } 441 442 static bool sh_eth_is_gether(struct sh_eth_private *mdp) 443 { 444 return mdp->reg_offset == sh_eth_offset_gigabit; 445 } 446 447 static bool sh_eth_is_rz_fast_ether(struct sh_eth_private *mdp) 448 { 449 return mdp->reg_offset == sh_eth_offset_fast_rz; 450 } 451 452 static void sh_eth_select_mii(struct net_device *ndev) 453 { 454 struct sh_eth_private *mdp = netdev_priv(ndev); 455 u32 value; 456 457 switch (mdp->phy_interface) { 458 case PHY_INTERFACE_MODE_GMII: 459 value = 0x2; 460 break; 461 case PHY_INTERFACE_MODE_MII: 462 value = 0x1; 463 break; 464 case PHY_INTERFACE_MODE_RMII: 465 value = 0x0; 466 break; 467 default: 468 netdev_warn(ndev, 469 "PHY interface mode was not setup. Set to MII.\n"); 470 value = 0x1; 471 break; 472 } 473 474 sh_eth_write(ndev, value, RMII_MII); 475 } 476 477 static void sh_eth_set_duplex(struct net_device *ndev) 478 { 479 struct sh_eth_private *mdp = netdev_priv(ndev); 480 481 sh_eth_modify(ndev, ECMR, ECMR_DM, mdp->duplex ? ECMR_DM : 0); 482 } 483 484 static void sh_eth_chip_reset(struct net_device *ndev) 485 { 486 struct sh_eth_private *mdp = netdev_priv(ndev); 487 488 /* reset device */ 489 sh_eth_tsu_write(mdp, ARSTR_ARST, ARSTR); 490 mdelay(1); 491 } 492 493 static void sh_eth_set_rate_gether(struct net_device *ndev) 494 { 495 struct sh_eth_private *mdp = netdev_priv(ndev); 496 497 switch (mdp->speed) { 498 case 10: /* 10BASE */ 499 sh_eth_write(ndev, GECMR_10, GECMR); 500 break; 501 case 100:/* 100BASE */ 502 sh_eth_write(ndev, GECMR_100, GECMR); 503 break; 504 case 1000: /* 1000BASE */ 505 sh_eth_write(ndev, GECMR_1000, GECMR); 506 break; 507 } 508 } 509 510 #ifdef CONFIG_OF 511 /* R7S72100 */ 512 static struct sh_eth_cpu_data r7s72100_data = { 513 .chip_reset = sh_eth_chip_reset, 514 .set_duplex = sh_eth_set_duplex, 515 516 .register_type = SH_ETH_REG_FAST_RZ, 517 518 .ecsr_value = ECSR_ICD, 519 .ecsipr_value = ECSIPR_ICDIP, 520 .eesipr_value = EESIPR_TWB1IP | EESIPR_TWBIP | EESIPR_TC1IP | 521 EESIPR_TABTIP | EESIPR_RABTIP | EESIPR_RFCOFIP | 522 EESIPR_ECIIP | 523 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 524 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 525 EESIPR_RMAFIP | EESIPR_RRFIP | 526 EESIPR_RTLFIP | EESIPR_RTSFIP | 527 EESIPR_PREIP | EESIPR_CERFIP, 528 529 .tx_check = EESR_TC1 | EESR_FTC, 530 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 531 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | 532 EESR_TDE, 533 .fdr_value = 0x0000070f, 534 535 .no_psr = 1, 536 .apr = 1, 537 .mpr = 1, 538 .tpauser = 1, 539 .hw_swap = 1, 540 .rpadir = 1, 541 .rpadir_value = 2 << 16, 542 .no_trimd = 1, 543 .no_ade = 1, 544 .hw_checksum = 1, 545 .tsu = 1, 546 }; 547 548 static void sh_eth_chip_reset_r8a7740(struct net_device *ndev) 549 { 550 sh_eth_chip_reset(ndev); 551 552 sh_eth_select_mii(ndev); 553 } 554 555 /* R8A7740 */ 556 static struct sh_eth_cpu_data r8a7740_data = { 557 .chip_reset = sh_eth_chip_reset_r8a7740, 558 .set_duplex = sh_eth_set_duplex, 559 .set_rate = sh_eth_set_rate_gether, 560 561 .register_type = SH_ETH_REG_GIGABIT, 562 563 .ecsr_value = ECSR_ICD | ECSR_MPD, 564 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 565 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 566 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 567 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 568 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP | 569 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP | 570 EESIPR_CEEFIP | EESIPR_CELFIP | 571 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 572 EESIPR_PREIP | EESIPR_CERFIP, 573 574 .tx_check = EESR_TC1 | EESR_FTC, 575 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 576 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | 577 EESR_TDE, 578 .fdr_value = 0x0000070f, 579 580 .apr = 1, 581 .mpr = 1, 582 .tpauser = 1, 583 .bculr = 1, 584 .hw_swap = 1, 585 .rpadir = 1, 586 .rpadir_value = 2 << 16, 587 .no_trimd = 1, 588 .no_ade = 1, 589 .hw_checksum = 1, 590 .tsu = 1, 591 .select_mii = 1, 592 .magic = 1, 593 }; 594 595 /* There is CPU dependent code */ 596 static void sh_eth_set_rate_rcar(struct net_device *ndev) 597 { 598 struct sh_eth_private *mdp = netdev_priv(ndev); 599 600 switch (mdp->speed) { 601 case 10: /* 10BASE */ 602 sh_eth_modify(ndev, ECMR, ECMR_ELB, 0); 603 break; 604 case 100:/* 100BASE */ 605 sh_eth_modify(ndev, ECMR, ECMR_ELB, ECMR_ELB); 606 break; 607 } 608 } 609 610 /* R-Car Gen1 */ 611 static struct sh_eth_cpu_data rcar_gen1_data = { 612 .set_duplex = sh_eth_set_duplex, 613 .set_rate = sh_eth_set_rate_rcar, 614 615 .register_type = SH_ETH_REG_FAST_RCAR, 616 617 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD, 618 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP, 619 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP | 620 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 621 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 622 EESIPR_RMAFIP | EESIPR_RRFIP | 623 EESIPR_RTLFIP | EESIPR_RTSFIP | 624 EESIPR_PREIP | EESIPR_CERFIP, 625 626 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, 627 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 628 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, 629 .fdr_value = 0x00000f0f, 630 631 .apr = 1, 632 .mpr = 1, 633 .tpauser = 1, 634 .hw_swap = 1, 635 }; 636 637 /* R-Car Gen2 and RZ/G1 */ 638 static struct sh_eth_cpu_data rcar_gen2_data = { 639 .set_duplex = sh_eth_set_duplex, 640 .set_rate = sh_eth_set_rate_rcar, 641 642 .register_type = SH_ETH_REG_FAST_RCAR, 643 644 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD | ECSR_MPD, 645 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP | 646 ECSIPR_MPDIP, 647 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP | 648 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 649 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 650 EESIPR_RMAFIP | EESIPR_RRFIP | 651 EESIPR_RTLFIP | EESIPR_RTSFIP | 652 EESIPR_PREIP | EESIPR_CERFIP, 653 654 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, 655 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 656 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, 657 .fdr_value = 0x00000f0f, 658 659 .trscer_err_mask = DESC_I_RINT8, 660 661 .apr = 1, 662 .mpr = 1, 663 .tpauser = 1, 664 .hw_swap = 1, 665 .rmiimode = 1, 666 .magic = 1, 667 }; 668 #endif /* CONFIG_OF */ 669 670 static void sh_eth_set_rate_sh7724(struct net_device *ndev) 671 { 672 struct sh_eth_private *mdp = netdev_priv(ndev); 673 674 switch (mdp->speed) { 675 case 10: /* 10BASE */ 676 sh_eth_modify(ndev, ECMR, ECMR_RTM, 0); 677 break; 678 case 100:/* 100BASE */ 679 sh_eth_modify(ndev, ECMR, ECMR_RTM, ECMR_RTM); 680 break; 681 } 682 } 683 684 /* SH7724 */ 685 static struct sh_eth_cpu_data sh7724_data = { 686 .set_duplex = sh_eth_set_duplex, 687 .set_rate = sh_eth_set_rate_sh7724, 688 689 .register_type = SH_ETH_REG_FAST_SH4, 690 691 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD, 692 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP, 693 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP | 694 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 695 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 696 EESIPR_RMAFIP | EESIPR_RRFIP | 697 EESIPR_RTLFIP | EESIPR_RTSFIP | 698 EESIPR_PREIP | EESIPR_CERFIP, 699 700 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, 701 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 702 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, 703 704 .apr = 1, 705 .mpr = 1, 706 .tpauser = 1, 707 .hw_swap = 1, 708 .rpadir = 1, 709 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */ 710 }; 711 712 static void sh_eth_set_rate_sh7757(struct net_device *ndev) 713 { 714 struct sh_eth_private *mdp = netdev_priv(ndev); 715 716 switch (mdp->speed) { 717 case 10: /* 10BASE */ 718 sh_eth_write(ndev, 0, RTRATE); 719 break; 720 case 100:/* 100BASE */ 721 sh_eth_write(ndev, 1, RTRATE); 722 break; 723 } 724 } 725 726 /* SH7757 */ 727 static struct sh_eth_cpu_data sh7757_data = { 728 .set_duplex = sh_eth_set_duplex, 729 .set_rate = sh_eth_set_rate_sh7757, 730 731 .register_type = SH_ETH_REG_FAST_SH4, 732 733 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 734 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 735 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 736 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP | 737 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP | 738 EESIPR_CEEFIP | EESIPR_CELFIP | 739 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 740 EESIPR_PREIP | EESIPR_CERFIP, 741 742 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, 743 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 744 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, 745 746 .irq_flags = IRQF_SHARED, 747 .apr = 1, 748 .mpr = 1, 749 .tpauser = 1, 750 .hw_swap = 1, 751 .no_ade = 1, 752 .rpadir = 1, 753 .rpadir_value = 2 << 16, 754 .rtrate = 1, 755 }; 756 757 #define SH_GIGA_ETH_BASE 0xfee00000UL 758 #define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8) 759 #define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0) 760 static void sh_eth_chip_reset_giga(struct net_device *ndev) 761 { 762 u32 mahr[2], malr[2]; 763 int i; 764 765 /* save MAHR and MALR */ 766 for (i = 0; i < 2; i++) { 767 malr[i] = ioread32((void *)GIGA_MALR(i)); 768 mahr[i] = ioread32((void *)GIGA_MAHR(i)); 769 } 770 771 sh_eth_chip_reset(ndev); 772 773 /* restore MAHR and MALR */ 774 for (i = 0; i < 2; i++) { 775 iowrite32(malr[i], (void *)GIGA_MALR(i)); 776 iowrite32(mahr[i], (void *)GIGA_MAHR(i)); 777 } 778 } 779 780 static void sh_eth_set_rate_giga(struct net_device *ndev) 781 { 782 struct sh_eth_private *mdp = netdev_priv(ndev); 783 784 switch (mdp->speed) { 785 case 10: /* 10BASE */ 786 sh_eth_write(ndev, 0x00000000, GECMR); 787 break; 788 case 100:/* 100BASE */ 789 sh_eth_write(ndev, 0x00000010, GECMR); 790 break; 791 case 1000: /* 1000BASE */ 792 sh_eth_write(ndev, 0x00000020, GECMR); 793 break; 794 } 795 } 796 797 /* SH7757(GETHERC) */ 798 static struct sh_eth_cpu_data sh7757_data_giga = { 799 .chip_reset = sh_eth_chip_reset_giga, 800 .set_duplex = sh_eth_set_duplex, 801 .set_rate = sh_eth_set_rate_giga, 802 803 .register_type = SH_ETH_REG_GIGABIT, 804 805 .ecsr_value = ECSR_ICD | ECSR_MPD, 806 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 807 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 808 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 809 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 810 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP | 811 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP | 812 EESIPR_CEEFIP | EESIPR_CELFIP | 813 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 814 EESIPR_PREIP | EESIPR_CERFIP, 815 816 .tx_check = EESR_TC1 | EESR_FTC, 817 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 818 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | 819 EESR_TDE, 820 .fdr_value = 0x0000072f, 821 822 .irq_flags = IRQF_SHARED, 823 .apr = 1, 824 .mpr = 1, 825 .tpauser = 1, 826 .bculr = 1, 827 .hw_swap = 1, 828 .rpadir = 1, 829 .rpadir_value = 2 << 16, 830 .no_trimd = 1, 831 .no_ade = 1, 832 .tsu = 1, 833 }; 834 835 /* SH7734 */ 836 static struct sh_eth_cpu_data sh7734_data = { 837 .chip_reset = sh_eth_chip_reset, 838 .set_duplex = sh_eth_set_duplex, 839 .set_rate = sh_eth_set_rate_gether, 840 841 .register_type = SH_ETH_REG_GIGABIT, 842 843 .ecsr_value = ECSR_ICD | ECSR_MPD, 844 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 845 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 846 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 847 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 848 EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP | 849 EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP | 850 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 851 EESIPR_PREIP | EESIPR_CERFIP, 852 853 .tx_check = EESR_TC1 | EESR_FTC, 854 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 855 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | 856 EESR_TDE, 857 858 .apr = 1, 859 .mpr = 1, 860 .tpauser = 1, 861 .bculr = 1, 862 .hw_swap = 1, 863 .no_trimd = 1, 864 .no_ade = 1, 865 .tsu = 1, 866 .hw_checksum = 1, 867 .select_mii = 1, 868 .magic = 1, 869 }; 870 871 /* SH7763 */ 872 static struct sh_eth_cpu_data sh7763_data = { 873 .chip_reset = sh_eth_chip_reset, 874 .set_duplex = sh_eth_set_duplex, 875 .set_rate = sh_eth_set_rate_gether, 876 877 .register_type = SH_ETH_REG_GIGABIT, 878 879 .ecsr_value = ECSR_ICD | ECSR_MPD, 880 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 881 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 882 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 883 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 884 EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP | 885 EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP | 886 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 887 EESIPR_PREIP | EESIPR_CERFIP, 888 889 .tx_check = EESR_TC1 | EESR_FTC, 890 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 891 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, 892 893 .apr = 1, 894 .mpr = 1, 895 .tpauser = 1, 896 .bculr = 1, 897 .hw_swap = 1, 898 .no_trimd = 1, 899 .no_ade = 1, 900 .tsu = 1, 901 .irq_flags = IRQF_SHARED, 902 .magic = 1, 903 }; 904 905 static struct sh_eth_cpu_data sh7619_data = { 906 .register_type = SH_ETH_REG_FAST_SH3_SH2, 907 908 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 909 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 910 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 911 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP | 912 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP | 913 EESIPR_CEEFIP | EESIPR_CELFIP | 914 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 915 EESIPR_PREIP | EESIPR_CERFIP, 916 917 .apr = 1, 918 .mpr = 1, 919 .tpauser = 1, 920 .hw_swap = 1, 921 }; 922 923 static struct sh_eth_cpu_data sh771x_data = { 924 .register_type = SH_ETH_REG_FAST_SH3_SH2, 925 926 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 927 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 928 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 929 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP | 930 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP | 931 EESIPR_CEEFIP | EESIPR_CELFIP | 932 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 933 EESIPR_PREIP | EESIPR_CERFIP, 934 .tsu = 1, 935 }; 936 937 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd) 938 { 939 if (!cd->ecsr_value) 940 cd->ecsr_value = DEFAULT_ECSR_INIT; 941 942 if (!cd->ecsipr_value) 943 cd->ecsipr_value = DEFAULT_ECSIPR_INIT; 944 945 if (!cd->fcftr_value) 946 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF | 947 DEFAULT_FIFO_F_D_RFD; 948 949 if (!cd->fdr_value) 950 cd->fdr_value = DEFAULT_FDR_INIT; 951 952 if (!cd->tx_check) 953 cd->tx_check = DEFAULT_TX_CHECK; 954 955 if (!cd->eesr_err_check) 956 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK; 957 958 if (!cd->trscer_err_mask) 959 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK; 960 } 961 962 static int sh_eth_check_reset(struct net_device *ndev) 963 { 964 int ret = 0; 965 int cnt = 100; 966 967 while (cnt > 0) { 968 if (!(sh_eth_read(ndev, EDMR) & EDMR_SRST_GETHER)) 969 break; 970 mdelay(1); 971 cnt--; 972 } 973 if (cnt <= 0) { 974 netdev_err(ndev, "Device reset failed\n"); 975 ret = -ETIMEDOUT; 976 } 977 return ret; 978 } 979 980 static int sh_eth_reset(struct net_device *ndev) 981 { 982 struct sh_eth_private *mdp = netdev_priv(ndev); 983 int ret = 0; 984 985 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) { 986 sh_eth_write(ndev, EDSR_ENALL, EDSR); 987 sh_eth_modify(ndev, EDMR, EDMR_SRST_GETHER, EDMR_SRST_GETHER); 988 989 ret = sh_eth_check_reset(ndev); 990 if (ret) 991 return ret; 992 993 /* Table Init */ 994 sh_eth_write(ndev, 0x0, TDLAR); 995 sh_eth_write(ndev, 0x0, TDFAR); 996 sh_eth_write(ndev, 0x0, TDFXR); 997 sh_eth_write(ndev, 0x0, TDFFR); 998 sh_eth_write(ndev, 0x0, RDLAR); 999 sh_eth_write(ndev, 0x0, RDFAR); 1000 sh_eth_write(ndev, 0x0, RDFXR); 1001 sh_eth_write(ndev, 0x0, RDFFR); 1002 1003 /* Reset HW CRC register */ 1004 if (mdp->cd->hw_checksum) 1005 sh_eth_write(ndev, 0x0, CSMR); 1006 1007 /* Select MII mode */ 1008 if (mdp->cd->select_mii) 1009 sh_eth_select_mii(ndev); 1010 } else { 1011 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, EDMR_SRST_ETHER); 1012 mdelay(3); 1013 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, 0); 1014 } 1015 1016 return ret; 1017 } 1018 1019 static void sh_eth_set_receive_align(struct sk_buff *skb) 1020 { 1021 uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1); 1022 1023 if (reserve) 1024 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve); 1025 } 1026 1027 /* Program the hardware MAC address from dev->dev_addr. */ 1028 static void update_mac_address(struct net_device *ndev) 1029 { 1030 sh_eth_write(ndev, 1031 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 1032 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 1033 sh_eth_write(ndev, 1034 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 1035 } 1036 1037 /* Get MAC address from SuperH MAC address register 1038 * 1039 * SuperH's Ethernet device doesn't have 'ROM' to MAC address. 1040 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g). 1041 * When you want use this device, you must set MAC address in bootloader. 1042 * 1043 */ 1044 static void read_mac_address(struct net_device *ndev, unsigned char *mac) 1045 { 1046 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) { 1047 memcpy(ndev->dev_addr, mac, ETH_ALEN); 1048 } else { 1049 u32 mahr = sh_eth_read(ndev, MAHR); 1050 u32 malr = sh_eth_read(ndev, MALR); 1051 1052 ndev->dev_addr[0] = (mahr >> 24) & 0xFF; 1053 ndev->dev_addr[1] = (mahr >> 16) & 0xFF; 1054 ndev->dev_addr[2] = (mahr >> 8) & 0xFF; 1055 ndev->dev_addr[3] = (mahr >> 0) & 0xFF; 1056 ndev->dev_addr[4] = (malr >> 8) & 0xFF; 1057 ndev->dev_addr[5] = (malr >> 0) & 0xFF; 1058 } 1059 } 1060 1061 static u32 sh_eth_get_edtrr_trns(struct sh_eth_private *mdp) 1062 { 1063 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) 1064 return EDTRR_TRNS_GETHER; 1065 else 1066 return EDTRR_TRNS_ETHER; 1067 } 1068 1069 struct bb_info { 1070 void (*set_gate)(void *addr); 1071 struct mdiobb_ctrl ctrl; 1072 void *addr; 1073 }; 1074 1075 static void sh_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set) 1076 { 1077 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); 1078 u32 pir; 1079 1080 if (bitbang->set_gate) 1081 bitbang->set_gate(bitbang->addr); 1082 1083 pir = ioread32(bitbang->addr); 1084 if (set) 1085 pir |= mask; 1086 else 1087 pir &= ~mask; 1088 iowrite32(pir, bitbang->addr); 1089 } 1090 1091 /* Data I/O pin control */ 1092 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit) 1093 { 1094 sh_mdio_ctrl(ctrl, PIR_MMD, bit); 1095 } 1096 1097 /* Set bit data*/ 1098 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit) 1099 { 1100 sh_mdio_ctrl(ctrl, PIR_MDO, bit); 1101 } 1102 1103 /* Get bit data*/ 1104 static int sh_get_mdio(struct mdiobb_ctrl *ctrl) 1105 { 1106 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); 1107 1108 if (bitbang->set_gate) 1109 bitbang->set_gate(bitbang->addr); 1110 1111 return (ioread32(bitbang->addr) & PIR_MDI) != 0; 1112 } 1113 1114 /* MDC pin control */ 1115 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit) 1116 { 1117 sh_mdio_ctrl(ctrl, PIR_MDC, bit); 1118 } 1119 1120 /* mdio bus control struct */ 1121 static struct mdiobb_ops bb_ops = { 1122 .owner = THIS_MODULE, 1123 .set_mdc = sh_mdc_ctrl, 1124 .set_mdio_dir = sh_mmd_ctrl, 1125 .set_mdio_data = sh_set_mdio, 1126 .get_mdio_data = sh_get_mdio, 1127 }; 1128 1129 /* free Tx skb function */ 1130 static int sh_eth_tx_free(struct net_device *ndev, bool sent_only) 1131 { 1132 struct sh_eth_private *mdp = netdev_priv(ndev); 1133 struct sh_eth_txdesc *txdesc; 1134 int free_num = 0; 1135 int entry; 1136 bool sent; 1137 1138 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) { 1139 entry = mdp->dirty_tx % mdp->num_tx_ring; 1140 txdesc = &mdp->tx_ring[entry]; 1141 sent = !(txdesc->status & cpu_to_le32(TD_TACT)); 1142 if (sent_only && !sent) 1143 break; 1144 /* TACT bit must be checked before all the following reads */ 1145 dma_rmb(); 1146 netif_info(mdp, tx_done, ndev, 1147 "tx entry %d status 0x%08x\n", 1148 entry, le32_to_cpu(txdesc->status)); 1149 /* Free the original skb. */ 1150 if (mdp->tx_skbuff[entry]) { 1151 dma_unmap_single(&mdp->pdev->dev, 1152 le32_to_cpu(txdesc->addr), 1153 le32_to_cpu(txdesc->len) >> 16, 1154 DMA_TO_DEVICE); 1155 dev_kfree_skb_irq(mdp->tx_skbuff[entry]); 1156 mdp->tx_skbuff[entry] = NULL; 1157 free_num++; 1158 } 1159 txdesc->status = cpu_to_le32(TD_TFP); 1160 if (entry >= mdp->num_tx_ring - 1) 1161 txdesc->status |= cpu_to_le32(TD_TDLE); 1162 1163 if (sent) { 1164 ndev->stats.tx_packets++; 1165 ndev->stats.tx_bytes += le32_to_cpu(txdesc->len) >> 16; 1166 } 1167 } 1168 return free_num; 1169 } 1170 1171 /* free skb and descriptor buffer */ 1172 static void sh_eth_ring_free(struct net_device *ndev) 1173 { 1174 struct sh_eth_private *mdp = netdev_priv(ndev); 1175 int ringsize, i; 1176 1177 if (mdp->rx_ring) { 1178 for (i = 0; i < mdp->num_rx_ring; i++) { 1179 if (mdp->rx_skbuff[i]) { 1180 struct sh_eth_rxdesc *rxdesc = &mdp->rx_ring[i]; 1181 1182 dma_unmap_single(&mdp->pdev->dev, 1183 le32_to_cpu(rxdesc->addr), 1184 ALIGN(mdp->rx_buf_sz, 32), 1185 DMA_FROM_DEVICE); 1186 } 1187 } 1188 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring; 1189 dma_free_coherent(&mdp->pdev->dev, ringsize, mdp->rx_ring, 1190 mdp->rx_desc_dma); 1191 mdp->rx_ring = NULL; 1192 } 1193 1194 /* Free Rx skb ringbuffer */ 1195 if (mdp->rx_skbuff) { 1196 for (i = 0; i < mdp->num_rx_ring; i++) 1197 dev_kfree_skb(mdp->rx_skbuff[i]); 1198 } 1199 kfree(mdp->rx_skbuff); 1200 mdp->rx_skbuff = NULL; 1201 1202 if (mdp->tx_ring) { 1203 sh_eth_tx_free(ndev, false); 1204 1205 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring; 1206 dma_free_coherent(&mdp->pdev->dev, ringsize, mdp->tx_ring, 1207 mdp->tx_desc_dma); 1208 mdp->tx_ring = NULL; 1209 } 1210 1211 /* Free Tx skb ringbuffer */ 1212 kfree(mdp->tx_skbuff); 1213 mdp->tx_skbuff = NULL; 1214 } 1215 1216 /* format skb and descriptor buffer */ 1217 static void sh_eth_ring_format(struct net_device *ndev) 1218 { 1219 struct sh_eth_private *mdp = netdev_priv(ndev); 1220 int i; 1221 struct sk_buff *skb; 1222 struct sh_eth_rxdesc *rxdesc = NULL; 1223 struct sh_eth_txdesc *txdesc = NULL; 1224 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring; 1225 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring; 1226 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1; 1227 dma_addr_t dma_addr; 1228 u32 buf_len; 1229 1230 mdp->cur_rx = 0; 1231 mdp->cur_tx = 0; 1232 mdp->dirty_rx = 0; 1233 mdp->dirty_tx = 0; 1234 1235 memset(mdp->rx_ring, 0, rx_ringsize); 1236 1237 /* build Rx ring buffer */ 1238 for (i = 0; i < mdp->num_rx_ring; i++) { 1239 /* skb */ 1240 mdp->rx_skbuff[i] = NULL; 1241 skb = netdev_alloc_skb(ndev, skbuff_size); 1242 if (skb == NULL) 1243 break; 1244 sh_eth_set_receive_align(skb); 1245 1246 /* The size of the buffer is a multiple of 32 bytes. */ 1247 buf_len = ALIGN(mdp->rx_buf_sz, 32); 1248 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, buf_len, 1249 DMA_FROM_DEVICE); 1250 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) { 1251 kfree_skb(skb); 1252 break; 1253 } 1254 mdp->rx_skbuff[i] = skb; 1255 1256 /* RX descriptor */ 1257 rxdesc = &mdp->rx_ring[i]; 1258 rxdesc->len = cpu_to_le32(buf_len << 16); 1259 rxdesc->addr = cpu_to_le32(dma_addr); 1260 rxdesc->status = cpu_to_le32(RD_RACT | RD_RFP); 1261 1262 /* Rx descriptor address set */ 1263 if (i == 0) { 1264 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR); 1265 if (sh_eth_is_gether(mdp) || 1266 sh_eth_is_rz_fast_ether(mdp)) 1267 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR); 1268 } 1269 } 1270 1271 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring); 1272 1273 /* Mark the last entry as wrapping the ring. */ 1274 if (rxdesc) 1275 rxdesc->status |= cpu_to_le32(RD_RDLE); 1276 1277 memset(mdp->tx_ring, 0, tx_ringsize); 1278 1279 /* build Tx ring buffer */ 1280 for (i = 0; i < mdp->num_tx_ring; i++) { 1281 mdp->tx_skbuff[i] = NULL; 1282 txdesc = &mdp->tx_ring[i]; 1283 txdesc->status = cpu_to_le32(TD_TFP); 1284 txdesc->len = cpu_to_le32(0); 1285 if (i == 0) { 1286 /* Tx descriptor address set */ 1287 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR); 1288 if (sh_eth_is_gether(mdp) || 1289 sh_eth_is_rz_fast_ether(mdp)) 1290 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR); 1291 } 1292 } 1293 1294 txdesc->status |= cpu_to_le32(TD_TDLE); 1295 } 1296 1297 /* Get skb and descriptor buffer */ 1298 static int sh_eth_ring_init(struct net_device *ndev) 1299 { 1300 struct sh_eth_private *mdp = netdev_priv(ndev); 1301 int rx_ringsize, tx_ringsize; 1302 1303 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the 1304 * card needs room to do 8 byte alignment, +2 so we can reserve 1305 * the first 2 bytes, and +16 gets room for the status word from the 1306 * card. 1307 */ 1308 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ : 1309 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16)); 1310 if (mdp->cd->rpadir) 1311 mdp->rx_buf_sz += NET_IP_ALIGN; 1312 1313 /* Allocate RX and TX skb rings */ 1314 mdp->rx_skbuff = kcalloc(mdp->num_rx_ring, sizeof(*mdp->rx_skbuff), 1315 GFP_KERNEL); 1316 if (!mdp->rx_skbuff) 1317 return -ENOMEM; 1318 1319 mdp->tx_skbuff = kcalloc(mdp->num_tx_ring, sizeof(*mdp->tx_skbuff), 1320 GFP_KERNEL); 1321 if (!mdp->tx_skbuff) 1322 goto ring_free; 1323 1324 /* Allocate all Rx descriptors. */ 1325 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring; 1326 mdp->rx_ring = dma_alloc_coherent(&mdp->pdev->dev, rx_ringsize, 1327 &mdp->rx_desc_dma, GFP_KERNEL); 1328 if (!mdp->rx_ring) 1329 goto ring_free; 1330 1331 mdp->dirty_rx = 0; 1332 1333 /* Allocate all Tx descriptors. */ 1334 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring; 1335 mdp->tx_ring = dma_alloc_coherent(&mdp->pdev->dev, tx_ringsize, 1336 &mdp->tx_desc_dma, GFP_KERNEL); 1337 if (!mdp->tx_ring) 1338 goto ring_free; 1339 return 0; 1340 1341 ring_free: 1342 /* Free Rx and Tx skb ring buffer and DMA buffer */ 1343 sh_eth_ring_free(ndev); 1344 1345 return -ENOMEM; 1346 } 1347 1348 static int sh_eth_dev_init(struct net_device *ndev) 1349 { 1350 struct sh_eth_private *mdp = netdev_priv(ndev); 1351 int ret; 1352 1353 /* Soft Reset */ 1354 ret = sh_eth_reset(ndev); 1355 if (ret) 1356 return ret; 1357 1358 if (mdp->cd->rmiimode) 1359 sh_eth_write(ndev, 0x1, RMIIMODE); 1360 1361 /* Descriptor format */ 1362 sh_eth_ring_format(ndev); 1363 if (mdp->cd->rpadir) 1364 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR); 1365 1366 /* all sh_eth int mask */ 1367 sh_eth_write(ndev, 0, EESIPR); 1368 1369 #if defined(__LITTLE_ENDIAN) 1370 if (mdp->cd->hw_swap) 1371 sh_eth_write(ndev, EDMR_EL, EDMR); 1372 else 1373 #endif 1374 sh_eth_write(ndev, 0, EDMR); 1375 1376 /* FIFO size set */ 1377 sh_eth_write(ndev, mdp->cd->fdr_value, FDR); 1378 sh_eth_write(ndev, 0, TFTR); 1379 1380 /* Frame recv control (enable multiple-packets per rx irq) */ 1381 sh_eth_write(ndev, RMCR_RNC, RMCR); 1382 1383 sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER); 1384 1385 if (mdp->cd->bculr) 1386 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */ 1387 1388 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR); 1389 1390 if (!mdp->cd->no_trimd) 1391 sh_eth_write(ndev, 0, TRIMD); 1392 1393 /* Recv frame limit set register */ 1394 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, 1395 RFLR); 1396 1397 sh_eth_modify(ndev, EESR, 0, 0); 1398 mdp->irq_enabled = true; 1399 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR); 1400 1401 /* PAUSE Prohibition */ 1402 sh_eth_write(ndev, ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | 1403 ECMR_TE | ECMR_RE, ECMR); 1404 1405 if (mdp->cd->set_rate) 1406 mdp->cd->set_rate(ndev); 1407 1408 /* E-MAC Status Register clear */ 1409 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR); 1410 1411 /* E-MAC Interrupt Enable register */ 1412 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR); 1413 1414 /* Set MAC address */ 1415 update_mac_address(ndev); 1416 1417 /* mask reset */ 1418 if (mdp->cd->apr) 1419 sh_eth_write(ndev, APR_AP, APR); 1420 if (mdp->cd->mpr) 1421 sh_eth_write(ndev, MPR_MP, MPR); 1422 if (mdp->cd->tpauser) 1423 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER); 1424 1425 /* Setting the Rx mode will start the Rx process. */ 1426 sh_eth_write(ndev, EDRRR_R, EDRRR); 1427 1428 return ret; 1429 } 1430 1431 static void sh_eth_dev_exit(struct net_device *ndev) 1432 { 1433 struct sh_eth_private *mdp = netdev_priv(ndev); 1434 int i; 1435 1436 /* Deactivate all TX descriptors, so DMA should stop at next 1437 * packet boundary if it's currently running 1438 */ 1439 for (i = 0; i < mdp->num_tx_ring; i++) 1440 mdp->tx_ring[i].status &= ~cpu_to_le32(TD_TACT); 1441 1442 /* Disable TX FIFO egress to MAC */ 1443 sh_eth_rcv_snd_disable(ndev); 1444 1445 /* Stop RX DMA at next packet boundary */ 1446 sh_eth_write(ndev, 0, EDRRR); 1447 1448 /* Aside from TX DMA, we can't tell when the hardware is 1449 * really stopped, so we need to reset to make sure. 1450 * Before doing that, wait for long enough to *probably* 1451 * finish transmitting the last packet and poll stats. 1452 */ 1453 msleep(2); /* max frame time at 10 Mbps < 1250 us */ 1454 sh_eth_get_stats(ndev); 1455 sh_eth_reset(ndev); 1456 1457 /* Set MAC address again */ 1458 update_mac_address(ndev); 1459 } 1460 1461 /* Packet receive function */ 1462 static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota) 1463 { 1464 struct sh_eth_private *mdp = netdev_priv(ndev); 1465 struct sh_eth_rxdesc *rxdesc; 1466 1467 int entry = mdp->cur_rx % mdp->num_rx_ring; 1468 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx; 1469 int limit; 1470 struct sk_buff *skb; 1471 u32 desc_status; 1472 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1; 1473 dma_addr_t dma_addr; 1474 u16 pkt_len; 1475 u32 buf_len; 1476 1477 boguscnt = min(boguscnt, *quota); 1478 limit = boguscnt; 1479 rxdesc = &mdp->rx_ring[entry]; 1480 while (!(rxdesc->status & cpu_to_le32(RD_RACT))) { 1481 /* RACT bit must be checked before all the following reads */ 1482 dma_rmb(); 1483 desc_status = le32_to_cpu(rxdesc->status); 1484 pkt_len = le32_to_cpu(rxdesc->len) & RD_RFL; 1485 1486 if (--boguscnt < 0) 1487 break; 1488 1489 netif_info(mdp, rx_status, ndev, 1490 "rx entry %d status 0x%08x len %d\n", 1491 entry, desc_status, pkt_len); 1492 1493 if (!(desc_status & RDFEND)) 1494 ndev->stats.rx_length_errors++; 1495 1496 /* In case of almost all GETHER/ETHERs, the Receive Frame State 1497 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to 1498 * bit 0. However, in case of the R8A7740 and R7S72100 1499 * the RFS bits are from bit 25 to bit 16. So, the 1500 * driver needs right shifting by 16. 1501 */ 1502 if (mdp->cd->hw_checksum) 1503 desc_status >>= 16; 1504 1505 skb = mdp->rx_skbuff[entry]; 1506 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 | 1507 RD_RFS5 | RD_RFS6 | RD_RFS10)) { 1508 ndev->stats.rx_errors++; 1509 if (desc_status & RD_RFS1) 1510 ndev->stats.rx_crc_errors++; 1511 if (desc_status & RD_RFS2) 1512 ndev->stats.rx_frame_errors++; 1513 if (desc_status & RD_RFS3) 1514 ndev->stats.rx_length_errors++; 1515 if (desc_status & RD_RFS4) 1516 ndev->stats.rx_length_errors++; 1517 if (desc_status & RD_RFS6) 1518 ndev->stats.rx_missed_errors++; 1519 if (desc_status & RD_RFS10) 1520 ndev->stats.rx_over_errors++; 1521 } else if (skb) { 1522 dma_addr = le32_to_cpu(rxdesc->addr); 1523 if (!mdp->cd->hw_swap) 1524 sh_eth_soft_swap( 1525 phys_to_virt(ALIGN(dma_addr, 4)), 1526 pkt_len + 2); 1527 mdp->rx_skbuff[entry] = NULL; 1528 if (mdp->cd->rpadir) 1529 skb_reserve(skb, NET_IP_ALIGN); 1530 dma_unmap_single(&mdp->pdev->dev, dma_addr, 1531 ALIGN(mdp->rx_buf_sz, 32), 1532 DMA_FROM_DEVICE); 1533 skb_put(skb, pkt_len); 1534 skb->protocol = eth_type_trans(skb, ndev); 1535 netif_receive_skb(skb); 1536 ndev->stats.rx_packets++; 1537 ndev->stats.rx_bytes += pkt_len; 1538 if (desc_status & RD_RFS8) 1539 ndev->stats.multicast++; 1540 } 1541 entry = (++mdp->cur_rx) % mdp->num_rx_ring; 1542 rxdesc = &mdp->rx_ring[entry]; 1543 } 1544 1545 /* Refill the Rx ring buffers. */ 1546 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) { 1547 entry = mdp->dirty_rx % mdp->num_rx_ring; 1548 rxdesc = &mdp->rx_ring[entry]; 1549 /* The size of the buffer is 32 byte boundary. */ 1550 buf_len = ALIGN(mdp->rx_buf_sz, 32); 1551 rxdesc->len = cpu_to_le32(buf_len << 16); 1552 1553 if (mdp->rx_skbuff[entry] == NULL) { 1554 skb = netdev_alloc_skb(ndev, skbuff_size); 1555 if (skb == NULL) 1556 break; /* Better luck next round. */ 1557 sh_eth_set_receive_align(skb); 1558 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, 1559 buf_len, DMA_FROM_DEVICE); 1560 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) { 1561 kfree_skb(skb); 1562 break; 1563 } 1564 mdp->rx_skbuff[entry] = skb; 1565 1566 skb_checksum_none_assert(skb); 1567 rxdesc->addr = cpu_to_le32(dma_addr); 1568 } 1569 dma_wmb(); /* RACT bit must be set after all the above writes */ 1570 if (entry >= mdp->num_rx_ring - 1) 1571 rxdesc->status |= 1572 cpu_to_le32(RD_RACT | RD_RFP | RD_RDLE); 1573 else 1574 rxdesc->status |= cpu_to_le32(RD_RACT | RD_RFP); 1575 } 1576 1577 /* Restart Rx engine if stopped. */ 1578 /* If we don't need to check status, don't. -KDU */ 1579 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) { 1580 /* fix the values for the next receiving if RDE is set */ 1581 if (intr_status & EESR_RDE && 1582 mdp->reg_offset[RDFAR] != SH_ETH_OFFSET_INVALID) { 1583 u32 count = (sh_eth_read(ndev, RDFAR) - 1584 sh_eth_read(ndev, RDLAR)) >> 4; 1585 1586 mdp->cur_rx = count; 1587 mdp->dirty_rx = count; 1588 } 1589 sh_eth_write(ndev, EDRRR_R, EDRRR); 1590 } 1591 1592 *quota -= limit - boguscnt - 1; 1593 1594 return *quota <= 0; 1595 } 1596 1597 static void sh_eth_rcv_snd_disable(struct net_device *ndev) 1598 { 1599 /* disable tx and rx */ 1600 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0); 1601 } 1602 1603 static void sh_eth_rcv_snd_enable(struct net_device *ndev) 1604 { 1605 /* enable tx and rx */ 1606 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE); 1607 } 1608 1609 /* E-MAC interrupt handler */ 1610 static void sh_eth_emac_interrupt(struct net_device *ndev) 1611 { 1612 struct sh_eth_private *mdp = netdev_priv(ndev); 1613 u32 felic_stat; 1614 u32 link_stat; 1615 1616 felic_stat = sh_eth_read(ndev, ECSR) & sh_eth_read(ndev, ECSIPR); 1617 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */ 1618 if (felic_stat & ECSR_ICD) 1619 ndev->stats.tx_carrier_errors++; 1620 if (felic_stat & ECSR_MPD) 1621 pm_wakeup_event(&mdp->pdev->dev, 0); 1622 if (felic_stat & ECSR_LCHNG) { 1623 /* Link Changed */ 1624 if (mdp->cd->no_psr || mdp->no_ether_link) 1625 return; 1626 link_stat = sh_eth_read(ndev, PSR); 1627 if (mdp->ether_link_active_low) 1628 link_stat = ~link_stat; 1629 if (!(link_stat & PHY_ST_LINK)) { 1630 sh_eth_rcv_snd_disable(ndev); 1631 } else { 1632 /* Link Up */ 1633 sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, 0); 1634 /* clear int */ 1635 sh_eth_modify(ndev, ECSR, 0, 0); 1636 sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, EESIPR_ECIIP); 1637 /* enable tx and rx */ 1638 sh_eth_rcv_snd_enable(ndev); 1639 } 1640 } 1641 } 1642 1643 /* error control function */ 1644 static void sh_eth_error(struct net_device *ndev, u32 intr_status) 1645 { 1646 struct sh_eth_private *mdp = netdev_priv(ndev); 1647 u32 mask; 1648 1649 if (intr_status & EESR_TWB) { 1650 /* Unused write back interrupt */ 1651 if (intr_status & EESR_TABT) { /* Transmit Abort int */ 1652 ndev->stats.tx_aborted_errors++; 1653 netif_err(mdp, tx_err, ndev, "Transmit Abort\n"); 1654 } 1655 } 1656 1657 if (intr_status & EESR_RABT) { 1658 /* Receive Abort int */ 1659 if (intr_status & EESR_RFRMER) { 1660 /* Receive Frame Overflow int */ 1661 ndev->stats.rx_frame_errors++; 1662 } 1663 } 1664 1665 if (intr_status & EESR_TDE) { 1666 /* Transmit Descriptor Empty int */ 1667 ndev->stats.tx_fifo_errors++; 1668 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n"); 1669 } 1670 1671 if (intr_status & EESR_TFE) { 1672 /* FIFO under flow */ 1673 ndev->stats.tx_fifo_errors++; 1674 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n"); 1675 } 1676 1677 if (intr_status & EESR_RDE) { 1678 /* Receive Descriptor Empty int */ 1679 ndev->stats.rx_over_errors++; 1680 } 1681 1682 if (intr_status & EESR_RFE) { 1683 /* Receive FIFO Overflow int */ 1684 ndev->stats.rx_fifo_errors++; 1685 } 1686 1687 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) { 1688 /* Address Error */ 1689 ndev->stats.tx_fifo_errors++; 1690 netif_err(mdp, tx_err, ndev, "Address Error\n"); 1691 } 1692 1693 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE; 1694 if (mdp->cd->no_ade) 1695 mask &= ~EESR_ADE; 1696 if (intr_status & mask) { 1697 /* Tx error */ 1698 u32 edtrr = sh_eth_read(ndev, EDTRR); 1699 1700 /* dmesg */ 1701 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n", 1702 intr_status, mdp->cur_tx, mdp->dirty_tx, 1703 (u32)ndev->state, edtrr); 1704 /* dirty buffer free */ 1705 sh_eth_tx_free(ndev, true); 1706 1707 /* SH7712 BUG */ 1708 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) { 1709 /* tx dma start */ 1710 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR); 1711 } 1712 /* wakeup */ 1713 netif_wake_queue(ndev); 1714 } 1715 } 1716 1717 static irqreturn_t sh_eth_interrupt(int irq, void *netdev) 1718 { 1719 struct net_device *ndev = netdev; 1720 struct sh_eth_private *mdp = netdev_priv(ndev); 1721 struct sh_eth_cpu_data *cd = mdp->cd; 1722 irqreturn_t ret = IRQ_NONE; 1723 u32 intr_status, intr_enable; 1724 1725 spin_lock(&mdp->lock); 1726 1727 /* Get interrupt status */ 1728 intr_status = sh_eth_read(ndev, EESR); 1729 /* Mask it with the interrupt mask, forcing ECI interrupt to be always 1730 * enabled since it's the one that comes thru regardless of the mask, 1731 * and we need to fully handle it in sh_eth_emac_interrupt() in order 1732 * to quench it as it doesn't get cleared by just writing 1 to the ECI 1733 * bit... 1734 */ 1735 intr_enable = sh_eth_read(ndev, EESIPR); 1736 intr_status &= intr_enable | EESIPR_ECIIP; 1737 if (intr_status & (EESR_RX_CHECK | cd->tx_check | EESR_ECI | 1738 cd->eesr_err_check)) 1739 ret = IRQ_HANDLED; 1740 else 1741 goto out; 1742 1743 if (unlikely(!mdp->irq_enabled)) { 1744 sh_eth_write(ndev, 0, EESIPR); 1745 goto out; 1746 } 1747 1748 if (intr_status & EESR_RX_CHECK) { 1749 if (napi_schedule_prep(&mdp->napi)) { 1750 /* Mask Rx interrupts */ 1751 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK, 1752 EESIPR); 1753 __napi_schedule(&mdp->napi); 1754 } else { 1755 netdev_warn(ndev, 1756 "ignoring interrupt, status 0x%08x, mask 0x%08x.\n", 1757 intr_status, intr_enable); 1758 } 1759 } 1760 1761 /* Tx Check */ 1762 if (intr_status & cd->tx_check) { 1763 /* Clear Tx interrupts */ 1764 sh_eth_write(ndev, intr_status & cd->tx_check, EESR); 1765 1766 sh_eth_tx_free(ndev, true); 1767 netif_wake_queue(ndev); 1768 } 1769 1770 /* E-MAC interrupt */ 1771 if (intr_status & EESR_ECI) 1772 sh_eth_emac_interrupt(ndev); 1773 1774 if (intr_status & cd->eesr_err_check) { 1775 /* Clear error interrupts */ 1776 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR); 1777 1778 sh_eth_error(ndev, intr_status); 1779 } 1780 1781 out: 1782 spin_unlock(&mdp->lock); 1783 1784 return ret; 1785 } 1786 1787 static int sh_eth_poll(struct napi_struct *napi, int budget) 1788 { 1789 struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private, 1790 napi); 1791 struct net_device *ndev = napi->dev; 1792 int quota = budget; 1793 u32 intr_status; 1794 1795 for (;;) { 1796 intr_status = sh_eth_read(ndev, EESR); 1797 if (!(intr_status & EESR_RX_CHECK)) 1798 break; 1799 /* Clear Rx interrupts */ 1800 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR); 1801 1802 if (sh_eth_rx(ndev, intr_status, "a)) 1803 goto out; 1804 } 1805 1806 napi_complete(napi); 1807 1808 /* Reenable Rx interrupts */ 1809 if (mdp->irq_enabled) 1810 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR); 1811 out: 1812 return budget - quota; 1813 } 1814 1815 /* PHY state control function */ 1816 static void sh_eth_adjust_link(struct net_device *ndev) 1817 { 1818 struct sh_eth_private *mdp = netdev_priv(ndev); 1819 struct phy_device *phydev = ndev->phydev; 1820 int new_state = 0; 1821 1822 if (phydev->link) { 1823 if (phydev->duplex != mdp->duplex) { 1824 new_state = 1; 1825 mdp->duplex = phydev->duplex; 1826 if (mdp->cd->set_duplex) 1827 mdp->cd->set_duplex(ndev); 1828 } 1829 1830 if (phydev->speed != mdp->speed) { 1831 new_state = 1; 1832 mdp->speed = phydev->speed; 1833 if (mdp->cd->set_rate) 1834 mdp->cd->set_rate(ndev); 1835 } 1836 if (!mdp->link) { 1837 sh_eth_modify(ndev, ECMR, ECMR_TXF, 0); 1838 new_state = 1; 1839 mdp->link = phydev->link; 1840 if (mdp->cd->no_psr || mdp->no_ether_link) 1841 sh_eth_rcv_snd_enable(ndev); 1842 } 1843 } else if (mdp->link) { 1844 new_state = 1; 1845 mdp->link = 0; 1846 mdp->speed = 0; 1847 mdp->duplex = -1; 1848 if (mdp->cd->no_psr || mdp->no_ether_link) 1849 sh_eth_rcv_snd_disable(ndev); 1850 } 1851 1852 if (new_state && netif_msg_link(mdp)) 1853 phy_print_status(phydev); 1854 } 1855 1856 /* PHY init function */ 1857 static int sh_eth_phy_init(struct net_device *ndev) 1858 { 1859 struct device_node *np = ndev->dev.parent->of_node; 1860 struct sh_eth_private *mdp = netdev_priv(ndev); 1861 struct phy_device *phydev; 1862 1863 mdp->link = 0; 1864 mdp->speed = 0; 1865 mdp->duplex = -1; 1866 1867 /* Try connect to PHY */ 1868 if (np) { 1869 struct device_node *pn; 1870 1871 pn = of_parse_phandle(np, "phy-handle", 0); 1872 phydev = of_phy_connect(ndev, pn, 1873 sh_eth_adjust_link, 0, 1874 mdp->phy_interface); 1875 1876 of_node_put(pn); 1877 if (!phydev) 1878 phydev = ERR_PTR(-ENOENT); 1879 } else { 1880 char phy_id[MII_BUS_ID_SIZE + 3]; 1881 1882 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, 1883 mdp->mii_bus->id, mdp->phy_id); 1884 1885 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link, 1886 mdp->phy_interface); 1887 } 1888 1889 if (IS_ERR(phydev)) { 1890 netdev_err(ndev, "failed to connect PHY\n"); 1891 return PTR_ERR(phydev); 1892 } 1893 1894 /* mask with MAC supported features */ 1895 if (mdp->cd->register_type != SH_ETH_REG_GIGABIT) { 1896 int err = phy_set_max_speed(phydev, SPEED_100); 1897 if (err) { 1898 netdev_err(ndev, "failed to limit PHY to 100 Mbit/s\n"); 1899 phy_disconnect(phydev); 1900 return err; 1901 } 1902 } 1903 1904 phy_attached_info(phydev); 1905 1906 return 0; 1907 } 1908 1909 /* PHY control start function */ 1910 static int sh_eth_phy_start(struct net_device *ndev) 1911 { 1912 int ret; 1913 1914 ret = sh_eth_phy_init(ndev); 1915 if (ret) 1916 return ret; 1917 1918 phy_start(ndev->phydev); 1919 1920 return 0; 1921 } 1922 1923 static int sh_eth_get_link_ksettings(struct net_device *ndev, 1924 struct ethtool_link_ksettings *cmd) 1925 { 1926 struct sh_eth_private *mdp = netdev_priv(ndev); 1927 unsigned long flags; 1928 1929 if (!ndev->phydev) 1930 return -ENODEV; 1931 1932 spin_lock_irqsave(&mdp->lock, flags); 1933 phy_ethtool_ksettings_get(ndev->phydev, cmd); 1934 spin_unlock_irqrestore(&mdp->lock, flags); 1935 1936 return 0; 1937 } 1938 1939 static int sh_eth_set_link_ksettings(struct net_device *ndev, 1940 const struct ethtool_link_ksettings *cmd) 1941 { 1942 struct sh_eth_private *mdp = netdev_priv(ndev); 1943 unsigned long flags; 1944 int ret; 1945 1946 if (!ndev->phydev) 1947 return -ENODEV; 1948 1949 spin_lock_irqsave(&mdp->lock, flags); 1950 1951 /* disable tx and rx */ 1952 sh_eth_rcv_snd_disable(ndev); 1953 1954 ret = phy_ethtool_ksettings_set(ndev->phydev, cmd); 1955 if (ret) 1956 goto error_exit; 1957 1958 if (cmd->base.duplex == DUPLEX_FULL) 1959 mdp->duplex = 1; 1960 else 1961 mdp->duplex = 0; 1962 1963 if (mdp->cd->set_duplex) 1964 mdp->cd->set_duplex(ndev); 1965 1966 error_exit: 1967 mdelay(1); 1968 1969 /* enable tx and rx */ 1970 sh_eth_rcv_snd_enable(ndev); 1971 1972 spin_unlock_irqrestore(&mdp->lock, flags); 1973 1974 return ret; 1975 } 1976 1977 /* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the 1978 * version must be bumped as well. Just adding registers up to that 1979 * limit is fine, as long as the existing register indices don't 1980 * change. 1981 */ 1982 #define SH_ETH_REG_DUMP_VERSION 1 1983 #define SH_ETH_REG_DUMP_MAX_REGS 256 1984 1985 static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf) 1986 { 1987 struct sh_eth_private *mdp = netdev_priv(ndev); 1988 struct sh_eth_cpu_data *cd = mdp->cd; 1989 u32 *valid_map; 1990 size_t len; 1991 1992 BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET > SH_ETH_REG_DUMP_MAX_REGS); 1993 1994 /* Dump starts with a bitmap that tells ethtool which 1995 * registers are defined for this chip. 1996 */ 1997 len = DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS, 32); 1998 if (buf) { 1999 valid_map = buf; 2000 buf += len; 2001 } else { 2002 valid_map = NULL; 2003 } 2004 2005 /* Add a register to the dump, if it has a defined offset. 2006 * This automatically skips most undefined registers, but for 2007 * some it is also necessary to check a capability flag in 2008 * struct sh_eth_cpu_data. 2009 */ 2010 #define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32) 2011 #define add_reg_from(reg, read_expr) do { \ 2012 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) { \ 2013 if (buf) { \ 2014 mark_reg_valid(reg); \ 2015 *buf++ = read_expr; \ 2016 } \ 2017 ++len; \ 2018 } \ 2019 } while (0) 2020 #define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg)) 2021 #define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg)) 2022 2023 add_reg(EDSR); 2024 add_reg(EDMR); 2025 add_reg(EDTRR); 2026 add_reg(EDRRR); 2027 add_reg(EESR); 2028 add_reg(EESIPR); 2029 add_reg(TDLAR); 2030 add_reg(TDFAR); 2031 add_reg(TDFXR); 2032 add_reg(TDFFR); 2033 add_reg(RDLAR); 2034 add_reg(RDFAR); 2035 add_reg(RDFXR); 2036 add_reg(RDFFR); 2037 add_reg(TRSCER); 2038 add_reg(RMFCR); 2039 add_reg(TFTR); 2040 add_reg(FDR); 2041 add_reg(RMCR); 2042 add_reg(TFUCR); 2043 add_reg(RFOCR); 2044 if (cd->rmiimode) 2045 add_reg(RMIIMODE); 2046 add_reg(FCFTR); 2047 if (cd->rpadir) 2048 add_reg(RPADIR); 2049 if (!cd->no_trimd) 2050 add_reg(TRIMD); 2051 add_reg(ECMR); 2052 add_reg(ECSR); 2053 add_reg(ECSIPR); 2054 add_reg(PIR); 2055 if (!cd->no_psr) 2056 add_reg(PSR); 2057 add_reg(RDMLR); 2058 add_reg(RFLR); 2059 add_reg(IPGR); 2060 if (cd->apr) 2061 add_reg(APR); 2062 if (cd->mpr) 2063 add_reg(MPR); 2064 add_reg(RFCR); 2065 add_reg(RFCF); 2066 if (cd->tpauser) 2067 add_reg(TPAUSER); 2068 add_reg(TPAUSECR); 2069 add_reg(GECMR); 2070 if (cd->bculr) 2071 add_reg(BCULR); 2072 add_reg(MAHR); 2073 add_reg(MALR); 2074 add_reg(TROCR); 2075 add_reg(CDCR); 2076 add_reg(LCCR); 2077 add_reg(CNDCR); 2078 add_reg(CEFCR); 2079 add_reg(FRECR); 2080 add_reg(TSFRCR); 2081 add_reg(TLFRCR); 2082 add_reg(CERCR); 2083 add_reg(CEECR); 2084 add_reg(MAFCR); 2085 if (cd->rtrate) 2086 add_reg(RTRATE); 2087 if (cd->hw_checksum) 2088 add_reg(CSMR); 2089 if (cd->select_mii) 2090 add_reg(RMII_MII); 2091 if (cd->tsu) { 2092 add_tsu_reg(ARSTR); 2093 add_tsu_reg(TSU_CTRST); 2094 add_tsu_reg(TSU_FWEN0); 2095 add_tsu_reg(TSU_FWEN1); 2096 add_tsu_reg(TSU_FCM); 2097 add_tsu_reg(TSU_BSYSL0); 2098 add_tsu_reg(TSU_BSYSL1); 2099 add_tsu_reg(TSU_PRISL0); 2100 add_tsu_reg(TSU_PRISL1); 2101 add_tsu_reg(TSU_FWSL0); 2102 add_tsu_reg(TSU_FWSL1); 2103 add_tsu_reg(TSU_FWSLC); 2104 add_tsu_reg(TSU_QTAG0); 2105 add_tsu_reg(TSU_QTAG1); 2106 add_tsu_reg(TSU_QTAGM0); 2107 add_tsu_reg(TSU_QTAGM1); 2108 add_tsu_reg(TSU_FWSR); 2109 add_tsu_reg(TSU_FWINMK); 2110 add_tsu_reg(TSU_ADQT0); 2111 add_tsu_reg(TSU_ADQT1); 2112 add_tsu_reg(TSU_VTAG0); 2113 add_tsu_reg(TSU_VTAG1); 2114 add_tsu_reg(TSU_ADSBSY); 2115 add_tsu_reg(TSU_TEN); 2116 add_tsu_reg(TSU_POST1); 2117 add_tsu_reg(TSU_POST2); 2118 add_tsu_reg(TSU_POST3); 2119 add_tsu_reg(TSU_POST4); 2120 if (mdp->reg_offset[TSU_ADRH0] != SH_ETH_OFFSET_INVALID) { 2121 /* This is the start of a table, not just a single 2122 * register. 2123 */ 2124 if (buf) { 2125 unsigned int i; 2126 2127 mark_reg_valid(TSU_ADRH0); 2128 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++) 2129 *buf++ = ioread32( 2130 mdp->tsu_addr + 2131 mdp->reg_offset[TSU_ADRH0] + 2132 i * 4); 2133 } 2134 len += SH_ETH_TSU_CAM_ENTRIES * 2; 2135 } 2136 } 2137 2138 #undef mark_reg_valid 2139 #undef add_reg_from 2140 #undef add_reg 2141 #undef add_tsu_reg 2142 2143 return len * 4; 2144 } 2145 2146 static int sh_eth_get_regs_len(struct net_device *ndev) 2147 { 2148 return __sh_eth_get_regs(ndev, NULL); 2149 } 2150 2151 static void sh_eth_get_regs(struct net_device *ndev, struct ethtool_regs *regs, 2152 void *buf) 2153 { 2154 struct sh_eth_private *mdp = netdev_priv(ndev); 2155 2156 regs->version = SH_ETH_REG_DUMP_VERSION; 2157 2158 pm_runtime_get_sync(&mdp->pdev->dev); 2159 __sh_eth_get_regs(ndev, buf); 2160 pm_runtime_put_sync(&mdp->pdev->dev); 2161 } 2162 2163 static int sh_eth_nway_reset(struct net_device *ndev) 2164 { 2165 struct sh_eth_private *mdp = netdev_priv(ndev); 2166 unsigned long flags; 2167 int ret; 2168 2169 if (!ndev->phydev) 2170 return -ENODEV; 2171 2172 spin_lock_irqsave(&mdp->lock, flags); 2173 ret = phy_start_aneg(ndev->phydev); 2174 spin_unlock_irqrestore(&mdp->lock, flags); 2175 2176 return ret; 2177 } 2178 2179 static u32 sh_eth_get_msglevel(struct net_device *ndev) 2180 { 2181 struct sh_eth_private *mdp = netdev_priv(ndev); 2182 return mdp->msg_enable; 2183 } 2184 2185 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value) 2186 { 2187 struct sh_eth_private *mdp = netdev_priv(ndev); 2188 mdp->msg_enable = value; 2189 } 2190 2191 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = { 2192 "rx_current", "tx_current", 2193 "rx_dirty", "tx_dirty", 2194 }; 2195 #define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats) 2196 2197 static int sh_eth_get_sset_count(struct net_device *netdev, int sset) 2198 { 2199 switch (sset) { 2200 case ETH_SS_STATS: 2201 return SH_ETH_STATS_LEN; 2202 default: 2203 return -EOPNOTSUPP; 2204 } 2205 } 2206 2207 static void sh_eth_get_ethtool_stats(struct net_device *ndev, 2208 struct ethtool_stats *stats, u64 *data) 2209 { 2210 struct sh_eth_private *mdp = netdev_priv(ndev); 2211 int i = 0; 2212 2213 /* device-specific stats */ 2214 data[i++] = mdp->cur_rx; 2215 data[i++] = mdp->cur_tx; 2216 data[i++] = mdp->dirty_rx; 2217 data[i++] = mdp->dirty_tx; 2218 } 2219 2220 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 2221 { 2222 switch (stringset) { 2223 case ETH_SS_STATS: 2224 memcpy(data, *sh_eth_gstrings_stats, 2225 sizeof(sh_eth_gstrings_stats)); 2226 break; 2227 } 2228 } 2229 2230 static void sh_eth_get_ringparam(struct net_device *ndev, 2231 struct ethtool_ringparam *ring) 2232 { 2233 struct sh_eth_private *mdp = netdev_priv(ndev); 2234 2235 ring->rx_max_pending = RX_RING_MAX; 2236 ring->tx_max_pending = TX_RING_MAX; 2237 ring->rx_pending = mdp->num_rx_ring; 2238 ring->tx_pending = mdp->num_tx_ring; 2239 } 2240 2241 static int sh_eth_set_ringparam(struct net_device *ndev, 2242 struct ethtool_ringparam *ring) 2243 { 2244 struct sh_eth_private *mdp = netdev_priv(ndev); 2245 int ret; 2246 2247 if (ring->tx_pending > TX_RING_MAX || 2248 ring->rx_pending > RX_RING_MAX || 2249 ring->tx_pending < TX_RING_MIN || 2250 ring->rx_pending < RX_RING_MIN) 2251 return -EINVAL; 2252 if (ring->rx_mini_pending || ring->rx_jumbo_pending) 2253 return -EINVAL; 2254 2255 if (netif_running(ndev)) { 2256 netif_device_detach(ndev); 2257 netif_tx_disable(ndev); 2258 2259 /* Serialise with the interrupt handler and NAPI, then 2260 * disable interrupts. We have to clear the 2261 * irq_enabled flag first to ensure that interrupts 2262 * won't be re-enabled. 2263 */ 2264 mdp->irq_enabled = false; 2265 synchronize_irq(ndev->irq); 2266 napi_synchronize(&mdp->napi); 2267 sh_eth_write(ndev, 0x0000, EESIPR); 2268 2269 sh_eth_dev_exit(ndev); 2270 2271 /* Free all the skbuffs in the Rx queue and the DMA buffers. */ 2272 sh_eth_ring_free(ndev); 2273 } 2274 2275 /* Set new parameters */ 2276 mdp->num_rx_ring = ring->rx_pending; 2277 mdp->num_tx_ring = ring->tx_pending; 2278 2279 if (netif_running(ndev)) { 2280 ret = sh_eth_ring_init(ndev); 2281 if (ret < 0) { 2282 netdev_err(ndev, "%s: sh_eth_ring_init failed.\n", 2283 __func__); 2284 return ret; 2285 } 2286 ret = sh_eth_dev_init(ndev); 2287 if (ret < 0) { 2288 netdev_err(ndev, "%s: sh_eth_dev_init failed.\n", 2289 __func__); 2290 return ret; 2291 } 2292 2293 netif_device_attach(ndev); 2294 } 2295 2296 return 0; 2297 } 2298 2299 static void sh_eth_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2300 { 2301 struct sh_eth_private *mdp = netdev_priv(ndev); 2302 2303 wol->supported = 0; 2304 wol->wolopts = 0; 2305 2306 if (mdp->cd->magic) { 2307 wol->supported = WAKE_MAGIC; 2308 wol->wolopts = mdp->wol_enabled ? WAKE_MAGIC : 0; 2309 } 2310 } 2311 2312 static int sh_eth_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2313 { 2314 struct sh_eth_private *mdp = netdev_priv(ndev); 2315 2316 if (!mdp->cd->magic || wol->wolopts & ~WAKE_MAGIC) 2317 return -EOPNOTSUPP; 2318 2319 mdp->wol_enabled = !!(wol->wolopts & WAKE_MAGIC); 2320 2321 device_set_wakeup_enable(&mdp->pdev->dev, mdp->wol_enabled); 2322 2323 return 0; 2324 } 2325 2326 static const struct ethtool_ops sh_eth_ethtool_ops = { 2327 .get_regs_len = sh_eth_get_regs_len, 2328 .get_regs = sh_eth_get_regs, 2329 .nway_reset = sh_eth_nway_reset, 2330 .get_msglevel = sh_eth_get_msglevel, 2331 .set_msglevel = sh_eth_set_msglevel, 2332 .get_link = ethtool_op_get_link, 2333 .get_strings = sh_eth_get_strings, 2334 .get_ethtool_stats = sh_eth_get_ethtool_stats, 2335 .get_sset_count = sh_eth_get_sset_count, 2336 .get_ringparam = sh_eth_get_ringparam, 2337 .set_ringparam = sh_eth_set_ringparam, 2338 .get_link_ksettings = sh_eth_get_link_ksettings, 2339 .set_link_ksettings = sh_eth_set_link_ksettings, 2340 .get_wol = sh_eth_get_wol, 2341 .set_wol = sh_eth_set_wol, 2342 }; 2343 2344 /* network device open function */ 2345 static int sh_eth_open(struct net_device *ndev) 2346 { 2347 struct sh_eth_private *mdp = netdev_priv(ndev); 2348 int ret; 2349 2350 pm_runtime_get_sync(&mdp->pdev->dev); 2351 2352 napi_enable(&mdp->napi); 2353 2354 ret = request_irq(ndev->irq, sh_eth_interrupt, 2355 mdp->cd->irq_flags, ndev->name, ndev); 2356 if (ret) { 2357 netdev_err(ndev, "Can not assign IRQ number\n"); 2358 goto out_napi_off; 2359 } 2360 2361 /* Descriptor set */ 2362 ret = sh_eth_ring_init(ndev); 2363 if (ret) 2364 goto out_free_irq; 2365 2366 /* device init */ 2367 ret = sh_eth_dev_init(ndev); 2368 if (ret) 2369 goto out_free_irq; 2370 2371 /* PHY control start*/ 2372 ret = sh_eth_phy_start(ndev); 2373 if (ret) 2374 goto out_free_irq; 2375 2376 netif_start_queue(ndev); 2377 2378 mdp->is_opened = 1; 2379 2380 return ret; 2381 2382 out_free_irq: 2383 free_irq(ndev->irq, ndev); 2384 out_napi_off: 2385 napi_disable(&mdp->napi); 2386 pm_runtime_put_sync(&mdp->pdev->dev); 2387 return ret; 2388 } 2389 2390 /* Timeout function */ 2391 static void sh_eth_tx_timeout(struct net_device *ndev) 2392 { 2393 struct sh_eth_private *mdp = netdev_priv(ndev); 2394 struct sh_eth_rxdesc *rxdesc; 2395 int i; 2396 2397 netif_stop_queue(ndev); 2398 2399 netif_err(mdp, timer, ndev, 2400 "transmit timed out, status %8.8x, resetting...\n", 2401 sh_eth_read(ndev, EESR)); 2402 2403 /* tx_errors count up */ 2404 ndev->stats.tx_errors++; 2405 2406 /* Free all the skbuffs in the Rx queue. */ 2407 for (i = 0; i < mdp->num_rx_ring; i++) { 2408 rxdesc = &mdp->rx_ring[i]; 2409 rxdesc->status = cpu_to_le32(0); 2410 rxdesc->addr = cpu_to_le32(0xBADF00D0); 2411 dev_kfree_skb(mdp->rx_skbuff[i]); 2412 mdp->rx_skbuff[i] = NULL; 2413 } 2414 for (i = 0; i < mdp->num_tx_ring; i++) { 2415 dev_kfree_skb(mdp->tx_skbuff[i]); 2416 mdp->tx_skbuff[i] = NULL; 2417 } 2418 2419 /* device init */ 2420 sh_eth_dev_init(ndev); 2421 2422 netif_start_queue(ndev); 2423 } 2424 2425 /* Packet transmit function */ 2426 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev) 2427 { 2428 struct sh_eth_private *mdp = netdev_priv(ndev); 2429 struct sh_eth_txdesc *txdesc; 2430 dma_addr_t dma_addr; 2431 u32 entry; 2432 unsigned long flags; 2433 2434 spin_lock_irqsave(&mdp->lock, flags); 2435 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) { 2436 if (!sh_eth_tx_free(ndev, true)) { 2437 netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n"); 2438 netif_stop_queue(ndev); 2439 spin_unlock_irqrestore(&mdp->lock, flags); 2440 return NETDEV_TX_BUSY; 2441 } 2442 } 2443 spin_unlock_irqrestore(&mdp->lock, flags); 2444 2445 if (skb_put_padto(skb, ETH_ZLEN)) 2446 return NETDEV_TX_OK; 2447 2448 entry = mdp->cur_tx % mdp->num_tx_ring; 2449 mdp->tx_skbuff[entry] = skb; 2450 txdesc = &mdp->tx_ring[entry]; 2451 /* soft swap. */ 2452 if (!mdp->cd->hw_swap) 2453 sh_eth_soft_swap(PTR_ALIGN(skb->data, 4), skb->len + 2); 2454 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, skb->len, 2455 DMA_TO_DEVICE); 2456 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) { 2457 kfree_skb(skb); 2458 return NETDEV_TX_OK; 2459 } 2460 txdesc->addr = cpu_to_le32(dma_addr); 2461 txdesc->len = cpu_to_le32(skb->len << 16); 2462 2463 dma_wmb(); /* TACT bit must be set after all the above writes */ 2464 if (entry >= mdp->num_tx_ring - 1) 2465 txdesc->status |= cpu_to_le32(TD_TACT | TD_TDLE); 2466 else 2467 txdesc->status |= cpu_to_le32(TD_TACT); 2468 2469 mdp->cur_tx++; 2470 2471 if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp))) 2472 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR); 2473 2474 return NETDEV_TX_OK; 2475 } 2476 2477 /* The statistics registers have write-clear behaviour, which means we 2478 * will lose any increment between the read and write. We mitigate 2479 * this by only clearing when we read a non-zero value, so we will 2480 * never falsely report a total of zero. 2481 */ 2482 static void 2483 sh_eth_update_stat(struct net_device *ndev, unsigned long *stat, int reg) 2484 { 2485 u32 delta = sh_eth_read(ndev, reg); 2486 2487 if (delta) { 2488 *stat += delta; 2489 sh_eth_write(ndev, 0, reg); 2490 } 2491 } 2492 2493 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev) 2494 { 2495 struct sh_eth_private *mdp = netdev_priv(ndev); 2496 2497 if (sh_eth_is_rz_fast_ether(mdp)) 2498 return &ndev->stats; 2499 2500 if (!mdp->is_opened) 2501 return &ndev->stats; 2502 2503 sh_eth_update_stat(ndev, &ndev->stats.tx_dropped, TROCR); 2504 sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR); 2505 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR); 2506 2507 if (sh_eth_is_gether(mdp)) { 2508 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, 2509 CERCR); 2510 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, 2511 CEECR); 2512 } else { 2513 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, 2514 CNDCR); 2515 } 2516 2517 return &ndev->stats; 2518 } 2519 2520 /* device close function */ 2521 static int sh_eth_close(struct net_device *ndev) 2522 { 2523 struct sh_eth_private *mdp = netdev_priv(ndev); 2524 2525 netif_stop_queue(ndev); 2526 2527 /* Serialise with the interrupt handler and NAPI, then disable 2528 * interrupts. We have to clear the irq_enabled flag first to 2529 * ensure that interrupts won't be re-enabled. 2530 */ 2531 mdp->irq_enabled = false; 2532 synchronize_irq(ndev->irq); 2533 napi_disable(&mdp->napi); 2534 sh_eth_write(ndev, 0x0000, EESIPR); 2535 2536 sh_eth_dev_exit(ndev); 2537 2538 /* PHY Disconnect */ 2539 if (ndev->phydev) { 2540 phy_stop(ndev->phydev); 2541 phy_disconnect(ndev->phydev); 2542 } 2543 2544 free_irq(ndev->irq, ndev); 2545 2546 /* Free all the skbuffs in the Rx queue and the DMA buffer. */ 2547 sh_eth_ring_free(ndev); 2548 2549 pm_runtime_put_sync(&mdp->pdev->dev); 2550 2551 mdp->is_opened = 0; 2552 2553 return 0; 2554 } 2555 2556 /* ioctl to device function */ 2557 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) 2558 { 2559 struct phy_device *phydev = ndev->phydev; 2560 2561 if (!netif_running(ndev)) 2562 return -EINVAL; 2563 2564 if (!phydev) 2565 return -ENODEV; 2566 2567 return phy_mii_ioctl(phydev, rq, cmd); 2568 } 2569 2570 static int sh_eth_change_mtu(struct net_device *ndev, int new_mtu) 2571 { 2572 if (netif_running(ndev)) 2573 return -EBUSY; 2574 2575 ndev->mtu = new_mtu; 2576 netdev_update_features(ndev); 2577 2578 return 0; 2579 } 2580 2581 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */ 2582 static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp, 2583 int entry) 2584 { 2585 return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4); 2586 } 2587 2588 static u32 sh_eth_tsu_get_post_mask(int entry) 2589 { 2590 return 0x0f << (28 - ((entry % 8) * 4)); 2591 } 2592 2593 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry) 2594 { 2595 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4)); 2596 } 2597 2598 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev, 2599 int entry) 2600 { 2601 struct sh_eth_private *mdp = netdev_priv(ndev); 2602 u32 tmp; 2603 void *reg_offset; 2604 2605 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry); 2606 tmp = ioread32(reg_offset); 2607 iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset); 2608 } 2609 2610 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev, 2611 int entry) 2612 { 2613 struct sh_eth_private *mdp = netdev_priv(ndev); 2614 u32 post_mask, ref_mask, tmp; 2615 void *reg_offset; 2616 2617 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry); 2618 post_mask = sh_eth_tsu_get_post_mask(entry); 2619 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask; 2620 2621 tmp = ioread32(reg_offset); 2622 iowrite32(tmp & ~post_mask, reg_offset); 2623 2624 /* If other port enables, the function returns "true" */ 2625 return tmp & ref_mask; 2626 } 2627 2628 static int sh_eth_tsu_busy(struct net_device *ndev) 2629 { 2630 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100; 2631 struct sh_eth_private *mdp = netdev_priv(ndev); 2632 2633 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) { 2634 udelay(10); 2635 timeout--; 2636 if (timeout <= 0) { 2637 netdev_err(ndev, "%s: timeout\n", __func__); 2638 return -ETIMEDOUT; 2639 } 2640 } 2641 2642 return 0; 2643 } 2644 2645 static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg, 2646 const u8 *addr) 2647 { 2648 u32 val; 2649 2650 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3]; 2651 iowrite32(val, reg); 2652 if (sh_eth_tsu_busy(ndev) < 0) 2653 return -EBUSY; 2654 2655 val = addr[4] << 8 | addr[5]; 2656 iowrite32(val, reg + 4); 2657 if (sh_eth_tsu_busy(ndev) < 0) 2658 return -EBUSY; 2659 2660 return 0; 2661 } 2662 2663 static void sh_eth_tsu_read_entry(void *reg, u8 *addr) 2664 { 2665 u32 val; 2666 2667 val = ioread32(reg); 2668 addr[0] = (val >> 24) & 0xff; 2669 addr[1] = (val >> 16) & 0xff; 2670 addr[2] = (val >> 8) & 0xff; 2671 addr[3] = val & 0xff; 2672 val = ioread32(reg + 4); 2673 addr[4] = (val >> 8) & 0xff; 2674 addr[5] = val & 0xff; 2675 } 2676 2677 2678 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr) 2679 { 2680 struct sh_eth_private *mdp = netdev_priv(ndev); 2681 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2682 int i; 2683 u8 c_addr[ETH_ALEN]; 2684 2685 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) { 2686 sh_eth_tsu_read_entry(reg_offset, c_addr); 2687 if (ether_addr_equal(addr, c_addr)) 2688 return i; 2689 } 2690 2691 return -ENOENT; 2692 } 2693 2694 static int sh_eth_tsu_find_empty(struct net_device *ndev) 2695 { 2696 u8 blank[ETH_ALEN]; 2697 int entry; 2698 2699 memset(blank, 0, sizeof(blank)); 2700 entry = sh_eth_tsu_find_entry(ndev, blank); 2701 return (entry < 0) ? -ENOMEM : entry; 2702 } 2703 2704 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev, 2705 int entry) 2706 { 2707 struct sh_eth_private *mdp = netdev_priv(ndev); 2708 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2709 int ret; 2710 u8 blank[ETH_ALEN]; 2711 2712 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) & 2713 ~(1 << (31 - entry)), TSU_TEN); 2714 2715 memset(blank, 0, sizeof(blank)); 2716 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank); 2717 if (ret < 0) 2718 return ret; 2719 return 0; 2720 } 2721 2722 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr) 2723 { 2724 struct sh_eth_private *mdp = netdev_priv(ndev); 2725 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2726 int i, ret; 2727 2728 if (!mdp->cd->tsu) 2729 return 0; 2730 2731 i = sh_eth_tsu_find_entry(ndev, addr); 2732 if (i < 0) { 2733 /* No entry found, create one */ 2734 i = sh_eth_tsu_find_empty(ndev); 2735 if (i < 0) 2736 return -ENOMEM; 2737 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr); 2738 if (ret < 0) 2739 return ret; 2740 2741 /* Enable the entry */ 2742 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) | 2743 (1 << (31 - i)), TSU_TEN); 2744 } 2745 2746 /* Entry found or created, enable POST */ 2747 sh_eth_tsu_enable_cam_entry_post(ndev, i); 2748 2749 return 0; 2750 } 2751 2752 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr) 2753 { 2754 struct sh_eth_private *mdp = netdev_priv(ndev); 2755 int i, ret; 2756 2757 if (!mdp->cd->tsu) 2758 return 0; 2759 2760 i = sh_eth_tsu_find_entry(ndev, addr); 2761 if (i) { 2762 /* Entry found */ 2763 if (sh_eth_tsu_disable_cam_entry_post(ndev, i)) 2764 goto done; 2765 2766 /* Disable the entry if both ports was disabled */ 2767 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i); 2768 if (ret < 0) 2769 return ret; 2770 } 2771 done: 2772 return 0; 2773 } 2774 2775 static int sh_eth_tsu_purge_all(struct net_device *ndev) 2776 { 2777 struct sh_eth_private *mdp = netdev_priv(ndev); 2778 int i, ret; 2779 2780 if (!mdp->cd->tsu) 2781 return 0; 2782 2783 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) { 2784 if (sh_eth_tsu_disable_cam_entry_post(ndev, i)) 2785 continue; 2786 2787 /* Disable the entry if both ports was disabled */ 2788 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i); 2789 if (ret < 0) 2790 return ret; 2791 } 2792 2793 return 0; 2794 } 2795 2796 static void sh_eth_tsu_purge_mcast(struct net_device *ndev) 2797 { 2798 struct sh_eth_private *mdp = netdev_priv(ndev); 2799 u8 addr[ETH_ALEN]; 2800 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2801 int i; 2802 2803 if (!mdp->cd->tsu) 2804 return; 2805 2806 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) { 2807 sh_eth_tsu_read_entry(reg_offset, addr); 2808 if (is_multicast_ether_addr(addr)) 2809 sh_eth_tsu_del_entry(ndev, addr); 2810 } 2811 } 2812 2813 /* Update promiscuous flag and multicast filter */ 2814 static void sh_eth_set_rx_mode(struct net_device *ndev) 2815 { 2816 struct sh_eth_private *mdp = netdev_priv(ndev); 2817 u32 ecmr_bits; 2818 int mcast_all = 0; 2819 unsigned long flags; 2820 2821 spin_lock_irqsave(&mdp->lock, flags); 2822 /* Initial condition is MCT = 1, PRM = 0. 2823 * Depending on ndev->flags, set PRM or clear MCT 2824 */ 2825 ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM; 2826 if (mdp->cd->tsu) 2827 ecmr_bits |= ECMR_MCT; 2828 2829 if (!(ndev->flags & IFF_MULTICAST)) { 2830 sh_eth_tsu_purge_mcast(ndev); 2831 mcast_all = 1; 2832 } 2833 if (ndev->flags & IFF_ALLMULTI) { 2834 sh_eth_tsu_purge_mcast(ndev); 2835 ecmr_bits &= ~ECMR_MCT; 2836 mcast_all = 1; 2837 } 2838 2839 if (ndev->flags & IFF_PROMISC) { 2840 sh_eth_tsu_purge_all(ndev); 2841 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM; 2842 } else if (mdp->cd->tsu) { 2843 struct netdev_hw_addr *ha; 2844 netdev_for_each_mc_addr(ha, ndev) { 2845 if (mcast_all && is_multicast_ether_addr(ha->addr)) 2846 continue; 2847 2848 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) { 2849 if (!mcast_all) { 2850 sh_eth_tsu_purge_mcast(ndev); 2851 ecmr_bits &= ~ECMR_MCT; 2852 mcast_all = 1; 2853 } 2854 } 2855 } 2856 } 2857 2858 /* update the ethernet mode */ 2859 sh_eth_write(ndev, ecmr_bits, ECMR); 2860 2861 spin_unlock_irqrestore(&mdp->lock, flags); 2862 } 2863 2864 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp) 2865 { 2866 if (!mdp->port) 2867 return TSU_VTAG0; 2868 else 2869 return TSU_VTAG1; 2870 } 2871 2872 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev, 2873 __be16 proto, u16 vid) 2874 { 2875 struct sh_eth_private *mdp = netdev_priv(ndev); 2876 int vtag_reg_index = sh_eth_get_vtag_index(mdp); 2877 2878 if (unlikely(!mdp->cd->tsu)) 2879 return -EPERM; 2880 2881 /* No filtering if vid = 0 */ 2882 if (!vid) 2883 return 0; 2884 2885 mdp->vlan_num_ids++; 2886 2887 /* The controller has one VLAN tag HW filter. So, if the filter is 2888 * already enabled, the driver disables it and the filte 2889 */ 2890 if (mdp->vlan_num_ids > 1) { 2891 /* disable VLAN filter */ 2892 sh_eth_tsu_write(mdp, 0, vtag_reg_index); 2893 return 0; 2894 } 2895 2896 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK), 2897 vtag_reg_index); 2898 2899 return 0; 2900 } 2901 2902 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev, 2903 __be16 proto, u16 vid) 2904 { 2905 struct sh_eth_private *mdp = netdev_priv(ndev); 2906 int vtag_reg_index = sh_eth_get_vtag_index(mdp); 2907 2908 if (unlikely(!mdp->cd->tsu)) 2909 return -EPERM; 2910 2911 /* No filtering if vid = 0 */ 2912 if (!vid) 2913 return 0; 2914 2915 mdp->vlan_num_ids--; 2916 sh_eth_tsu_write(mdp, 0, vtag_reg_index); 2917 2918 return 0; 2919 } 2920 2921 /* SuperH's TSU register init function */ 2922 static void sh_eth_tsu_init(struct sh_eth_private *mdp) 2923 { 2924 if (sh_eth_is_rz_fast_ether(mdp)) { 2925 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */ 2926 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, 2927 TSU_FWSLC); /* Enable POST registers */ 2928 return; 2929 } 2930 2931 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */ 2932 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */ 2933 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */ 2934 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0); 2935 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1); 2936 sh_eth_tsu_write(mdp, 0, TSU_PRISL0); 2937 sh_eth_tsu_write(mdp, 0, TSU_PRISL1); 2938 sh_eth_tsu_write(mdp, 0, TSU_FWSL0); 2939 sh_eth_tsu_write(mdp, 0, TSU_FWSL1); 2940 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC); 2941 if (sh_eth_is_gether(mdp)) { 2942 sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */ 2943 sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */ 2944 } else { 2945 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */ 2946 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */ 2947 } 2948 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */ 2949 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */ 2950 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */ 2951 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */ 2952 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */ 2953 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */ 2954 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */ 2955 } 2956 2957 /* MDIO bus release function */ 2958 static int sh_mdio_release(struct sh_eth_private *mdp) 2959 { 2960 /* unregister mdio bus */ 2961 mdiobus_unregister(mdp->mii_bus); 2962 2963 /* free bitbang info */ 2964 free_mdio_bitbang(mdp->mii_bus); 2965 2966 return 0; 2967 } 2968 2969 /* MDIO bus init function */ 2970 static int sh_mdio_init(struct sh_eth_private *mdp, 2971 struct sh_eth_plat_data *pd) 2972 { 2973 int ret; 2974 struct bb_info *bitbang; 2975 struct platform_device *pdev = mdp->pdev; 2976 struct device *dev = &mdp->pdev->dev; 2977 2978 /* create bit control struct for PHY */ 2979 bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL); 2980 if (!bitbang) 2981 return -ENOMEM; 2982 2983 /* bitbang init */ 2984 bitbang->addr = mdp->addr + mdp->reg_offset[PIR]; 2985 bitbang->set_gate = pd->set_mdio_gate; 2986 bitbang->ctrl.ops = &bb_ops; 2987 2988 /* MII controller setting */ 2989 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl); 2990 if (!mdp->mii_bus) 2991 return -ENOMEM; 2992 2993 /* Hook up MII support for ethtool */ 2994 mdp->mii_bus->name = "sh_mii"; 2995 mdp->mii_bus->parent = dev; 2996 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 2997 pdev->name, pdev->id); 2998 2999 /* register MDIO bus */ 3000 if (dev->of_node) { 3001 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node); 3002 } else { 3003 if (pd->phy_irq > 0) 3004 mdp->mii_bus->irq[pd->phy] = pd->phy_irq; 3005 3006 ret = mdiobus_register(mdp->mii_bus); 3007 } 3008 3009 if (ret) 3010 goto out_free_bus; 3011 3012 return 0; 3013 3014 out_free_bus: 3015 free_mdio_bitbang(mdp->mii_bus); 3016 return ret; 3017 } 3018 3019 static const u16 *sh_eth_get_register_offset(int register_type) 3020 { 3021 const u16 *reg_offset = NULL; 3022 3023 switch (register_type) { 3024 case SH_ETH_REG_GIGABIT: 3025 reg_offset = sh_eth_offset_gigabit; 3026 break; 3027 case SH_ETH_REG_FAST_RZ: 3028 reg_offset = sh_eth_offset_fast_rz; 3029 break; 3030 case SH_ETH_REG_FAST_RCAR: 3031 reg_offset = sh_eth_offset_fast_rcar; 3032 break; 3033 case SH_ETH_REG_FAST_SH4: 3034 reg_offset = sh_eth_offset_fast_sh4; 3035 break; 3036 case SH_ETH_REG_FAST_SH3_SH2: 3037 reg_offset = sh_eth_offset_fast_sh3_sh2; 3038 break; 3039 } 3040 3041 return reg_offset; 3042 } 3043 3044 static const struct net_device_ops sh_eth_netdev_ops = { 3045 .ndo_open = sh_eth_open, 3046 .ndo_stop = sh_eth_close, 3047 .ndo_start_xmit = sh_eth_start_xmit, 3048 .ndo_get_stats = sh_eth_get_stats, 3049 .ndo_set_rx_mode = sh_eth_set_rx_mode, 3050 .ndo_tx_timeout = sh_eth_tx_timeout, 3051 .ndo_do_ioctl = sh_eth_do_ioctl, 3052 .ndo_change_mtu = sh_eth_change_mtu, 3053 .ndo_validate_addr = eth_validate_addr, 3054 .ndo_set_mac_address = eth_mac_addr, 3055 }; 3056 3057 static const struct net_device_ops sh_eth_netdev_ops_tsu = { 3058 .ndo_open = sh_eth_open, 3059 .ndo_stop = sh_eth_close, 3060 .ndo_start_xmit = sh_eth_start_xmit, 3061 .ndo_get_stats = sh_eth_get_stats, 3062 .ndo_set_rx_mode = sh_eth_set_rx_mode, 3063 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid, 3064 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid, 3065 .ndo_tx_timeout = sh_eth_tx_timeout, 3066 .ndo_do_ioctl = sh_eth_do_ioctl, 3067 .ndo_change_mtu = sh_eth_change_mtu, 3068 .ndo_validate_addr = eth_validate_addr, 3069 .ndo_set_mac_address = eth_mac_addr, 3070 }; 3071 3072 #ifdef CONFIG_OF 3073 static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev) 3074 { 3075 struct device_node *np = dev->of_node; 3076 struct sh_eth_plat_data *pdata; 3077 const char *mac_addr; 3078 3079 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 3080 if (!pdata) 3081 return NULL; 3082 3083 pdata->phy_interface = of_get_phy_mode(np); 3084 3085 mac_addr = of_get_mac_address(np); 3086 if (mac_addr) 3087 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN); 3088 3089 pdata->no_ether_link = 3090 of_property_read_bool(np, "renesas,no-ether-link"); 3091 pdata->ether_link_active_low = 3092 of_property_read_bool(np, "renesas,ether-link-active-low"); 3093 3094 return pdata; 3095 } 3096 3097 static const struct of_device_id sh_eth_match_table[] = { 3098 { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data }, 3099 { .compatible = "renesas,ether-r8a7743", .data = &rcar_gen2_data }, 3100 { .compatible = "renesas,ether-r8a7745", .data = &rcar_gen2_data }, 3101 { .compatible = "renesas,ether-r8a7778", .data = &rcar_gen1_data }, 3102 { .compatible = "renesas,ether-r8a7779", .data = &rcar_gen1_data }, 3103 { .compatible = "renesas,ether-r8a7790", .data = &rcar_gen2_data }, 3104 { .compatible = "renesas,ether-r8a7791", .data = &rcar_gen2_data }, 3105 { .compatible = "renesas,ether-r8a7793", .data = &rcar_gen2_data }, 3106 { .compatible = "renesas,ether-r8a7794", .data = &rcar_gen2_data }, 3107 { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data }, 3108 { .compatible = "renesas,rcar-gen1-ether", .data = &rcar_gen1_data }, 3109 { .compatible = "renesas,rcar-gen2-ether", .data = &rcar_gen2_data }, 3110 { } 3111 }; 3112 MODULE_DEVICE_TABLE(of, sh_eth_match_table); 3113 #else 3114 static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev) 3115 { 3116 return NULL; 3117 } 3118 #endif 3119 3120 static int sh_eth_drv_probe(struct platform_device *pdev) 3121 { 3122 struct resource *res; 3123 struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev); 3124 const struct platform_device_id *id = platform_get_device_id(pdev); 3125 struct sh_eth_private *mdp; 3126 struct net_device *ndev; 3127 int ret; 3128 3129 /* get base addr */ 3130 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 3131 3132 ndev = alloc_etherdev(sizeof(struct sh_eth_private)); 3133 if (!ndev) 3134 return -ENOMEM; 3135 3136 pm_runtime_enable(&pdev->dev); 3137 pm_runtime_get_sync(&pdev->dev); 3138 3139 ret = platform_get_irq(pdev, 0); 3140 if (ret < 0) 3141 goto out_release; 3142 ndev->irq = ret; 3143 3144 SET_NETDEV_DEV(ndev, &pdev->dev); 3145 3146 mdp = netdev_priv(ndev); 3147 mdp->num_tx_ring = TX_RING_SIZE; 3148 mdp->num_rx_ring = RX_RING_SIZE; 3149 mdp->addr = devm_ioremap_resource(&pdev->dev, res); 3150 if (IS_ERR(mdp->addr)) { 3151 ret = PTR_ERR(mdp->addr); 3152 goto out_release; 3153 } 3154 3155 ndev->base_addr = res->start; 3156 3157 spin_lock_init(&mdp->lock); 3158 mdp->pdev = pdev; 3159 3160 if (pdev->dev.of_node) 3161 pd = sh_eth_parse_dt(&pdev->dev); 3162 if (!pd) { 3163 dev_err(&pdev->dev, "no platform data\n"); 3164 ret = -EINVAL; 3165 goto out_release; 3166 } 3167 3168 /* get PHY ID */ 3169 mdp->phy_id = pd->phy; 3170 mdp->phy_interface = pd->phy_interface; 3171 mdp->no_ether_link = pd->no_ether_link; 3172 mdp->ether_link_active_low = pd->ether_link_active_low; 3173 3174 /* set cpu data */ 3175 if (id) 3176 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data; 3177 else 3178 mdp->cd = (struct sh_eth_cpu_data *)of_device_get_match_data(&pdev->dev); 3179 3180 mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type); 3181 if (!mdp->reg_offset) { 3182 dev_err(&pdev->dev, "Unknown register type (%d)\n", 3183 mdp->cd->register_type); 3184 ret = -EINVAL; 3185 goto out_release; 3186 } 3187 sh_eth_set_default_cpu_data(mdp->cd); 3188 3189 /* User's manual states max MTU should be 2048 but due to the 3190 * alignment calculations in sh_eth_ring_init() the practical 3191 * MTU is a bit less. Maybe this can be optimized some more. 3192 */ 3193 ndev->max_mtu = 2000 - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN); 3194 ndev->min_mtu = ETH_MIN_MTU; 3195 3196 /* set function */ 3197 if (mdp->cd->tsu) 3198 ndev->netdev_ops = &sh_eth_netdev_ops_tsu; 3199 else 3200 ndev->netdev_ops = &sh_eth_netdev_ops; 3201 ndev->ethtool_ops = &sh_eth_ethtool_ops; 3202 ndev->watchdog_timeo = TX_TIMEOUT; 3203 3204 /* debug message level */ 3205 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE; 3206 3207 /* read and set MAC address */ 3208 read_mac_address(ndev, pd->mac_addr); 3209 if (!is_valid_ether_addr(ndev->dev_addr)) { 3210 dev_warn(&pdev->dev, 3211 "no valid MAC address supplied, using a random one.\n"); 3212 eth_hw_addr_random(ndev); 3213 } 3214 3215 if (mdp->cd->tsu) { 3216 int port = pdev->id < 0 ? 0 : pdev->id % 2; 3217 struct resource *rtsu; 3218 3219 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1); 3220 if (!rtsu) { 3221 dev_err(&pdev->dev, "no TSU resource\n"); 3222 ret = -ENODEV; 3223 goto out_release; 3224 } 3225 /* We can only request the TSU region for the first port 3226 * of the two sharing this TSU for the probe to succeed... 3227 */ 3228 if (port == 0 && 3229 !devm_request_mem_region(&pdev->dev, rtsu->start, 3230 resource_size(rtsu), 3231 dev_name(&pdev->dev))) { 3232 dev_err(&pdev->dev, "can't request TSU resource.\n"); 3233 ret = -EBUSY; 3234 goto out_release; 3235 } 3236 /* ioremap the TSU registers */ 3237 mdp->tsu_addr = devm_ioremap(&pdev->dev, rtsu->start, 3238 resource_size(rtsu)); 3239 if (!mdp->tsu_addr) { 3240 dev_err(&pdev->dev, "TSU region ioremap() failed.\n"); 3241 ret = -ENOMEM; 3242 goto out_release; 3243 } 3244 mdp->port = port; 3245 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER; 3246 3247 /* Need to init only the first port of the two sharing a TSU */ 3248 if (port == 0) { 3249 if (mdp->cd->chip_reset) 3250 mdp->cd->chip_reset(ndev); 3251 3252 /* TSU init (Init only)*/ 3253 sh_eth_tsu_init(mdp); 3254 } 3255 } 3256 3257 if (mdp->cd->rmiimode) 3258 sh_eth_write(ndev, 0x1, RMIIMODE); 3259 3260 /* MDIO bus init */ 3261 ret = sh_mdio_init(mdp, pd); 3262 if (ret) { 3263 if (ret != -EPROBE_DEFER) 3264 dev_err(&pdev->dev, "MDIO init failed: %d\n", ret); 3265 goto out_release; 3266 } 3267 3268 netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64); 3269 3270 /* network device register */ 3271 ret = register_netdev(ndev); 3272 if (ret) 3273 goto out_napi_del; 3274 3275 if (mdp->cd->magic) 3276 device_set_wakeup_capable(&pdev->dev, 1); 3277 3278 /* print device information */ 3279 netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n", 3280 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq); 3281 3282 pm_runtime_put(&pdev->dev); 3283 platform_set_drvdata(pdev, ndev); 3284 3285 return ret; 3286 3287 out_napi_del: 3288 netif_napi_del(&mdp->napi); 3289 sh_mdio_release(mdp); 3290 3291 out_release: 3292 /* net_dev free */ 3293 free_netdev(ndev); 3294 3295 pm_runtime_put(&pdev->dev); 3296 pm_runtime_disable(&pdev->dev); 3297 return ret; 3298 } 3299 3300 static int sh_eth_drv_remove(struct platform_device *pdev) 3301 { 3302 struct net_device *ndev = platform_get_drvdata(pdev); 3303 struct sh_eth_private *mdp = netdev_priv(ndev); 3304 3305 unregister_netdev(ndev); 3306 netif_napi_del(&mdp->napi); 3307 sh_mdio_release(mdp); 3308 pm_runtime_disable(&pdev->dev); 3309 free_netdev(ndev); 3310 3311 return 0; 3312 } 3313 3314 #ifdef CONFIG_PM 3315 #ifdef CONFIG_PM_SLEEP 3316 static int sh_eth_wol_setup(struct net_device *ndev) 3317 { 3318 struct sh_eth_private *mdp = netdev_priv(ndev); 3319 3320 /* Only allow ECI interrupts */ 3321 synchronize_irq(ndev->irq); 3322 napi_disable(&mdp->napi); 3323 sh_eth_write(ndev, EESIPR_ECIIP, EESIPR); 3324 3325 /* Enable MagicPacket */ 3326 sh_eth_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE); 3327 3328 return enable_irq_wake(ndev->irq); 3329 } 3330 3331 static int sh_eth_wol_restore(struct net_device *ndev) 3332 { 3333 struct sh_eth_private *mdp = netdev_priv(ndev); 3334 int ret; 3335 3336 napi_enable(&mdp->napi); 3337 3338 /* Disable MagicPacket */ 3339 sh_eth_modify(ndev, ECMR, ECMR_MPDE, 0); 3340 3341 /* The device needs to be reset to restore MagicPacket logic 3342 * for next wakeup. If we close and open the device it will 3343 * both be reset and all registers restored. This is what 3344 * happens during suspend and resume without WoL enabled. 3345 */ 3346 ret = sh_eth_close(ndev); 3347 if (ret < 0) 3348 return ret; 3349 ret = sh_eth_open(ndev); 3350 if (ret < 0) 3351 return ret; 3352 3353 return disable_irq_wake(ndev->irq); 3354 } 3355 3356 static int sh_eth_suspend(struct device *dev) 3357 { 3358 struct net_device *ndev = dev_get_drvdata(dev); 3359 struct sh_eth_private *mdp = netdev_priv(ndev); 3360 int ret = 0; 3361 3362 if (!netif_running(ndev)) 3363 return 0; 3364 3365 netif_device_detach(ndev); 3366 3367 if (mdp->wol_enabled) 3368 ret = sh_eth_wol_setup(ndev); 3369 else 3370 ret = sh_eth_close(ndev); 3371 3372 return ret; 3373 } 3374 3375 static int sh_eth_resume(struct device *dev) 3376 { 3377 struct net_device *ndev = dev_get_drvdata(dev); 3378 struct sh_eth_private *mdp = netdev_priv(ndev); 3379 int ret = 0; 3380 3381 if (!netif_running(ndev)) 3382 return 0; 3383 3384 if (mdp->wol_enabled) 3385 ret = sh_eth_wol_restore(ndev); 3386 else 3387 ret = sh_eth_open(ndev); 3388 3389 if (ret < 0) 3390 return ret; 3391 3392 netif_device_attach(ndev); 3393 3394 return ret; 3395 } 3396 #endif 3397 3398 static int sh_eth_runtime_nop(struct device *dev) 3399 { 3400 /* Runtime PM callback shared between ->runtime_suspend() 3401 * and ->runtime_resume(). Simply returns success. 3402 * 3403 * This driver re-initializes all registers after 3404 * pm_runtime_get_sync() anyway so there is no need 3405 * to save and restore registers here. 3406 */ 3407 return 0; 3408 } 3409 3410 static const struct dev_pm_ops sh_eth_dev_pm_ops = { 3411 SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume) 3412 SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL) 3413 }; 3414 #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops) 3415 #else 3416 #define SH_ETH_PM_OPS NULL 3417 #endif 3418 3419 static const struct platform_device_id sh_eth_id_table[] = { 3420 { "sh7619-ether", (kernel_ulong_t)&sh7619_data }, 3421 { "sh771x-ether", (kernel_ulong_t)&sh771x_data }, 3422 { "sh7724-ether", (kernel_ulong_t)&sh7724_data }, 3423 { "sh7734-gether", (kernel_ulong_t)&sh7734_data }, 3424 { "sh7757-ether", (kernel_ulong_t)&sh7757_data }, 3425 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga }, 3426 { "sh7763-gether", (kernel_ulong_t)&sh7763_data }, 3427 { } 3428 }; 3429 MODULE_DEVICE_TABLE(platform, sh_eth_id_table); 3430 3431 static struct platform_driver sh_eth_driver = { 3432 .probe = sh_eth_drv_probe, 3433 .remove = sh_eth_drv_remove, 3434 .id_table = sh_eth_id_table, 3435 .driver = { 3436 .name = CARDNAME, 3437 .pm = SH_ETH_PM_OPS, 3438 .of_match_table = of_match_ptr(sh_eth_match_table), 3439 }, 3440 }; 3441 3442 module_platform_driver(sh_eth_driver); 3443 3444 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda"); 3445 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver"); 3446 MODULE_LICENSE("GPL v2"); 3447