1 /* 2 * mt2701-reg.h -- Mediatek 2701 audio driver reg definition 3 * 4 * Copyright (c) 2016 MediaTek Inc. 5 * Author: Garlic Tseng <garlic.tseng@mediatek.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 and 9 * only version 2 as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 */ 16 17 #ifndef _MT2701_REG_H_ 18 #define _MT2701_REG_H_ 19 20 #define AUDIO_TOP_CON0 0x0000 21 #define AUDIO_TOP_CON4 0x0010 22 #define AUDIO_TOP_CON5 0x0014 23 #define AFE_DAIBT_CON0 0x001c 24 #define AFE_MRGIF_CON 0x003c 25 #define ASMI_TIMING_CON1 0x0100 26 #define ASMO_TIMING_CON1 0x0104 27 #define PWR1_ASM_CON1 0x0108 28 #define ASYS_TOP_CON 0x0600 29 #define ASYS_I2SIN1_CON 0x0604 30 #define ASYS_I2SIN2_CON 0x0608 31 #define ASYS_I2SIN3_CON 0x060c 32 #define ASYS_I2SIN4_CON 0x0610 33 #define ASYS_I2SIN5_CON 0x0614 34 #define ASYS_I2SO1_CON 0x061C 35 #define ASYS_I2SO2_CON 0x0620 36 #define ASYS_I2SO3_CON 0x0624 37 #define ASYS_I2SO4_CON 0x0628 38 #define ASYS_I2SO5_CON 0x062c 39 #define PWR2_TOP_CON 0x0634 40 #define AFE_CONN0 0x06c0 41 #define AFE_CONN1 0x06c4 42 #define AFE_CONN2 0x06c8 43 #define AFE_CONN3 0x06cc 44 #define AFE_CONN14 0x06f8 45 #define AFE_CONN15 0x06fc 46 #define AFE_CONN16 0x0700 47 #define AFE_CONN17 0x0704 48 #define AFE_CONN18 0x0708 49 #define AFE_CONN19 0x070c 50 #define AFE_CONN20 0x0710 51 #define AFE_CONN21 0x0714 52 #define AFE_CONN22 0x0718 53 #define AFE_CONN23 0x071c 54 #define AFE_CONN24 0x0720 55 #define AFE_CONN41 0x0764 56 #define ASYS_IRQ1_CON 0x0780 57 #define ASYS_IRQ2_CON 0x0784 58 #define ASYS_IRQ3_CON 0x0788 59 #define ASYS_IRQ_CLR 0x07c0 60 #define ASYS_IRQ_STATUS 0x07c4 61 #define PWR2_ASM_CON1 0x1070 62 #define AFE_DAC_CON0 0x1200 63 #define AFE_DAC_CON1 0x1204 64 #define AFE_DAC_CON2 0x1208 65 #define AFE_DAC_CON3 0x120c 66 #define AFE_DAC_CON4 0x1210 67 #define AFE_MEMIF_HD_CON1 0x121c 68 #define AFE_MEMIF_PBUF_SIZE 0x1238 69 #define AFE_MEMIF_HD_CON0 0x123c 70 #define AFE_DL1_BASE 0x1240 71 #define AFE_DL1_CUR 0x1244 72 #define AFE_DL2_BASE 0x1250 73 #define AFE_DL2_CUR 0x1254 74 #define AFE_DL3_BASE 0x1260 75 #define AFE_DL3_CUR 0x1264 76 #define AFE_DL4_BASE 0x1270 77 #define AFE_DL4_CUR 0x1274 78 #define AFE_DL5_BASE 0x1280 79 #define AFE_DL5_CUR 0x1284 80 #define AFE_DLMCH_BASE 0x12a0 81 #define AFE_DLMCH_CUR 0x12a4 82 #define AFE_ARB1_BASE 0x12b0 83 #define AFE_ARB1_CUR 0x12b4 84 #define AFE_VUL_BASE 0x1300 85 #define AFE_VUL_CUR 0x130c 86 #define AFE_UL2_BASE 0x1310 87 #define AFE_UL2_END 0x1318 88 #define AFE_UL2_CUR 0x131c 89 #define AFE_UL3_BASE 0x1320 90 #define AFE_UL3_END 0x1328 91 #define AFE_UL3_CUR 0x132c 92 #define AFE_UL4_BASE 0x1330 93 #define AFE_UL4_END 0x1338 94 #define AFE_UL4_CUR 0x133c 95 #define AFE_UL5_BASE 0x1340 96 #define AFE_UL5_END 0x1348 97 #define AFE_UL5_CUR 0x134c 98 #define AFE_DAI_BASE 0x1370 99 #define AFE_DAI_CUR 0x137c 100 101 /* AFE_DAIBT_CON0 (0x001c) */ 102 #define AFE_DAIBT_CON0_DAIBT_EN (0x1 << 0) 103 #define AFE_DAIBT_CON0_BT_FUNC_EN (0x1 << 1) 104 #define AFE_DAIBT_CON0_BT_FUNC_RDY (0x1 << 3) 105 #define AFE_DAIBT_CON0_BT_WIDE_MODE_EN (0x1 << 9) 106 #define AFE_DAIBT_CON0_MRG_USE (0x1 << 12) 107 108 /* PWR1_ASM_CON1 (0x0108) */ 109 #define PWR1_ASM_CON1_INIT_VAL (0x492) 110 111 /* AFE_MRGIF_CON (0x003c) */ 112 #define AFE_MRGIF_CON_MRG_EN (0x1 << 0) 113 #define AFE_MRGIF_CON_MRG_I2S_EN (0x1 << 16) 114 #define AFE_MRGIF_CON_I2S_MODE_MASK (0xf << 20) 115 #define AFE_MRGIF_CON_I2S_MODE_32K (0x4 << 20) 116 117 /* ASYS_TOP_CON (0x0600) */ 118 #define ASYS_TOP_CON_ASYS_TIMING_ON (0x3 << 0) 119 120 /* PWR2_ASM_CON1 (0x1070) */ 121 #define PWR2_ASM_CON1_INIT_VAL (0x492492) 122 123 /* AFE_DAC_CON0 (0x1200) */ 124 #define AFE_DAC_CON0_AFE_ON (0x1 << 0) 125 126 /* AFE_MEMIF_PBUF_SIZE (0x1238) */ 127 #define AFE_MEMIF_PBUF_SIZE_DLM_MASK (0x1 << 29) 128 #define AFE_MEMIF_PBUF_SIZE_PAIR_INTERLEAVE (0x0 << 29) 129 #define AFE_MEMIF_PBUF_SIZE_FULL_INTERLEAVE (0x1 << 29) 130 #define DLMCH_BIT_WIDTH_MASK (0x1 << 28) 131 #define AFE_MEMIF_PBUF_SIZE_DLM_CH_MASK (0xf << 24) 132 #define AFE_MEMIF_PBUF_SIZE_DLM_CH(x) ((x) << 24) 133 #define AFE_MEMIF_PBUF_SIZE_DLM_BYTE_MASK (0x3 << 12) 134 #define AFE_MEMIF_PBUF_SIZE_DLM_32BYTES (0x1 << 12) 135 136 /* I2S in/out register bit control */ 137 #define ASYS_I2S_CON_FS (0x1f << 8) 138 #define ASYS_I2S_CON_FS_SET(x) ((x) << 8) 139 #define ASYS_I2S_CON_RESET (0x1 << 30) 140 #define ASYS_I2S_CON_I2S_EN (0x1 << 0) 141 #define ASYS_I2S_CON_I2S_COUPLE_MODE (0x1 << 17) 142 /* 0:EIAJ 1:I2S */ 143 #define ASYS_I2S_CON_I2S_MODE (0x1 << 3) 144 #define ASYS_I2S_CON_WIDE_MODE (0x1 << 1) 145 #define ASYS_I2S_CON_WIDE_MODE_SET(x) ((x) << 1) 146 #define ASYS_I2S_IN_PHASE_FIX (0x1 << 31) 147 148 #endif 149