1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 #include <drm/drmP.h> 27 #include <drm/drm_edid.h> 28 #include <drm/drm_crtc_helper.h> 29 #include <drm/drm_fb_helper.h> 30 #include <drm/amdgpu_drm.h> 31 #include "amdgpu.h" 32 #include "atom.h" 33 #include "atombios_encoders.h" 34 #include "atombios_dp.h" 35 #include "amdgpu_connectors.h" 36 #include "amdgpu_i2c.h" 37 38 #include <linux/pm_runtime.h> 39 40 void amdgpu_connector_hotplug(struct drm_connector *connector) 41 { 42 struct drm_device *dev = connector->dev; 43 struct amdgpu_device *adev = dev->dev_private; 44 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 45 46 /* bail if the connector does not have hpd pin, e.g., 47 * VGA, TV, etc. 48 */ 49 if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) 50 return; 51 52 amdgpu_display_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); 53 54 /* if the connector is already off, don't turn it back on */ 55 if (connector->dpms != DRM_MODE_DPMS_ON) 56 return; 57 58 /* just deal with DP (not eDP) here. */ 59 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { 60 struct amdgpu_connector_atom_dig *dig_connector = 61 amdgpu_connector->con_priv; 62 63 /* if existing sink type was not DP no need to retrain */ 64 if (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) 65 return; 66 67 /* first get sink type as it may be reset after (un)plug */ 68 dig_connector->dp_sink_type = amdgpu_atombios_dp_get_sinktype(amdgpu_connector); 69 /* don't do anything if sink is not display port, i.e., 70 * passive dp->(dvi|hdmi) adaptor 71 */ 72 if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) { 73 int saved_dpms = connector->dpms; 74 /* Only turn off the display if it's physically disconnected */ 75 if (!amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { 76 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); 77 } else if (amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) { 78 /* Don't try to start link training before we 79 * have the dpcd */ 80 if (amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 81 return; 82 83 /* set it to OFF so that drm_helper_connector_dpms() 84 * won't return immediately since the current state 85 * is ON at this point. 86 */ 87 connector->dpms = DRM_MODE_DPMS_OFF; 88 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); 89 } 90 connector->dpms = saved_dpms; 91 } 92 } 93 } 94 95 static void amdgpu_connector_property_change_mode(struct drm_encoder *encoder) 96 { 97 struct drm_crtc *crtc = encoder->crtc; 98 99 if (crtc && crtc->enabled) { 100 drm_crtc_helper_set_mode(crtc, &crtc->mode, 101 crtc->x, crtc->y, crtc->primary->fb); 102 } 103 } 104 105 int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector) 106 { 107 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 108 struct amdgpu_connector_atom_dig *dig_connector; 109 int bpc = 8; 110 unsigned mode_clock, max_tmds_clock; 111 112 switch (connector->connector_type) { 113 case DRM_MODE_CONNECTOR_DVII: 114 case DRM_MODE_CONNECTOR_HDMIB: 115 if (amdgpu_connector->use_digital) { 116 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 117 if (connector->display_info.bpc) 118 bpc = connector->display_info.bpc; 119 } 120 } 121 break; 122 case DRM_MODE_CONNECTOR_DVID: 123 case DRM_MODE_CONNECTOR_HDMIA: 124 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 125 if (connector->display_info.bpc) 126 bpc = connector->display_info.bpc; 127 } 128 break; 129 case DRM_MODE_CONNECTOR_DisplayPort: 130 dig_connector = amdgpu_connector->con_priv; 131 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 132 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) || 133 drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 134 if (connector->display_info.bpc) 135 bpc = connector->display_info.bpc; 136 } 137 break; 138 case DRM_MODE_CONNECTOR_eDP: 139 case DRM_MODE_CONNECTOR_LVDS: 140 if (connector->display_info.bpc) 141 bpc = connector->display_info.bpc; 142 else { 143 const struct drm_connector_helper_funcs *connector_funcs = 144 connector->helper_private; 145 struct drm_encoder *encoder = connector_funcs->best_encoder(connector); 146 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 147 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 148 149 if (dig->lcd_misc & ATOM_PANEL_MISC_V13_6BIT_PER_COLOR) 150 bpc = 6; 151 else if (dig->lcd_misc & ATOM_PANEL_MISC_V13_8BIT_PER_COLOR) 152 bpc = 8; 153 } 154 break; 155 } 156 157 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 158 /* 159 * Pre DCE-8 hw can't handle > 12 bpc, and more than 12 bpc doesn't make 160 * much sense without support for > 12 bpc framebuffers. RGB 4:4:4 at 161 * 12 bpc is always supported on hdmi deep color sinks, as this is 162 * required by the HDMI-1.3 spec. Clamp to a safe 12 bpc maximum. 163 */ 164 if (bpc > 12) { 165 DRM_DEBUG("%s: HDMI deep color %d bpc unsupported. Using 12 bpc.\n", 166 connector->name, bpc); 167 bpc = 12; 168 } 169 170 /* Any defined maximum tmds clock limit we must not exceed? */ 171 if (connector->display_info.max_tmds_clock > 0) { 172 /* mode_clock is clock in kHz for mode to be modeset on this connector */ 173 mode_clock = amdgpu_connector->pixelclock_for_modeset; 174 175 /* Maximum allowable input clock in kHz */ 176 max_tmds_clock = connector->display_info.max_tmds_clock; 177 178 DRM_DEBUG("%s: hdmi mode dotclock %d kHz, max tmds input clock %d kHz.\n", 179 connector->name, mode_clock, max_tmds_clock); 180 181 /* Check if bpc is within clock limit. Try to degrade gracefully otherwise */ 182 if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) { 183 if ((connector->display_info.edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_30) && 184 (mode_clock * 5/4 <= max_tmds_clock)) 185 bpc = 10; 186 else 187 bpc = 8; 188 189 DRM_DEBUG("%s: HDMI deep color 12 bpc exceeds max tmds clock. Using %d bpc.\n", 190 connector->name, bpc); 191 } 192 193 if ((bpc == 10) && (mode_clock * 5/4 > max_tmds_clock)) { 194 bpc = 8; 195 DRM_DEBUG("%s: HDMI deep color 10 bpc exceeds max tmds clock. Using %d bpc.\n", 196 connector->name, bpc); 197 } 198 } else if (bpc > 8) { 199 /* max_tmds_clock missing, but hdmi spec mandates it for deep color. */ 200 DRM_DEBUG("%s: Required max tmds clock for HDMI deep color missing. Using 8 bpc.\n", 201 connector->name); 202 bpc = 8; 203 } 204 } 205 206 if ((amdgpu_deep_color == 0) && (bpc > 8)) { 207 DRM_DEBUG("%s: Deep color disabled. Set amdgpu module param deep_color=1 to enable.\n", 208 connector->name); 209 bpc = 8; 210 } 211 212 DRM_DEBUG("%s: Display bpc=%d, returned bpc=%d\n", 213 connector->name, connector->display_info.bpc, bpc); 214 215 return bpc; 216 } 217 218 static void 219 amdgpu_connector_update_scratch_regs(struct drm_connector *connector, 220 enum drm_connector_status status) 221 { 222 struct drm_encoder *best_encoder = NULL; 223 struct drm_encoder *encoder = NULL; 224 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 225 bool connected; 226 int i; 227 228 best_encoder = connector_funcs->best_encoder(connector); 229 230 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { 231 if (connector->encoder_ids[i] == 0) 232 break; 233 234 encoder = drm_encoder_find(connector->dev, NULL, 235 connector->encoder_ids[i]); 236 if (!encoder) 237 continue; 238 239 if ((encoder == best_encoder) && (status == connector_status_connected)) 240 connected = true; 241 else 242 connected = false; 243 244 amdgpu_atombios_encoder_set_bios_scratch_regs(connector, encoder, connected); 245 246 } 247 } 248 249 static struct drm_encoder * 250 amdgpu_connector_find_encoder(struct drm_connector *connector, 251 int encoder_type) 252 { 253 struct drm_encoder *encoder; 254 int i; 255 256 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { 257 if (connector->encoder_ids[i] == 0) 258 break; 259 encoder = drm_encoder_find(connector->dev, NULL, 260 connector->encoder_ids[i]); 261 if (!encoder) 262 continue; 263 264 if (encoder->encoder_type == encoder_type) 265 return encoder; 266 } 267 return NULL; 268 } 269 270 struct edid *amdgpu_connector_edid(struct drm_connector *connector) 271 { 272 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 273 struct drm_property_blob *edid_blob = connector->edid_blob_ptr; 274 275 if (amdgpu_connector->edid) { 276 return amdgpu_connector->edid; 277 } else if (edid_blob) { 278 struct edid *edid = kmemdup(edid_blob->data, edid_blob->length, GFP_KERNEL); 279 if (edid) 280 amdgpu_connector->edid = edid; 281 } 282 return amdgpu_connector->edid; 283 } 284 285 static struct edid * 286 amdgpu_connector_get_hardcoded_edid(struct amdgpu_device *adev) 287 { 288 struct edid *edid; 289 290 if (adev->mode_info.bios_hardcoded_edid) { 291 edid = kmalloc(adev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL); 292 if (edid) { 293 memcpy((unsigned char *)edid, 294 (unsigned char *)adev->mode_info.bios_hardcoded_edid, 295 adev->mode_info.bios_hardcoded_edid_size); 296 return edid; 297 } 298 } 299 return NULL; 300 } 301 302 static void amdgpu_connector_get_edid(struct drm_connector *connector) 303 { 304 struct drm_device *dev = connector->dev; 305 struct amdgpu_device *adev = dev->dev_private; 306 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 307 308 if (amdgpu_connector->edid) 309 return; 310 311 /* on hw with routers, select right port */ 312 if (amdgpu_connector->router.ddc_valid) 313 amdgpu_i2c_router_select_ddc_port(amdgpu_connector); 314 315 if ((amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 316 ENCODER_OBJECT_ID_NONE) && 317 amdgpu_connector->ddc_bus->has_aux) { 318 amdgpu_connector->edid = drm_get_edid(connector, 319 &amdgpu_connector->ddc_bus->aux.ddc); 320 } else if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) || 321 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { 322 struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv; 323 324 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT || 325 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && 326 amdgpu_connector->ddc_bus->has_aux) 327 amdgpu_connector->edid = drm_get_edid(connector, 328 &amdgpu_connector->ddc_bus->aux.ddc); 329 else if (amdgpu_connector->ddc_bus) 330 amdgpu_connector->edid = drm_get_edid(connector, 331 &amdgpu_connector->ddc_bus->adapter); 332 } else if (amdgpu_connector->ddc_bus) { 333 amdgpu_connector->edid = drm_get_edid(connector, 334 &amdgpu_connector->ddc_bus->adapter); 335 } 336 337 if (!amdgpu_connector->edid) { 338 /* some laptops provide a hardcoded edid in rom for LCDs */ 339 if (((connector->connector_type == DRM_MODE_CONNECTOR_LVDS) || 340 (connector->connector_type == DRM_MODE_CONNECTOR_eDP))) 341 amdgpu_connector->edid = amdgpu_connector_get_hardcoded_edid(adev); 342 } 343 } 344 345 static void amdgpu_connector_free_edid(struct drm_connector *connector) 346 { 347 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 348 349 kfree(amdgpu_connector->edid); 350 amdgpu_connector->edid = NULL; 351 } 352 353 static int amdgpu_connector_ddc_get_modes(struct drm_connector *connector) 354 { 355 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 356 int ret; 357 358 if (amdgpu_connector->edid) { 359 drm_mode_connector_update_edid_property(connector, amdgpu_connector->edid); 360 ret = drm_add_edid_modes(connector, amdgpu_connector->edid); 361 return ret; 362 } 363 drm_mode_connector_update_edid_property(connector, NULL); 364 return 0; 365 } 366 367 static struct drm_encoder * 368 amdgpu_connector_best_single_encoder(struct drm_connector *connector) 369 { 370 int enc_id = connector->encoder_ids[0]; 371 372 /* pick the encoder ids */ 373 if (enc_id) 374 return drm_encoder_find(connector->dev, NULL, enc_id); 375 return NULL; 376 } 377 378 static void amdgpu_get_native_mode(struct drm_connector *connector) 379 { 380 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 381 struct amdgpu_encoder *amdgpu_encoder; 382 383 if (encoder == NULL) 384 return; 385 386 amdgpu_encoder = to_amdgpu_encoder(encoder); 387 388 if (!list_empty(&connector->probed_modes)) { 389 struct drm_display_mode *preferred_mode = 390 list_first_entry(&connector->probed_modes, 391 struct drm_display_mode, head); 392 393 amdgpu_encoder->native_mode = *preferred_mode; 394 } else { 395 amdgpu_encoder->native_mode.clock = 0; 396 } 397 } 398 399 static struct drm_display_mode * 400 amdgpu_connector_lcd_native_mode(struct drm_encoder *encoder) 401 { 402 struct drm_device *dev = encoder->dev; 403 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 404 struct drm_display_mode *mode = NULL; 405 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 406 407 if (native_mode->hdisplay != 0 && 408 native_mode->vdisplay != 0 && 409 native_mode->clock != 0) { 410 mode = drm_mode_duplicate(dev, native_mode); 411 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; 412 drm_mode_set_name(mode); 413 414 DRM_DEBUG_KMS("Adding native panel mode %s\n", mode->name); 415 } else if (native_mode->hdisplay != 0 && 416 native_mode->vdisplay != 0) { 417 /* mac laptops without an edid */ 418 /* Note that this is not necessarily the exact panel mode, 419 * but an approximation based on the cvt formula. For these 420 * systems we should ideally read the mode info out of the 421 * registers or add a mode table, but this works and is much 422 * simpler. 423 */ 424 mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false); 425 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; 426 DRM_DEBUG_KMS("Adding cvt approximation of native panel mode %s\n", mode->name); 427 } 428 return mode; 429 } 430 431 static void amdgpu_connector_add_common_modes(struct drm_encoder *encoder, 432 struct drm_connector *connector) 433 { 434 struct drm_device *dev = encoder->dev; 435 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 436 struct drm_display_mode *mode = NULL; 437 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 438 int i; 439 static const struct mode_size { 440 int w; 441 int h; 442 } common_modes[17] = { 443 { 640, 480}, 444 { 720, 480}, 445 { 800, 600}, 446 { 848, 480}, 447 {1024, 768}, 448 {1152, 768}, 449 {1280, 720}, 450 {1280, 800}, 451 {1280, 854}, 452 {1280, 960}, 453 {1280, 1024}, 454 {1440, 900}, 455 {1400, 1050}, 456 {1680, 1050}, 457 {1600, 1200}, 458 {1920, 1080}, 459 {1920, 1200} 460 }; 461 462 for (i = 0; i < 17; i++) { 463 if (amdgpu_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) { 464 if (common_modes[i].w > 1024 || 465 common_modes[i].h > 768) 466 continue; 467 } 468 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 469 if (common_modes[i].w > native_mode->hdisplay || 470 common_modes[i].h > native_mode->vdisplay || 471 (common_modes[i].w == native_mode->hdisplay && 472 common_modes[i].h == native_mode->vdisplay)) 473 continue; 474 } 475 if (common_modes[i].w < 320 || common_modes[i].h < 200) 476 continue; 477 478 mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false); 479 drm_mode_probed_add(connector, mode); 480 } 481 } 482 483 static int amdgpu_connector_set_property(struct drm_connector *connector, 484 struct drm_property *property, 485 uint64_t val) 486 { 487 struct drm_device *dev = connector->dev; 488 struct amdgpu_device *adev = dev->dev_private; 489 struct drm_encoder *encoder; 490 struct amdgpu_encoder *amdgpu_encoder; 491 492 if (property == adev->mode_info.coherent_mode_property) { 493 struct amdgpu_encoder_atom_dig *dig; 494 bool new_coherent_mode; 495 496 /* need to find digital encoder on connector */ 497 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 498 if (!encoder) 499 return 0; 500 501 amdgpu_encoder = to_amdgpu_encoder(encoder); 502 503 if (!amdgpu_encoder->enc_priv) 504 return 0; 505 506 dig = amdgpu_encoder->enc_priv; 507 new_coherent_mode = val ? true : false; 508 if (dig->coherent_mode != new_coherent_mode) { 509 dig->coherent_mode = new_coherent_mode; 510 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 511 } 512 } 513 514 if (property == adev->mode_info.audio_property) { 515 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 516 /* need to find digital encoder on connector */ 517 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 518 if (!encoder) 519 return 0; 520 521 amdgpu_encoder = to_amdgpu_encoder(encoder); 522 523 if (amdgpu_connector->audio != val) { 524 amdgpu_connector->audio = val; 525 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 526 } 527 } 528 529 if (property == adev->mode_info.dither_property) { 530 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 531 /* need to find digital encoder on connector */ 532 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 533 if (!encoder) 534 return 0; 535 536 amdgpu_encoder = to_amdgpu_encoder(encoder); 537 538 if (amdgpu_connector->dither != val) { 539 amdgpu_connector->dither = val; 540 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 541 } 542 } 543 544 if (property == adev->mode_info.underscan_property) { 545 /* need to find digital encoder on connector */ 546 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 547 if (!encoder) 548 return 0; 549 550 amdgpu_encoder = to_amdgpu_encoder(encoder); 551 552 if (amdgpu_encoder->underscan_type != val) { 553 amdgpu_encoder->underscan_type = val; 554 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 555 } 556 } 557 558 if (property == adev->mode_info.underscan_hborder_property) { 559 /* need to find digital encoder on connector */ 560 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 561 if (!encoder) 562 return 0; 563 564 amdgpu_encoder = to_amdgpu_encoder(encoder); 565 566 if (amdgpu_encoder->underscan_hborder != val) { 567 amdgpu_encoder->underscan_hborder = val; 568 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 569 } 570 } 571 572 if (property == adev->mode_info.underscan_vborder_property) { 573 /* need to find digital encoder on connector */ 574 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 575 if (!encoder) 576 return 0; 577 578 amdgpu_encoder = to_amdgpu_encoder(encoder); 579 580 if (amdgpu_encoder->underscan_vborder != val) { 581 amdgpu_encoder->underscan_vborder = val; 582 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 583 } 584 } 585 586 if (property == adev->mode_info.load_detect_property) { 587 struct amdgpu_connector *amdgpu_connector = 588 to_amdgpu_connector(connector); 589 590 if (val == 0) 591 amdgpu_connector->dac_load_detect = false; 592 else 593 amdgpu_connector->dac_load_detect = true; 594 } 595 596 if (property == dev->mode_config.scaling_mode_property) { 597 enum amdgpu_rmx_type rmx_type; 598 599 if (connector->encoder) { 600 amdgpu_encoder = to_amdgpu_encoder(connector->encoder); 601 } else { 602 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 603 amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector)); 604 } 605 606 switch (val) { 607 default: 608 case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break; 609 case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break; 610 case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break; 611 case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break; 612 } 613 if (amdgpu_encoder->rmx_type == rmx_type) 614 return 0; 615 616 if ((rmx_type != DRM_MODE_SCALE_NONE) && 617 (amdgpu_encoder->native_mode.clock == 0)) 618 return 0; 619 620 amdgpu_encoder->rmx_type = rmx_type; 621 622 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 623 } 624 625 return 0; 626 } 627 628 static void 629 amdgpu_connector_fixup_lcd_native_mode(struct drm_encoder *encoder, 630 struct drm_connector *connector) 631 { 632 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 633 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 634 struct drm_display_mode *t, *mode; 635 636 /* If the EDID preferred mode doesn't match the native mode, use it */ 637 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) { 638 if (mode->type & DRM_MODE_TYPE_PREFERRED) { 639 if (mode->hdisplay != native_mode->hdisplay || 640 mode->vdisplay != native_mode->vdisplay) 641 memcpy(native_mode, mode, sizeof(*mode)); 642 } 643 } 644 645 /* Try to get native mode details from EDID if necessary */ 646 if (!native_mode->clock) { 647 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) { 648 if (mode->hdisplay == native_mode->hdisplay && 649 mode->vdisplay == native_mode->vdisplay) { 650 *native_mode = *mode; 651 drm_mode_set_crtcinfo(native_mode, CRTC_INTERLACE_HALVE_V); 652 DRM_DEBUG_KMS("Determined LVDS native mode details from EDID\n"); 653 break; 654 } 655 } 656 } 657 658 if (!native_mode->clock) { 659 DRM_DEBUG_KMS("No LVDS native mode details, disabling RMX\n"); 660 amdgpu_encoder->rmx_type = RMX_OFF; 661 } 662 } 663 664 static int amdgpu_connector_lvds_get_modes(struct drm_connector *connector) 665 { 666 struct drm_encoder *encoder; 667 int ret = 0; 668 struct drm_display_mode *mode; 669 670 amdgpu_connector_get_edid(connector); 671 ret = amdgpu_connector_ddc_get_modes(connector); 672 if (ret > 0) { 673 encoder = amdgpu_connector_best_single_encoder(connector); 674 if (encoder) { 675 amdgpu_connector_fixup_lcd_native_mode(encoder, connector); 676 /* add scaled modes */ 677 amdgpu_connector_add_common_modes(encoder, connector); 678 } 679 return ret; 680 } 681 682 encoder = amdgpu_connector_best_single_encoder(connector); 683 if (!encoder) 684 return 0; 685 686 /* we have no EDID modes */ 687 mode = amdgpu_connector_lcd_native_mode(encoder); 688 if (mode) { 689 ret = 1; 690 drm_mode_probed_add(connector, mode); 691 /* add the width/height from vbios tables if available */ 692 connector->display_info.width_mm = mode->width_mm; 693 connector->display_info.height_mm = mode->height_mm; 694 /* add scaled modes */ 695 amdgpu_connector_add_common_modes(encoder, connector); 696 } 697 698 return ret; 699 } 700 701 static int amdgpu_connector_lvds_mode_valid(struct drm_connector *connector, 702 struct drm_display_mode *mode) 703 { 704 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 705 706 if ((mode->hdisplay < 320) || (mode->vdisplay < 240)) 707 return MODE_PANEL; 708 709 if (encoder) { 710 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 711 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 712 713 /* AVIVO hardware supports downscaling modes larger than the panel 714 * to the panel size, but I'm not sure this is desirable. 715 */ 716 if ((mode->hdisplay > native_mode->hdisplay) || 717 (mode->vdisplay > native_mode->vdisplay)) 718 return MODE_PANEL; 719 720 /* if scaling is disabled, block non-native modes */ 721 if (amdgpu_encoder->rmx_type == RMX_OFF) { 722 if ((mode->hdisplay != native_mode->hdisplay) || 723 (mode->vdisplay != native_mode->vdisplay)) 724 return MODE_PANEL; 725 } 726 } 727 728 return MODE_OK; 729 } 730 731 static enum drm_connector_status 732 amdgpu_connector_lvds_detect(struct drm_connector *connector, bool force) 733 { 734 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 735 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 736 enum drm_connector_status ret = connector_status_disconnected; 737 int r; 738 739 if (!drm_kms_helper_is_poll_worker()) { 740 r = pm_runtime_get_sync(connector->dev->dev); 741 if (r < 0) 742 return connector_status_disconnected; 743 } 744 745 if (encoder) { 746 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 747 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 748 749 /* check if panel is valid */ 750 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240) 751 ret = connector_status_connected; 752 753 } 754 755 /* check for edid as well */ 756 amdgpu_connector_get_edid(connector); 757 if (amdgpu_connector->edid) 758 ret = connector_status_connected; 759 /* check acpi lid status ??? */ 760 761 amdgpu_connector_update_scratch_regs(connector, ret); 762 763 if (!drm_kms_helper_is_poll_worker()) { 764 pm_runtime_mark_last_busy(connector->dev->dev); 765 pm_runtime_put_autosuspend(connector->dev->dev); 766 } 767 768 return ret; 769 } 770 771 static void amdgpu_connector_unregister(struct drm_connector *connector) 772 { 773 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 774 775 if (amdgpu_connector->ddc_bus && amdgpu_connector->ddc_bus->has_aux) { 776 drm_dp_aux_unregister(&amdgpu_connector->ddc_bus->aux); 777 amdgpu_connector->ddc_bus->has_aux = false; 778 } 779 } 780 781 static void amdgpu_connector_destroy(struct drm_connector *connector) 782 { 783 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 784 785 amdgpu_connector_free_edid(connector); 786 kfree(amdgpu_connector->con_priv); 787 drm_connector_unregister(connector); 788 drm_connector_cleanup(connector); 789 kfree(connector); 790 } 791 792 static int amdgpu_connector_set_lcd_property(struct drm_connector *connector, 793 struct drm_property *property, 794 uint64_t value) 795 { 796 struct drm_device *dev = connector->dev; 797 struct amdgpu_encoder *amdgpu_encoder; 798 enum amdgpu_rmx_type rmx_type; 799 800 DRM_DEBUG_KMS("\n"); 801 if (property != dev->mode_config.scaling_mode_property) 802 return 0; 803 804 if (connector->encoder) 805 amdgpu_encoder = to_amdgpu_encoder(connector->encoder); 806 else { 807 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 808 amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector)); 809 } 810 811 switch (value) { 812 case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break; 813 case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break; 814 case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break; 815 default: 816 case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break; 817 } 818 if (amdgpu_encoder->rmx_type == rmx_type) 819 return 0; 820 821 amdgpu_encoder->rmx_type = rmx_type; 822 823 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 824 return 0; 825 } 826 827 828 static const struct drm_connector_helper_funcs amdgpu_connector_lvds_helper_funcs = { 829 .get_modes = amdgpu_connector_lvds_get_modes, 830 .mode_valid = amdgpu_connector_lvds_mode_valid, 831 .best_encoder = amdgpu_connector_best_single_encoder, 832 }; 833 834 static const struct drm_connector_funcs amdgpu_connector_lvds_funcs = { 835 .dpms = drm_helper_connector_dpms, 836 .detect = amdgpu_connector_lvds_detect, 837 .fill_modes = drm_helper_probe_single_connector_modes, 838 .early_unregister = amdgpu_connector_unregister, 839 .destroy = amdgpu_connector_destroy, 840 .set_property = amdgpu_connector_set_lcd_property, 841 }; 842 843 static int amdgpu_connector_vga_get_modes(struct drm_connector *connector) 844 { 845 int ret; 846 847 amdgpu_connector_get_edid(connector); 848 ret = amdgpu_connector_ddc_get_modes(connector); 849 850 return ret; 851 } 852 853 static int amdgpu_connector_vga_mode_valid(struct drm_connector *connector, 854 struct drm_display_mode *mode) 855 { 856 struct drm_device *dev = connector->dev; 857 struct amdgpu_device *adev = dev->dev_private; 858 859 /* XXX check mode bandwidth */ 860 861 if ((mode->clock / 10) > adev->clock.max_pixel_clock) 862 return MODE_CLOCK_HIGH; 863 864 return MODE_OK; 865 } 866 867 static enum drm_connector_status 868 amdgpu_connector_vga_detect(struct drm_connector *connector, bool force) 869 { 870 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 871 struct drm_encoder *encoder; 872 const struct drm_encoder_helper_funcs *encoder_funcs; 873 bool dret = false; 874 enum drm_connector_status ret = connector_status_disconnected; 875 int r; 876 877 if (!drm_kms_helper_is_poll_worker()) { 878 r = pm_runtime_get_sync(connector->dev->dev); 879 if (r < 0) 880 return connector_status_disconnected; 881 } 882 883 encoder = amdgpu_connector_best_single_encoder(connector); 884 if (!encoder) 885 ret = connector_status_disconnected; 886 887 if (amdgpu_connector->ddc_bus) 888 dret = amdgpu_ddc_probe(amdgpu_connector, false); 889 if (dret) { 890 amdgpu_connector->detected_by_load = false; 891 amdgpu_connector_free_edid(connector); 892 amdgpu_connector_get_edid(connector); 893 894 if (!amdgpu_connector->edid) { 895 DRM_ERROR("%s: probed a monitor but no|invalid EDID\n", 896 connector->name); 897 ret = connector_status_connected; 898 } else { 899 amdgpu_connector->use_digital = 900 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL); 901 902 /* some oems have boards with separate digital and analog connectors 903 * with a shared ddc line (often vga + hdmi) 904 */ 905 if (amdgpu_connector->use_digital && amdgpu_connector->shared_ddc) { 906 amdgpu_connector_free_edid(connector); 907 ret = connector_status_disconnected; 908 } else { 909 ret = connector_status_connected; 910 } 911 } 912 } else { 913 914 /* if we aren't forcing don't do destructive polling */ 915 if (!force) { 916 /* only return the previous status if we last 917 * detected a monitor via load. 918 */ 919 if (amdgpu_connector->detected_by_load) 920 ret = connector->status; 921 goto out; 922 } 923 924 if (amdgpu_connector->dac_load_detect && encoder) { 925 encoder_funcs = encoder->helper_private; 926 ret = encoder_funcs->detect(encoder, connector); 927 if (ret != connector_status_disconnected) 928 amdgpu_connector->detected_by_load = true; 929 } 930 } 931 932 amdgpu_connector_update_scratch_regs(connector, ret); 933 934 out: 935 if (!drm_kms_helper_is_poll_worker()) { 936 pm_runtime_mark_last_busy(connector->dev->dev); 937 pm_runtime_put_autosuspend(connector->dev->dev); 938 } 939 940 return ret; 941 } 942 943 static const struct drm_connector_helper_funcs amdgpu_connector_vga_helper_funcs = { 944 .get_modes = amdgpu_connector_vga_get_modes, 945 .mode_valid = amdgpu_connector_vga_mode_valid, 946 .best_encoder = amdgpu_connector_best_single_encoder, 947 }; 948 949 static const struct drm_connector_funcs amdgpu_connector_vga_funcs = { 950 .dpms = drm_helper_connector_dpms, 951 .detect = amdgpu_connector_vga_detect, 952 .fill_modes = drm_helper_probe_single_connector_modes, 953 .early_unregister = amdgpu_connector_unregister, 954 .destroy = amdgpu_connector_destroy, 955 .set_property = amdgpu_connector_set_property, 956 }; 957 958 static bool 959 amdgpu_connector_check_hpd_status_unchanged(struct drm_connector *connector) 960 { 961 struct drm_device *dev = connector->dev; 962 struct amdgpu_device *adev = dev->dev_private; 963 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 964 enum drm_connector_status status; 965 966 if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) { 967 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) 968 status = connector_status_connected; 969 else 970 status = connector_status_disconnected; 971 if (connector->status == status) 972 return true; 973 } 974 975 return false; 976 } 977 978 /* 979 * DVI is complicated 980 * Do a DDC probe, if DDC probe passes, get the full EDID so 981 * we can do analog/digital monitor detection at this point. 982 * If the monitor is an analog monitor or we got no DDC, 983 * we need to find the DAC encoder object for this connector. 984 * If we got no DDC, we do load detection on the DAC encoder object. 985 * If we got analog DDC or load detection passes on the DAC encoder 986 * we have to check if this analog encoder is shared with anyone else (TV) 987 * if its shared we have to set the other connector to disconnected. 988 */ 989 static enum drm_connector_status 990 amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force) 991 { 992 struct drm_device *dev = connector->dev; 993 struct amdgpu_device *adev = dev->dev_private; 994 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 995 struct drm_encoder *encoder = NULL; 996 const struct drm_encoder_helper_funcs *encoder_funcs; 997 int i, r; 998 enum drm_connector_status ret = connector_status_disconnected; 999 bool dret = false, broken_edid = false; 1000 1001 if (!drm_kms_helper_is_poll_worker()) { 1002 r = pm_runtime_get_sync(connector->dev->dev); 1003 if (r < 0) 1004 return connector_status_disconnected; 1005 } 1006 1007 if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) { 1008 ret = connector->status; 1009 goto exit; 1010 } 1011 1012 if (amdgpu_connector->ddc_bus) 1013 dret = amdgpu_ddc_probe(amdgpu_connector, false); 1014 if (dret) { 1015 amdgpu_connector->detected_by_load = false; 1016 amdgpu_connector_free_edid(connector); 1017 amdgpu_connector_get_edid(connector); 1018 1019 if (!amdgpu_connector->edid) { 1020 DRM_ERROR("%s: probed a monitor but no|invalid EDID\n", 1021 connector->name); 1022 ret = connector_status_connected; 1023 broken_edid = true; /* defer use_digital to later */ 1024 } else { 1025 amdgpu_connector->use_digital = 1026 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL); 1027 1028 /* some oems have boards with separate digital and analog connectors 1029 * with a shared ddc line (often vga + hdmi) 1030 */ 1031 if ((!amdgpu_connector->use_digital) && amdgpu_connector->shared_ddc) { 1032 amdgpu_connector_free_edid(connector); 1033 ret = connector_status_disconnected; 1034 } else { 1035 ret = connector_status_connected; 1036 } 1037 1038 /* This gets complicated. We have boards with VGA + HDMI with a 1039 * shared DDC line and we have boards with DVI-D + HDMI with a shared 1040 * DDC line. The latter is more complex because with DVI<->HDMI adapters 1041 * you don't really know what's connected to which port as both are digital. 1042 */ 1043 if (amdgpu_connector->shared_ddc && (ret == connector_status_connected)) { 1044 struct drm_connector *list_connector; 1045 struct amdgpu_connector *list_amdgpu_connector; 1046 list_for_each_entry(list_connector, &dev->mode_config.connector_list, head) { 1047 if (connector == list_connector) 1048 continue; 1049 list_amdgpu_connector = to_amdgpu_connector(list_connector); 1050 if (list_amdgpu_connector->shared_ddc && 1051 (list_amdgpu_connector->ddc_bus->rec.i2c_id == 1052 amdgpu_connector->ddc_bus->rec.i2c_id)) { 1053 /* cases where both connectors are digital */ 1054 if (list_connector->connector_type != DRM_MODE_CONNECTOR_VGA) { 1055 /* hpd is our only option in this case */ 1056 if (!amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { 1057 amdgpu_connector_free_edid(connector); 1058 ret = connector_status_disconnected; 1059 } 1060 } 1061 } 1062 } 1063 } 1064 } 1065 } 1066 1067 if ((ret == connector_status_connected) && (amdgpu_connector->use_digital == true)) 1068 goto out; 1069 1070 /* DVI-D and HDMI-A are digital only */ 1071 if ((connector->connector_type == DRM_MODE_CONNECTOR_DVID) || 1072 (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA)) 1073 goto out; 1074 1075 /* if we aren't forcing don't do destructive polling */ 1076 if (!force) { 1077 /* only return the previous status if we last 1078 * detected a monitor via load. 1079 */ 1080 if (amdgpu_connector->detected_by_load) 1081 ret = connector->status; 1082 goto out; 1083 } 1084 1085 /* find analog encoder */ 1086 if (amdgpu_connector->dac_load_detect) { 1087 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { 1088 if (connector->encoder_ids[i] == 0) 1089 break; 1090 1091 encoder = drm_encoder_find(connector->dev, NULL, connector->encoder_ids[i]); 1092 if (!encoder) 1093 continue; 1094 1095 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC && 1096 encoder->encoder_type != DRM_MODE_ENCODER_TVDAC) 1097 continue; 1098 1099 encoder_funcs = encoder->helper_private; 1100 if (encoder_funcs->detect) { 1101 if (!broken_edid) { 1102 if (ret != connector_status_connected) { 1103 /* deal with analog monitors without DDC */ 1104 ret = encoder_funcs->detect(encoder, connector); 1105 if (ret == connector_status_connected) { 1106 amdgpu_connector->use_digital = false; 1107 } 1108 if (ret != connector_status_disconnected) 1109 amdgpu_connector->detected_by_load = true; 1110 } 1111 } else { 1112 enum drm_connector_status lret; 1113 /* assume digital unless load detected otherwise */ 1114 amdgpu_connector->use_digital = true; 1115 lret = encoder_funcs->detect(encoder, connector); 1116 DRM_DEBUG_KMS("load_detect %x returned: %x\n",encoder->encoder_type,lret); 1117 if (lret == connector_status_connected) 1118 amdgpu_connector->use_digital = false; 1119 } 1120 break; 1121 } 1122 } 1123 } 1124 1125 out: 1126 /* updated in get modes as well since we need to know if it's analog or digital */ 1127 amdgpu_connector_update_scratch_regs(connector, ret); 1128 1129 exit: 1130 if (!drm_kms_helper_is_poll_worker()) { 1131 pm_runtime_mark_last_busy(connector->dev->dev); 1132 pm_runtime_put_autosuspend(connector->dev->dev); 1133 } 1134 1135 return ret; 1136 } 1137 1138 /* okay need to be smart in here about which encoder to pick */ 1139 static struct drm_encoder * 1140 amdgpu_connector_dvi_encoder(struct drm_connector *connector) 1141 { 1142 int enc_id = connector->encoder_ids[0]; 1143 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1144 struct drm_encoder *encoder; 1145 int i; 1146 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { 1147 if (connector->encoder_ids[i] == 0) 1148 break; 1149 1150 encoder = drm_encoder_find(connector->dev, NULL, connector->encoder_ids[i]); 1151 if (!encoder) 1152 continue; 1153 1154 if (amdgpu_connector->use_digital == true) { 1155 if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS) 1156 return encoder; 1157 } else { 1158 if (encoder->encoder_type == DRM_MODE_ENCODER_DAC || 1159 encoder->encoder_type == DRM_MODE_ENCODER_TVDAC) 1160 return encoder; 1161 } 1162 } 1163 1164 /* see if we have a default encoder TODO */ 1165 1166 /* then check use digitial */ 1167 /* pick the first one */ 1168 if (enc_id) 1169 return drm_encoder_find(connector->dev, NULL, enc_id); 1170 return NULL; 1171 } 1172 1173 static void amdgpu_connector_dvi_force(struct drm_connector *connector) 1174 { 1175 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1176 if (connector->force == DRM_FORCE_ON) 1177 amdgpu_connector->use_digital = false; 1178 if (connector->force == DRM_FORCE_ON_DIGITAL) 1179 amdgpu_connector->use_digital = true; 1180 } 1181 1182 static int amdgpu_connector_dvi_mode_valid(struct drm_connector *connector, 1183 struct drm_display_mode *mode) 1184 { 1185 struct drm_device *dev = connector->dev; 1186 struct amdgpu_device *adev = dev->dev_private; 1187 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1188 1189 /* XXX check mode bandwidth */ 1190 1191 if (amdgpu_connector->use_digital && (mode->clock > 165000)) { 1192 if ((amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I) || 1193 (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) || 1194 (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_B)) { 1195 return MODE_OK; 1196 } else if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 1197 /* HDMI 1.3+ supports max clock of 340 Mhz */ 1198 if (mode->clock > 340000) 1199 return MODE_CLOCK_HIGH; 1200 else 1201 return MODE_OK; 1202 } else { 1203 return MODE_CLOCK_HIGH; 1204 } 1205 } 1206 1207 /* check against the max pixel clock */ 1208 if ((mode->clock / 10) > adev->clock.max_pixel_clock) 1209 return MODE_CLOCK_HIGH; 1210 1211 return MODE_OK; 1212 } 1213 1214 static const struct drm_connector_helper_funcs amdgpu_connector_dvi_helper_funcs = { 1215 .get_modes = amdgpu_connector_vga_get_modes, 1216 .mode_valid = amdgpu_connector_dvi_mode_valid, 1217 .best_encoder = amdgpu_connector_dvi_encoder, 1218 }; 1219 1220 static const struct drm_connector_funcs amdgpu_connector_dvi_funcs = { 1221 .dpms = drm_helper_connector_dpms, 1222 .detect = amdgpu_connector_dvi_detect, 1223 .fill_modes = drm_helper_probe_single_connector_modes, 1224 .set_property = amdgpu_connector_set_property, 1225 .early_unregister = amdgpu_connector_unregister, 1226 .destroy = amdgpu_connector_destroy, 1227 .force = amdgpu_connector_dvi_force, 1228 }; 1229 1230 static int amdgpu_connector_dp_get_modes(struct drm_connector *connector) 1231 { 1232 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1233 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1234 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1235 int ret; 1236 1237 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1238 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1239 struct drm_display_mode *mode; 1240 1241 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1242 if (!amdgpu_dig_connector->edp_on) 1243 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1244 ATOM_TRANSMITTER_ACTION_POWER_ON); 1245 amdgpu_connector_get_edid(connector); 1246 ret = amdgpu_connector_ddc_get_modes(connector); 1247 if (!amdgpu_dig_connector->edp_on) 1248 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1249 ATOM_TRANSMITTER_ACTION_POWER_OFF); 1250 } else { 1251 /* need to setup ddc on the bridge */ 1252 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1253 ENCODER_OBJECT_ID_NONE) { 1254 if (encoder) 1255 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1256 } 1257 amdgpu_connector_get_edid(connector); 1258 ret = amdgpu_connector_ddc_get_modes(connector); 1259 } 1260 1261 if (ret > 0) { 1262 if (encoder) { 1263 amdgpu_connector_fixup_lcd_native_mode(encoder, connector); 1264 /* add scaled modes */ 1265 amdgpu_connector_add_common_modes(encoder, connector); 1266 } 1267 return ret; 1268 } 1269 1270 if (!encoder) 1271 return 0; 1272 1273 /* we have no EDID modes */ 1274 mode = amdgpu_connector_lcd_native_mode(encoder); 1275 if (mode) { 1276 ret = 1; 1277 drm_mode_probed_add(connector, mode); 1278 /* add the width/height from vbios tables if available */ 1279 connector->display_info.width_mm = mode->width_mm; 1280 connector->display_info.height_mm = mode->height_mm; 1281 /* add scaled modes */ 1282 amdgpu_connector_add_common_modes(encoder, connector); 1283 } 1284 } else { 1285 /* need to setup ddc on the bridge */ 1286 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1287 ENCODER_OBJECT_ID_NONE) { 1288 if (encoder) 1289 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1290 } 1291 amdgpu_connector_get_edid(connector); 1292 ret = amdgpu_connector_ddc_get_modes(connector); 1293 1294 amdgpu_get_native_mode(connector); 1295 } 1296 1297 return ret; 1298 } 1299 1300 u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector) 1301 { 1302 struct drm_encoder *encoder; 1303 struct amdgpu_encoder *amdgpu_encoder; 1304 int i; 1305 1306 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { 1307 if (connector->encoder_ids[i] == 0) 1308 break; 1309 1310 encoder = drm_encoder_find(connector->dev, NULL, 1311 connector->encoder_ids[i]); 1312 if (!encoder) 1313 continue; 1314 1315 amdgpu_encoder = to_amdgpu_encoder(encoder); 1316 1317 switch (amdgpu_encoder->encoder_id) { 1318 case ENCODER_OBJECT_ID_TRAVIS: 1319 case ENCODER_OBJECT_ID_NUTMEG: 1320 return amdgpu_encoder->encoder_id; 1321 default: 1322 break; 1323 } 1324 } 1325 1326 return ENCODER_OBJECT_ID_NONE; 1327 } 1328 1329 static bool amdgpu_connector_encoder_is_hbr2(struct drm_connector *connector) 1330 { 1331 struct drm_encoder *encoder; 1332 struct amdgpu_encoder *amdgpu_encoder; 1333 int i; 1334 bool found = false; 1335 1336 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { 1337 if (connector->encoder_ids[i] == 0) 1338 break; 1339 encoder = drm_encoder_find(connector->dev, NULL, 1340 connector->encoder_ids[i]); 1341 if (!encoder) 1342 continue; 1343 1344 amdgpu_encoder = to_amdgpu_encoder(encoder); 1345 if (amdgpu_encoder->caps & ATOM_ENCODER_CAP_RECORD_HBR2) 1346 found = true; 1347 } 1348 1349 return found; 1350 } 1351 1352 bool amdgpu_connector_is_dp12_capable(struct drm_connector *connector) 1353 { 1354 struct drm_device *dev = connector->dev; 1355 struct amdgpu_device *adev = dev->dev_private; 1356 1357 if ((adev->clock.default_dispclk >= 53900) && 1358 amdgpu_connector_encoder_is_hbr2(connector)) { 1359 return true; 1360 } 1361 1362 return false; 1363 } 1364 1365 static enum drm_connector_status 1366 amdgpu_connector_dp_detect(struct drm_connector *connector, bool force) 1367 { 1368 struct drm_device *dev = connector->dev; 1369 struct amdgpu_device *adev = dev->dev_private; 1370 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1371 enum drm_connector_status ret = connector_status_disconnected; 1372 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1373 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1374 int r; 1375 1376 if (!drm_kms_helper_is_poll_worker()) { 1377 r = pm_runtime_get_sync(connector->dev->dev); 1378 if (r < 0) 1379 return connector_status_disconnected; 1380 } 1381 1382 if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) { 1383 ret = connector->status; 1384 goto out; 1385 } 1386 1387 amdgpu_connector_free_edid(connector); 1388 1389 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1390 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1391 if (encoder) { 1392 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1393 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 1394 1395 /* check if panel is valid */ 1396 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240) 1397 ret = connector_status_connected; 1398 } 1399 /* eDP is always DP */ 1400 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT; 1401 if (!amdgpu_dig_connector->edp_on) 1402 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1403 ATOM_TRANSMITTER_ACTION_POWER_ON); 1404 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 1405 ret = connector_status_connected; 1406 if (!amdgpu_dig_connector->edp_on) 1407 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1408 ATOM_TRANSMITTER_ACTION_POWER_OFF); 1409 } else if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1410 ENCODER_OBJECT_ID_NONE) { 1411 /* DP bridges are always DP */ 1412 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT; 1413 /* get the DPCD from the bridge */ 1414 amdgpu_atombios_dp_get_dpcd(amdgpu_connector); 1415 1416 if (encoder) { 1417 /* setup ddc on the bridge */ 1418 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1419 /* bridge chips are always aux */ 1420 if (amdgpu_ddc_probe(amdgpu_connector, true)) /* try DDC */ 1421 ret = connector_status_connected; 1422 else if (amdgpu_connector->dac_load_detect) { /* try load detection */ 1423 const struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; 1424 ret = encoder_funcs->detect(encoder, connector); 1425 } 1426 } 1427 } else { 1428 amdgpu_dig_connector->dp_sink_type = 1429 amdgpu_atombios_dp_get_sinktype(amdgpu_connector); 1430 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { 1431 ret = connector_status_connected; 1432 if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) 1433 amdgpu_atombios_dp_get_dpcd(amdgpu_connector); 1434 } else { 1435 if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) { 1436 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 1437 ret = connector_status_connected; 1438 } else { 1439 /* try non-aux ddc (DP to DVI/HDMI/etc. adapter) */ 1440 if (amdgpu_ddc_probe(amdgpu_connector, false)) 1441 ret = connector_status_connected; 1442 } 1443 } 1444 } 1445 1446 amdgpu_connector_update_scratch_regs(connector, ret); 1447 out: 1448 if (!drm_kms_helper_is_poll_worker()) { 1449 pm_runtime_mark_last_busy(connector->dev->dev); 1450 pm_runtime_put_autosuspend(connector->dev->dev); 1451 } 1452 1453 return ret; 1454 } 1455 1456 static int amdgpu_connector_dp_mode_valid(struct drm_connector *connector, 1457 struct drm_display_mode *mode) 1458 { 1459 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1460 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1461 1462 /* XXX check mode bandwidth */ 1463 1464 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1465 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1466 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1467 1468 if ((mode->hdisplay < 320) || (mode->vdisplay < 240)) 1469 return MODE_PANEL; 1470 1471 if (encoder) { 1472 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1473 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 1474 1475 /* AVIVO hardware supports downscaling modes larger than the panel 1476 * to the panel size, but I'm not sure this is desirable. 1477 */ 1478 if ((mode->hdisplay > native_mode->hdisplay) || 1479 (mode->vdisplay > native_mode->vdisplay)) 1480 return MODE_PANEL; 1481 1482 /* if scaling is disabled, block non-native modes */ 1483 if (amdgpu_encoder->rmx_type == RMX_OFF) { 1484 if ((mode->hdisplay != native_mode->hdisplay) || 1485 (mode->vdisplay != native_mode->vdisplay)) 1486 return MODE_PANEL; 1487 } 1488 } 1489 return MODE_OK; 1490 } else { 1491 if ((amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 1492 (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { 1493 return amdgpu_atombios_dp_mode_valid_helper(connector, mode); 1494 } else { 1495 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 1496 /* HDMI 1.3+ supports max clock of 340 Mhz */ 1497 if (mode->clock > 340000) 1498 return MODE_CLOCK_HIGH; 1499 } else { 1500 if (mode->clock > 165000) 1501 return MODE_CLOCK_HIGH; 1502 } 1503 } 1504 } 1505 1506 return MODE_OK; 1507 } 1508 1509 static const struct drm_connector_helper_funcs amdgpu_connector_dp_helper_funcs = { 1510 .get_modes = amdgpu_connector_dp_get_modes, 1511 .mode_valid = amdgpu_connector_dp_mode_valid, 1512 .best_encoder = amdgpu_connector_dvi_encoder, 1513 }; 1514 1515 static const struct drm_connector_funcs amdgpu_connector_dp_funcs = { 1516 .dpms = drm_helper_connector_dpms, 1517 .detect = amdgpu_connector_dp_detect, 1518 .fill_modes = drm_helper_probe_single_connector_modes, 1519 .set_property = amdgpu_connector_set_property, 1520 .early_unregister = amdgpu_connector_unregister, 1521 .destroy = amdgpu_connector_destroy, 1522 .force = amdgpu_connector_dvi_force, 1523 }; 1524 1525 static const struct drm_connector_funcs amdgpu_connector_edp_funcs = { 1526 .dpms = drm_helper_connector_dpms, 1527 .detect = amdgpu_connector_dp_detect, 1528 .fill_modes = drm_helper_probe_single_connector_modes, 1529 .set_property = amdgpu_connector_set_lcd_property, 1530 .early_unregister = amdgpu_connector_unregister, 1531 .destroy = amdgpu_connector_destroy, 1532 .force = amdgpu_connector_dvi_force, 1533 }; 1534 1535 void 1536 amdgpu_connector_add(struct amdgpu_device *adev, 1537 uint32_t connector_id, 1538 uint32_t supported_device, 1539 int connector_type, 1540 struct amdgpu_i2c_bus_rec *i2c_bus, 1541 uint16_t connector_object_id, 1542 struct amdgpu_hpd *hpd, 1543 struct amdgpu_router *router) 1544 { 1545 struct drm_device *dev = adev->ddev; 1546 struct drm_connector *connector; 1547 struct amdgpu_connector *amdgpu_connector; 1548 struct amdgpu_connector_atom_dig *amdgpu_dig_connector; 1549 struct drm_encoder *encoder; 1550 struct amdgpu_encoder *amdgpu_encoder; 1551 uint32_t subpixel_order = SubPixelNone; 1552 bool shared_ddc = false; 1553 bool is_dp_bridge = false; 1554 bool has_aux = false; 1555 1556 if (connector_type == DRM_MODE_CONNECTOR_Unknown) 1557 return; 1558 1559 /* see if we already added it */ 1560 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 1561 amdgpu_connector = to_amdgpu_connector(connector); 1562 if (amdgpu_connector->connector_id == connector_id) { 1563 amdgpu_connector->devices |= supported_device; 1564 return; 1565 } 1566 if (amdgpu_connector->ddc_bus && i2c_bus->valid) { 1567 if (amdgpu_connector->ddc_bus->rec.i2c_id == i2c_bus->i2c_id) { 1568 amdgpu_connector->shared_ddc = true; 1569 shared_ddc = true; 1570 } 1571 if (amdgpu_connector->router_bus && router->ddc_valid && 1572 (amdgpu_connector->router.router_id == router->router_id)) { 1573 amdgpu_connector->shared_ddc = false; 1574 shared_ddc = false; 1575 } 1576 } 1577 } 1578 1579 /* check if it's a dp bridge */ 1580 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1581 amdgpu_encoder = to_amdgpu_encoder(encoder); 1582 if (amdgpu_encoder->devices & supported_device) { 1583 switch (amdgpu_encoder->encoder_id) { 1584 case ENCODER_OBJECT_ID_TRAVIS: 1585 case ENCODER_OBJECT_ID_NUTMEG: 1586 is_dp_bridge = true; 1587 break; 1588 default: 1589 break; 1590 } 1591 } 1592 } 1593 1594 amdgpu_connector = kzalloc(sizeof(struct amdgpu_connector), GFP_KERNEL); 1595 if (!amdgpu_connector) 1596 return; 1597 1598 connector = &amdgpu_connector->base; 1599 1600 amdgpu_connector->connector_id = connector_id; 1601 amdgpu_connector->devices = supported_device; 1602 amdgpu_connector->shared_ddc = shared_ddc; 1603 amdgpu_connector->connector_object_id = connector_object_id; 1604 amdgpu_connector->hpd = *hpd; 1605 1606 amdgpu_connector->router = *router; 1607 if (router->ddc_valid || router->cd_valid) { 1608 amdgpu_connector->router_bus = amdgpu_i2c_lookup(adev, &router->i2c_info); 1609 if (!amdgpu_connector->router_bus) 1610 DRM_ERROR("Failed to assign router i2c bus! Check dmesg for i2c errors.\n"); 1611 } 1612 1613 if (is_dp_bridge) { 1614 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1615 if (!amdgpu_dig_connector) 1616 goto failed; 1617 amdgpu_connector->con_priv = amdgpu_dig_connector; 1618 if (i2c_bus->valid) { 1619 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1620 if (amdgpu_connector->ddc_bus) 1621 has_aux = true; 1622 else 1623 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1624 } 1625 switch (connector_type) { 1626 case DRM_MODE_CONNECTOR_VGA: 1627 case DRM_MODE_CONNECTOR_DVIA: 1628 default: 1629 drm_connector_init(dev, &amdgpu_connector->base, 1630 &amdgpu_connector_dp_funcs, connector_type); 1631 drm_connector_helper_add(&amdgpu_connector->base, 1632 &amdgpu_connector_dp_helper_funcs); 1633 connector->interlace_allowed = true; 1634 connector->doublescan_allowed = true; 1635 amdgpu_connector->dac_load_detect = true; 1636 drm_object_attach_property(&amdgpu_connector->base.base, 1637 adev->mode_info.load_detect_property, 1638 1); 1639 drm_object_attach_property(&amdgpu_connector->base.base, 1640 dev->mode_config.scaling_mode_property, 1641 DRM_MODE_SCALE_NONE); 1642 break; 1643 case DRM_MODE_CONNECTOR_DVII: 1644 case DRM_MODE_CONNECTOR_DVID: 1645 case DRM_MODE_CONNECTOR_HDMIA: 1646 case DRM_MODE_CONNECTOR_HDMIB: 1647 case DRM_MODE_CONNECTOR_DisplayPort: 1648 drm_connector_init(dev, &amdgpu_connector->base, 1649 &amdgpu_connector_dp_funcs, connector_type); 1650 drm_connector_helper_add(&amdgpu_connector->base, 1651 &amdgpu_connector_dp_helper_funcs); 1652 drm_object_attach_property(&amdgpu_connector->base.base, 1653 adev->mode_info.underscan_property, 1654 UNDERSCAN_OFF); 1655 drm_object_attach_property(&amdgpu_connector->base.base, 1656 adev->mode_info.underscan_hborder_property, 1657 0); 1658 drm_object_attach_property(&amdgpu_connector->base.base, 1659 adev->mode_info.underscan_vborder_property, 1660 0); 1661 1662 drm_object_attach_property(&amdgpu_connector->base.base, 1663 dev->mode_config.scaling_mode_property, 1664 DRM_MODE_SCALE_NONE); 1665 1666 drm_object_attach_property(&amdgpu_connector->base.base, 1667 adev->mode_info.dither_property, 1668 AMDGPU_FMT_DITHER_DISABLE); 1669 1670 if (amdgpu_audio != 0) 1671 drm_object_attach_property(&amdgpu_connector->base.base, 1672 adev->mode_info.audio_property, 1673 AMDGPU_AUDIO_AUTO); 1674 1675 subpixel_order = SubPixelHorizontalRGB; 1676 connector->interlace_allowed = true; 1677 if (connector_type == DRM_MODE_CONNECTOR_HDMIB) 1678 connector->doublescan_allowed = true; 1679 else 1680 connector->doublescan_allowed = false; 1681 if (connector_type == DRM_MODE_CONNECTOR_DVII) { 1682 amdgpu_connector->dac_load_detect = true; 1683 drm_object_attach_property(&amdgpu_connector->base.base, 1684 adev->mode_info.load_detect_property, 1685 1); 1686 } 1687 break; 1688 case DRM_MODE_CONNECTOR_LVDS: 1689 case DRM_MODE_CONNECTOR_eDP: 1690 drm_connector_init(dev, &amdgpu_connector->base, 1691 &amdgpu_connector_edp_funcs, connector_type); 1692 drm_connector_helper_add(&amdgpu_connector->base, 1693 &amdgpu_connector_dp_helper_funcs); 1694 drm_object_attach_property(&amdgpu_connector->base.base, 1695 dev->mode_config.scaling_mode_property, 1696 DRM_MODE_SCALE_FULLSCREEN); 1697 subpixel_order = SubPixelHorizontalRGB; 1698 connector->interlace_allowed = false; 1699 connector->doublescan_allowed = false; 1700 break; 1701 } 1702 } else { 1703 switch (connector_type) { 1704 case DRM_MODE_CONNECTOR_VGA: 1705 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_vga_funcs, connector_type); 1706 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs); 1707 if (i2c_bus->valid) { 1708 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1709 if (!amdgpu_connector->ddc_bus) 1710 DRM_ERROR("VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1711 } 1712 amdgpu_connector->dac_load_detect = true; 1713 drm_object_attach_property(&amdgpu_connector->base.base, 1714 adev->mode_info.load_detect_property, 1715 1); 1716 drm_object_attach_property(&amdgpu_connector->base.base, 1717 dev->mode_config.scaling_mode_property, 1718 DRM_MODE_SCALE_NONE); 1719 /* no HPD on analog connectors */ 1720 amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE; 1721 connector->interlace_allowed = true; 1722 connector->doublescan_allowed = true; 1723 break; 1724 case DRM_MODE_CONNECTOR_DVIA: 1725 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_vga_funcs, connector_type); 1726 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs); 1727 if (i2c_bus->valid) { 1728 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1729 if (!amdgpu_connector->ddc_bus) 1730 DRM_ERROR("DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1731 } 1732 amdgpu_connector->dac_load_detect = true; 1733 drm_object_attach_property(&amdgpu_connector->base.base, 1734 adev->mode_info.load_detect_property, 1735 1); 1736 drm_object_attach_property(&amdgpu_connector->base.base, 1737 dev->mode_config.scaling_mode_property, 1738 DRM_MODE_SCALE_NONE); 1739 /* no HPD on analog connectors */ 1740 amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE; 1741 connector->interlace_allowed = true; 1742 connector->doublescan_allowed = true; 1743 break; 1744 case DRM_MODE_CONNECTOR_DVII: 1745 case DRM_MODE_CONNECTOR_DVID: 1746 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1747 if (!amdgpu_dig_connector) 1748 goto failed; 1749 amdgpu_connector->con_priv = amdgpu_dig_connector; 1750 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dvi_funcs, connector_type); 1751 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs); 1752 if (i2c_bus->valid) { 1753 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1754 if (!amdgpu_connector->ddc_bus) 1755 DRM_ERROR("DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1756 } 1757 subpixel_order = SubPixelHorizontalRGB; 1758 drm_object_attach_property(&amdgpu_connector->base.base, 1759 adev->mode_info.coherent_mode_property, 1760 1); 1761 drm_object_attach_property(&amdgpu_connector->base.base, 1762 adev->mode_info.underscan_property, 1763 UNDERSCAN_OFF); 1764 drm_object_attach_property(&amdgpu_connector->base.base, 1765 adev->mode_info.underscan_hborder_property, 1766 0); 1767 drm_object_attach_property(&amdgpu_connector->base.base, 1768 adev->mode_info.underscan_vborder_property, 1769 0); 1770 drm_object_attach_property(&amdgpu_connector->base.base, 1771 dev->mode_config.scaling_mode_property, 1772 DRM_MODE_SCALE_NONE); 1773 1774 if (amdgpu_audio != 0) { 1775 drm_object_attach_property(&amdgpu_connector->base.base, 1776 adev->mode_info.audio_property, 1777 AMDGPU_AUDIO_AUTO); 1778 } 1779 drm_object_attach_property(&amdgpu_connector->base.base, 1780 adev->mode_info.dither_property, 1781 AMDGPU_FMT_DITHER_DISABLE); 1782 if (connector_type == DRM_MODE_CONNECTOR_DVII) { 1783 amdgpu_connector->dac_load_detect = true; 1784 drm_object_attach_property(&amdgpu_connector->base.base, 1785 adev->mode_info.load_detect_property, 1786 1); 1787 } 1788 connector->interlace_allowed = true; 1789 if (connector_type == DRM_MODE_CONNECTOR_DVII) 1790 connector->doublescan_allowed = true; 1791 else 1792 connector->doublescan_allowed = false; 1793 break; 1794 case DRM_MODE_CONNECTOR_HDMIA: 1795 case DRM_MODE_CONNECTOR_HDMIB: 1796 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1797 if (!amdgpu_dig_connector) 1798 goto failed; 1799 amdgpu_connector->con_priv = amdgpu_dig_connector; 1800 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dvi_funcs, connector_type); 1801 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs); 1802 if (i2c_bus->valid) { 1803 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1804 if (!amdgpu_connector->ddc_bus) 1805 DRM_ERROR("HDMI: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1806 } 1807 drm_object_attach_property(&amdgpu_connector->base.base, 1808 adev->mode_info.coherent_mode_property, 1809 1); 1810 drm_object_attach_property(&amdgpu_connector->base.base, 1811 adev->mode_info.underscan_property, 1812 UNDERSCAN_OFF); 1813 drm_object_attach_property(&amdgpu_connector->base.base, 1814 adev->mode_info.underscan_hborder_property, 1815 0); 1816 drm_object_attach_property(&amdgpu_connector->base.base, 1817 adev->mode_info.underscan_vborder_property, 1818 0); 1819 drm_object_attach_property(&amdgpu_connector->base.base, 1820 dev->mode_config.scaling_mode_property, 1821 DRM_MODE_SCALE_NONE); 1822 if (amdgpu_audio != 0) { 1823 drm_object_attach_property(&amdgpu_connector->base.base, 1824 adev->mode_info.audio_property, 1825 AMDGPU_AUDIO_AUTO); 1826 } 1827 drm_object_attach_property(&amdgpu_connector->base.base, 1828 adev->mode_info.dither_property, 1829 AMDGPU_FMT_DITHER_DISABLE); 1830 subpixel_order = SubPixelHorizontalRGB; 1831 connector->interlace_allowed = true; 1832 if (connector_type == DRM_MODE_CONNECTOR_HDMIB) 1833 connector->doublescan_allowed = true; 1834 else 1835 connector->doublescan_allowed = false; 1836 break; 1837 case DRM_MODE_CONNECTOR_DisplayPort: 1838 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1839 if (!amdgpu_dig_connector) 1840 goto failed; 1841 amdgpu_connector->con_priv = amdgpu_dig_connector; 1842 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dp_funcs, connector_type); 1843 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs); 1844 if (i2c_bus->valid) { 1845 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1846 if (amdgpu_connector->ddc_bus) 1847 has_aux = true; 1848 else 1849 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1850 } 1851 subpixel_order = SubPixelHorizontalRGB; 1852 drm_object_attach_property(&amdgpu_connector->base.base, 1853 adev->mode_info.coherent_mode_property, 1854 1); 1855 drm_object_attach_property(&amdgpu_connector->base.base, 1856 adev->mode_info.underscan_property, 1857 UNDERSCAN_OFF); 1858 drm_object_attach_property(&amdgpu_connector->base.base, 1859 adev->mode_info.underscan_hborder_property, 1860 0); 1861 drm_object_attach_property(&amdgpu_connector->base.base, 1862 adev->mode_info.underscan_vborder_property, 1863 0); 1864 drm_object_attach_property(&amdgpu_connector->base.base, 1865 dev->mode_config.scaling_mode_property, 1866 DRM_MODE_SCALE_NONE); 1867 if (amdgpu_audio != 0) { 1868 drm_object_attach_property(&amdgpu_connector->base.base, 1869 adev->mode_info.audio_property, 1870 AMDGPU_AUDIO_AUTO); 1871 } 1872 drm_object_attach_property(&amdgpu_connector->base.base, 1873 adev->mode_info.dither_property, 1874 AMDGPU_FMT_DITHER_DISABLE); 1875 connector->interlace_allowed = true; 1876 /* in theory with a DP to VGA converter... */ 1877 connector->doublescan_allowed = false; 1878 break; 1879 case DRM_MODE_CONNECTOR_eDP: 1880 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1881 if (!amdgpu_dig_connector) 1882 goto failed; 1883 amdgpu_connector->con_priv = amdgpu_dig_connector; 1884 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_edp_funcs, connector_type); 1885 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs); 1886 if (i2c_bus->valid) { 1887 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1888 if (amdgpu_connector->ddc_bus) 1889 has_aux = true; 1890 else 1891 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1892 } 1893 drm_object_attach_property(&amdgpu_connector->base.base, 1894 dev->mode_config.scaling_mode_property, 1895 DRM_MODE_SCALE_FULLSCREEN); 1896 subpixel_order = SubPixelHorizontalRGB; 1897 connector->interlace_allowed = false; 1898 connector->doublescan_allowed = false; 1899 break; 1900 case DRM_MODE_CONNECTOR_LVDS: 1901 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1902 if (!amdgpu_dig_connector) 1903 goto failed; 1904 amdgpu_connector->con_priv = amdgpu_dig_connector; 1905 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_lvds_funcs, connector_type); 1906 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_lvds_helper_funcs); 1907 if (i2c_bus->valid) { 1908 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1909 if (!amdgpu_connector->ddc_bus) 1910 DRM_ERROR("LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1911 } 1912 drm_object_attach_property(&amdgpu_connector->base.base, 1913 dev->mode_config.scaling_mode_property, 1914 DRM_MODE_SCALE_FULLSCREEN); 1915 subpixel_order = SubPixelHorizontalRGB; 1916 connector->interlace_allowed = false; 1917 connector->doublescan_allowed = false; 1918 break; 1919 } 1920 } 1921 1922 if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) { 1923 if (i2c_bus->valid) { 1924 connector->polled = DRM_CONNECTOR_POLL_CONNECT | 1925 DRM_CONNECTOR_POLL_DISCONNECT; 1926 } 1927 } else 1928 connector->polled = DRM_CONNECTOR_POLL_HPD; 1929 1930 connector->display_info.subpixel_order = subpixel_order; 1931 drm_connector_register(connector); 1932 1933 if (has_aux) 1934 amdgpu_atombios_dp_aux_init(amdgpu_connector); 1935 1936 return; 1937 1938 failed: 1939 drm_connector_cleanup(connector); 1940 kfree(connector); 1941 } 1942