1* HiSilicon SAS controller 2 3The HiSilicon SAS controller supports SAS/SATA. 4 5Main node required properties: 6 - compatible : value should be as follows: 7 (a) "hisilicon,hip05-sas-v1" for v1 hw in hip05 chipset 8 (b) "hisilicon,hip06-sas-v2" for v2 hw in hip06 chipset 9 (c) "hisilicon,hip07-sas-v2" for v2 hw in hip07 chipset 10 - sas-addr : array of 8 bytes for host SAS address 11 - reg : Contains two regions. The first is the address and length of the SAS 12 register. The second is the address and length of CPLD register for 13 SGPIO control. The second is optional, and should be set only when 14 we use a CPLD for directly attached disk LED control. 15 - hisilicon,sas-syscon: phandle of syscon used for sas control 16 - ctrl-reset-reg : offset to controller reset register in ctrl reg 17 - ctrl-reset-sts-reg : offset to controller reset status register in ctrl reg 18 - ctrl-clock-ena-reg : offset to controller clock enable register in ctrl reg 19 - queue-count : number of delivery and completion queues in the controller 20 - phy-count : number of phys accessible by the controller 21 - interrupts : For v1 hw: Interrupts for phys, completion queues, and fatal 22 sources; the interrupts are ordered in 3 groups, as follows: 23 - Phy interrupts 24 - Completion queue interrupts 25 - Fatal interrupts 26 Phy interrupts : Each phy has 3 interrupt sources: 27 - broadcast 28 - phyup 29 - abnormal 30 The phy interrupts are ordered into groups of 3 per phy 31 (broadcast, phyup, and abnormal) in increasing order. 32 Completion queue interrupts : each completion queue has 1 33 interrupt source. 34 The interrupts are ordered in increasing order. 35 Fatal interrupts : the fatal interrupts are ordered as follows: 36 - ECC 37 - AXI bus 38 For v2 hw: Interrupts for phys, Sata, and completion queues; 39 the interrupts are ordered in 3 groups, as follows: 40 - Phy interrupts 41 - Sata interrupts 42 - Completion queue interrupts 43 Phy interrupts : Each controller has 2 phy interrupts: 44 - phy up/down 45 - channel interrupt 46 Sata interrupts : Each phy on the controller has 1 Sata 47 interrupt. The interrupts are ordered in increasing 48 order. 49 Completion queue interrupts : each completion queue has 1 50 interrupt source. The interrupts are ordered in 51 increasing order. 52 53Optional main node properties: 54 - hip06-sas-v2-quirk-amt : when set, indicates that the v2 controller has the 55 "am-max-transmissions" limitation. 56 57Example: 58 sas0: sas@c1000000 { 59 compatible = "hisilicon,hip05-sas-v1"; 60 sas-addr = [50 01 88 20 16 00 00 0a]; 61 reg = <0x0 0xc1000000 0x0 0x10000>; 62 hisilicon,sas-syscon = <&pcie_sas>; 63 ctrl-reset-reg = <0xa60>; 64 ctrl-reset-sts-reg = <0x5a30>; 65 ctrl-clock-ena-reg = <0x338>; 66 queue-count = <32>; 67 phy-count = <8>; 68 dma-coherent; 69 interrupt-parent = <&mbigen_dsa>; 70 interrupts = <259 4>,<263 4>,<264 4>,/* phy0 */ 71 <269 4>,<273 4>,<274 4>,/* phy1 */ 72 <279 4>,<283 4>,<284 4>,/* phy2 */ 73 <289 4>,<293 4>,<294 4>,/* phy3 */ 74 <299 4>,<303 4>,<304 4>,/* phy4 */ 75 <309 4>,<313 4>,<314 4>,/* phy5 */ 76 <319 4>,<323 4>,<324 4>,/* phy6 */ 77 <329 4>,<333 4>,<334 4>,/* phy7 */ 78 <336 1>,<337 1>,<338 1>,/* cq0-2 */ 79 <339 1>,<340 1>,<341 1>,/* cq3-5 */ 80 <342 1>,<343 1>,<344 1>,/* cq6-8 */ 81 <345 1>,<346 1>,<347 1>,/* cq9-11 */ 82 <348 1>,<349 1>,<350 1>,/* cq12-14 */ 83 <351 1>,<352 1>,<353 1>,/* cq15-17 */ 84 <354 1>,<355 1>,<356 1>,/* cq18-20 */ 85 <357 1>,<358 1>,<359 1>,/* cq21-23 */ 86 <360 1>,<361 1>,<362 1>,/* cq24-26 */ 87 <363 1>,<364 1>,<365 1>,/* cq27-29 */ 88 <366 1>,<367 1>/* cq30-31 */ 89 <376 4>,/* fatal ecc */ 90 <381 4>;/* fatal axi */ 91 }; 92