1 // SPDX-License-Identifier: GPL-2.0 2 /******************************************************************************* 3 * 4 Intel PRO/1000 Linux driver 5 Copyright(c) 1999 - 2006 Intel Corporation. 6 7 This program is free software; you can redistribute it and/or modify it 8 under the terms and conditions of the GNU General Public License, 9 version 2, as published by the Free Software Foundation. 10 11 This program is distributed in the hope it will be useful, but WITHOUT 12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 more details. 15 16 You should have received a copy of the GNU General Public License along with 17 this program; if not, write to the Free Software Foundation, Inc., 18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 19 20 The full GNU General Public License is included in this distribution in 21 the file called "COPYING". 22 23 Contact Information: 24 Linux NICS <linux.nics@intel.com> 25 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 26 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 27 28 */ 29 30 /* e1000_hw.c 31 * Shared functions for accessing and configuring the MAC 32 */ 33 34 #include "e1000.h" 35 36 static s32 e1000_check_downshift(struct e1000_hw *hw); 37 static s32 e1000_check_polarity(struct e1000_hw *hw, 38 e1000_rev_polarity *polarity); 39 static void e1000_clear_hw_cntrs(struct e1000_hw *hw); 40 static void e1000_clear_vfta(struct e1000_hw *hw); 41 static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, 42 bool link_up); 43 static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw); 44 static s32 e1000_detect_gig_phy(struct e1000_hw *hw); 45 static s32 e1000_get_auto_rd_done(struct e1000_hw *hw); 46 static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length, 47 u16 *max_length); 48 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw); 49 static s32 e1000_id_led_init(struct e1000_hw *hw); 50 static void e1000_init_rx_addrs(struct e1000_hw *hw); 51 static s32 e1000_phy_igp_get_info(struct e1000_hw *hw, 52 struct e1000_phy_info *phy_info); 53 static s32 e1000_phy_m88_get_info(struct e1000_hw *hw, 54 struct e1000_phy_info *phy_info); 55 static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active); 56 static s32 e1000_wait_autoneg(struct e1000_hw *hw); 57 static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value); 58 static s32 e1000_set_phy_type(struct e1000_hw *hw); 59 static void e1000_phy_init_script(struct e1000_hw *hw); 60 static s32 e1000_setup_copper_link(struct e1000_hw *hw); 61 static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw); 62 static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw); 63 static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw); 64 static s32 e1000_config_mac_to_phy(struct e1000_hw *hw); 65 static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl); 66 static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl); 67 static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count); 68 static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw); 69 static s32 e1000_phy_reset_dsp(struct e1000_hw *hw); 70 static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset, 71 u16 words, u16 *data); 72 static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset, 73 u16 words, u16 *data); 74 static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw); 75 static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd); 76 static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd); 77 static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count); 78 static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr, 79 u16 phy_data); 80 static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr, 81 u16 *phy_data); 82 static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count); 83 static s32 e1000_acquire_eeprom(struct e1000_hw *hw); 84 static void e1000_release_eeprom(struct e1000_hw *hw); 85 static void e1000_standby_eeprom(struct e1000_hw *hw); 86 static s32 e1000_set_vco_speed(struct e1000_hw *hw); 87 static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw); 88 static s32 e1000_set_phy_mode(struct e1000_hw *hw); 89 static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, 90 u16 *data); 91 static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, 92 u16 *data); 93 94 /* IGP cable length table */ 95 static const 96 u16 e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = { 97 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 98 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25, 99 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40, 100 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60, 101 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90, 102 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 103 100, 104 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 105 110, 110, 106 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 107 120, 120 108 }; 109 110 static DEFINE_MUTEX(e1000_eeprom_lock); 111 static DEFINE_SPINLOCK(e1000_phy_lock); 112 113 /** 114 * e1000_set_phy_type - Set the phy type member in the hw struct. 115 * @hw: Struct containing variables accessed by shared code 116 */ 117 static s32 e1000_set_phy_type(struct e1000_hw *hw) 118 { 119 if (hw->mac_type == e1000_undefined) 120 return -E1000_ERR_PHY_TYPE; 121 122 switch (hw->phy_id) { 123 case M88E1000_E_PHY_ID: 124 case M88E1000_I_PHY_ID: 125 case M88E1011_I_PHY_ID: 126 case M88E1111_I_PHY_ID: 127 case M88E1118_E_PHY_ID: 128 hw->phy_type = e1000_phy_m88; 129 break; 130 case IGP01E1000_I_PHY_ID: 131 if (hw->mac_type == e1000_82541 || 132 hw->mac_type == e1000_82541_rev_2 || 133 hw->mac_type == e1000_82547 || 134 hw->mac_type == e1000_82547_rev_2) 135 hw->phy_type = e1000_phy_igp; 136 break; 137 case RTL8211B_PHY_ID: 138 hw->phy_type = e1000_phy_8211; 139 break; 140 case RTL8201N_PHY_ID: 141 hw->phy_type = e1000_phy_8201; 142 break; 143 default: 144 /* Should never have loaded on this device */ 145 hw->phy_type = e1000_phy_undefined; 146 return -E1000_ERR_PHY_TYPE; 147 } 148 149 return E1000_SUCCESS; 150 } 151 152 /** 153 * e1000_phy_init_script - IGP phy init script - initializes the GbE PHY 154 * @hw: Struct containing variables accessed by shared code 155 */ 156 static void e1000_phy_init_script(struct e1000_hw *hw) 157 { 158 u32 ret_val; 159 u16 phy_saved_data; 160 161 if (hw->phy_init_script) { 162 msleep(20); 163 164 /* Save off the current value of register 0x2F5B to be restored 165 * at the end of this routine. 166 */ 167 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 168 169 /* Disabled the PHY transmitter */ 170 e1000_write_phy_reg(hw, 0x2F5B, 0x0003); 171 msleep(20); 172 173 e1000_write_phy_reg(hw, 0x0000, 0x0140); 174 msleep(5); 175 176 switch (hw->mac_type) { 177 case e1000_82541: 178 case e1000_82547: 179 e1000_write_phy_reg(hw, 0x1F95, 0x0001); 180 e1000_write_phy_reg(hw, 0x1F71, 0xBD21); 181 e1000_write_phy_reg(hw, 0x1F79, 0x0018); 182 e1000_write_phy_reg(hw, 0x1F30, 0x1600); 183 e1000_write_phy_reg(hw, 0x1F31, 0x0014); 184 e1000_write_phy_reg(hw, 0x1F32, 0x161C); 185 e1000_write_phy_reg(hw, 0x1F94, 0x0003); 186 e1000_write_phy_reg(hw, 0x1F96, 0x003F); 187 e1000_write_phy_reg(hw, 0x2010, 0x0008); 188 break; 189 190 case e1000_82541_rev_2: 191 case e1000_82547_rev_2: 192 e1000_write_phy_reg(hw, 0x1F73, 0x0099); 193 break; 194 default: 195 break; 196 } 197 198 e1000_write_phy_reg(hw, 0x0000, 0x3300); 199 msleep(20); 200 201 /* Now enable the transmitter */ 202 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); 203 204 if (hw->mac_type == e1000_82547) { 205 u16 fused, fine, coarse; 206 207 /* Move to analog registers page */ 208 e1000_read_phy_reg(hw, 209 IGP01E1000_ANALOG_SPARE_FUSE_STATUS, 210 &fused); 211 212 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { 213 e1000_read_phy_reg(hw, 214 IGP01E1000_ANALOG_FUSE_STATUS, 215 &fused); 216 217 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK; 218 coarse = 219 fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK; 220 221 if (coarse > 222 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { 223 coarse -= 224 IGP01E1000_ANALOG_FUSE_COARSE_10; 225 fine -= IGP01E1000_ANALOG_FUSE_FINE_1; 226 } else if (coarse == 227 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) 228 fine -= IGP01E1000_ANALOG_FUSE_FINE_10; 229 230 fused = 231 (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) | 232 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) | 233 (coarse & 234 IGP01E1000_ANALOG_FUSE_COARSE_MASK); 235 236 e1000_write_phy_reg(hw, 237 IGP01E1000_ANALOG_FUSE_CONTROL, 238 fused); 239 e1000_write_phy_reg(hw, 240 IGP01E1000_ANALOG_FUSE_BYPASS, 241 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL); 242 } 243 } 244 } 245 } 246 247 /** 248 * e1000_set_mac_type - Set the mac type member in the hw struct. 249 * @hw: Struct containing variables accessed by shared code 250 */ 251 s32 e1000_set_mac_type(struct e1000_hw *hw) 252 { 253 switch (hw->device_id) { 254 case E1000_DEV_ID_82542: 255 switch (hw->revision_id) { 256 case E1000_82542_2_0_REV_ID: 257 hw->mac_type = e1000_82542_rev2_0; 258 break; 259 case E1000_82542_2_1_REV_ID: 260 hw->mac_type = e1000_82542_rev2_1; 261 break; 262 default: 263 /* Invalid 82542 revision ID */ 264 return -E1000_ERR_MAC_TYPE; 265 } 266 break; 267 case E1000_DEV_ID_82543GC_FIBER: 268 case E1000_DEV_ID_82543GC_COPPER: 269 hw->mac_type = e1000_82543; 270 break; 271 case E1000_DEV_ID_82544EI_COPPER: 272 case E1000_DEV_ID_82544EI_FIBER: 273 case E1000_DEV_ID_82544GC_COPPER: 274 case E1000_DEV_ID_82544GC_LOM: 275 hw->mac_type = e1000_82544; 276 break; 277 case E1000_DEV_ID_82540EM: 278 case E1000_DEV_ID_82540EM_LOM: 279 case E1000_DEV_ID_82540EP: 280 case E1000_DEV_ID_82540EP_LOM: 281 case E1000_DEV_ID_82540EP_LP: 282 hw->mac_type = e1000_82540; 283 break; 284 case E1000_DEV_ID_82545EM_COPPER: 285 case E1000_DEV_ID_82545EM_FIBER: 286 hw->mac_type = e1000_82545; 287 break; 288 case E1000_DEV_ID_82545GM_COPPER: 289 case E1000_DEV_ID_82545GM_FIBER: 290 case E1000_DEV_ID_82545GM_SERDES: 291 hw->mac_type = e1000_82545_rev_3; 292 break; 293 case E1000_DEV_ID_82546EB_COPPER: 294 case E1000_DEV_ID_82546EB_FIBER: 295 case E1000_DEV_ID_82546EB_QUAD_COPPER: 296 hw->mac_type = e1000_82546; 297 break; 298 case E1000_DEV_ID_82546GB_COPPER: 299 case E1000_DEV_ID_82546GB_FIBER: 300 case E1000_DEV_ID_82546GB_SERDES: 301 case E1000_DEV_ID_82546GB_PCIE: 302 case E1000_DEV_ID_82546GB_QUAD_COPPER: 303 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 304 hw->mac_type = e1000_82546_rev_3; 305 break; 306 case E1000_DEV_ID_82541EI: 307 case E1000_DEV_ID_82541EI_MOBILE: 308 case E1000_DEV_ID_82541ER_LOM: 309 hw->mac_type = e1000_82541; 310 break; 311 case E1000_DEV_ID_82541ER: 312 case E1000_DEV_ID_82541GI: 313 case E1000_DEV_ID_82541GI_LF: 314 case E1000_DEV_ID_82541GI_MOBILE: 315 hw->mac_type = e1000_82541_rev_2; 316 break; 317 case E1000_DEV_ID_82547EI: 318 case E1000_DEV_ID_82547EI_MOBILE: 319 hw->mac_type = e1000_82547; 320 break; 321 case E1000_DEV_ID_82547GI: 322 hw->mac_type = e1000_82547_rev_2; 323 break; 324 case E1000_DEV_ID_INTEL_CE4100_GBE: 325 hw->mac_type = e1000_ce4100; 326 break; 327 default: 328 /* Should never have loaded on this device */ 329 return -E1000_ERR_MAC_TYPE; 330 } 331 332 switch (hw->mac_type) { 333 case e1000_82541: 334 case e1000_82547: 335 case e1000_82541_rev_2: 336 case e1000_82547_rev_2: 337 hw->asf_firmware_present = true; 338 break; 339 default: 340 break; 341 } 342 343 /* The 82543 chip does not count tx_carrier_errors properly in 344 * FD mode 345 */ 346 if (hw->mac_type == e1000_82543) 347 hw->bad_tx_carr_stats_fd = true; 348 349 if (hw->mac_type > e1000_82544) 350 hw->has_smbus = true; 351 352 return E1000_SUCCESS; 353 } 354 355 /** 356 * e1000_set_media_type - Set media type and TBI compatibility. 357 * @hw: Struct containing variables accessed by shared code 358 */ 359 void e1000_set_media_type(struct e1000_hw *hw) 360 { 361 u32 status; 362 363 if (hw->mac_type != e1000_82543) { 364 /* tbi_compatibility is only valid on 82543 */ 365 hw->tbi_compatibility_en = false; 366 } 367 368 switch (hw->device_id) { 369 case E1000_DEV_ID_82545GM_SERDES: 370 case E1000_DEV_ID_82546GB_SERDES: 371 hw->media_type = e1000_media_type_internal_serdes; 372 break; 373 default: 374 switch (hw->mac_type) { 375 case e1000_82542_rev2_0: 376 case e1000_82542_rev2_1: 377 hw->media_type = e1000_media_type_fiber; 378 break; 379 case e1000_ce4100: 380 hw->media_type = e1000_media_type_copper; 381 break; 382 default: 383 status = er32(STATUS); 384 if (status & E1000_STATUS_TBIMODE) { 385 hw->media_type = e1000_media_type_fiber; 386 /* tbi_compatibility not valid on fiber */ 387 hw->tbi_compatibility_en = false; 388 } else { 389 hw->media_type = e1000_media_type_copper; 390 } 391 break; 392 } 393 } 394 } 395 396 /** 397 * e1000_reset_hw - reset the hardware completely 398 * @hw: Struct containing variables accessed by shared code 399 * 400 * Reset the transmit and receive units; mask and clear all interrupts. 401 */ 402 s32 e1000_reset_hw(struct e1000_hw *hw) 403 { 404 u32 ctrl; 405 u32 ctrl_ext; 406 u32 icr; 407 u32 manc; 408 u32 led_ctrl; 409 s32 ret_val; 410 411 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ 412 if (hw->mac_type == e1000_82542_rev2_0) { 413 e_dbg("Disabling MWI on 82542 rev 2.0\n"); 414 e1000_pci_clear_mwi(hw); 415 } 416 417 /* Clear interrupt mask to stop board from generating interrupts */ 418 e_dbg("Masking off all interrupts\n"); 419 ew32(IMC, 0xffffffff); 420 421 /* Disable the Transmit and Receive units. Then delay to allow 422 * any pending transactions to complete before we hit the MAC with 423 * the global reset. 424 */ 425 ew32(RCTL, 0); 426 ew32(TCTL, E1000_TCTL_PSP); 427 E1000_WRITE_FLUSH(); 428 429 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */ 430 hw->tbi_compatibility_on = false; 431 432 /* Delay to allow any outstanding PCI transactions to complete before 433 * resetting the device 434 */ 435 msleep(10); 436 437 ctrl = er32(CTRL); 438 439 /* Must reset the PHY before resetting the MAC */ 440 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 441 ew32(CTRL, (ctrl | E1000_CTRL_PHY_RST)); 442 E1000_WRITE_FLUSH(); 443 msleep(5); 444 } 445 446 /* Issue a global reset to the MAC. This will reset the chip's 447 * transmit, receive, DMA, and link units. It will not effect 448 * the current PCI configuration. The global reset bit is self- 449 * clearing, and should clear within a microsecond. 450 */ 451 e_dbg("Issuing a global reset to MAC\n"); 452 453 switch (hw->mac_type) { 454 case e1000_82544: 455 case e1000_82540: 456 case e1000_82545: 457 case e1000_82546: 458 case e1000_82541: 459 case e1000_82541_rev_2: 460 /* These controllers can't ack the 64-bit write when issuing the 461 * reset, so use IO-mapping as a workaround to issue the reset 462 */ 463 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST)); 464 break; 465 case e1000_82545_rev_3: 466 case e1000_82546_rev_3: 467 /* Reset is performed on a shadow of the control register */ 468 ew32(CTRL_DUP, (ctrl | E1000_CTRL_RST)); 469 break; 470 case e1000_ce4100: 471 default: 472 ew32(CTRL, (ctrl | E1000_CTRL_RST)); 473 break; 474 } 475 476 /* After MAC reset, force reload of EEPROM to restore power-on settings 477 * to device. Later controllers reload the EEPROM automatically, so 478 * just wait for reload to complete. 479 */ 480 switch (hw->mac_type) { 481 case e1000_82542_rev2_0: 482 case e1000_82542_rev2_1: 483 case e1000_82543: 484 case e1000_82544: 485 /* Wait for reset to complete */ 486 udelay(10); 487 ctrl_ext = er32(CTRL_EXT); 488 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 489 ew32(CTRL_EXT, ctrl_ext); 490 E1000_WRITE_FLUSH(); 491 /* Wait for EEPROM reload */ 492 msleep(2); 493 break; 494 case e1000_82541: 495 case e1000_82541_rev_2: 496 case e1000_82547: 497 case e1000_82547_rev_2: 498 /* Wait for EEPROM reload */ 499 msleep(20); 500 break; 501 default: 502 /* Auto read done will delay 5ms or poll based on mac type */ 503 ret_val = e1000_get_auto_rd_done(hw); 504 if (ret_val) 505 return ret_val; 506 break; 507 } 508 509 /* Disable HW ARPs on ASF enabled adapters */ 510 if (hw->mac_type >= e1000_82540) { 511 manc = er32(MANC); 512 manc &= ~(E1000_MANC_ARP_EN); 513 ew32(MANC, manc); 514 } 515 516 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 517 e1000_phy_init_script(hw); 518 519 /* Configure activity LED after PHY reset */ 520 led_ctrl = er32(LEDCTL); 521 led_ctrl &= IGP_ACTIVITY_LED_MASK; 522 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 523 ew32(LEDCTL, led_ctrl); 524 } 525 526 /* Clear interrupt mask to stop board from generating interrupts */ 527 e_dbg("Masking off all interrupts\n"); 528 ew32(IMC, 0xffffffff); 529 530 /* Clear any pending interrupt events. */ 531 icr = er32(ICR); 532 533 /* If MWI was previously enabled, reenable it. */ 534 if (hw->mac_type == e1000_82542_rev2_0) { 535 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE) 536 e1000_pci_set_mwi(hw); 537 } 538 539 return E1000_SUCCESS; 540 } 541 542 /** 543 * e1000_init_hw - Performs basic configuration of the adapter. 544 * @hw: Struct containing variables accessed by shared code 545 * 546 * Assumes that the controller has previously been reset and is in a 547 * post-reset uninitialized state. Initializes the receive address registers, 548 * multicast table, and VLAN filter table. Calls routines to setup link 549 * configuration and flow control settings. Clears all on-chip counters. Leaves 550 * the transmit and receive units disabled and uninitialized. 551 */ 552 s32 e1000_init_hw(struct e1000_hw *hw) 553 { 554 u32 ctrl; 555 u32 i; 556 s32 ret_val; 557 u32 mta_size; 558 u32 ctrl_ext; 559 560 /* Initialize Identification LED */ 561 ret_val = e1000_id_led_init(hw); 562 if (ret_val) { 563 e_dbg("Error Initializing Identification LED\n"); 564 return ret_val; 565 } 566 567 /* Set the media type and TBI compatibility */ 568 e1000_set_media_type(hw); 569 570 /* Disabling VLAN filtering. */ 571 e_dbg("Initializing the IEEE VLAN\n"); 572 if (hw->mac_type < e1000_82545_rev_3) 573 ew32(VET, 0); 574 e1000_clear_vfta(hw); 575 576 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ 577 if (hw->mac_type == e1000_82542_rev2_0) { 578 e_dbg("Disabling MWI on 82542 rev 2.0\n"); 579 e1000_pci_clear_mwi(hw); 580 ew32(RCTL, E1000_RCTL_RST); 581 E1000_WRITE_FLUSH(); 582 msleep(5); 583 } 584 585 /* Setup the receive address. This involves initializing all of the 586 * Receive Address Registers (RARs 0 - 15). 587 */ 588 e1000_init_rx_addrs(hw); 589 590 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */ 591 if (hw->mac_type == e1000_82542_rev2_0) { 592 ew32(RCTL, 0); 593 E1000_WRITE_FLUSH(); 594 msleep(1); 595 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE) 596 e1000_pci_set_mwi(hw); 597 } 598 599 /* Zero out the Multicast HASH table */ 600 e_dbg("Zeroing the MTA\n"); 601 mta_size = E1000_MC_TBL_SIZE; 602 for (i = 0; i < mta_size; i++) { 603 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 604 /* use write flush to prevent Memory Write Block (MWB) from 605 * occurring when accessing our register space 606 */ 607 E1000_WRITE_FLUSH(); 608 } 609 610 /* Set the PCI priority bit correctly in the CTRL register. This 611 * determines if the adapter gives priority to receives, or if it 612 * gives equal priority to transmits and receives. Valid only on 613 * 82542 and 82543 silicon. 614 */ 615 if (hw->dma_fairness && hw->mac_type <= e1000_82543) { 616 ctrl = er32(CTRL); 617 ew32(CTRL, ctrl | E1000_CTRL_PRIOR); 618 } 619 620 switch (hw->mac_type) { 621 case e1000_82545_rev_3: 622 case e1000_82546_rev_3: 623 break; 624 default: 625 /* Workaround for PCI-X problem when BIOS sets MMRBC 626 * incorrectly. 627 */ 628 if (hw->bus_type == e1000_bus_type_pcix && 629 e1000_pcix_get_mmrbc(hw) > 2048) 630 e1000_pcix_set_mmrbc(hw, 2048); 631 break; 632 } 633 634 /* Call a subroutine to configure the link and setup flow control. */ 635 ret_val = e1000_setup_link(hw); 636 637 /* Set the transmit descriptor write-back policy */ 638 if (hw->mac_type > e1000_82544) { 639 ctrl = er32(TXDCTL); 640 ctrl = 641 (ctrl & ~E1000_TXDCTL_WTHRESH) | 642 E1000_TXDCTL_FULL_TX_DESC_WB; 643 ew32(TXDCTL, ctrl); 644 } 645 646 /* Clear all of the statistics registers (clear on read). It is 647 * important that we do this after we have tried to establish link 648 * because the symbol error count will increment wildly if there 649 * is no link. 650 */ 651 e1000_clear_hw_cntrs(hw); 652 653 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER || 654 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) { 655 ctrl_ext = er32(CTRL_EXT); 656 /* Relaxed ordering must be disabled to avoid a parity 657 * error crash in a PCI slot. 658 */ 659 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 660 ew32(CTRL_EXT, ctrl_ext); 661 } 662 663 return ret_val; 664 } 665 666 /** 667 * e1000_adjust_serdes_amplitude - Adjust SERDES output amplitude based on EEPROM setting. 668 * @hw: Struct containing variables accessed by shared code. 669 */ 670 static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw) 671 { 672 u16 eeprom_data; 673 s32 ret_val; 674 675 if (hw->media_type != e1000_media_type_internal_serdes) 676 return E1000_SUCCESS; 677 678 switch (hw->mac_type) { 679 case e1000_82545_rev_3: 680 case e1000_82546_rev_3: 681 break; 682 default: 683 return E1000_SUCCESS; 684 } 685 686 ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, 687 &eeprom_data); 688 if (ret_val) 689 return ret_val; 690 691 if (eeprom_data != EEPROM_RESERVED_WORD) { 692 /* Adjust SERDES output amplitude only. */ 693 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK; 694 ret_val = 695 e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data); 696 if (ret_val) 697 return ret_val; 698 } 699 700 return E1000_SUCCESS; 701 } 702 703 /** 704 * e1000_setup_link - Configures flow control and link settings. 705 * @hw: Struct containing variables accessed by shared code 706 * 707 * Determines which flow control settings to use. Calls the appropriate media- 708 * specific link configuration function. Configures the flow control settings. 709 * Assuming the adapter has a valid link partner, a valid link should be 710 * established. Assumes the hardware has previously been reset and the 711 * transmitter and receiver are not enabled. 712 */ 713 s32 e1000_setup_link(struct e1000_hw *hw) 714 { 715 u32 ctrl_ext; 716 s32 ret_val; 717 u16 eeprom_data; 718 719 /* Read and store word 0x0F of the EEPROM. This word contains bits 720 * that determine the hardware's default PAUSE (flow control) mode, 721 * a bit that determines whether the HW defaults to enabling or 722 * disabling auto-negotiation, and the direction of the 723 * SW defined pins. If there is no SW over-ride of the flow 724 * control setting, then the variable hw->fc will 725 * be initialized based on a value in the EEPROM. 726 */ 727 if (hw->fc == E1000_FC_DEFAULT) { 728 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 729 1, &eeprom_data); 730 if (ret_val) { 731 e_dbg("EEPROM Read Error\n"); 732 return -E1000_ERR_EEPROM; 733 } 734 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0) 735 hw->fc = E1000_FC_NONE; 736 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 737 EEPROM_WORD0F_ASM_DIR) 738 hw->fc = E1000_FC_TX_PAUSE; 739 else 740 hw->fc = E1000_FC_FULL; 741 } 742 743 /* We want to save off the original Flow Control configuration just 744 * in case we get disconnected and then reconnected into a different 745 * hub or switch with different Flow Control capabilities. 746 */ 747 if (hw->mac_type == e1000_82542_rev2_0) 748 hw->fc &= (~E1000_FC_TX_PAUSE); 749 750 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1)) 751 hw->fc &= (~E1000_FC_RX_PAUSE); 752 753 hw->original_fc = hw->fc; 754 755 e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc); 756 757 /* Take the 4 bits from EEPROM word 0x0F that determine the initial 758 * polarity value for the SW controlled pins, and setup the 759 * Extended Device Control reg with that info. 760 * This is needed because one of the SW controlled pins is used for 761 * signal detection. So this should be done before e1000_setup_pcs_link() 762 * or e1000_phy_setup() is called. 763 */ 764 if (hw->mac_type == e1000_82543) { 765 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 766 1, &eeprom_data); 767 if (ret_val) { 768 e_dbg("EEPROM Read Error\n"); 769 return -E1000_ERR_EEPROM; 770 } 771 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << 772 SWDPIO__EXT_SHIFT); 773 ew32(CTRL_EXT, ctrl_ext); 774 } 775 776 /* Call the necessary subroutine to configure the link. */ 777 ret_val = (hw->media_type == e1000_media_type_copper) ? 778 e1000_setup_copper_link(hw) : e1000_setup_fiber_serdes_link(hw); 779 780 /* Initialize the flow control address, type, and PAUSE timer 781 * registers to their default values. This is done even if flow 782 * control is disabled, because it does not hurt anything to 783 * initialize these registers. 784 */ 785 e_dbg("Initializing the Flow Control address, type and timer regs\n"); 786 787 ew32(FCT, FLOW_CONTROL_TYPE); 788 ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH); 789 ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW); 790 791 ew32(FCTTV, hw->fc_pause_time); 792 793 /* Set the flow control receive threshold registers. Normally, 794 * these registers will be set to a default threshold that may be 795 * adjusted later by the driver's runtime code. However, if the 796 * ability to transmit pause frames in not enabled, then these 797 * registers will be set to 0. 798 */ 799 if (!(hw->fc & E1000_FC_TX_PAUSE)) { 800 ew32(FCRTL, 0); 801 ew32(FCRTH, 0); 802 } else { 803 /* We need to set up the Receive Threshold high and low water 804 * marks as well as (optionally) enabling the transmission of 805 * XON frames. 806 */ 807 if (hw->fc_send_xon) { 808 ew32(FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE)); 809 ew32(FCRTH, hw->fc_high_water); 810 } else { 811 ew32(FCRTL, hw->fc_low_water); 812 ew32(FCRTH, hw->fc_high_water); 813 } 814 } 815 return ret_val; 816 } 817 818 /** 819 * e1000_setup_fiber_serdes_link - prepare fiber or serdes link 820 * @hw: Struct containing variables accessed by shared code 821 * 822 * Manipulates Physical Coding Sublayer functions in order to configure 823 * link. Assumes the hardware has been previously reset and the transmitter 824 * and receiver are not enabled. 825 */ 826 static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw) 827 { 828 u32 ctrl; 829 u32 status; 830 u32 txcw = 0; 831 u32 i; 832 u32 signal = 0; 833 s32 ret_val; 834 835 /* On adapters with a MAC newer than 82544, SWDP 1 will be 836 * set when the optics detect a signal. On older adapters, it will be 837 * cleared when there is a signal. This applies to fiber media only. 838 * If we're on serdes media, adjust the output amplitude to value 839 * set in the EEPROM. 840 */ 841 ctrl = er32(CTRL); 842 if (hw->media_type == e1000_media_type_fiber) 843 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0; 844 845 ret_val = e1000_adjust_serdes_amplitude(hw); 846 if (ret_val) 847 return ret_val; 848 849 /* Take the link out of reset */ 850 ctrl &= ~(E1000_CTRL_LRST); 851 852 /* Adjust VCO speed to improve BER performance */ 853 ret_val = e1000_set_vco_speed(hw); 854 if (ret_val) 855 return ret_val; 856 857 e1000_config_collision_dist(hw); 858 859 /* Check for a software override of the flow control settings, and setup 860 * the device accordingly. If auto-negotiation is enabled, then 861 * software will have to set the "PAUSE" bits to the correct value in 862 * the Tranmsit Config Word Register (TXCW) and re-start 863 * auto-negotiation. However, if auto-negotiation is disabled, then 864 * software will have to manually configure the two flow control enable 865 * bits in the CTRL register. 866 * 867 * The possible values of the "fc" parameter are: 868 * 0: Flow control is completely disabled 869 * 1: Rx flow control is enabled (we can receive pause frames, but 870 * not send pause frames). 871 * 2: Tx flow control is enabled (we can send pause frames but we do 872 * not support receiving pause frames). 873 * 3: Both Rx and TX flow control (symmetric) are enabled. 874 */ 875 switch (hw->fc) { 876 case E1000_FC_NONE: 877 /* Flow ctrl is completely disabled by a software over-ride */ 878 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 879 break; 880 case E1000_FC_RX_PAUSE: 881 /* Rx Flow control is enabled and Tx Flow control is disabled by 882 * a software over-ride. Since there really isn't a way to 883 * advertise that we are capable of Rx Pause ONLY, we will 884 * advertise that we support both symmetric and asymmetric Rx 885 * PAUSE. Later, we will disable the adapter's ability to send 886 * PAUSE frames. 887 */ 888 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 889 break; 890 case E1000_FC_TX_PAUSE: 891 /* Tx Flow control is enabled, and Rx Flow control is disabled, 892 * by a software over-ride. 893 */ 894 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 895 break; 896 case E1000_FC_FULL: 897 /* Flow control (both Rx and Tx) is enabled by a software 898 * over-ride. 899 */ 900 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 901 break; 902 default: 903 e_dbg("Flow control param set incorrectly\n"); 904 return -E1000_ERR_CONFIG; 905 } 906 907 /* Since auto-negotiation is enabled, take the link out of reset (the 908 * link will be in reset, because we previously reset the chip). This 909 * will restart auto-negotiation. If auto-negotiation is successful 910 * then the link-up status bit will be set and the flow control enable 911 * bits (RFCE and TFCE) will be set according to their negotiated value. 912 */ 913 e_dbg("Auto-negotiation enabled\n"); 914 915 ew32(TXCW, txcw); 916 ew32(CTRL, ctrl); 917 E1000_WRITE_FLUSH(); 918 919 hw->txcw = txcw; 920 msleep(1); 921 922 /* If we have a signal (the cable is plugged in) then poll for a 923 * "Link-Up" indication in the Device Status Register. Time-out if a 924 * link isn't seen in 500 milliseconds seconds (Auto-negotiation should 925 * complete in less than 500 milliseconds even if the other end is doing 926 * it in SW). For internal serdes, we just assume a signal is present, 927 * then poll. 928 */ 929 if (hw->media_type == e1000_media_type_internal_serdes || 930 (er32(CTRL) & E1000_CTRL_SWDPIN1) == signal) { 931 e_dbg("Looking for Link\n"); 932 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { 933 msleep(10); 934 status = er32(STATUS); 935 if (status & E1000_STATUS_LU) 936 break; 937 } 938 if (i == (LINK_UP_TIMEOUT / 10)) { 939 e_dbg("Never got a valid link from auto-neg!!!\n"); 940 hw->autoneg_failed = 1; 941 /* AutoNeg failed to achieve a link, so we'll call 942 * e1000_check_for_link. This routine will force the 943 * link up if we detect a signal. This will allow us to 944 * communicate with non-autonegotiating link partners. 945 */ 946 ret_val = e1000_check_for_link(hw); 947 if (ret_val) { 948 e_dbg("Error while checking for link\n"); 949 return ret_val; 950 } 951 hw->autoneg_failed = 0; 952 } else { 953 hw->autoneg_failed = 0; 954 e_dbg("Valid Link Found\n"); 955 } 956 } else { 957 e_dbg("No Signal Detected\n"); 958 } 959 return E1000_SUCCESS; 960 } 961 962 /** 963 * e1000_copper_link_rtl_setup - Copper link setup for e1000_phy_rtl series. 964 * @hw: Struct containing variables accessed by shared code 965 * 966 * Commits changes to PHY configuration by calling e1000_phy_reset(). 967 */ 968 static s32 e1000_copper_link_rtl_setup(struct e1000_hw *hw) 969 { 970 s32 ret_val; 971 972 /* SW reset the PHY so all changes take effect */ 973 ret_val = e1000_phy_reset(hw); 974 if (ret_val) { 975 e_dbg("Error Resetting the PHY\n"); 976 return ret_val; 977 } 978 979 return E1000_SUCCESS; 980 } 981 982 static s32 gbe_dhg_phy_setup(struct e1000_hw *hw) 983 { 984 s32 ret_val; 985 u32 ctrl_aux; 986 987 switch (hw->phy_type) { 988 case e1000_phy_8211: 989 ret_val = e1000_copper_link_rtl_setup(hw); 990 if (ret_val) { 991 e_dbg("e1000_copper_link_rtl_setup failed!\n"); 992 return ret_val; 993 } 994 break; 995 case e1000_phy_8201: 996 /* Set RMII mode */ 997 ctrl_aux = er32(CTL_AUX); 998 ctrl_aux |= E1000_CTL_AUX_RMII; 999 ew32(CTL_AUX, ctrl_aux); 1000 E1000_WRITE_FLUSH(); 1001 1002 /* Disable the J/K bits required for receive */ 1003 ctrl_aux = er32(CTL_AUX); 1004 ctrl_aux |= 0x4; 1005 ctrl_aux &= ~0x2; 1006 ew32(CTL_AUX, ctrl_aux); 1007 E1000_WRITE_FLUSH(); 1008 ret_val = e1000_copper_link_rtl_setup(hw); 1009 1010 if (ret_val) { 1011 e_dbg("e1000_copper_link_rtl_setup failed!\n"); 1012 return ret_val; 1013 } 1014 break; 1015 default: 1016 e_dbg("Error Resetting the PHY\n"); 1017 return E1000_ERR_PHY_TYPE; 1018 } 1019 1020 return E1000_SUCCESS; 1021 } 1022 1023 /** 1024 * e1000_copper_link_preconfig - early configuration for copper 1025 * @hw: Struct containing variables accessed by shared code 1026 * 1027 * Make sure we have a valid PHY and change PHY mode before link setup. 1028 */ 1029 static s32 e1000_copper_link_preconfig(struct e1000_hw *hw) 1030 { 1031 u32 ctrl; 1032 s32 ret_val; 1033 u16 phy_data; 1034 1035 ctrl = er32(CTRL); 1036 /* With 82543, we need to force speed and duplex on the MAC equal to 1037 * what the PHY speed and duplex configuration is. In addition, we need 1038 * to perform a hardware reset on the PHY to take it out of reset. 1039 */ 1040 if (hw->mac_type > e1000_82543) { 1041 ctrl |= E1000_CTRL_SLU; 1042 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1043 ew32(CTRL, ctrl); 1044 } else { 1045 ctrl |= 1046 (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU); 1047 ew32(CTRL, ctrl); 1048 ret_val = e1000_phy_hw_reset(hw); 1049 if (ret_val) 1050 return ret_val; 1051 } 1052 1053 /* Make sure we have a valid PHY */ 1054 ret_val = e1000_detect_gig_phy(hw); 1055 if (ret_val) { 1056 e_dbg("Error, did not detect valid phy.\n"); 1057 return ret_val; 1058 } 1059 e_dbg("Phy ID = %x\n", hw->phy_id); 1060 1061 /* Set PHY to class A mode (if necessary) */ 1062 ret_val = e1000_set_phy_mode(hw); 1063 if (ret_val) 1064 return ret_val; 1065 1066 if ((hw->mac_type == e1000_82545_rev_3) || 1067 (hw->mac_type == e1000_82546_rev_3)) { 1068 ret_val = 1069 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1070 phy_data |= 0x00000008; 1071 ret_val = 1072 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1073 } 1074 1075 if (hw->mac_type <= e1000_82543 || 1076 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 || 1077 hw->mac_type == e1000_82541_rev_2 || 1078 hw->mac_type == e1000_82547_rev_2) 1079 hw->phy_reset_disable = false; 1080 1081 return E1000_SUCCESS; 1082 } 1083 1084 /** 1085 * e1000_copper_link_igp_setup - Copper link setup for e1000_phy_igp series. 1086 * @hw: Struct containing variables accessed by shared code 1087 */ 1088 static s32 e1000_copper_link_igp_setup(struct e1000_hw *hw) 1089 { 1090 u32 led_ctrl; 1091 s32 ret_val; 1092 u16 phy_data; 1093 1094 if (hw->phy_reset_disable) 1095 return E1000_SUCCESS; 1096 1097 ret_val = e1000_phy_reset(hw); 1098 if (ret_val) { 1099 e_dbg("Error Resetting the PHY\n"); 1100 return ret_val; 1101 } 1102 1103 /* Wait 15ms for MAC to configure PHY from eeprom settings */ 1104 msleep(15); 1105 /* Configure activity LED after PHY reset */ 1106 led_ctrl = er32(LEDCTL); 1107 led_ctrl &= IGP_ACTIVITY_LED_MASK; 1108 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 1109 ew32(LEDCTL, led_ctrl); 1110 1111 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */ 1112 if (hw->phy_type == e1000_phy_igp) { 1113 /* disable lplu d3 during driver init */ 1114 ret_val = e1000_set_d3_lplu_state(hw, false); 1115 if (ret_val) { 1116 e_dbg("Error Disabling LPLU D3\n"); 1117 return ret_val; 1118 } 1119 } 1120 1121 /* Configure mdi-mdix settings */ 1122 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 1123 if (ret_val) 1124 return ret_val; 1125 1126 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 1127 hw->dsp_config_state = e1000_dsp_config_disabled; 1128 /* Force MDI for earlier revs of the IGP PHY */ 1129 phy_data &= 1130 ~(IGP01E1000_PSCR_AUTO_MDIX | 1131 IGP01E1000_PSCR_FORCE_MDI_MDIX); 1132 hw->mdix = 1; 1133 1134 } else { 1135 hw->dsp_config_state = e1000_dsp_config_enabled; 1136 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 1137 1138 switch (hw->mdix) { 1139 case 1: 1140 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 1141 break; 1142 case 2: 1143 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; 1144 break; 1145 case 0: 1146 default: 1147 phy_data |= IGP01E1000_PSCR_AUTO_MDIX; 1148 break; 1149 } 1150 } 1151 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 1152 if (ret_val) 1153 return ret_val; 1154 1155 /* set auto-master slave resolution settings */ 1156 if (hw->autoneg) { 1157 e1000_ms_type phy_ms_setting = hw->master_slave; 1158 1159 if (hw->ffe_config_state == e1000_ffe_config_active) 1160 hw->ffe_config_state = e1000_ffe_config_enabled; 1161 1162 if (hw->dsp_config_state == e1000_dsp_config_activated) 1163 hw->dsp_config_state = e1000_dsp_config_enabled; 1164 1165 /* when autonegotiation advertisement is only 1000Mbps then we 1166 * should disable SmartSpeed and enable Auto MasterSlave 1167 * resolution as hardware default. 1168 */ 1169 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) { 1170 /* Disable SmartSpeed */ 1171 ret_val = 1172 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 1173 &phy_data); 1174 if (ret_val) 1175 return ret_val; 1176 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1177 ret_val = 1178 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 1179 phy_data); 1180 if (ret_val) 1181 return ret_val; 1182 /* Set auto Master/Slave resolution process */ 1183 ret_val = 1184 e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); 1185 if (ret_val) 1186 return ret_val; 1187 phy_data &= ~CR_1000T_MS_ENABLE; 1188 ret_val = 1189 e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); 1190 if (ret_val) 1191 return ret_val; 1192 } 1193 1194 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); 1195 if (ret_val) 1196 return ret_val; 1197 1198 /* load defaults for future use */ 1199 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ? 1200 ((phy_data & CR_1000T_MS_VALUE) ? 1201 e1000_ms_force_master : 1202 e1000_ms_force_slave) : e1000_ms_auto; 1203 1204 switch (phy_ms_setting) { 1205 case e1000_ms_force_master: 1206 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 1207 break; 1208 case e1000_ms_force_slave: 1209 phy_data |= CR_1000T_MS_ENABLE; 1210 phy_data &= ~(CR_1000T_MS_VALUE); 1211 break; 1212 case e1000_ms_auto: 1213 phy_data &= ~CR_1000T_MS_ENABLE; 1214 default: 1215 break; 1216 } 1217 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); 1218 if (ret_val) 1219 return ret_val; 1220 } 1221 1222 return E1000_SUCCESS; 1223 } 1224 1225 /** 1226 * e1000_copper_link_mgp_setup - Copper link setup for e1000_phy_m88 series. 1227 * @hw: Struct containing variables accessed by shared code 1228 */ 1229 static s32 e1000_copper_link_mgp_setup(struct e1000_hw *hw) 1230 { 1231 s32 ret_val; 1232 u16 phy_data; 1233 1234 if (hw->phy_reset_disable) 1235 return E1000_SUCCESS; 1236 1237 /* Enable CRS on TX. This must be set for half-duplex operation. */ 1238 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1239 if (ret_val) 1240 return ret_val; 1241 1242 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 1243 1244 /* Options: 1245 * MDI/MDI-X = 0 (default) 1246 * 0 - Auto for all speeds 1247 * 1 - MDI mode 1248 * 2 - MDI-X mode 1249 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 1250 */ 1251 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1252 1253 switch (hw->mdix) { 1254 case 1: 1255 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 1256 break; 1257 case 2: 1258 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 1259 break; 1260 case 3: 1261 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 1262 break; 1263 case 0: 1264 default: 1265 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 1266 break; 1267 } 1268 1269 /* Options: 1270 * disable_polarity_correction = 0 (default) 1271 * Automatic Correction for Reversed Cable Polarity 1272 * 0 - Disabled 1273 * 1 - Enabled 1274 */ 1275 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 1276 if (hw->disable_polarity_correction == 1) 1277 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 1278 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1279 if (ret_val) 1280 return ret_val; 1281 1282 if (hw->phy_revision < M88E1011_I_REV_4) { 1283 /* Force TX_CLK in the Extended PHY Specific Control Register 1284 * to 25MHz clock. 1285 */ 1286 ret_val = 1287 e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 1288 &phy_data); 1289 if (ret_val) 1290 return ret_val; 1291 1292 phy_data |= M88E1000_EPSCR_TX_CLK_25; 1293 1294 if ((hw->phy_revision == E1000_REVISION_2) && 1295 (hw->phy_id == M88E1111_I_PHY_ID)) { 1296 /* Vidalia Phy, set the downshift counter to 5x */ 1297 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK); 1298 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; 1299 ret_val = e1000_write_phy_reg(hw, 1300 M88E1000_EXT_PHY_SPEC_CTRL, 1301 phy_data); 1302 if (ret_val) 1303 return ret_val; 1304 } else { 1305 /* Configure Master and Slave downshift values */ 1306 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 1307 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 1308 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 1309 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 1310 ret_val = e1000_write_phy_reg(hw, 1311 M88E1000_EXT_PHY_SPEC_CTRL, 1312 phy_data); 1313 if (ret_val) 1314 return ret_val; 1315 } 1316 } 1317 1318 /* SW Reset the PHY so all changes take effect */ 1319 ret_val = e1000_phy_reset(hw); 1320 if (ret_val) { 1321 e_dbg("Error Resetting the PHY\n"); 1322 return ret_val; 1323 } 1324 1325 return E1000_SUCCESS; 1326 } 1327 1328 /** 1329 * e1000_copper_link_autoneg - setup auto-neg 1330 * @hw: Struct containing variables accessed by shared code 1331 * 1332 * Setup auto-negotiation and flow control advertisements, 1333 * and then perform auto-negotiation. 1334 */ 1335 static s32 e1000_copper_link_autoneg(struct e1000_hw *hw) 1336 { 1337 s32 ret_val; 1338 u16 phy_data; 1339 1340 /* Perform some bounds checking on the hw->autoneg_advertised 1341 * parameter. If this variable is zero, then set it to the default. 1342 */ 1343 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT; 1344 1345 /* If autoneg_advertised is zero, we assume it was not defaulted 1346 * by the calling code so we set to advertise full capability. 1347 */ 1348 if (hw->autoneg_advertised == 0) 1349 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 1350 1351 /* IFE/RTL8201N PHY only supports 10/100 */ 1352 if (hw->phy_type == e1000_phy_8201) 1353 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL; 1354 1355 e_dbg("Reconfiguring auto-neg advertisement params\n"); 1356 ret_val = e1000_phy_setup_autoneg(hw); 1357 if (ret_val) { 1358 e_dbg("Error Setting up Auto-Negotiation\n"); 1359 return ret_val; 1360 } 1361 e_dbg("Restarting Auto-Neg\n"); 1362 1363 /* Restart auto-negotiation by setting the Auto Neg Enable bit and 1364 * the Auto Neg Restart bit in the PHY control register. 1365 */ 1366 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); 1367 if (ret_val) 1368 return ret_val; 1369 1370 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 1371 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); 1372 if (ret_val) 1373 return ret_val; 1374 1375 /* Does the user want to wait for Auto-Neg to complete here, or 1376 * check at a later time (for example, callback routine). 1377 */ 1378 if (hw->wait_autoneg_complete) { 1379 ret_val = e1000_wait_autoneg(hw); 1380 if (ret_val) { 1381 e_dbg 1382 ("Error while waiting for autoneg to complete\n"); 1383 return ret_val; 1384 } 1385 } 1386 1387 hw->get_link_status = true; 1388 1389 return E1000_SUCCESS; 1390 } 1391 1392 /** 1393 * e1000_copper_link_postconfig - post link setup 1394 * @hw: Struct containing variables accessed by shared code 1395 * 1396 * Config the MAC and the PHY after link is up. 1397 * 1) Set up the MAC to the current PHY speed/duplex 1398 * if we are on 82543. If we 1399 * are on newer silicon, we only need to configure 1400 * collision distance in the Transmit Control Register. 1401 * 2) Set up flow control on the MAC to that established with 1402 * the link partner. 1403 * 3) Config DSP to improve Gigabit link quality for some PHY revisions. 1404 */ 1405 static s32 e1000_copper_link_postconfig(struct e1000_hw *hw) 1406 { 1407 s32 ret_val; 1408 1409 if ((hw->mac_type >= e1000_82544) && (hw->mac_type != e1000_ce4100)) { 1410 e1000_config_collision_dist(hw); 1411 } else { 1412 ret_val = e1000_config_mac_to_phy(hw); 1413 if (ret_val) { 1414 e_dbg("Error configuring MAC to PHY settings\n"); 1415 return ret_val; 1416 } 1417 } 1418 ret_val = e1000_config_fc_after_link_up(hw); 1419 if (ret_val) { 1420 e_dbg("Error Configuring Flow Control\n"); 1421 return ret_val; 1422 } 1423 1424 /* Config DSP to improve Giga link quality */ 1425 if (hw->phy_type == e1000_phy_igp) { 1426 ret_val = e1000_config_dsp_after_link_change(hw, true); 1427 if (ret_val) { 1428 e_dbg("Error Configuring DSP after link up\n"); 1429 return ret_val; 1430 } 1431 } 1432 1433 return E1000_SUCCESS; 1434 } 1435 1436 /** 1437 * e1000_setup_copper_link - phy/speed/duplex setting 1438 * @hw: Struct containing variables accessed by shared code 1439 * 1440 * Detects which PHY is present and sets up the speed and duplex 1441 */ 1442 static s32 e1000_setup_copper_link(struct e1000_hw *hw) 1443 { 1444 s32 ret_val; 1445 u16 i; 1446 u16 phy_data; 1447 1448 /* Check if it is a valid PHY and set PHY mode if necessary. */ 1449 ret_val = e1000_copper_link_preconfig(hw); 1450 if (ret_val) 1451 return ret_val; 1452 1453 if (hw->phy_type == e1000_phy_igp) { 1454 ret_val = e1000_copper_link_igp_setup(hw); 1455 if (ret_val) 1456 return ret_val; 1457 } else if (hw->phy_type == e1000_phy_m88) { 1458 ret_val = e1000_copper_link_mgp_setup(hw); 1459 if (ret_val) 1460 return ret_val; 1461 } else { 1462 ret_val = gbe_dhg_phy_setup(hw); 1463 if (ret_val) { 1464 e_dbg("gbe_dhg_phy_setup failed!\n"); 1465 return ret_val; 1466 } 1467 } 1468 1469 if (hw->autoneg) { 1470 /* Setup autoneg and flow control advertisement 1471 * and perform autonegotiation 1472 */ 1473 ret_val = e1000_copper_link_autoneg(hw); 1474 if (ret_val) 1475 return ret_val; 1476 } else { 1477 /* PHY will be set to 10H, 10F, 100H,or 100F 1478 * depending on value from forced_speed_duplex. 1479 */ 1480 e_dbg("Forcing speed and duplex\n"); 1481 ret_val = e1000_phy_force_speed_duplex(hw); 1482 if (ret_val) { 1483 e_dbg("Error Forcing Speed and Duplex\n"); 1484 return ret_val; 1485 } 1486 } 1487 1488 /* Check link status. Wait up to 100 microseconds for link to become 1489 * valid. 1490 */ 1491 for (i = 0; i < 10; i++) { 1492 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 1493 if (ret_val) 1494 return ret_val; 1495 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 1496 if (ret_val) 1497 return ret_val; 1498 1499 if (phy_data & MII_SR_LINK_STATUS) { 1500 /* Config the MAC and PHY after link is up */ 1501 ret_val = e1000_copper_link_postconfig(hw); 1502 if (ret_val) 1503 return ret_val; 1504 1505 e_dbg("Valid link established!!!\n"); 1506 return E1000_SUCCESS; 1507 } 1508 udelay(10); 1509 } 1510 1511 e_dbg("Unable to establish link!!!\n"); 1512 return E1000_SUCCESS; 1513 } 1514 1515 /** 1516 * e1000_phy_setup_autoneg - phy settings 1517 * @hw: Struct containing variables accessed by shared code 1518 * 1519 * Configures PHY autoneg and flow control advertisement settings 1520 */ 1521 s32 e1000_phy_setup_autoneg(struct e1000_hw *hw) 1522 { 1523 s32 ret_val; 1524 u16 mii_autoneg_adv_reg; 1525 u16 mii_1000t_ctrl_reg; 1526 1527 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 1528 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 1529 if (ret_val) 1530 return ret_val; 1531 1532 /* Read the MII 1000Base-T Control Register (Address 9). */ 1533 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg); 1534 if (ret_val) 1535 return ret_val; 1536 else if (hw->phy_type == e1000_phy_8201) 1537 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK; 1538 1539 /* Need to parse both autoneg_advertised and fc and set up 1540 * the appropriate PHY registers. First we will parse for 1541 * autoneg_advertised software override. Since we can advertise 1542 * a plethora of combinations, we need to check each bit 1543 * individually. 1544 */ 1545 1546 /* First we clear all the 10/100 mb speed bits in the Auto-Neg 1547 * Advertisement Register (Address 4) and the 1000 mb speed bits in 1548 * the 1000Base-T Control Register (Address 9). 1549 */ 1550 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK; 1551 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK; 1552 1553 e_dbg("autoneg_advertised %x\n", hw->autoneg_advertised); 1554 1555 /* Do we want to advertise 10 Mb Half Duplex? */ 1556 if (hw->autoneg_advertised & ADVERTISE_10_HALF) { 1557 e_dbg("Advertise 10mb Half duplex\n"); 1558 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 1559 } 1560 1561 /* Do we want to advertise 10 Mb Full Duplex? */ 1562 if (hw->autoneg_advertised & ADVERTISE_10_FULL) { 1563 e_dbg("Advertise 10mb Full duplex\n"); 1564 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 1565 } 1566 1567 /* Do we want to advertise 100 Mb Half Duplex? */ 1568 if (hw->autoneg_advertised & ADVERTISE_100_HALF) { 1569 e_dbg("Advertise 100mb Half duplex\n"); 1570 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 1571 } 1572 1573 /* Do we want to advertise 100 Mb Full Duplex? */ 1574 if (hw->autoneg_advertised & ADVERTISE_100_FULL) { 1575 e_dbg("Advertise 100mb Full duplex\n"); 1576 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 1577 } 1578 1579 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 1580 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) { 1581 e_dbg 1582 ("Advertise 1000mb Half duplex requested, request denied!\n"); 1583 } 1584 1585 /* Do we want to advertise 1000 Mb Full Duplex? */ 1586 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) { 1587 e_dbg("Advertise 1000mb Full duplex\n"); 1588 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 1589 } 1590 1591 /* Check for a software override of the flow control settings, and 1592 * setup the PHY advertisement registers accordingly. If 1593 * auto-negotiation is enabled, then software will have to set the 1594 * "PAUSE" bits to the correct value in the Auto-Negotiation 1595 * Advertisement Register (PHY_AUTONEG_ADV) and re-start 1596 * auto-negotiation. 1597 * 1598 * The possible values of the "fc" parameter are: 1599 * 0: Flow control is completely disabled 1600 * 1: Rx flow control is enabled (we can receive pause frames 1601 * but not send pause frames). 1602 * 2: Tx flow control is enabled (we can send pause frames 1603 * but we do not support receiving pause frames). 1604 * 3: Both Rx and TX flow control (symmetric) are enabled. 1605 * other: No software override. The flow control configuration 1606 * in the EEPROM is used. 1607 */ 1608 switch (hw->fc) { 1609 case E1000_FC_NONE: /* 0 */ 1610 /* Flow control (RX & TX) is completely disabled by a 1611 * software over-ride. 1612 */ 1613 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1614 break; 1615 case E1000_FC_RX_PAUSE: /* 1 */ 1616 /* RX Flow control is enabled, and TX Flow control is 1617 * disabled, by a software over-ride. 1618 */ 1619 /* Since there really isn't a way to advertise that we are 1620 * capable of RX Pause ONLY, we will advertise that we 1621 * support both symmetric and asymmetric RX PAUSE. Later 1622 * (in e1000_config_fc_after_link_up) we will disable the 1623 * hw's ability to send PAUSE frames. 1624 */ 1625 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1626 break; 1627 case E1000_FC_TX_PAUSE: /* 2 */ 1628 /* TX Flow control is enabled, and RX Flow control is 1629 * disabled, by a software over-ride. 1630 */ 1631 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 1632 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 1633 break; 1634 case E1000_FC_FULL: /* 3 */ 1635 /* Flow control (both RX and TX) is enabled by a software 1636 * over-ride. 1637 */ 1638 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1639 break; 1640 default: 1641 e_dbg("Flow control param set incorrectly\n"); 1642 return -E1000_ERR_CONFIG; 1643 } 1644 1645 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 1646 if (ret_val) 1647 return ret_val; 1648 1649 e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 1650 1651 if (hw->phy_type == e1000_phy_8201) { 1652 mii_1000t_ctrl_reg = 0; 1653 } else { 1654 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, 1655 mii_1000t_ctrl_reg); 1656 if (ret_val) 1657 return ret_val; 1658 } 1659 1660 return E1000_SUCCESS; 1661 } 1662 1663 /** 1664 * e1000_phy_force_speed_duplex - force link settings 1665 * @hw: Struct containing variables accessed by shared code 1666 * 1667 * Force PHY speed and duplex settings to hw->forced_speed_duplex 1668 */ 1669 static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw) 1670 { 1671 u32 ctrl; 1672 s32 ret_val; 1673 u16 mii_ctrl_reg; 1674 u16 mii_status_reg; 1675 u16 phy_data; 1676 u16 i; 1677 1678 /* Turn off Flow control if we are forcing speed and duplex. */ 1679 hw->fc = E1000_FC_NONE; 1680 1681 e_dbg("hw->fc = %d\n", hw->fc); 1682 1683 /* Read the Device Control Register. */ 1684 ctrl = er32(CTRL); 1685 1686 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */ 1687 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1688 ctrl &= ~(DEVICE_SPEED_MASK); 1689 1690 /* Clear the Auto Speed Detect Enable bit. */ 1691 ctrl &= ~E1000_CTRL_ASDE; 1692 1693 /* Read the MII Control Register. */ 1694 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg); 1695 if (ret_val) 1696 return ret_val; 1697 1698 /* We need to disable autoneg in order to force link and duplex. */ 1699 1700 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN; 1701 1702 /* Are we forcing Full or Half Duplex? */ 1703 if (hw->forced_speed_duplex == e1000_100_full || 1704 hw->forced_speed_duplex == e1000_10_full) { 1705 /* We want to force full duplex so we SET the full duplex bits 1706 * in the Device and MII Control Registers. 1707 */ 1708 ctrl |= E1000_CTRL_FD; 1709 mii_ctrl_reg |= MII_CR_FULL_DUPLEX; 1710 e_dbg("Full Duplex\n"); 1711 } else { 1712 /* We want to force half duplex so we CLEAR the full duplex bits 1713 * in the Device and MII Control Registers. 1714 */ 1715 ctrl &= ~E1000_CTRL_FD; 1716 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX; 1717 e_dbg("Half Duplex\n"); 1718 } 1719 1720 /* Are we forcing 100Mbps??? */ 1721 if (hw->forced_speed_duplex == e1000_100_full || 1722 hw->forced_speed_duplex == e1000_100_half) { 1723 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */ 1724 ctrl |= E1000_CTRL_SPD_100; 1725 mii_ctrl_reg |= MII_CR_SPEED_100; 1726 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); 1727 e_dbg("Forcing 100mb "); 1728 } else { 1729 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */ 1730 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 1731 mii_ctrl_reg |= MII_CR_SPEED_10; 1732 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); 1733 e_dbg("Forcing 10mb "); 1734 } 1735 1736 e1000_config_collision_dist(hw); 1737 1738 /* Write the configured values back to the Device Control Reg. */ 1739 ew32(CTRL, ctrl); 1740 1741 if (hw->phy_type == e1000_phy_m88) { 1742 ret_val = 1743 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1744 if (ret_val) 1745 return ret_val; 1746 1747 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires 1748 * MDI forced whenever speed are duplex are forced. 1749 */ 1750 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1751 ret_val = 1752 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1753 if (ret_val) 1754 return ret_val; 1755 1756 e_dbg("M88E1000 PSCR: %x\n", phy_data); 1757 1758 /* Need to reset the PHY or these changes will be ignored */ 1759 mii_ctrl_reg |= MII_CR_RESET; 1760 1761 /* Disable MDI-X support for 10/100 */ 1762 } else { 1763 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI 1764 * forced whenever speed or duplex are forced. 1765 */ 1766 ret_val = 1767 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 1768 if (ret_val) 1769 return ret_val; 1770 1771 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 1772 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 1773 1774 ret_val = 1775 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 1776 if (ret_val) 1777 return ret_val; 1778 } 1779 1780 /* Write back the modified PHY MII control register. */ 1781 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg); 1782 if (ret_val) 1783 return ret_val; 1784 1785 udelay(1); 1786 1787 /* The wait_autoneg_complete flag may be a little misleading here. 1788 * Since we are forcing speed and duplex, Auto-Neg is not enabled. 1789 * But we do want to delay for a period while forcing only so we 1790 * don't generate false No Link messages. So we will wait here 1791 * only if the user has set wait_autoneg_complete to 1, which is 1792 * the default. 1793 */ 1794 if (hw->wait_autoneg_complete) { 1795 /* We will wait for autoneg to complete. */ 1796 e_dbg("Waiting for forced speed/duplex link.\n"); 1797 mii_status_reg = 0; 1798 1799 /* Wait for autoneg to complete or 4.5 seconds to expire */ 1800 for (i = PHY_FORCE_TIME; i > 0; i--) { 1801 /* Read the MII Status Register and wait for Auto-Neg 1802 * Complete bit to be set. 1803 */ 1804 ret_val = 1805 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 1806 if (ret_val) 1807 return ret_val; 1808 1809 ret_val = 1810 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 1811 if (ret_val) 1812 return ret_val; 1813 1814 if (mii_status_reg & MII_SR_LINK_STATUS) 1815 break; 1816 msleep(100); 1817 } 1818 if ((i == 0) && (hw->phy_type == e1000_phy_m88)) { 1819 /* We didn't get link. Reset the DSP and wait again 1820 * for link. 1821 */ 1822 ret_val = e1000_phy_reset_dsp(hw); 1823 if (ret_val) { 1824 e_dbg("Error Resetting PHY DSP\n"); 1825 return ret_val; 1826 } 1827 } 1828 /* This loop will early-out if the link condition has been 1829 * met 1830 */ 1831 for (i = PHY_FORCE_TIME; i > 0; i--) { 1832 if (mii_status_reg & MII_SR_LINK_STATUS) 1833 break; 1834 msleep(100); 1835 /* Read the MII Status Register and wait for Auto-Neg 1836 * Complete bit to be set. 1837 */ 1838 ret_val = 1839 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 1840 if (ret_val) 1841 return ret_val; 1842 1843 ret_val = 1844 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 1845 if (ret_val) 1846 return ret_val; 1847 } 1848 } 1849 1850 if (hw->phy_type == e1000_phy_m88) { 1851 /* Because we reset the PHY above, we need to re-force TX_CLK in 1852 * the Extended PHY Specific Control Register to 25MHz clock. 1853 * This value defaults back to a 2.5MHz clock when the PHY is 1854 * reset. 1855 */ 1856 ret_val = 1857 e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 1858 &phy_data); 1859 if (ret_val) 1860 return ret_val; 1861 1862 phy_data |= M88E1000_EPSCR_TX_CLK_25; 1863 ret_val = 1864 e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 1865 phy_data); 1866 if (ret_val) 1867 return ret_val; 1868 1869 /* In addition, because of the s/w reset above, we need to 1870 * enable CRS on Tx. This must be set for both full and half 1871 * duplex operation. 1872 */ 1873 ret_val = 1874 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1875 if (ret_val) 1876 return ret_val; 1877 1878 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 1879 ret_val = 1880 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1881 if (ret_val) 1882 return ret_val; 1883 1884 if ((hw->mac_type == e1000_82544 || 1885 hw->mac_type == e1000_82543) && 1886 (!hw->autoneg) && 1887 (hw->forced_speed_duplex == e1000_10_full || 1888 hw->forced_speed_duplex == e1000_10_half)) { 1889 ret_val = e1000_polarity_reversal_workaround(hw); 1890 if (ret_val) 1891 return ret_val; 1892 } 1893 } 1894 return E1000_SUCCESS; 1895 } 1896 1897 /** 1898 * e1000_config_collision_dist - set collision distance register 1899 * @hw: Struct containing variables accessed by shared code 1900 * 1901 * Sets the collision distance in the Transmit Control register. 1902 * Link should have been established previously. Reads the speed and duplex 1903 * information from the Device Status register. 1904 */ 1905 void e1000_config_collision_dist(struct e1000_hw *hw) 1906 { 1907 u32 tctl, coll_dist; 1908 1909 if (hw->mac_type < e1000_82543) 1910 coll_dist = E1000_COLLISION_DISTANCE_82542; 1911 else 1912 coll_dist = E1000_COLLISION_DISTANCE; 1913 1914 tctl = er32(TCTL); 1915 1916 tctl &= ~E1000_TCTL_COLD; 1917 tctl |= coll_dist << E1000_COLD_SHIFT; 1918 1919 ew32(TCTL, tctl); 1920 E1000_WRITE_FLUSH(); 1921 } 1922 1923 /** 1924 * e1000_config_mac_to_phy - sync phy and mac settings 1925 * @hw: Struct containing variables accessed by shared code 1926 * @mii_reg: data to write to the MII control register 1927 * 1928 * Sets MAC speed and duplex settings to reflect the those in the PHY 1929 * The contents of the PHY register containing the needed information need to 1930 * be passed in. 1931 */ 1932 static s32 e1000_config_mac_to_phy(struct e1000_hw *hw) 1933 { 1934 u32 ctrl; 1935 s32 ret_val; 1936 u16 phy_data; 1937 1938 /* 82544 or newer MAC, Auto Speed Detection takes care of 1939 * MAC speed/duplex configuration. 1940 */ 1941 if ((hw->mac_type >= e1000_82544) && (hw->mac_type != e1000_ce4100)) 1942 return E1000_SUCCESS; 1943 1944 /* Read the Device Control Register and set the bits to Force Speed 1945 * and Duplex. 1946 */ 1947 ctrl = er32(CTRL); 1948 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1949 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); 1950 1951 switch (hw->phy_type) { 1952 case e1000_phy_8201: 1953 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); 1954 if (ret_val) 1955 return ret_val; 1956 1957 if (phy_data & RTL_PHY_CTRL_FD) 1958 ctrl |= E1000_CTRL_FD; 1959 else 1960 ctrl &= ~E1000_CTRL_FD; 1961 1962 if (phy_data & RTL_PHY_CTRL_SPD_100) 1963 ctrl |= E1000_CTRL_SPD_100; 1964 else 1965 ctrl |= E1000_CTRL_SPD_10; 1966 1967 e1000_config_collision_dist(hw); 1968 break; 1969 default: 1970 /* Set up duplex in the Device Control and Transmit Control 1971 * registers depending on negotiated values. 1972 */ 1973 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, 1974 &phy_data); 1975 if (ret_val) 1976 return ret_val; 1977 1978 if (phy_data & M88E1000_PSSR_DPLX) 1979 ctrl |= E1000_CTRL_FD; 1980 else 1981 ctrl &= ~E1000_CTRL_FD; 1982 1983 e1000_config_collision_dist(hw); 1984 1985 /* Set up speed in the Device Control register depending on 1986 * negotiated values. 1987 */ 1988 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) 1989 ctrl |= E1000_CTRL_SPD_1000; 1990 else if ((phy_data & M88E1000_PSSR_SPEED) == 1991 M88E1000_PSSR_100MBS) 1992 ctrl |= E1000_CTRL_SPD_100; 1993 } 1994 1995 /* Write the configured values back to the Device Control Reg. */ 1996 ew32(CTRL, ctrl); 1997 return E1000_SUCCESS; 1998 } 1999 2000 /** 2001 * e1000_force_mac_fc - force flow control settings 2002 * @hw: Struct containing variables accessed by shared code 2003 * 2004 * Forces the MAC's flow control settings. 2005 * Sets the TFCE and RFCE bits in the device control register to reflect 2006 * the adapter settings. TFCE and RFCE need to be explicitly set by 2007 * software when a Copper PHY is used because autonegotiation is managed 2008 * by the PHY rather than the MAC. Software must also configure these 2009 * bits when link is forced on a fiber connection. 2010 */ 2011 s32 e1000_force_mac_fc(struct e1000_hw *hw) 2012 { 2013 u32 ctrl; 2014 2015 /* Get the current configuration of the Device Control Register */ 2016 ctrl = er32(CTRL); 2017 2018 /* Because we didn't get link via the internal auto-negotiation 2019 * mechanism (we either forced link or we got link via PHY 2020 * auto-neg), we have to manually enable/disable transmit an 2021 * receive flow control. 2022 * 2023 * The "Case" statement below enables/disable flow control 2024 * according to the "hw->fc" parameter. 2025 * 2026 * The possible values of the "fc" parameter are: 2027 * 0: Flow control is completely disabled 2028 * 1: Rx flow control is enabled (we can receive pause 2029 * frames but not send pause frames). 2030 * 2: Tx flow control is enabled (we can send pause frames 2031 * frames but we do not receive pause frames). 2032 * 3: Both Rx and TX flow control (symmetric) is enabled. 2033 * other: No other values should be possible at this point. 2034 */ 2035 2036 switch (hw->fc) { 2037 case E1000_FC_NONE: 2038 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 2039 break; 2040 case E1000_FC_RX_PAUSE: 2041 ctrl &= (~E1000_CTRL_TFCE); 2042 ctrl |= E1000_CTRL_RFCE; 2043 break; 2044 case E1000_FC_TX_PAUSE: 2045 ctrl &= (~E1000_CTRL_RFCE); 2046 ctrl |= E1000_CTRL_TFCE; 2047 break; 2048 case E1000_FC_FULL: 2049 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 2050 break; 2051 default: 2052 e_dbg("Flow control param set incorrectly\n"); 2053 return -E1000_ERR_CONFIG; 2054 } 2055 2056 /* Disable TX Flow Control for 82542 (rev 2.0) */ 2057 if (hw->mac_type == e1000_82542_rev2_0) 2058 ctrl &= (~E1000_CTRL_TFCE); 2059 2060 ew32(CTRL, ctrl); 2061 return E1000_SUCCESS; 2062 } 2063 2064 /** 2065 * e1000_config_fc_after_link_up - configure flow control after autoneg 2066 * @hw: Struct containing variables accessed by shared code 2067 * 2068 * Configures flow control settings after link is established 2069 * Should be called immediately after a valid link has been established. 2070 * Forces MAC flow control settings if link was forced. When in MII/GMII mode 2071 * and autonegotiation is enabled, the MAC flow control settings will be set 2072 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE 2073 * and RFCE bits will be automatically set to the negotiated flow control mode. 2074 */ 2075 static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw) 2076 { 2077 s32 ret_val; 2078 u16 mii_status_reg; 2079 u16 mii_nway_adv_reg; 2080 u16 mii_nway_lp_ability_reg; 2081 u16 speed; 2082 u16 duplex; 2083 2084 /* Check for the case where we have fiber media and auto-neg failed 2085 * so we had to force link. In this case, we need to force the 2086 * configuration of the MAC to match the "fc" parameter. 2087 */ 2088 if (((hw->media_type == e1000_media_type_fiber) && 2089 (hw->autoneg_failed)) || 2090 ((hw->media_type == e1000_media_type_internal_serdes) && 2091 (hw->autoneg_failed)) || 2092 ((hw->media_type == e1000_media_type_copper) && 2093 (!hw->autoneg))) { 2094 ret_val = e1000_force_mac_fc(hw); 2095 if (ret_val) { 2096 e_dbg("Error forcing flow control settings\n"); 2097 return ret_val; 2098 } 2099 } 2100 2101 /* Check for the case where we have copper media and auto-neg is 2102 * enabled. In this case, we need to check and see if Auto-Neg 2103 * has completed, and if so, how the PHY and link partner has 2104 * flow control configured. 2105 */ 2106 if ((hw->media_type == e1000_media_type_copper) && hw->autoneg) { 2107 /* Read the MII Status Register and check to see if AutoNeg 2108 * has completed. We read this twice because this reg has 2109 * some "sticky" (latched) bits. 2110 */ 2111 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 2112 if (ret_val) 2113 return ret_val; 2114 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 2115 if (ret_val) 2116 return ret_val; 2117 2118 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) { 2119 /* The AutoNeg process has completed, so we now need to 2120 * read both the Auto Negotiation Advertisement Register 2121 * (Address 4) and the Auto_Negotiation Base Page 2122 * Ability Register (Address 5) to determine how flow 2123 * control was negotiated. 2124 */ 2125 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, 2126 &mii_nway_adv_reg); 2127 if (ret_val) 2128 return ret_val; 2129 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, 2130 &mii_nway_lp_ability_reg); 2131 if (ret_val) 2132 return ret_val; 2133 2134 /* Two bits in the Auto Negotiation Advertisement 2135 * Register (Address 4) and two bits in the Auto 2136 * Negotiation Base Page Ability Register (Address 5) 2137 * determine flow control for both the PHY and the link 2138 * partner. The following table, taken out of the IEEE 2139 * 802.3ab/D6.0 dated March 25, 1999, describes these 2140 * PAUSE resolution bits and how flow control is 2141 * determined based upon these settings. 2142 * NOTE: DC = Don't Care 2143 * 2144 * LOCAL DEVICE | LINK PARTNER 2145 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 2146 *-------|---------|-------|---------|------------------ 2147 * 0 | 0 | DC | DC | E1000_FC_NONE 2148 * 0 | 1 | 0 | DC | E1000_FC_NONE 2149 * 0 | 1 | 1 | 0 | E1000_FC_NONE 2150 * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE 2151 * 1 | 0 | 0 | DC | E1000_FC_NONE 2152 * 1 | DC | 1 | DC | E1000_FC_FULL 2153 * 1 | 1 | 0 | 0 | E1000_FC_NONE 2154 * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE 2155 * 2156 */ 2157 /* Are both PAUSE bits set to 1? If so, this implies 2158 * Symmetric Flow Control is enabled at both ends. The 2159 * ASM_DIR bits are irrelevant per the spec. 2160 * 2161 * For Symmetric Flow Control: 2162 * 2163 * LOCAL DEVICE | LINK PARTNER 2164 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 2165 *-------|---------|-------|---------|------------------ 2166 * 1 | DC | 1 | DC | E1000_FC_FULL 2167 * 2168 */ 2169 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 2170 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 2171 /* Now we need to check if the user selected Rx 2172 * ONLY of pause frames. In this case, we had 2173 * to advertise FULL flow control because we 2174 * could not advertise Rx ONLY. Hence, we must 2175 * now check to see if we need to turn OFF the 2176 * TRANSMISSION of PAUSE frames. 2177 */ 2178 if (hw->original_fc == E1000_FC_FULL) { 2179 hw->fc = E1000_FC_FULL; 2180 e_dbg("Flow Control = FULL.\n"); 2181 } else { 2182 hw->fc = E1000_FC_RX_PAUSE; 2183 e_dbg 2184 ("Flow Control = RX PAUSE frames only.\n"); 2185 } 2186 } 2187 /* For receiving PAUSE frames ONLY. 2188 * 2189 * LOCAL DEVICE | LINK PARTNER 2190 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 2191 *-------|---------|-------|---------|------------------ 2192 * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE 2193 * 2194 */ 2195 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 2196 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 2197 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 2198 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 2199 hw->fc = E1000_FC_TX_PAUSE; 2200 e_dbg 2201 ("Flow Control = TX PAUSE frames only.\n"); 2202 } 2203 /* For transmitting PAUSE frames ONLY. 2204 * 2205 * LOCAL DEVICE | LINK PARTNER 2206 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 2207 *-------|---------|-------|---------|------------------ 2208 * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE 2209 * 2210 */ 2211 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 2212 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 2213 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 2214 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 2215 hw->fc = E1000_FC_RX_PAUSE; 2216 e_dbg 2217 ("Flow Control = RX PAUSE frames only.\n"); 2218 } 2219 /* Per the IEEE spec, at this point flow control should 2220 * be disabled. However, we want to consider that we 2221 * could be connected to a legacy switch that doesn't 2222 * advertise desired flow control, but can be forced on 2223 * the link partner. So if we advertised no flow 2224 * control, that is what we will resolve to. If we 2225 * advertised some kind of receive capability (Rx Pause 2226 * Only or Full Flow Control) and the link partner 2227 * advertised none, we will configure ourselves to 2228 * enable Rx Flow Control only. We can do this safely 2229 * for two reasons: If the link partner really 2230 * didn't want flow control enabled, and we enable Rx, 2231 * no harm done since we won't be receiving any PAUSE 2232 * frames anyway. If the intent on the link partner was 2233 * to have flow control enabled, then by us enabling Rx 2234 * only, we can at least receive pause frames and 2235 * process them. This is a good idea because in most 2236 * cases, since we are predominantly a server NIC, more 2237 * times than not we will be asked to delay transmission 2238 * of packets than asking our link partner to pause 2239 * transmission of frames. 2240 */ 2241 else if ((hw->original_fc == E1000_FC_NONE || 2242 hw->original_fc == E1000_FC_TX_PAUSE) || 2243 hw->fc_strict_ieee) { 2244 hw->fc = E1000_FC_NONE; 2245 e_dbg("Flow Control = NONE.\n"); 2246 } else { 2247 hw->fc = E1000_FC_RX_PAUSE; 2248 e_dbg 2249 ("Flow Control = RX PAUSE frames only.\n"); 2250 } 2251 2252 /* Now we need to do one last check... If we auto- 2253 * negotiated to HALF DUPLEX, flow control should not be 2254 * enabled per IEEE 802.3 spec. 2255 */ 2256 ret_val = 2257 e1000_get_speed_and_duplex(hw, &speed, &duplex); 2258 if (ret_val) { 2259 e_dbg 2260 ("Error getting link speed and duplex\n"); 2261 return ret_val; 2262 } 2263 2264 if (duplex == HALF_DUPLEX) 2265 hw->fc = E1000_FC_NONE; 2266 2267 /* Now we call a subroutine to actually force the MAC 2268 * controller to use the correct flow control settings. 2269 */ 2270 ret_val = e1000_force_mac_fc(hw); 2271 if (ret_val) { 2272 e_dbg 2273 ("Error forcing flow control settings\n"); 2274 return ret_val; 2275 } 2276 } else { 2277 e_dbg 2278 ("Copper PHY and Auto Neg has not completed.\n"); 2279 } 2280 } 2281 return E1000_SUCCESS; 2282 } 2283 2284 /** 2285 * e1000_check_for_serdes_link_generic - Check for link (Serdes) 2286 * @hw: pointer to the HW structure 2287 * 2288 * Checks for link up on the hardware. If link is not up and we have 2289 * a signal, then we need to force link up. 2290 */ 2291 static s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw) 2292 { 2293 u32 rxcw; 2294 u32 ctrl; 2295 u32 status; 2296 s32 ret_val = E1000_SUCCESS; 2297 2298 ctrl = er32(CTRL); 2299 status = er32(STATUS); 2300 rxcw = er32(RXCW); 2301 2302 /* If we don't have link (auto-negotiation failed or link partner 2303 * cannot auto-negotiate), and our link partner is not trying to 2304 * auto-negotiate with us (we are receiving idles or data), 2305 * we need to force link up. We also need to give auto-negotiation 2306 * time to complete. 2307 */ 2308 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 2309 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) { 2310 if (hw->autoneg_failed == 0) { 2311 hw->autoneg_failed = 1; 2312 goto out; 2313 } 2314 e_dbg("NOT RXing /C/, disable AutoNeg and force link.\n"); 2315 2316 /* Disable auto-negotiation in the TXCW register */ 2317 ew32(TXCW, (hw->txcw & ~E1000_TXCW_ANE)); 2318 2319 /* Force link-up and also force full-duplex. */ 2320 ctrl = er32(CTRL); 2321 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 2322 ew32(CTRL, ctrl); 2323 2324 /* Configure Flow Control after forcing link up. */ 2325 ret_val = e1000_config_fc_after_link_up(hw); 2326 if (ret_val) { 2327 e_dbg("Error configuring flow control\n"); 2328 goto out; 2329 } 2330 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 2331 /* If we are forcing link and we are receiving /C/ ordered 2332 * sets, re-enable auto-negotiation in the TXCW register 2333 * and disable forced link in the Device Control register 2334 * in an attempt to auto-negotiate with our link partner. 2335 */ 2336 e_dbg("RXing /C/, enable AutoNeg and stop forcing link.\n"); 2337 ew32(TXCW, hw->txcw); 2338 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU)); 2339 2340 hw->serdes_has_link = true; 2341 } else if (!(E1000_TXCW_ANE & er32(TXCW))) { 2342 /* If we force link for non-auto-negotiation switch, check 2343 * link status based on MAC synchronization for internal 2344 * serdes media type. 2345 */ 2346 /* SYNCH bit and IV bit are sticky. */ 2347 udelay(10); 2348 rxcw = er32(RXCW); 2349 if (rxcw & E1000_RXCW_SYNCH) { 2350 if (!(rxcw & E1000_RXCW_IV)) { 2351 hw->serdes_has_link = true; 2352 e_dbg("SERDES: Link up - forced.\n"); 2353 } 2354 } else { 2355 hw->serdes_has_link = false; 2356 e_dbg("SERDES: Link down - force failed.\n"); 2357 } 2358 } 2359 2360 if (E1000_TXCW_ANE & er32(TXCW)) { 2361 status = er32(STATUS); 2362 if (status & E1000_STATUS_LU) { 2363 /* SYNCH bit and IV bit are sticky, so reread rxcw. */ 2364 udelay(10); 2365 rxcw = er32(RXCW); 2366 if (rxcw & E1000_RXCW_SYNCH) { 2367 if (!(rxcw & E1000_RXCW_IV)) { 2368 hw->serdes_has_link = true; 2369 e_dbg("SERDES: Link up - autoneg " 2370 "completed successfully.\n"); 2371 } else { 2372 hw->serdes_has_link = false; 2373 e_dbg("SERDES: Link down - invalid" 2374 "codewords detected in autoneg.\n"); 2375 } 2376 } else { 2377 hw->serdes_has_link = false; 2378 e_dbg("SERDES: Link down - no sync.\n"); 2379 } 2380 } else { 2381 hw->serdes_has_link = false; 2382 e_dbg("SERDES: Link down - autoneg failed\n"); 2383 } 2384 } 2385 2386 out: 2387 return ret_val; 2388 } 2389 2390 /** 2391 * e1000_check_for_link 2392 * @hw: Struct containing variables accessed by shared code 2393 * 2394 * Checks to see if the link status of the hardware has changed. 2395 * Called by any function that needs to check the link status of the adapter. 2396 */ 2397 s32 e1000_check_for_link(struct e1000_hw *hw) 2398 { 2399 u32 rxcw = 0; 2400 u32 ctrl; 2401 u32 status; 2402 u32 rctl; 2403 u32 icr; 2404 u32 signal = 0; 2405 s32 ret_val; 2406 u16 phy_data; 2407 2408 ctrl = er32(CTRL); 2409 status = er32(STATUS); 2410 2411 /* On adapters with a MAC newer than 82544, SW Definable pin 1 will be 2412 * set when the optics detect a signal. On older adapters, it will be 2413 * cleared when there is a signal. This applies to fiber media only. 2414 */ 2415 if ((hw->media_type == e1000_media_type_fiber) || 2416 (hw->media_type == e1000_media_type_internal_serdes)) { 2417 rxcw = er32(RXCW); 2418 2419 if (hw->media_type == e1000_media_type_fiber) { 2420 signal = 2421 (hw->mac_type > 2422 e1000_82544) ? E1000_CTRL_SWDPIN1 : 0; 2423 if (status & E1000_STATUS_LU) 2424 hw->get_link_status = false; 2425 } 2426 } 2427 2428 /* If we have a copper PHY then we only want to go out to the PHY 2429 * registers to see if Auto-Neg has completed and/or if our link 2430 * status has changed. The get_link_status flag will be set if we 2431 * receive a Link Status Change interrupt or we have Rx Sequence 2432 * Errors. 2433 */ 2434 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) { 2435 /* First we want to see if the MII Status Register reports 2436 * link. If so, then we want to get the current speed/duplex 2437 * of the PHY. 2438 * Read the register twice since the link bit is sticky. 2439 */ 2440 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 2441 if (ret_val) 2442 return ret_val; 2443 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 2444 if (ret_val) 2445 return ret_val; 2446 2447 if (phy_data & MII_SR_LINK_STATUS) { 2448 hw->get_link_status = false; 2449 /* Check if there was DownShift, must be checked 2450 * immediately after link-up 2451 */ 2452 e1000_check_downshift(hw); 2453 2454 /* If we are on 82544 or 82543 silicon and speed/duplex 2455 * are forced to 10H or 10F, then we will implement the 2456 * polarity reversal workaround. We disable interrupts 2457 * first, and upon returning, place the devices 2458 * interrupt state to its previous value except for the 2459 * link status change interrupt which will 2460 * happen due to the execution of this workaround. 2461 */ 2462 2463 if ((hw->mac_type == e1000_82544 || 2464 hw->mac_type == e1000_82543) && 2465 (!hw->autoneg) && 2466 (hw->forced_speed_duplex == e1000_10_full || 2467 hw->forced_speed_duplex == e1000_10_half)) { 2468 ew32(IMC, 0xffffffff); 2469 ret_val = 2470 e1000_polarity_reversal_workaround(hw); 2471 icr = er32(ICR); 2472 ew32(ICS, (icr & ~E1000_ICS_LSC)); 2473 ew32(IMS, IMS_ENABLE_MASK); 2474 } 2475 2476 } else { 2477 /* No link detected */ 2478 e1000_config_dsp_after_link_change(hw, false); 2479 return 0; 2480 } 2481 2482 /* If we are forcing speed/duplex, then we simply return since 2483 * we have already determined whether we have link or not. 2484 */ 2485 if (!hw->autoneg) 2486 return -E1000_ERR_CONFIG; 2487 2488 /* optimize the dsp settings for the igp phy */ 2489 e1000_config_dsp_after_link_change(hw, true); 2490 2491 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we 2492 * have Si on board that is 82544 or newer, Auto 2493 * Speed Detection takes care of MAC speed/duplex 2494 * configuration. So we only need to configure Collision 2495 * Distance in the MAC. Otherwise, we need to force 2496 * speed/duplex on the MAC to the current PHY speed/duplex 2497 * settings. 2498 */ 2499 if ((hw->mac_type >= e1000_82544) && 2500 (hw->mac_type != e1000_ce4100)) 2501 e1000_config_collision_dist(hw); 2502 else { 2503 ret_val = e1000_config_mac_to_phy(hw); 2504 if (ret_val) { 2505 e_dbg 2506 ("Error configuring MAC to PHY settings\n"); 2507 return ret_val; 2508 } 2509 } 2510 2511 /* Configure Flow Control now that Auto-Neg has completed. 2512 * First, we need to restore the desired flow control settings 2513 * because we may have had to re-autoneg with a different link 2514 * partner. 2515 */ 2516 ret_val = e1000_config_fc_after_link_up(hw); 2517 if (ret_val) { 2518 e_dbg("Error configuring flow control\n"); 2519 return ret_val; 2520 } 2521 2522 /* At this point we know that we are on copper and we have 2523 * auto-negotiated link. These are conditions for checking the 2524 * link partner capability register. We use the link speed to 2525 * determine if TBI compatibility needs to be turned on or off. 2526 * If the link is not at gigabit speed, then TBI compatibility 2527 * is not needed. If we are at gigabit speed, we turn on TBI 2528 * compatibility. 2529 */ 2530 if (hw->tbi_compatibility_en) { 2531 u16 speed, duplex; 2532 2533 ret_val = 2534 e1000_get_speed_and_duplex(hw, &speed, &duplex); 2535 2536 if (ret_val) { 2537 e_dbg 2538 ("Error getting link speed and duplex\n"); 2539 return ret_val; 2540 } 2541 if (speed != SPEED_1000) { 2542 /* If link speed is not set to gigabit speed, we 2543 * do not need to enable TBI compatibility. 2544 */ 2545 if (hw->tbi_compatibility_on) { 2546 /* If we previously were in the mode, 2547 * turn it off. 2548 */ 2549 rctl = er32(RCTL); 2550 rctl &= ~E1000_RCTL_SBP; 2551 ew32(RCTL, rctl); 2552 hw->tbi_compatibility_on = false; 2553 } 2554 } else { 2555 /* If TBI compatibility is was previously off, 2556 * turn it on. For compatibility with a TBI link 2557 * partner, we will store bad packets. Some 2558 * frames have an additional byte on the end and 2559 * will look like CRC errors to to the hardware. 2560 */ 2561 if (!hw->tbi_compatibility_on) { 2562 hw->tbi_compatibility_on = true; 2563 rctl = er32(RCTL); 2564 rctl |= E1000_RCTL_SBP; 2565 ew32(RCTL, rctl); 2566 } 2567 } 2568 } 2569 } 2570 2571 if ((hw->media_type == e1000_media_type_fiber) || 2572 (hw->media_type == e1000_media_type_internal_serdes)) 2573 e1000_check_for_serdes_link_generic(hw); 2574 2575 return E1000_SUCCESS; 2576 } 2577 2578 /** 2579 * e1000_get_speed_and_duplex 2580 * @hw: Struct containing variables accessed by shared code 2581 * @speed: Speed of the connection 2582 * @duplex: Duplex setting of the connection 2583 * 2584 * Detects the current speed and duplex settings of the hardware. 2585 */ 2586 s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed, u16 *duplex) 2587 { 2588 u32 status; 2589 s32 ret_val; 2590 u16 phy_data; 2591 2592 if (hw->mac_type >= e1000_82543) { 2593 status = er32(STATUS); 2594 if (status & E1000_STATUS_SPEED_1000) { 2595 *speed = SPEED_1000; 2596 e_dbg("1000 Mbs, "); 2597 } else if (status & E1000_STATUS_SPEED_100) { 2598 *speed = SPEED_100; 2599 e_dbg("100 Mbs, "); 2600 } else { 2601 *speed = SPEED_10; 2602 e_dbg("10 Mbs, "); 2603 } 2604 2605 if (status & E1000_STATUS_FD) { 2606 *duplex = FULL_DUPLEX; 2607 e_dbg("Full Duplex\n"); 2608 } else { 2609 *duplex = HALF_DUPLEX; 2610 e_dbg(" Half Duplex\n"); 2611 } 2612 } else { 2613 e_dbg("1000 Mbs, Full Duplex\n"); 2614 *speed = SPEED_1000; 2615 *duplex = FULL_DUPLEX; 2616 } 2617 2618 /* IGP01 PHY may advertise full duplex operation after speed downgrade 2619 * even if it is operating at half duplex. Here we set the duplex 2620 * settings to match the duplex in the link partner's capabilities. 2621 */ 2622 if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) { 2623 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data); 2624 if (ret_val) 2625 return ret_val; 2626 2627 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS)) 2628 *duplex = HALF_DUPLEX; 2629 else { 2630 ret_val = 2631 e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data); 2632 if (ret_val) 2633 return ret_val; 2634 if ((*speed == SPEED_100 && 2635 !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) || 2636 (*speed == SPEED_10 && 2637 !(phy_data & NWAY_LPAR_10T_FD_CAPS))) 2638 *duplex = HALF_DUPLEX; 2639 } 2640 } 2641 2642 return E1000_SUCCESS; 2643 } 2644 2645 /** 2646 * e1000_wait_autoneg 2647 * @hw: Struct containing variables accessed by shared code 2648 * 2649 * Blocks until autoneg completes or times out (~4.5 seconds) 2650 */ 2651 static s32 e1000_wait_autoneg(struct e1000_hw *hw) 2652 { 2653 s32 ret_val; 2654 u16 i; 2655 u16 phy_data; 2656 2657 e_dbg("Waiting for Auto-Neg to complete.\n"); 2658 2659 /* We will wait for autoneg to complete or 4.5 seconds to expire. */ 2660 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) { 2661 /* Read the MII Status Register and wait for Auto-Neg 2662 * Complete bit to be set. 2663 */ 2664 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 2665 if (ret_val) 2666 return ret_val; 2667 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 2668 if (ret_val) 2669 return ret_val; 2670 if (phy_data & MII_SR_AUTONEG_COMPLETE) 2671 return E1000_SUCCESS; 2672 2673 msleep(100); 2674 } 2675 return E1000_SUCCESS; 2676 } 2677 2678 /** 2679 * e1000_raise_mdi_clk - Raises the Management Data Clock 2680 * @hw: Struct containing variables accessed by shared code 2681 * @ctrl: Device control register's current value 2682 */ 2683 static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl) 2684 { 2685 /* Raise the clock input to the Management Data Clock (by setting the 2686 * MDC bit), and then delay 10 microseconds. 2687 */ 2688 ew32(CTRL, (*ctrl | E1000_CTRL_MDC)); 2689 E1000_WRITE_FLUSH(); 2690 udelay(10); 2691 } 2692 2693 /** 2694 * e1000_lower_mdi_clk - Lowers the Management Data Clock 2695 * @hw: Struct containing variables accessed by shared code 2696 * @ctrl: Device control register's current value 2697 */ 2698 static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl) 2699 { 2700 /* Lower the clock input to the Management Data Clock (by clearing the 2701 * MDC bit), and then delay 10 microseconds. 2702 */ 2703 ew32(CTRL, (*ctrl & ~E1000_CTRL_MDC)); 2704 E1000_WRITE_FLUSH(); 2705 udelay(10); 2706 } 2707 2708 /** 2709 * e1000_shift_out_mdi_bits - Shifts data bits out to the PHY 2710 * @hw: Struct containing variables accessed by shared code 2711 * @data: Data to send out to the PHY 2712 * @count: Number of bits to shift out 2713 * 2714 * Bits are shifted out in MSB to LSB order. 2715 */ 2716 static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count) 2717 { 2718 u32 ctrl; 2719 u32 mask; 2720 2721 /* We need to shift "count" number of bits out to the PHY. So, the value 2722 * in the "data" parameter will be shifted out to the PHY one bit at a 2723 * time. In order to do this, "data" must be broken down into bits. 2724 */ 2725 mask = 0x01; 2726 mask <<= (count - 1); 2727 2728 ctrl = er32(CTRL); 2729 2730 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ 2731 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); 2732 2733 while (mask) { 2734 /* A "1" is shifted out to the PHY by setting the MDIO bit to 2735 * "1" and then raising and lowering the Management Data Clock. 2736 * A "0" is shifted out to the PHY by setting the MDIO bit to 2737 * "0" and then raising and lowering the clock. 2738 */ 2739 if (data & mask) 2740 ctrl |= E1000_CTRL_MDIO; 2741 else 2742 ctrl &= ~E1000_CTRL_MDIO; 2743 2744 ew32(CTRL, ctrl); 2745 E1000_WRITE_FLUSH(); 2746 2747 udelay(10); 2748 2749 e1000_raise_mdi_clk(hw, &ctrl); 2750 e1000_lower_mdi_clk(hw, &ctrl); 2751 2752 mask = mask >> 1; 2753 } 2754 } 2755 2756 /** 2757 * e1000_shift_in_mdi_bits - Shifts data bits in from the PHY 2758 * @hw: Struct containing variables accessed by shared code 2759 * 2760 * Bits are shifted in in MSB to LSB order. 2761 */ 2762 static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw) 2763 { 2764 u32 ctrl; 2765 u16 data = 0; 2766 u8 i; 2767 2768 /* In order to read a register from the PHY, we need to shift in a total 2769 * of 18 bits from the PHY. The first two bit (turnaround) times are 2770 * used to avoid contention on the MDIO pin when a read operation is 2771 * performed. These two bits are ignored by us and thrown away. Bits are 2772 * "shifted in" by raising the input to the Management Data Clock 2773 * (setting the MDC bit), and then reading the value of the MDIO bit. 2774 */ 2775 ctrl = er32(CTRL); 2776 2777 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as 2778 * input. 2779 */ 2780 ctrl &= ~E1000_CTRL_MDIO_DIR; 2781 ctrl &= ~E1000_CTRL_MDIO; 2782 2783 ew32(CTRL, ctrl); 2784 E1000_WRITE_FLUSH(); 2785 2786 /* Raise and Lower the clock before reading in the data. This accounts 2787 * for the turnaround bits. The first clock occurred when we clocked out 2788 * the last bit of the Register Address. 2789 */ 2790 e1000_raise_mdi_clk(hw, &ctrl); 2791 e1000_lower_mdi_clk(hw, &ctrl); 2792 2793 for (data = 0, i = 0; i < 16; i++) { 2794 data = data << 1; 2795 e1000_raise_mdi_clk(hw, &ctrl); 2796 ctrl = er32(CTRL); 2797 /* Check to see if we shifted in a "1". */ 2798 if (ctrl & E1000_CTRL_MDIO) 2799 data |= 1; 2800 e1000_lower_mdi_clk(hw, &ctrl); 2801 } 2802 2803 e1000_raise_mdi_clk(hw, &ctrl); 2804 e1000_lower_mdi_clk(hw, &ctrl); 2805 2806 return data; 2807 } 2808 2809 /** 2810 * e1000_read_phy_reg - read a phy register 2811 * @hw: Struct containing variables accessed by shared code 2812 * @reg_addr: address of the PHY register to read 2813 * @phy_data: pointer to the value on the PHY register 2814 * 2815 * Reads the value from a PHY register, if the value is on a specific non zero 2816 * page, sets the page first. 2817 */ 2818 s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 *phy_data) 2819 { 2820 u32 ret_val; 2821 unsigned long flags; 2822 2823 spin_lock_irqsave(&e1000_phy_lock, flags); 2824 2825 if ((hw->phy_type == e1000_phy_igp) && 2826 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { 2827 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 2828 (u16) reg_addr); 2829 if (ret_val) 2830 goto out; 2831 } 2832 2833 ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, 2834 phy_data); 2835 out: 2836 spin_unlock_irqrestore(&e1000_phy_lock, flags); 2837 2838 return ret_val; 2839 } 2840 2841 static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr, 2842 u16 *phy_data) 2843 { 2844 u32 i; 2845 u32 mdic = 0; 2846 const u32 phy_addr = (hw->mac_type == e1000_ce4100) ? hw->phy_addr : 1; 2847 2848 if (reg_addr > MAX_PHY_REG_ADDRESS) { 2849 e_dbg("PHY Address %d is out of range\n", reg_addr); 2850 return -E1000_ERR_PARAM; 2851 } 2852 2853 if (hw->mac_type > e1000_82543) { 2854 /* Set up Op-code, Phy Address, and register address in the MDI 2855 * Control register. The MAC will take care of interfacing with 2856 * the PHY to retrieve the desired data. 2857 */ 2858 if (hw->mac_type == e1000_ce4100) { 2859 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) | 2860 (phy_addr << E1000_MDIC_PHY_SHIFT) | 2861 (INTEL_CE_GBE_MDIC_OP_READ) | 2862 (INTEL_CE_GBE_MDIC_GO)); 2863 2864 writel(mdic, E1000_MDIO_CMD); 2865 2866 /* Poll the ready bit to see if the MDI read 2867 * completed 2868 */ 2869 for (i = 0; i < 64; i++) { 2870 udelay(50); 2871 mdic = readl(E1000_MDIO_CMD); 2872 if (!(mdic & INTEL_CE_GBE_MDIC_GO)) 2873 break; 2874 } 2875 2876 if (mdic & INTEL_CE_GBE_MDIC_GO) { 2877 e_dbg("MDI Read did not complete\n"); 2878 return -E1000_ERR_PHY; 2879 } 2880 2881 mdic = readl(E1000_MDIO_STS); 2882 if (mdic & INTEL_CE_GBE_MDIC_READ_ERROR) { 2883 e_dbg("MDI Read Error\n"); 2884 return -E1000_ERR_PHY; 2885 } 2886 *phy_data = (u16)mdic; 2887 } else { 2888 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) | 2889 (phy_addr << E1000_MDIC_PHY_SHIFT) | 2890 (E1000_MDIC_OP_READ)); 2891 2892 ew32(MDIC, mdic); 2893 2894 /* Poll the ready bit to see if the MDI read 2895 * completed 2896 */ 2897 for (i = 0; i < 64; i++) { 2898 udelay(50); 2899 mdic = er32(MDIC); 2900 if (mdic & E1000_MDIC_READY) 2901 break; 2902 } 2903 if (!(mdic & E1000_MDIC_READY)) { 2904 e_dbg("MDI Read did not complete\n"); 2905 return -E1000_ERR_PHY; 2906 } 2907 if (mdic & E1000_MDIC_ERROR) { 2908 e_dbg("MDI Error\n"); 2909 return -E1000_ERR_PHY; 2910 } 2911 *phy_data = (u16)mdic; 2912 } 2913 } else { 2914 /* We must first send a preamble through the MDIO pin to signal 2915 * the beginning of an MII instruction. This is done by sending 2916 * 32 consecutive "1" bits. 2917 */ 2918 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 2919 2920 /* Now combine the next few fields that are required for a read 2921 * operation. We use this method instead of calling the 2922 * e1000_shift_out_mdi_bits routine five different times. The 2923 * format of a MII read instruction consists of a shift out of 2924 * 14 bits and is defined as follows: 2925 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr> 2926 * followed by a shift in of 18 bits. This first two bits 2927 * shifted in are TurnAround bits used to avoid contention on 2928 * the MDIO pin when a READ operation is performed. These two 2929 * bits are thrown away followed by a shift in of 16 bits which 2930 * contains the desired data. 2931 */ 2932 mdic = ((reg_addr) | (phy_addr << 5) | 2933 (PHY_OP_READ << 10) | (PHY_SOF << 12)); 2934 2935 e1000_shift_out_mdi_bits(hw, mdic, 14); 2936 2937 /* Now that we've shifted out the read command to the MII, we 2938 * need to "shift in" the 16-bit value (18 total bits) of the 2939 * requested PHY register address. 2940 */ 2941 *phy_data = e1000_shift_in_mdi_bits(hw); 2942 } 2943 return E1000_SUCCESS; 2944 } 2945 2946 /** 2947 * e1000_write_phy_reg - write a phy register 2948 * 2949 * @hw: Struct containing variables accessed by shared code 2950 * @reg_addr: address of the PHY register to write 2951 * @data: data to write to the PHY 2952 * 2953 * Writes a value to a PHY register 2954 */ 2955 s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 phy_data) 2956 { 2957 u32 ret_val; 2958 unsigned long flags; 2959 2960 spin_lock_irqsave(&e1000_phy_lock, flags); 2961 2962 if ((hw->phy_type == e1000_phy_igp) && 2963 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { 2964 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 2965 (u16)reg_addr); 2966 if (ret_val) { 2967 spin_unlock_irqrestore(&e1000_phy_lock, flags); 2968 return ret_val; 2969 } 2970 } 2971 2972 ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, 2973 phy_data); 2974 spin_unlock_irqrestore(&e1000_phy_lock, flags); 2975 2976 return ret_val; 2977 } 2978 2979 static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr, 2980 u16 phy_data) 2981 { 2982 u32 i; 2983 u32 mdic = 0; 2984 const u32 phy_addr = (hw->mac_type == e1000_ce4100) ? hw->phy_addr : 1; 2985 2986 if (reg_addr > MAX_PHY_REG_ADDRESS) { 2987 e_dbg("PHY Address %d is out of range\n", reg_addr); 2988 return -E1000_ERR_PARAM; 2989 } 2990 2991 if (hw->mac_type > e1000_82543) { 2992 /* Set up Op-code, Phy Address, register address, and data 2993 * intended for the PHY register in the MDI Control register. 2994 * The MAC will take care of interfacing with the PHY to send 2995 * the desired data. 2996 */ 2997 if (hw->mac_type == e1000_ce4100) { 2998 mdic = (((u32)phy_data) | 2999 (reg_addr << E1000_MDIC_REG_SHIFT) | 3000 (phy_addr << E1000_MDIC_PHY_SHIFT) | 3001 (INTEL_CE_GBE_MDIC_OP_WRITE) | 3002 (INTEL_CE_GBE_MDIC_GO)); 3003 3004 writel(mdic, E1000_MDIO_CMD); 3005 3006 /* Poll the ready bit to see if the MDI read 3007 * completed 3008 */ 3009 for (i = 0; i < 640; i++) { 3010 udelay(5); 3011 mdic = readl(E1000_MDIO_CMD); 3012 if (!(mdic & INTEL_CE_GBE_MDIC_GO)) 3013 break; 3014 } 3015 if (mdic & INTEL_CE_GBE_MDIC_GO) { 3016 e_dbg("MDI Write did not complete\n"); 3017 return -E1000_ERR_PHY; 3018 } 3019 } else { 3020 mdic = (((u32)phy_data) | 3021 (reg_addr << E1000_MDIC_REG_SHIFT) | 3022 (phy_addr << E1000_MDIC_PHY_SHIFT) | 3023 (E1000_MDIC_OP_WRITE)); 3024 3025 ew32(MDIC, mdic); 3026 3027 /* Poll the ready bit to see if the MDI read 3028 * completed 3029 */ 3030 for (i = 0; i < 641; i++) { 3031 udelay(5); 3032 mdic = er32(MDIC); 3033 if (mdic & E1000_MDIC_READY) 3034 break; 3035 } 3036 if (!(mdic & E1000_MDIC_READY)) { 3037 e_dbg("MDI Write did not complete\n"); 3038 return -E1000_ERR_PHY; 3039 } 3040 } 3041 } else { 3042 /* We'll need to use the SW defined pins to shift the write 3043 * command out to the PHY. We first send a preamble to the PHY 3044 * to signal the beginning of the MII instruction. This is done 3045 * by sending 32 consecutive "1" bits. 3046 */ 3047 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 3048 3049 /* Now combine the remaining required fields that will indicate 3050 * a write operation. We use this method instead of calling the 3051 * e1000_shift_out_mdi_bits routine for each field in the 3052 * command. The format of a MII write instruction is as follows: 3053 * <Preamble><SOF><OpCode><PhyAddr><RegAddr><Turnaround><Data>. 3054 */ 3055 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) | 3056 (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); 3057 mdic <<= 16; 3058 mdic |= (u32)phy_data; 3059 3060 e1000_shift_out_mdi_bits(hw, mdic, 32); 3061 } 3062 3063 return E1000_SUCCESS; 3064 } 3065 3066 /** 3067 * e1000_phy_hw_reset - reset the phy, hardware style 3068 * @hw: Struct containing variables accessed by shared code 3069 * 3070 * Returns the PHY to the power-on reset state 3071 */ 3072 s32 e1000_phy_hw_reset(struct e1000_hw *hw) 3073 { 3074 u32 ctrl, ctrl_ext; 3075 u32 led_ctrl; 3076 3077 e_dbg("Resetting Phy...\n"); 3078 3079 if (hw->mac_type > e1000_82543) { 3080 /* Read the device control register and assert the 3081 * E1000_CTRL_PHY_RST bit. Then, take it out of reset. 3082 * For e1000 hardware, we delay for 10ms between the assert 3083 * and de-assert. 3084 */ 3085 ctrl = er32(CTRL); 3086 ew32(CTRL, ctrl | E1000_CTRL_PHY_RST); 3087 E1000_WRITE_FLUSH(); 3088 3089 msleep(10); 3090 3091 ew32(CTRL, ctrl); 3092 E1000_WRITE_FLUSH(); 3093 3094 } else { 3095 /* Read the Extended Device Control Register, assert the 3096 * PHY_RESET_DIR bit to put the PHY into reset. Then, take it 3097 * out of reset. 3098 */ 3099 ctrl_ext = er32(CTRL_EXT); 3100 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; 3101 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; 3102 ew32(CTRL_EXT, ctrl_ext); 3103 E1000_WRITE_FLUSH(); 3104 msleep(10); 3105 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; 3106 ew32(CTRL_EXT, ctrl_ext); 3107 E1000_WRITE_FLUSH(); 3108 } 3109 udelay(150); 3110 3111 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 3112 /* Configure activity LED after PHY reset */ 3113 led_ctrl = er32(LEDCTL); 3114 led_ctrl &= IGP_ACTIVITY_LED_MASK; 3115 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 3116 ew32(LEDCTL, led_ctrl); 3117 } 3118 3119 /* Wait for FW to finish PHY configuration. */ 3120 return e1000_get_phy_cfg_done(hw); 3121 } 3122 3123 /** 3124 * e1000_phy_reset - reset the phy to commit settings 3125 * @hw: Struct containing variables accessed by shared code 3126 * 3127 * Resets the PHY 3128 * Sets bit 15 of the MII Control register 3129 */ 3130 s32 e1000_phy_reset(struct e1000_hw *hw) 3131 { 3132 s32 ret_val; 3133 u16 phy_data; 3134 3135 switch (hw->phy_type) { 3136 case e1000_phy_igp: 3137 ret_val = e1000_phy_hw_reset(hw); 3138 if (ret_val) 3139 return ret_val; 3140 break; 3141 default: 3142 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); 3143 if (ret_val) 3144 return ret_val; 3145 3146 phy_data |= MII_CR_RESET; 3147 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); 3148 if (ret_val) 3149 return ret_val; 3150 3151 udelay(1); 3152 break; 3153 } 3154 3155 if (hw->phy_type == e1000_phy_igp) 3156 e1000_phy_init_script(hw); 3157 3158 return E1000_SUCCESS; 3159 } 3160 3161 /** 3162 * e1000_detect_gig_phy - check the phy type 3163 * @hw: Struct containing variables accessed by shared code 3164 * 3165 * Probes the expected PHY address for known PHY IDs 3166 */ 3167 static s32 e1000_detect_gig_phy(struct e1000_hw *hw) 3168 { 3169 s32 phy_init_status, ret_val; 3170 u16 phy_id_high, phy_id_low; 3171 bool match = false; 3172 3173 if (hw->phy_id != 0) 3174 return E1000_SUCCESS; 3175 3176 /* Read the PHY ID Registers to identify which PHY is onboard. */ 3177 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high); 3178 if (ret_val) 3179 return ret_val; 3180 3181 hw->phy_id = (u32)(phy_id_high << 16); 3182 udelay(20); 3183 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low); 3184 if (ret_val) 3185 return ret_val; 3186 3187 hw->phy_id |= (u32)(phy_id_low & PHY_REVISION_MASK); 3188 hw->phy_revision = (u32)phy_id_low & ~PHY_REVISION_MASK; 3189 3190 switch (hw->mac_type) { 3191 case e1000_82543: 3192 if (hw->phy_id == M88E1000_E_PHY_ID) 3193 match = true; 3194 break; 3195 case e1000_82544: 3196 if (hw->phy_id == M88E1000_I_PHY_ID) 3197 match = true; 3198 break; 3199 case e1000_82540: 3200 case e1000_82545: 3201 case e1000_82545_rev_3: 3202 case e1000_82546: 3203 case e1000_82546_rev_3: 3204 if (hw->phy_id == M88E1011_I_PHY_ID) 3205 match = true; 3206 break; 3207 case e1000_ce4100: 3208 if ((hw->phy_id == RTL8211B_PHY_ID) || 3209 (hw->phy_id == RTL8201N_PHY_ID) || 3210 (hw->phy_id == M88E1118_E_PHY_ID)) 3211 match = true; 3212 break; 3213 case e1000_82541: 3214 case e1000_82541_rev_2: 3215 case e1000_82547: 3216 case e1000_82547_rev_2: 3217 if (hw->phy_id == IGP01E1000_I_PHY_ID) 3218 match = true; 3219 break; 3220 default: 3221 e_dbg("Invalid MAC type %d\n", hw->mac_type); 3222 return -E1000_ERR_CONFIG; 3223 } 3224 phy_init_status = e1000_set_phy_type(hw); 3225 3226 if ((match) && (phy_init_status == E1000_SUCCESS)) { 3227 e_dbg("PHY ID 0x%X detected\n", hw->phy_id); 3228 return E1000_SUCCESS; 3229 } 3230 e_dbg("Invalid PHY ID 0x%X\n", hw->phy_id); 3231 return -E1000_ERR_PHY; 3232 } 3233 3234 /** 3235 * e1000_phy_reset_dsp - reset DSP 3236 * @hw: Struct containing variables accessed by shared code 3237 * 3238 * Resets the PHY's DSP 3239 */ 3240 static s32 e1000_phy_reset_dsp(struct e1000_hw *hw) 3241 { 3242 s32 ret_val; 3243 3244 do { 3245 ret_val = e1000_write_phy_reg(hw, 29, 0x001d); 3246 if (ret_val) 3247 break; 3248 ret_val = e1000_write_phy_reg(hw, 30, 0x00c1); 3249 if (ret_val) 3250 break; 3251 ret_val = e1000_write_phy_reg(hw, 30, 0x0000); 3252 if (ret_val) 3253 break; 3254 ret_val = E1000_SUCCESS; 3255 } while (0); 3256 3257 return ret_val; 3258 } 3259 3260 /** 3261 * e1000_phy_igp_get_info - get igp specific registers 3262 * @hw: Struct containing variables accessed by shared code 3263 * @phy_info: PHY information structure 3264 * 3265 * Get PHY information from various PHY registers for igp PHY only. 3266 */ 3267 static s32 e1000_phy_igp_get_info(struct e1000_hw *hw, 3268 struct e1000_phy_info *phy_info) 3269 { 3270 s32 ret_val; 3271 u16 phy_data, min_length, max_length, average; 3272 e1000_rev_polarity polarity; 3273 3274 /* The downshift status is checked only once, after link is established, 3275 * and it stored in the hw->speed_downgraded parameter. 3276 */ 3277 phy_info->downshift = (e1000_downshift) hw->speed_downgraded; 3278 3279 /* IGP01E1000 does not need to support it. */ 3280 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal; 3281 3282 /* IGP01E1000 always correct polarity reversal */ 3283 phy_info->polarity_correction = e1000_polarity_reversal_enabled; 3284 3285 /* Check polarity status */ 3286 ret_val = e1000_check_polarity(hw, &polarity); 3287 if (ret_val) 3288 return ret_val; 3289 3290 phy_info->cable_polarity = polarity; 3291 3292 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data); 3293 if (ret_val) 3294 return ret_val; 3295 3296 phy_info->mdix_mode = 3297 (e1000_auto_x_mode) ((phy_data & IGP01E1000_PSSR_MDIX) >> 3298 IGP01E1000_PSSR_MDIX_SHIFT); 3299 3300 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) == 3301 IGP01E1000_PSSR_SPEED_1000MBPS) { 3302 /* Local/Remote Receiver Information are only valid @ 1000 3303 * Mbps 3304 */ 3305 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); 3306 if (ret_val) 3307 return ret_val; 3308 3309 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >> 3310 SR_1000T_LOCAL_RX_STATUS_SHIFT) ? 3311 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; 3312 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >> 3313 SR_1000T_REMOTE_RX_STATUS_SHIFT) ? 3314 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; 3315 3316 /* Get cable length */ 3317 ret_val = e1000_get_cable_length(hw, &min_length, &max_length); 3318 if (ret_val) 3319 return ret_val; 3320 3321 /* Translate to old method */ 3322 average = (max_length + min_length) / 2; 3323 3324 if (average <= e1000_igp_cable_length_50) 3325 phy_info->cable_length = e1000_cable_length_50; 3326 else if (average <= e1000_igp_cable_length_80) 3327 phy_info->cable_length = e1000_cable_length_50_80; 3328 else if (average <= e1000_igp_cable_length_110) 3329 phy_info->cable_length = e1000_cable_length_80_110; 3330 else if (average <= e1000_igp_cable_length_140) 3331 phy_info->cable_length = e1000_cable_length_110_140; 3332 else 3333 phy_info->cable_length = e1000_cable_length_140; 3334 } 3335 3336 return E1000_SUCCESS; 3337 } 3338 3339 /** 3340 * e1000_phy_m88_get_info - get m88 specific registers 3341 * @hw: Struct containing variables accessed by shared code 3342 * @phy_info: PHY information structure 3343 * 3344 * Get PHY information from various PHY registers for m88 PHY only. 3345 */ 3346 static s32 e1000_phy_m88_get_info(struct e1000_hw *hw, 3347 struct e1000_phy_info *phy_info) 3348 { 3349 s32 ret_val; 3350 u16 phy_data; 3351 e1000_rev_polarity polarity; 3352 3353 /* The downshift status is checked only once, after link is established, 3354 * and it stored in the hw->speed_downgraded parameter. 3355 */ 3356 phy_info->downshift = (e1000_downshift) hw->speed_downgraded; 3357 3358 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 3359 if (ret_val) 3360 return ret_val; 3361 3362 phy_info->extended_10bt_distance = 3363 ((phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >> 3364 M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT) ? 3365 e1000_10bt_ext_dist_enable_lower : 3366 e1000_10bt_ext_dist_enable_normal; 3367 3368 phy_info->polarity_correction = 3369 ((phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >> 3370 M88E1000_PSCR_POLARITY_REVERSAL_SHIFT) ? 3371 e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled; 3372 3373 /* Check polarity status */ 3374 ret_val = e1000_check_polarity(hw, &polarity); 3375 if (ret_val) 3376 return ret_val; 3377 phy_info->cable_polarity = polarity; 3378 3379 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 3380 if (ret_val) 3381 return ret_val; 3382 3383 phy_info->mdix_mode = 3384 (e1000_auto_x_mode) ((phy_data & M88E1000_PSSR_MDIX) >> 3385 M88E1000_PSSR_MDIX_SHIFT); 3386 3387 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { 3388 /* Cable Length Estimation and Local/Remote Receiver Information 3389 * are only valid at 1000 Mbps. 3390 */ 3391 phy_info->cable_length = 3392 (e1000_cable_length) ((phy_data & 3393 M88E1000_PSSR_CABLE_LENGTH) >> 3394 M88E1000_PSSR_CABLE_LENGTH_SHIFT); 3395 3396 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); 3397 if (ret_val) 3398 return ret_val; 3399 3400 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >> 3401 SR_1000T_LOCAL_RX_STATUS_SHIFT) ? 3402 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; 3403 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >> 3404 SR_1000T_REMOTE_RX_STATUS_SHIFT) ? 3405 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; 3406 } 3407 3408 return E1000_SUCCESS; 3409 } 3410 3411 /** 3412 * e1000_phy_get_info - request phy info 3413 * @hw: Struct containing variables accessed by shared code 3414 * @phy_info: PHY information structure 3415 * 3416 * Get PHY information from various PHY registers 3417 */ 3418 s32 e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info) 3419 { 3420 s32 ret_val; 3421 u16 phy_data; 3422 3423 phy_info->cable_length = e1000_cable_length_undefined; 3424 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined; 3425 phy_info->cable_polarity = e1000_rev_polarity_undefined; 3426 phy_info->downshift = e1000_downshift_undefined; 3427 phy_info->polarity_correction = e1000_polarity_reversal_undefined; 3428 phy_info->mdix_mode = e1000_auto_x_mode_undefined; 3429 phy_info->local_rx = e1000_1000t_rx_status_undefined; 3430 phy_info->remote_rx = e1000_1000t_rx_status_undefined; 3431 3432 if (hw->media_type != e1000_media_type_copper) { 3433 e_dbg("PHY info is only valid for copper media\n"); 3434 return -E1000_ERR_CONFIG; 3435 } 3436 3437 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 3438 if (ret_val) 3439 return ret_val; 3440 3441 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 3442 if (ret_val) 3443 return ret_val; 3444 3445 if ((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) { 3446 e_dbg("PHY info is only valid if link is up\n"); 3447 return -E1000_ERR_CONFIG; 3448 } 3449 3450 if (hw->phy_type == e1000_phy_igp) 3451 return e1000_phy_igp_get_info(hw, phy_info); 3452 else if ((hw->phy_type == e1000_phy_8211) || 3453 (hw->phy_type == e1000_phy_8201)) 3454 return E1000_SUCCESS; 3455 else 3456 return e1000_phy_m88_get_info(hw, phy_info); 3457 } 3458 3459 s32 e1000_validate_mdi_setting(struct e1000_hw *hw) 3460 { 3461 if (!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) { 3462 e_dbg("Invalid MDI setting detected\n"); 3463 hw->mdix = 1; 3464 return -E1000_ERR_CONFIG; 3465 } 3466 return E1000_SUCCESS; 3467 } 3468 3469 /** 3470 * e1000_init_eeprom_params - initialize sw eeprom vars 3471 * @hw: Struct containing variables accessed by shared code 3472 * 3473 * Sets up eeprom variables in the hw struct. Must be called after mac_type 3474 * is configured. 3475 */ 3476 s32 e1000_init_eeprom_params(struct e1000_hw *hw) 3477 { 3478 struct e1000_eeprom_info *eeprom = &hw->eeprom; 3479 u32 eecd = er32(EECD); 3480 s32 ret_val = E1000_SUCCESS; 3481 u16 eeprom_size; 3482 3483 switch (hw->mac_type) { 3484 case e1000_82542_rev2_0: 3485 case e1000_82542_rev2_1: 3486 case e1000_82543: 3487 case e1000_82544: 3488 eeprom->type = e1000_eeprom_microwire; 3489 eeprom->word_size = 64; 3490 eeprom->opcode_bits = 3; 3491 eeprom->address_bits = 6; 3492 eeprom->delay_usec = 50; 3493 break; 3494 case e1000_82540: 3495 case e1000_82545: 3496 case e1000_82545_rev_3: 3497 case e1000_82546: 3498 case e1000_82546_rev_3: 3499 eeprom->type = e1000_eeprom_microwire; 3500 eeprom->opcode_bits = 3; 3501 eeprom->delay_usec = 50; 3502 if (eecd & E1000_EECD_SIZE) { 3503 eeprom->word_size = 256; 3504 eeprom->address_bits = 8; 3505 } else { 3506 eeprom->word_size = 64; 3507 eeprom->address_bits = 6; 3508 } 3509 break; 3510 case e1000_82541: 3511 case e1000_82541_rev_2: 3512 case e1000_82547: 3513 case e1000_82547_rev_2: 3514 if (eecd & E1000_EECD_TYPE) { 3515 eeprom->type = e1000_eeprom_spi; 3516 eeprom->opcode_bits = 8; 3517 eeprom->delay_usec = 1; 3518 if (eecd & E1000_EECD_ADDR_BITS) { 3519 eeprom->page_size = 32; 3520 eeprom->address_bits = 16; 3521 } else { 3522 eeprom->page_size = 8; 3523 eeprom->address_bits = 8; 3524 } 3525 } else { 3526 eeprom->type = e1000_eeprom_microwire; 3527 eeprom->opcode_bits = 3; 3528 eeprom->delay_usec = 50; 3529 if (eecd & E1000_EECD_ADDR_BITS) { 3530 eeprom->word_size = 256; 3531 eeprom->address_bits = 8; 3532 } else { 3533 eeprom->word_size = 64; 3534 eeprom->address_bits = 6; 3535 } 3536 } 3537 break; 3538 default: 3539 break; 3540 } 3541 3542 if (eeprom->type == e1000_eeprom_spi) { 3543 /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 3544 * 128B to 32KB (incremented by powers of 2). 3545 */ 3546 /* Set to default value for initial eeprom read. */ 3547 eeprom->word_size = 64; 3548 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size); 3549 if (ret_val) 3550 return ret_val; 3551 eeprom_size = 3552 (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT; 3553 /* 256B eeprom size was not supported in earlier hardware, so we 3554 * bump eeprom_size up one to ensure that "1" (which maps to 3555 * 256B) is never the result used in the shifting logic below. 3556 */ 3557 if (eeprom_size) 3558 eeprom_size++; 3559 3560 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT); 3561 } 3562 return ret_val; 3563 } 3564 3565 /** 3566 * e1000_raise_ee_clk - Raises the EEPROM's clock input. 3567 * @hw: Struct containing variables accessed by shared code 3568 * @eecd: EECD's current value 3569 */ 3570 static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd) 3571 { 3572 /* Raise the clock input to the EEPROM (by setting the SK bit), and then 3573 * wait <delay> microseconds. 3574 */ 3575 *eecd = *eecd | E1000_EECD_SK; 3576 ew32(EECD, *eecd); 3577 E1000_WRITE_FLUSH(); 3578 udelay(hw->eeprom.delay_usec); 3579 } 3580 3581 /** 3582 * e1000_lower_ee_clk - Lowers the EEPROM's clock input. 3583 * @hw: Struct containing variables accessed by shared code 3584 * @eecd: EECD's current value 3585 */ 3586 static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd) 3587 { 3588 /* Lower the clock input to the EEPROM (by clearing the SK bit), and 3589 * then wait 50 microseconds. 3590 */ 3591 *eecd = *eecd & ~E1000_EECD_SK; 3592 ew32(EECD, *eecd); 3593 E1000_WRITE_FLUSH(); 3594 udelay(hw->eeprom.delay_usec); 3595 } 3596 3597 /** 3598 * e1000_shift_out_ee_bits - Shift data bits out to the EEPROM. 3599 * @hw: Struct containing variables accessed by shared code 3600 * @data: data to send to the EEPROM 3601 * @count: number of bits to shift out 3602 */ 3603 static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count) 3604 { 3605 struct e1000_eeprom_info *eeprom = &hw->eeprom; 3606 u32 eecd; 3607 u32 mask; 3608 3609 /* We need to shift "count" bits out to the EEPROM. So, value in the 3610 * "data" parameter will be shifted out to the EEPROM one bit at a time. 3611 * In order to do this, "data" must be broken down into bits. 3612 */ 3613 mask = 0x01 << (count - 1); 3614 eecd = er32(EECD); 3615 if (eeprom->type == e1000_eeprom_microwire) 3616 eecd &= ~E1000_EECD_DO; 3617 else if (eeprom->type == e1000_eeprom_spi) 3618 eecd |= E1000_EECD_DO; 3619 3620 do { 3621 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a 3622 * "1", and then raising and then lowering the clock (the SK bit 3623 * controls the clock input to the EEPROM). A "0" is shifted 3624 * out to the EEPROM by setting "DI" to "0" and then raising and 3625 * then lowering the clock. 3626 */ 3627 eecd &= ~E1000_EECD_DI; 3628 3629 if (data & mask) 3630 eecd |= E1000_EECD_DI; 3631 3632 ew32(EECD, eecd); 3633 E1000_WRITE_FLUSH(); 3634 3635 udelay(eeprom->delay_usec); 3636 3637 e1000_raise_ee_clk(hw, &eecd); 3638 e1000_lower_ee_clk(hw, &eecd); 3639 3640 mask = mask >> 1; 3641 3642 } while (mask); 3643 3644 /* We leave the "DI" bit set to "0" when we leave this routine. */ 3645 eecd &= ~E1000_EECD_DI; 3646 ew32(EECD, eecd); 3647 } 3648 3649 /** 3650 * e1000_shift_in_ee_bits - Shift data bits in from the EEPROM 3651 * @hw: Struct containing variables accessed by shared code 3652 * @count: number of bits to shift in 3653 */ 3654 static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count) 3655 { 3656 u32 eecd; 3657 u32 i; 3658 u16 data; 3659 3660 /* In order to read a register from the EEPROM, we need to shift 'count' 3661 * bits in from the EEPROM. Bits are "shifted in" by raising the clock 3662 * input to the EEPROM (setting the SK bit), and then reading the value 3663 * of the "DO" bit. During this "shifting in" process the "DI" bit 3664 * should always be clear. 3665 */ 3666 3667 eecd = er32(EECD); 3668 3669 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 3670 data = 0; 3671 3672 for (i = 0; i < count; i++) { 3673 data = data << 1; 3674 e1000_raise_ee_clk(hw, &eecd); 3675 3676 eecd = er32(EECD); 3677 3678 eecd &= ~(E1000_EECD_DI); 3679 if (eecd & E1000_EECD_DO) 3680 data |= 1; 3681 3682 e1000_lower_ee_clk(hw, &eecd); 3683 } 3684 3685 return data; 3686 } 3687 3688 /** 3689 * e1000_acquire_eeprom - Prepares EEPROM for access 3690 * @hw: Struct containing variables accessed by shared code 3691 * 3692 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This 3693 * function should be called before issuing a command to the EEPROM. 3694 */ 3695 static s32 e1000_acquire_eeprom(struct e1000_hw *hw) 3696 { 3697 struct e1000_eeprom_info *eeprom = &hw->eeprom; 3698 u32 eecd, i = 0; 3699 3700 eecd = er32(EECD); 3701 3702 /* Request EEPROM Access */ 3703 if (hw->mac_type > e1000_82544) { 3704 eecd |= E1000_EECD_REQ; 3705 ew32(EECD, eecd); 3706 eecd = er32(EECD); 3707 while ((!(eecd & E1000_EECD_GNT)) && 3708 (i < E1000_EEPROM_GRANT_ATTEMPTS)) { 3709 i++; 3710 udelay(5); 3711 eecd = er32(EECD); 3712 } 3713 if (!(eecd & E1000_EECD_GNT)) { 3714 eecd &= ~E1000_EECD_REQ; 3715 ew32(EECD, eecd); 3716 e_dbg("Could not acquire EEPROM grant\n"); 3717 return -E1000_ERR_EEPROM; 3718 } 3719 } 3720 3721 /* Setup EEPROM for Read/Write */ 3722 3723 if (eeprom->type == e1000_eeprom_microwire) { 3724 /* Clear SK and DI */ 3725 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); 3726 ew32(EECD, eecd); 3727 3728 /* Set CS */ 3729 eecd |= E1000_EECD_CS; 3730 ew32(EECD, eecd); 3731 } else if (eeprom->type == e1000_eeprom_spi) { 3732 /* Clear SK and CS */ 3733 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 3734 ew32(EECD, eecd); 3735 E1000_WRITE_FLUSH(); 3736 udelay(1); 3737 } 3738 3739 return E1000_SUCCESS; 3740 } 3741 3742 /** 3743 * e1000_standby_eeprom - Returns EEPROM to a "standby" state 3744 * @hw: Struct containing variables accessed by shared code 3745 */ 3746 static void e1000_standby_eeprom(struct e1000_hw *hw) 3747 { 3748 struct e1000_eeprom_info *eeprom = &hw->eeprom; 3749 u32 eecd; 3750 3751 eecd = er32(EECD); 3752 3753 if (eeprom->type == e1000_eeprom_microwire) { 3754 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 3755 ew32(EECD, eecd); 3756 E1000_WRITE_FLUSH(); 3757 udelay(eeprom->delay_usec); 3758 3759 /* Clock high */ 3760 eecd |= E1000_EECD_SK; 3761 ew32(EECD, eecd); 3762 E1000_WRITE_FLUSH(); 3763 udelay(eeprom->delay_usec); 3764 3765 /* Select EEPROM */ 3766 eecd |= E1000_EECD_CS; 3767 ew32(EECD, eecd); 3768 E1000_WRITE_FLUSH(); 3769 udelay(eeprom->delay_usec); 3770 3771 /* Clock low */ 3772 eecd &= ~E1000_EECD_SK; 3773 ew32(EECD, eecd); 3774 E1000_WRITE_FLUSH(); 3775 udelay(eeprom->delay_usec); 3776 } else if (eeprom->type == e1000_eeprom_spi) { 3777 /* Toggle CS to flush commands */ 3778 eecd |= E1000_EECD_CS; 3779 ew32(EECD, eecd); 3780 E1000_WRITE_FLUSH(); 3781 udelay(eeprom->delay_usec); 3782 eecd &= ~E1000_EECD_CS; 3783 ew32(EECD, eecd); 3784 E1000_WRITE_FLUSH(); 3785 udelay(eeprom->delay_usec); 3786 } 3787 } 3788 3789 /** 3790 * e1000_release_eeprom - drop chip select 3791 * @hw: Struct containing variables accessed by shared code 3792 * 3793 * Terminates a command by inverting the EEPROM's chip select pin 3794 */ 3795 static void e1000_release_eeprom(struct e1000_hw *hw) 3796 { 3797 u32 eecd; 3798 3799 eecd = er32(EECD); 3800 3801 if (hw->eeprom.type == e1000_eeprom_spi) { 3802 eecd |= E1000_EECD_CS; /* Pull CS high */ 3803 eecd &= ~E1000_EECD_SK; /* Lower SCK */ 3804 3805 ew32(EECD, eecd); 3806 E1000_WRITE_FLUSH(); 3807 3808 udelay(hw->eeprom.delay_usec); 3809 } else if (hw->eeprom.type == e1000_eeprom_microwire) { 3810 /* cleanup eeprom */ 3811 3812 /* CS on Microwire is active-high */ 3813 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); 3814 3815 ew32(EECD, eecd); 3816 3817 /* Rising edge of clock */ 3818 eecd |= E1000_EECD_SK; 3819 ew32(EECD, eecd); 3820 E1000_WRITE_FLUSH(); 3821 udelay(hw->eeprom.delay_usec); 3822 3823 /* Falling edge of clock */ 3824 eecd &= ~E1000_EECD_SK; 3825 ew32(EECD, eecd); 3826 E1000_WRITE_FLUSH(); 3827 udelay(hw->eeprom.delay_usec); 3828 } 3829 3830 /* Stop requesting EEPROM access */ 3831 if (hw->mac_type > e1000_82544) { 3832 eecd &= ~E1000_EECD_REQ; 3833 ew32(EECD, eecd); 3834 } 3835 } 3836 3837 /** 3838 * e1000_spi_eeprom_ready - Reads a 16 bit word from the EEPROM. 3839 * @hw: Struct containing variables accessed by shared code 3840 */ 3841 static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw) 3842 { 3843 u16 retry_count = 0; 3844 u8 spi_stat_reg; 3845 3846 /* Read "Status Register" repeatedly until the LSB is cleared. The 3847 * EEPROM will signal that the command has been completed by clearing 3848 * bit 0 of the internal status register. If it's not cleared within 3849 * 5 milliseconds, then error out. 3850 */ 3851 retry_count = 0; 3852 do { 3853 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI, 3854 hw->eeprom.opcode_bits); 3855 spi_stat_reg = (u8)e1000_shift_in_ee_bits(hw, 8); 3856 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI)) 3857 break; 3858 3859 udelay(5); 3860 retry_count += 5; 3861 3862 e1000_standby_eeprom(hw); 3863 } while (retry_count < EEPROM_MAX_RETRY_SPI); 3864 3865 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and 3866 * only 0-5mSec on 5V devices) 3867 */ 3868 if (retry_count >= EEPROM_MAX_RETRY_SPI) { 3869 e_dbg("SPI EEPROM Status error\n"); 3870 return -E1000_ERR_EEPROM; 3871 } 3872 3873 return E1000_SUCCESS; 3874 } 3875 3876 /** 3877 * e1000_read_eeprom - Reads a 16 bit word from the EEPROM. 3878 * @hw: Struct containing variables accessed by shared code 3879 * @offset: offset of word in the EEPROM to read 3880 * @data: word read from the EEPROM 3881 * @words: number of words to read 3882 */ 3883 s32 e1000_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 3884 { 3885 s32 ret; 3886 3887 mutex_lock(&e1000_eeprom_lock); 3888 ret = e1000_do_read_eeprom(hw, offset, words, data); 3889 mutex_unlock(&e1000_eeprom_lock); 3890 return ret; 3891 } 3892 3893 static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, 3894 u16 *data) 3895 { 3896 struct e1000_eeprom_info *eeprom = &hw->eeprom; 3897 u32 i = 0; 3898 3899 if (hw->mac_type == e1000_ce4100) { 3900 GBE_CONFIG_FLASH_READ(GBE_CONFIG_BASE_VIRT, offset, words, 3901 data); 3902 return E1000_SUCCESS; 3903 } 3904 3905 /* A check for invalid values: offset too large, too many words, and 3906 * not enough words. 3907 */ 3908 if ((offset >= eeprom->word_size) || 3909 (words > eeprom->word_size - offset) || 3910 (words == 0)) { 3911 e_dbg("\"words\" parameter out of bounds. Words = %d," 3912 "size = %d\n", offset, eeprom->word_size); 3913 return -E1000_ERR_EEPROM; 3914 } 3915 3916 /* EEPROM's that don't use EERD to read require us to bit-bang the SPI 3917 * directly. In this case, we need to acquire the EEPROM so that 3918 * FW or other port software does not interrupt. 3919 */ 3920 /* Prepare the EEPROM for bit-bang reading */ 3921 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) 3922 return -E1000_ERR_EEPROM; 3923 3924 /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have 3925 * acquired the EEPROM at this point, so any returns should release it 3926 */ 3927 if (eeprom->type == e1000_eeprom_spi) { 3928 u16 word_in; 3929 u8 read_opcode = EEPROM_READ_OPCODE_SPI; 3930 3931 if (e1000_spi_eeprom_ready(hw)) { 3932 e1000_release_eeprom(hw); 3933 return -E1000_ERR_EEPROM; 3934 } 3935 3936 e1000_standby_eeprom(hw); 3937 3938 /* Some SPI eeproms use the 8th address bit embedded in the 3939 * opcode 3940 */ 3941 if ((eeprom->address_bits == 8) && (offset >= 128)) 3942 read_opcode |= EEPROM_A8_OPCODE_SPI; 3943 3944 /* Send the READ command (opcode + addr) */ 3945 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits); 3946 e1000_shift_out_ee_bits(hw, (u16)(offset * 2), 3947 eeprom->address_bits); 3948 3949 /* Read the data. The address of the eeprom internally 3950 * increments with each byte (spi) being read, saving on the 3951 * overhead of eeprom setup and tear-down. The address counter 3952 * will roll over if reading beyond the size of the eeprom, thus 3953 * allowing the entire memory to be read starting from any 3954 * offset. 3955 */ 3956 for (i = 0; i < words; i++) { 3957 word_in = e1000_shift_in_ee_bits(hw, 16); 3958 data[i] = (word_in >> 8) | (word_in << 8); 3959 } 3960 } else if (eeprom->type == e1000_eeprom_microwire) { 3961 for (i = 0; i < words; i++) { 3962 /* Send the READ command (opcode + addr) */ 3963 e1000_shift_out_ee_bits(hw, 3964 EEPROM_READ_OPCODE_MICROWIRE, 3965 eeprom->opcode_bits); 3966 e1000_shift_out_ee_bits(hw, (u16)(offset + i), 3967 eeprom->address_bits); 3968 3969 /* Read the data. For microwire, each word requires the 3970 * overhead of eeprom setup and tear-down. 3971 */ 3972 data[i] = e1000_shift_in_ee_bits(hw, 16); 3973 e1000_standby_eeprom(hw); 3974 cond_resched(); 3975 } 3976 } 3977 3978 /* End this read operation */ 3979 e1000_release_eeprom(hw); 3980 3981 return E1000_SUCCESS; 3982 } 3983 3984 /** 3985 * e1000_validate_eeprom_checksum - Verifies that the EEPROM has a valid checksum 3986 * @hw: Struct containing variables accessed by shared code 3987 * 3988 * Reads the first 64 16 bit words of the EEPROM and sums the values read. 3989 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is 3990 * valid. 3991 */ 3992 s32 e1000_validate_eeprom_checksum(struct e1000_hw *hw) 3993 { 3994 u16 checksum = 0; 3995 u16 i, eeprom_data; 3996 3997 for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) { 3998 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { 3999 e_dbg("EEPROM Read Error\n"); 4000 return -E1000_ERR_EEPROM; 4001 } 4002 checksum += eeprom_data; 4003 } 4004 4005 #ifdef CONFIG_PARISC 4006 /* This is a signature and not a checksum on HP c8000 */ 4007 if ((hw->subsystem_vendor_id == 0x103C) && (eeprom_data == 0x16d6)) 4008 return E1000_SUCCESS; 4009 4010 #endif 4011 if (checksum == (u16)EEPROM_SUM) 4012 return E1000_SUCCESS; 4013 else { 4014 e_dbg("EEPROM Checksum Invalid\n"); 4015 return -E1000_ERR_EEPROM; 4016 } 4017 } 4018 4019 /** 4020 * e1000_update_eeprom_checksum - Calculates/writes the EEPROM checksum 4021 * @hw: Struct containing variables accessed by shared code 4022 * 4023 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA. 4024 * Writes the difference to word offset 63 of the EEPROM. 4025 */ 4026 s32 e1000_update_eeprom_checksum(struct e1000_hw *hw) 4027 { 4028 u16 checksum = 0; 4029 u16 i, eeprom_data; 4030 4031 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) { 4032 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { 4033 e_dbg("EEPROM Read Error\n"); 4034 return -E1000_ERR_EEPROM; 4035 } 4036 checksum += eeprom_data; 4037 } 4038 checksum = (u16)EEPROM_SUM - checksum; 4039 if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) { 4040 e_dbg("EEPROM Write Error\n"); 4041 return -E1000_ERR_EEPROM; 4042 } 4043 return E1000_SUCCESS; 4044 } 4045 4046 /** 4047 * e1000_write_eeprom - write words to the different EEPROM types. 4048 * @hw: Struct containing variables accessed by shared code 4049 * @offset: offset within the EEPROM to be written to 4050 * @words: number of words to write 4051 * @data: 16 bit word to be written to the EEPROM 4052 * 4053 * If e1000_update_eeprom_checksum is not called after this function, the 4054 * EEPROM will most likely contain an invalid checksum. 4055 */ 4056 s32 e1000_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 4057 { 4058 s32 ret; 4059 4060 mutex_lock(&e1000_eeprom_lock); 4061 ret = e1000_do_write_eeprom(hw, offset, words, data); 4062 mutex_unlock(&e1000_eeprom_lock); 4063 return ret; 4064 } 4065 4066 static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, 4067 u16 *data) 4068 { 4069 struct e1000_eeprom_info *eeprom = &hw->eeprom; 4070 s32 status = 0; 4071 4072 if (hw->mac_type == e1000_ce4100) { 4073 GBE_CONFIG_FLASH_WRITE(GBE_CONFIG_BASE_VIRT, offset, words, 4074 data); 4075 return E1000_SUCCESS; 4076 } 4077 4078 /* A check for invalid values: offset too large, too many words, and 4079 * not enough words. 4080 */ 4081 if ((offset >= eeprom->word_size) || 4082 (words > eeprom->word_size - offset) || 4083 (words == 0)) { 4084 e_dbg("\"words\" parameter out of bounds\n"); 4085 return -E1000_ERR_EEPROM; 4086 } 4087 4088 /* Prepare the EEPROM for writing */ 4089 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) 4090 return -E1000_ERR_EEPROM; 4091 4092 if (eeprom->type == e1000_eeprom_microwire) { 4093 status = e1000_write_eeprom_microwire(hw, offset, words, data); 4094 } else { 4095 status = e1000_write_eeprom_spi(hw, offset, words, data); 4096 msleep(10); 4097 } 4098 4099 /* Done with writing */ 4100 e1000_release_eeprom(hw); 4101 4102 return status; 4103 } 4104 4105 /** 4106 * e1000_write_eeprom_spi - Writes a 16 bit word to a given offset in an SPI EEPROM. 4107 * @hw: Struct containing variables accessed by shared code 4108 * @offset: offset within the EEPROM to be written to 4109 * @words: number of words to write 4110 * @data: pointer to array of 8 bit words to be written to the EEPROM 4111 */ 4112 static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset, u16 words, 4113 u16 *data) 4114 { 4115 struct e1000_eeprom_info *eeprom = &hw->eeprom; 4116 u16 widx = 0; 4117 4118 while (widx < words) { 4119 u8 write_opcode = EEPROM_WRITE_OPCODE_SPI; 4120 4121 if (e1000_spi_eeprom_ready(hw)) 4122 return -E1000_ERR_EEPROM; 4123 4124 e1000_standby_eeprom(hw); 4125 cond_resched(); 4126 4127 /* Send the WRITE ENABLE command (8 bit opcode ) */ 4128 e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI, 4129 eeprom->opcode_bits); 4130 4131 e1000_standby_eeprom(hw); 4132 4133 /* Some SPI eeproms use the 8th address bit embedded in the 4134 * opcode 4135 */ 4136 if ((eeprom->address_bits == 8) && (offset >= 128)) 4137 write_opcode |= EEPROM_A8_OPCODE_SPI; 4138 4139 /* Send the Write command (8-bit opcode + addr) */ 4140 e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits); 4141 4142 e1000_shift_out_ee_bits(hw, (u16)((offset + widx) * 2), 4143 eeprom->address_bits); 4144 4145 /* Send the data */ 4146 4147 /* Loop to allow for up to whole page write (32 bytes) of 4148 * eeprom 4149 */ 4150 while (widx < words) { 4151 u16 word_out = data[widx]; 4152 4153 word_out = (word_out >> 8) | (word_out << 8); 4154 e1000_shift_out_ee_bits(hw, word_out, 16); 4155 widx++; 4156 4157 /* Some larger eeprom sizes are capable of a 32-byte 4158 * PAGE WRITE operation, while the smaller eeproms are 4159 * capable of an 8-byte PAGE WRITE operation. Break the 4160 * inner loop to pass new address 4161 */ 4162 if ((((offset + widx) * 2) % eeprom->page_size) == 0) { 4163 e1000_standby_eeprom(hw); 4164 break; 4165 } 4166 } 4167 } 4168 4169 return E1000_SUCCESS; 4170 } 4171 4172 /** 4173 * e1000_write_eeprom_microwire - Writes a 16 bit word to a given offset in a Microwire EEPROM. 4174 * @hw: Struct containing variables accessed by shared code 4175 * @offset: offset within the EEPROM to be written to 4176 * @words: number of words to write 4177 * @data: pointer to array of 8 bit words to be written to the EEPROM 4178 */ 4179 static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset, 4180 u16 words, u16 *data) 4181 { 4182 struct e1000_eeprom_info *eeprom = &hw->eeprom; 4183 u32 eecd; 4184 u16 words_written = 0; 4185 u16 i = 0; 4186 4187 /* Send the write enable command to the EEPROM (3-bit opcode plus 4188 * 6/8-bit dummy address beginning with 11). It's less work to include 4189 * the 11 of the dummy address as part of the opcode than it is to shift 4190 * it over the correct number of bits for the address. This puts the 4191 * EEPROM into write/erase mode. 4192 */ 4193 e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE, 4194 (u16)(eeprom->opcode_bits + 2)); 4195 4196 e1000_shift_out_ee_bits(hw, 0, (u16)(eeprom->address_bits - 2)); 4197 4198 /* Prepare the EEPROM */ 4199 e1000_standby_eeprom(hw); 4200 4201 while (words_written < words) { 4202 /* Send the Write command (3-bit opcode + addr) */ 4203 e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE, 4204 eeprom->opcode_bits); 4205 4206 e1000_shift_out_ee_bits(hw, (u16)(offset + words_written), 4207 eeprom->address_bits); 4208 4209 /* Send the data */ 4210 e1000_shift_out_ee_bits(hw, data[words_written], 16); 4211 4212 /* Toggle the CS line. This in effect tells the EEPROM to 4213 * execute the previous command. 4214 */ 4215 e1000_standby_eeprom(hw); 4216 4217 /* Read DO repeatedly until it is high (equal to '1'). The 4218 * EEPROM will signal that the command has been completed by 4219 * raising the DO signal. If DO does not go high in 10 4220 * milliseconds, then error out. 4221 */ 4222 for (i = 0; i < 200; i++) { 4223 eecd = er32(EECD); 4224 if (eecd & E1000_EECD_DO) 4225 break; 4226 udelay(50); 4227 } 4228 if (i == 200) { 4229 e_dbg("EEPROM Write did not complete\n"); 4230 return -E1000_ERR_EEPROM; 4231 } 4232 4233 /* Recover from write */ 4234 e1000_standby_eeprom(hw); 4235 cond_resched(); 4236 4237 words_written++; 4238 } 4239 4240 /* Send the write disable command to the EEPROM (3-bit opcode plus 4241 * 6/8-bit dummy address beginning with 10). It's less work to include 4242 * the 10 of the dummy address as part of the opcode than it is to shift 4243 * it over the correct number of bits for the address. This takes the 4244 * EEPROM out of write/erase mode. 4245 */ 4246 e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE, 4247 (u16)(eeprom->opcode_bits + 2)); 4248 4249 e1000_shift_out_ee_bits(hw, 0, (u16)(eeprom->address_bits - 2)); 4250 4251 return E1000_SUCCESS; 4252 } 4253 4254 /** 4255 * e1000_read_mac_addr - read the adapters MAC from eeprom 4256 * @hw: Struct containing variables accessed by shared code 4257 * 4258 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the 4259 * second function of dual function devices 4260 */ 4261 s32 e1000_read_mac_addr(struct e1000_hw *hw) 4262 { 4263 u16 offset; 4264 u16 eeprom_data, i; 4265 4266 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) { 4267 offset = i >> 1; 4268 if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { 4269 e_dbg("EEPROM Read Error\n"); 4270 return -E1000_ERR_EEPROM; 4271 } 4272 hw->perm_mac_addr[i] = (u8)(eeprom_data & 0x00FF); 4273 hw->perm_mac_addr[i + 1] = (u8)(eeprom_data >> 8); 4274 } 4275 4276 switch (hw->mac_type) { 4277 default: 4278 break; 4279 case e1000_82546: 4280 case e1000_82546_rev_3: 4281 if (er32(STATUS) & E1000_STATUS_FUNC_1) 4282 hw->perm_mac_addr[5] ^= 0x01; 4283 break; 4284 } 4285 4286 for (i = 0; i < NODE_ADDRESS_SIZE; i++) 4287 hw->mac_addr[i] = hw->perm_mac_addr[i]; 4288 return E1000_SUCCESS; 4289 } 4290 4291 /** 4292 * e1000_init_rx_addrs - Initializes receive address filters. 4293 * @hw: Struct containing variables accessed by shared code 4294 * 4295 * Places the MAC address in receive address register 0 and clears the rest 4296 * of the receive address registers. Clears the multicast table. Assumes 4297 * the receiver is in reset when the routine is called. 4298 */ 4299 static void e1000_init_rx_addrs(struct e1000_hw *hw) 4300 { 4301 u32 i; 4302 u32 rar_num; 4303 4304 /* Setup the receive address. */ 4305 e_dbg("Programming MAC Address into RAR[0]\n"); 4306 4307 e1000_rar_set(hw, hw->mac_addr, 0); 4308 4309 rar_num = E1000_RAR_ENTRIES; 4310 4311 /* Zero out the following 14 receive addresses. RAR[15] is for 4312 * manageability 4313 */ 4314 e_dbg("Clearing RAR[1-14]\n"); 4315 for (i = 1; i < rar_num; i++) { 4316 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 4317 E1000_WRITE_FLUSH(); 4318 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 4319 E1000_WRITE_FLUSH(); 4320 } 4321 } 4322 4323 /** 4324 * e1000_hash_mc_addr - Hashes an address to determine its location in the multicast table 4325 * @hw: Struct containing variables accessed by shared code 4326 * @mc_addr: the multicast address to hash 4327 */ 4328 u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr) 4329 { 4330 u32 hash_value = 0; 4331 4332 /* The portion of the address that is used for the hash table is 4333 * determined by the mc_filter_type setting. 4334 */ 4335 switch (hw->mc_filter_type) { 4336 /* [0] [1] [2] [3] [4] [5] 4337 * 01 AA 00 12 34 56 4338 * LSB MSB 4339 */ 4340 case 0: 4341 /* [47:36] i.e. 0x563 for above example address */ 4342 hash_value = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4)); 4343 break; 4344 case 1: 4345 /* [46:35] i.e. 0xAC6 for above example address */ 4346 hash_value = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5)); 4347 break; 4348 case 2: 4349 /* [45:34] i.e. 0x5D8 for above example address */ 4350 hash_value = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6)); 4351 break; 4352 case 3: 4353 /* [43:32] i.e. 0x634 for above example address */ 4354 hash_value = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8)); 4355 break; 4356 } 4357 4358 hash_value &= 0xFFF; 4359 return hash_value; 4360 } 4361 4362 /** 4363 * e1000_rar_set - Puts an ethernet address into a receive address register. 4364 * @hw: Struct containing variables accessed by shared code 4365 * @addr: Address to put into receive address register 4366 * @index: Receive address register to write 4367 */ 4368 void e1000_rar_set(struct e1000_hw *hw, u8 *addr, u32 index) 4369 { 4370 u32 rar_low, rar_high; 4371 4372 /* HW expects these in little endian so we reverse the byte order 4373 * from network order (big endian) to little endian 4374 */ 4375 rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) | 4376 ((u32)addr[2] << 16) | ((u32)addr[3] << 24)); 4377 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8)); 4378 4379 /* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx 4380 * unit hang. 4381 * 4382 * Description: 4383 * If there are any Rx frames queued up or otherwise present in the HW 4384 * before RSS is enabled, and then we enable RSS, the HW Rx unit will 4385 * hang. To work around this issue, we have to disable receives and 4386 * flush out all Rx frames before we enable RSS. To do so, we modify we 4387 * redirect all Rx traffic to manageability and then reset the HW. 4388 * This flushes away Rx frames, and (since the redirections to 4389 * manageability persists across resets) keeps new ones from coming in 4390 * while we work. Then, we clear the Address Valid AV bit for all MAC 4391 * addresses and undo the re-direction to manageability. 4392 * Now, frames are coming in again, but the MAC won't accept them, so 4393 * far so good. We now proceed to initialize RSS (if necessary) and 4394 * configure the Rx unit. Last, we re-enable the AV bits and continue 4395 * on our merry way. 4396 */ 4397 switch (hw->mac_type) { 4398 default: 4399 /* Indicate to hardware the Address is Valid. */ 4400 rar_high |= E1000_RAH_AV; 4401 break; 4402 } 4403 4404 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low); 4405 E1000_WRITE_FLUSH(); 4406 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high); 4407 E1000_WRITE_FLUSH(); 4408 } 4409 4410 /** 4411 * e1000_write_vfta - Writes a value to the specified offset in the VLAN filter table. 4412 * @hw: Struct containing variables accessed by shared code 4413 * @offset: Offset in VLAN filer table to write 4414 * @value: Value to write into VLAN filter table 4415 */ 4416 void e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value) 4417 { 4418 u32 temp; 4419 4420 if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) { 4421 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1)); 4422 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); 4423 E1000_WRITE_FLUSH(); 4424 E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp); 4425 E1000_WRITE_FLUSH(); 4426 } else { 4427 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); 4428 E1000_WRITE_FLUSH(); 4429 } 4430 } 4431 4432 /** 4433 * e1000_clear_vfta - Clears the VLAN filer table 4434 * @hw: Struct containing variables accessed by shared code 4435 */ 4436 static void e1000_clear_vfta(struct e1000_hw *hw) 4437 { 4438 u32 offset; 4439 u32 vfta_value = 0; 4440 u32 vfta_offset = 0; 4441 u32 vfta_bit_in_reg = 0; 4442 4443 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 4444 /* If the offset we want to clear is the same offset of the 4445 * manageability VLAN ID, then clear all bits except that of the 4446 * manageability unit 4447 */ 4448 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; 4449 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value); 4450 E1000_WRITE_FLUSH(); 4451 } 4452 } 4453 4454 static s32 e1000_id_led_init(struct e1000_hw *hw) 4455 { 4456 u32 ledctl; 4457 const u32 ledctl_mask = 0x000000FF; 4458 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; 4459 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; 4460 u16 eeprom_data, i, temp; 4461 const u16 led_mask = 0x0F; 4462 4463 if (hw->mac_type < e1000_82540) { 4464 /* Nothing to do */ 4465 return E1000_SUCCESS; 4466 } 4467 4468 ledctl = er32(LEDCTL); 4469 hw->ledctl_default = ledctl; 4470 hw->ledctl_mode1 = hw->ledctl_default; 4471 hw->ledctl_mode2 = hw->ledctl_default; 4472 4473 if (e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) { 4474 e_dbg("EEPROM Read Error\n"); 4475 return -E1000_ERR_EEPROM; 4476 } 4477 4478 if ((eeprom_data == ID_LED_RESERVED_0000) || 4479 (eeprom_data == ID_LED_RESERVED_FFFF)) { 4480 eeprom_data = ID_LED_DEFAULT; 4481 } 4482 4483 for (i = 0; i < 4; i++) { 4484 temp = (eeprom_data >> (i << 2)) & led_mask; 4485 switch (temp) { 4486 case ID_LED_ON1_DEF2: 4487 case ID_LED_ON1_ON2: 4488 case ID_LED_ON1_OFF2: 4489 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 4490 hw->ledctl_mode1 |= ledctl_on << (i << 3); 4491 break; 4492 case ID_LED_OFF1_DEF2: 4493 case ID_LED_OFF1_ON2: 4494 case ID_LED_OFF1_OFF2: 4495 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 4496 hw->ledctl_mode1 |= ledctl_off << (i << 3); 4497 break; 4498 default: 4499 /* Do nothing */ 4500 break; 4501 } 4502 switch (temp) { 4503 case ID_LED_DEF1_ON2: 4504 case ID_LED_ON1_ON2: 4505 case ID_LED_OFF1_ON2: 4506 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 4507 hw->ledctl_mode2 |= ledctl_on << (i << 3); 4508 break; 4509 case ID_LED_DEF1_OFF2: 4510 case ID_LED_ON1_OFF2: 4511 case ID_LED_OFF1_OFF2: 4512 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 4513 hw->ledctl_mode2 |= ledctl_off << (i << 3); 4514 break; 4515 default: 4516 /* Do nothing */ 4517 break; 4518 } 4519 } 4520 return E1000_SUCCESS; 4521 } 4522 4523 /** 4524 * e1000_setup_led 4525 * @hw: Struct containing variables accessed by shared code 4526 * 4527 * Prepares SW controlable LED for use and saves the current state of the LED. 4528 */ 4529 s32 e1000_setup_led(struct e1000_hw *hw) 4530 { 4531 u32 ledctl; 4532 s32 ret_val = E1000_SUCCESS; 4533 4534 switch (hw->mac_type) { 4535 case e1000_82542_rev2_0: 4536 case e1000_82542_rev2_1: 4537 case e1000_82543: 4538 case e1000_82544: 4539 /* No setup necessary */ 4540 break; 4541 case e1000_82541: 4542 case e1000_82547: 4543 case e1000_82541_rev_2: 4544 case e1000_82547_rev_2: 4545 /* Turn off PHY Smart Power Down (if enabled) */ 4546 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, 4547 &hw->phy_spd_default); 4548 if (ret_val) 4549 return ret_val; 4550 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, 4551 (u16)(hw->phy_spd_default & 4552 ~IGP01E1000_GMII_SPD)); 4553 if (ret_val) 4554 return ret_val; 4555 /* Fall Through */ 4556 default: 4557 if (hw->media_type == e1000_media_type_fiber) { 4558 ledctl = er32(LEDCTL); 4559 /* Save current LEDCTL settings */ 4560 hw->ledctl_default = ledctl; 4561 /* Turn off LED0 */ 4562 ledctl &= ~(E1000_LEDCTL_LED0_IVRT | 4563 E1000_LEDCTL_LED0_BLINK | 4564 E1000_LEDCTL_LED0_MODE_MASK); 4565 ledctl |= (E1000_LEDCTL_MODE_LED_OFF << 4566 E1000_LEDCTL_LED0_MODE_SHIFT); 4567 ew32(LEDCTL, ledctl); 4568 } else if (hw->media_type == e1000_media_type_copper) 4569 ew32(LEDCTL, hw->ledctl_mode1); 4570 break; 4571 } 4572 4573 return E1000_SUCCESS; 4574 } 4575 4576 /** 4577 * e1000_cleanup_led - Restores the saved state of the SW controlable LED. 4578 * @hw: Struct containing variables accessed by shared code 4579 */ 4580 s32 e1000_cleanup_led(struct e1000_hw *hw) 4581 { 4582 s32 ret_val = E1000_SUCCESS; 4583 4584 switch (hw->mac_type) { 4585 case e1000_82542_rev2_0: 4586 case e1000_82542_rev2_1: 4587 case e1000_82543: 4588 case e1000_82544: 4589 /* No cleanup necessary */ 4590 break; 4591 case e1000_82541: 4592 case e1000_82547: 4593 case e1000_82541_rev_2: 4594 case e1000_82547_rev_2: 4595 /* Turn on PHY Smart Power Down (if previously enabled) */ 4596 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, 4597 hw->phy_spd_default); 4598 if (ret_val) 4599 return ret_val; 4600 /* Fall Through */ 4601 default: 4602 /* Restore LEDCTL settings */ 4603 ew32(LEDCTL, hw->ledctl_default); 4604 break; 4605 } 4606 4607 return E1000_SUCCESS; 4608 } 4609 4610 /** 4611 * e1000_led_on - Turns on the software controllable LED 4612 * @hw: Struct containing variables accessed by shared code 4613 */ 4614 s32 e1000_led_on(struct e1000_hw *hw) 4615 { 4616 u32 ctrl = er32(CTRL); 4617 4618 switch (hw->mac_type) { 4619 case e1000_82542_rev2_0: 4620 case e1000_82542_rev2_1: 4621 case e1000_82543: 4622 /* Set SW Defineable Pin 0 to turn on the LED */ 4623 ctrl |= E1000_CTRL_SWDPIN0; 4624 ctrl |= E1000_CTRL_SWDPIO0; 4625 break; 4626 case e1000_82544: 4627 if (hw->media_type == e1000_media_type_fiber) { 4628 /* Set SW Defineable Pin 0 to turn on the LED */ 4629 ctrl |= E1000_CTRL_SWDPIN0; 4630 ctrl |= E1000_CTRL_SWDPIO0; 4631 } else { 4632 /* Clear SW Defineable Pin 0 to turn on the LED */ 4633 ctrl &= ~E1000_CTRL_SWDPIN0; 4634 ctrl |= E1000_CTRL_SWDPIO0; 4635 } 4636 break; 4637 default: 4638 if (hw->media_type == e1000_media_type_fiber) { 4639 /* Clear SW Defineable Pin 0 to turn on the LED */ 4640 ctrl &= ~E1000_CTRL_SWDPIN0; 4641 ctrl |= E1000_CTRL_SWDPIO0; 4642 } else if (hw->media_type == e1000_media_type_copper) { 4643 ew32(LEDCTL, hw->ledctl_mode2); 4644 return E1000_SUCCESS; 4645 } 4646 break; 4647 } 4648 4649 ew32(CTRL, ctrl); 4650 4651 return E1000_SUCCESS; 4652 } 4653 4654 /** 4655 * e1000_led_off - Turns off the software controllable LED 4656 * @hw: Struct containing variables accessed by shared code 4657 */ 4658 s32 e1000_led_off(struct e1000_hw *hw) 4659 { 4660 u32 ctrl = er32(CTRL); 4661 4662 switch (hw->mac_type) { 4663 case e1000_82542_rev2_0: 4664 case e1000_82542_rev2_1: 4665 case e1000_82543: 4666 /* Clear SW Defineable Pin 0 to turn off the LED */ 4667 ctrl &= ~E1000_CTRL_SWDPIN0; 4668 ctrl |= E1000_CTRL_SWDPIO0; 4669 break; 4670 case e1000_82544: 4671 if (hw->media_type == e1000_media_type_fiber) { 4672 /* Clear SW Defineable Pin 0 to turn off the LED */ 4673 ctrl &= ~E1000_CTRL_SWDPIN0; 4674 ctrl |= E1000_CTRL_SWDPIO0; 4675 } else { 4676 /* Set SW Defineable Pin 0 to turn off the LED */ 4677 ctrl |= E1000_CTRL_SWDPIN0; 4678 ctrl |= E1000_CTRL_SWDPIO0; 4679 } 4680 break; 4681 default: 4682 if (hw->media_type == e1000_media_type_fiber) { 4683 /* Set SW Defineable Pin 0 to turn off the LED */ 4684 ctrl |= E1000_CTRL_SWDPIN0; 4685 ctrl |= E1000_CTRL_SWDPIO0; 4686 } else if (hw->media_type == e1000_media_type_copper) { 4687 ew32(LEDCTL, hw->ledctl_mode1); 4688 return E1000_SUCCESS; 4689 } 4690 break; 4691 } 4692 4693 ew32(CTRL, ctrl); 4694 4695 return E1000_SUCCESS; 4696 } 4697 4698 /** 4699 * e1000_clear_hw_cntrs - Clears all hardware statistics counters. 4700 * @hw: Struct containing variables accessed by shared code 4701 */ 4702 static void e1000_clear_hw_cntrs(struct e1000_hw *hw) 4703 { 4704 volatile u32 temp; 4705 4706 temp = er32(CRCERRS); 4707 temp = er32(SYMERRS); 4708 temp = er32(MPC); 4709 temp = er32(SCC); 4710 temp = er32(ECOL); 4711 temp = er32(MCC); 4712 temp = er32(LATECOL); 4713 temp = er32(COLC); 4714 temp = er32(DC); 4715 temp = er32(SEC); 4716 temp = er32(RLEC); 4717 temp = er32(XONRXC); 4718 temp = er32(XONTXC); 4719 temp = er32(XOFFRXC); 4720 temp = er32(XOFFTXC); 4721 temp = er32(FCRUC); 4722 4723 temp = er32(PRC64); 4724 temp = er32(PRC127); 4725 temp = er32(PRC255); 4726 temp = er32(PRC511); 4727 temp = er32(PRC1023); 4728 temp = er32(PRC1522); 4729 4730 temp = er32(GPRC); 4731 temp = er32(BPRC); 4732 temp = er32(MPRC); 4733 temp = er32(GPTC); 4734 temp = er32(GORCL); 4735 temp = er32(GORCH); 4736 temp = er32(GOTCL); 4737 temp = er32(GOTCH); 4738 temp = er32(RNBC); 4739 temp = er32(RUC); 4740 temp = er32(RFC); 4741 temp = er32(ROC); 4742 temp = er32(RJC); 4743 temp = er32(TORL); 4744 temp = er32(TORH); 4745 temp = er32(TOTL); 4746 temp = er32(TOTH); 4747 temp = er32(TPR); 4748 temp = er32(TPT); 4749 4750 temp = er32(PTC64); 4751 temp = er32(PTC127); 4752 temp = er32(PTC255); 4753 temp = er32(PTC511); 4754 temp = er32(PTC1023); 4755 temp = er32(PTC1522); 4756 4757 temp = er32(MPTC); 4758 temp = er32(BPTC); 4759 4760 if (hw->mac_type < e1000_82543) 4761 return; 4762 4763 temp = er32(ALGNERRC); 4764 temp = er32(RXERRC); 4765 temp = er32(TNCRS); 4766 temp = er32(CEXTERR); 4767 temp = er32(TSCTC); 4768 temp = er32(TSCTFC); 4769 4770 if (hw->mac_type <= e1000_82544) 4771 return; 4772 4773 temp = er32(MGTPRC); 4774 temp = er32(MGTPDC); 4775 temp = er32(MGTPTC); 4776 } 4777 4778 /** 4779 * e1000_reset_adaptive - Resets Adaptive IFS to its default state. 4780 * @hw: Struct containing variables accessed by shared code 4781 * 4782 * Call this after e1000_init_hw. You may override the IFS defaults by setting 4783 * hw->ifs_params_forced to true. However, you must initialize hw-> 4784 * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio 4785 * before calling this function. 4786 */ 4787 void e1000_reset_adaptive(struct e1000_hw *hw) 4788 { 4789 if (hw->adaptive_ifs) { 4790 if (!hw->ifs_params_forced) { 4791 hw->current_ifs_val = 0; 4792 hw->ifs_min_val = IFS_MIN; 4793 hw->ifs_max_val = IFS_MAX; 4794 hw->ifs_step_size = IFS_STEP; 4795 hw->ifs_ratio = IFS_RATIO; 4796 } 4797 hw->in_ifs_mode = false; 4798 ew32(AIT, 0); 4799 } else { 4800 e_dbg("Not in Adaptive IFS mode!\n"); 4801 } 4802 } 4803 4804 /** 4805 * e1000_update_adaptive - update adaptive IFS 4806 * @hw: Struct containing variables accessed by shared code 4807 * @tx_packets: Number of transmits since last callback 4808 * @total_collisions: Number of collisions since last callback 4809 * 4810 * Called during the callback/watchdog routine to update IFS value based on 4811 * the ratio of transmits to collisions. 4812 */ 4813 void e1000_update_adaptive(struct e1000_hw *hw) 4814 { 4815 if (hw->adaptive_ifs) { 4816 if ((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) { 4817 if (hw->tx_packet_delta > MIN_NUM_XMITS) { 4818 hw->in_ifs_mode = true; 4819 if (hw->current_ifs_val < hw->ifs_max_val) { 4820 if (hw->current_ifs_val == 0) 4821 hw->current_ifs_val = 4822 hw->ifs_min_val; 4823 else 4824 hw->current_ifs_val += 4825 hw->ifs_step_size; 4826 ew32(AIT, hw->current_ifs_val); 4827 } 4828 } 4829 } else { 4830 if (hw->in_ifs_mode && 4831 (hw->tx_packet_delta <= MIN_NUM_XMITS)) { 4832 hw->current_ifs_val = 0; 4833 hw->in_ifs_mode = false; 4834 ew32(AIT, 0); 4835 } 4836 } 4837 } else { 4838 e_dbg("Not in Adaptive IFS mode!\n"); 4839 } 4840 } 4841 4842 /** 4843 * e1000_get_bus_info 4844 * @hw: Struct containing variables accessed by shared code 4845 * 4846 * Gets the current PCI bus type, speed, and width of the hardware 4847 */ 4848 void e1000_get_bus_info(struct e1000_hw *hw) 4849 { 4850 u32 status; 4851 4852 switch (hw->mac_type) { 4853 case e1000_82542_rev2_0: 4854 case e1000_82542_rev2_1: 4855 hw->bus_type = e1000_bus_type_pci; 4856 hw->bus_speed = e1000_bus_speed_unknown; 4857 hw->bus_width = e1000_bus_width_unknown; 4858 break; 4859 default: 4860 status = er32(STATUS); 4861 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ? 4862 e1000_bus_type_pcix : e1000_bus_type_pci; 4863 4864 if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) { 4865 hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ? 4866 e1000_bus_speed_66 : e1000_bus_speed_120; 4867 } else if (hw->bus_type == e1000_bus_type_pci) { 4868 hw->bus_speed = (status & E1000_STATUS_PCI66) ? 4869 e1000_bus_speed_66 : e1000_bus_speed_33; 4870 } else { 4871 switch (status & E1000_STATUS_PCIX_SPEED) { 4872 case E1000_STATUS_PCIX_SPEED_66: 4873 hw->bus_speed = e1000_bus_speed_66; 4874 break; 4875 case E1000_STATUS_PCIX_SPEED_100: 4876 hw->bus_speed = e1000_bus_speed_100; 4877 break; 4878 case E1000_STATUS_PCIX_SPEED_133: 4879 hw->bus_speed = e1000_bus_speed_133; 4880 break; 4881 default: 4882 hw->bus_speed = e1000_bus_speed_reserved; 4883 break; 4884 } 4885 } 4886 hw->bus_width = (status & E1000_STATUS_BUS64) ? 4887 e1000_bus_width_64 : e1000_bus_width_32; 4888 break; 4889 } 4890 } 4891 4892 /** 4893 * e1000_write_reg_io 4894 * @hw: Struct containing variables accessed by shared code 4895 * @offset: offset to write to 4896 * @value: value to write 4897 * 4898 * Writes a value to one of the devices registers using port I/O (as opposed to 4899 * memory mapped I/O). Only 82544 and newer devices support port I/O. 4900 */ 4901 static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value) 4902 { 4903 unsigned long io_addr = hw->io_base; 4904 unsigned long io_data = hw->io_base + 4; 4905 4906 e1000_io_write(hw, io_addr, offset); 4907 e1000_io_write(hw, io_data, value); 4908 } 4909 4910 /** 4911 * e1000_get_cable_length - Estimates the cable length. 4912 * @hw: Struct containing variables accessed by shared code 4913 * @min_length: The estimated minimum length 4914 * @max_length: The estimated maximum length 4915 * 4916 * returns: - E1000_ERR_XXX 4917 * E1000_SUCCESS 4918 * 4919 * This function always returns a ranged length (minimum & maximum). 4920 * So for M88 phy's, this function interprets the one value returned from the 4921 * register to the minimum and maximum range. 4922 * For IGP phy's, the function calculates the range by the AGC registers. 4923 */ 4924 static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length, 4925 u16 *max_length) 4926 { 4927 s32 ret_val; 4928 u16 agc_value = 0; 4929 u16 i, phy_data; 4930 u16 cable_length; 4931 4932 *min_length = *max_length = 0; 4933 4934 /* Use old method for Phy older than IGP */ 4935 if (hw->phy_type == e1000_phy_m88) { 4936 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, 4937 &phy_data); 4938 if (ret_val) 4939 return ret_val; 4940 cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 4941 M88E1000_PSSR_CABLE_LENGTH_SHIFT; 4942 4943 /* Convert the enum value to ranged values */ 4944 switch (cable_length) { 4945 case e1000_cable_length_50: 4946 *min_length = 0; 4947 *max_length = e1000_igp_cable_length_50; 4948 break; 4949 case e1000_cable_length_50_80: 4950 *min_length = e1000_igp_cable_length_50; 4951 *max_length = e1000_igp_cable_length_80; 4952 break; 4953 case e1000_cable_length_80_110: 4954 *min_length = e1000_igp_cable_length_80; 4955 *max_length = e1000_igp_cable_length_110; 4956 break; 4957 case e1000_cable_length_110_140: 4958 *min_length = e1000_igp_cable_length_110; 4959 *max_length = e1000_igp_cable_length_140; 4960 break; 4961 case e1000_cable_length_140: 4962 *min_length = e1000_igp_cable_length_140; 4963 *max_length = e1000_igp_cable_length_170; 4964 break; 4965 default: 4966 return -E1000_ERR_PHY; 4967 } 4968 } else if (hw->phy_type == e1000_phy_igp) { /* For IGP PHY */ 4969 u16 cur_agc_value; 4970 u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE; 4971 static const u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = { 4972 IGP01E1000_PHY_AGC_A, 4973 IGP01E1000_PHY_AGC_B, 4974 IGP01E1000_PHY_AGC_C, 4975 IGP01E1000_PHY_AGC_D 4976 }; 4977 /* Read the AGC registers for all channels */ 4978 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 4979 ret_val = 4980 e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data); 4981 if (ret_val) 4982 return ret_val; 4983 4984 cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT; 4985 4986 /* Value bound check. */ 4987 if ((cur_agc_value >= 4988 IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) || 4989 (cur_agc_value == 0)) 4990 return -E1000_ERR_PHY; 4991 4992 agc_value += cur_agc_value; 4993 4994 /* Update minimal AGC value. */ 4995 if (min_agc_value > cur_agc_value) 4996 min_agc_value = cur_agc_value; 4997 } 4998 4999 /* Remove the minimal AGC result for length < 50m */ 5000 if (agc_value < 5001 IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) { 5002 agc_value -= min_agc_value; 5003 5004 /* Get the average length of the remaining 3 channels */ 5005 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1); 5006 } else { 5007 /* Get the average length of all the 4 channels. */ 5008 agc_value /= IGP01E1000_PHY_CHANNEL_NUM; 5009 } 5010 5011 /* Set the range of the calculated length. */ 5012 *min_length = ((e1000_igp_cable_length_table[agc_value] - 5013 IGP01E1000_AGC_RANGE) > 0) ? 5014 (e1000_igp_cable_length_table[agc_value] - 5015 IGP01E1000_AGC_RANGE) : 0; 5016 *max_length = e1000_igp_cable_length_table[agc_value] + 5017 IGP01E1000_AGC_RANGE; 5018 } 5019 5020 return E1000_SUCCESS; 5021 } 5022 5023 /** 5024 * e1000_check_polarity - Check the cable polarity 5025 * @hw: Struct containing variables accessed by shared code 5026 * @polarity: output parameter : 0 - Polarity is not reversed 5027 * 1 - Polarity is reversed. 5028 * 5029 * returns: - E1000_ERR_XXX 5030 * E1000_SUCCESS 5031 * 5032 * For phy's older than IGP, this function simply reads the polarity bit in the 5033 * Phy Status register. For IGP phy's, this bit is valid only if link speed is 5034 * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will 5035 * return 0. If the link speed is 1000 Mbps the polarity status is in the 5036 * IGP01E1000_PHY_PCS_INIT_REG. 5037 */ 5038 static s32 e1000_check_polarity(struct e1000_hw *hw, 5039 e1000_rev_polarity *polarity) 5040 { 5041 s32 ret_val; 5042 u16 phy_data; 5043 5044 if (hw->phy_type == e1000_phy_m88) { 5045 /* return the Polarity bit in the Status register. */ 5046 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, 5047 &phy_data); 5048 if (ret_val) 5049 return ret_val; 5050 *polarity = ((phy_data & M88E1000_PSSR_REV_POLARITY) >> 5051 M88E1000_PSSR_REV_POLARITY_SHIFT) ? 5052 e1000_rev_polarity_reversed : e1000_rev_polarity_normal; 5053 5054 } else if (hw->phy_type == e1000_phy_igp) { 5055 /* Read the Status register to check the speed */ 5056 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, 5057 &phy_data); 5058 if (ret_val) 5059 return ret_val; 5060 5061 /* If speed is 1000 Mbps, must read the 5062 * IGP01E1000_PHY_PCS_INIT_REG to find the polarity status 5063 */ 5064 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) == 5065 IGP01E1000_PSSR_SPEED_1000MBPS) { 5066 /* Read the GIG initialization PCS register (0x00B4) */ 5067 ret_val = 5068 e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG, 5069 &phy_data); 5070 if (ret_val) 5071 return ret_val; 5072 5073 /* Check the polarity bits */ 5074 *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ? 5075 e1000_rev_polarity_reversed : 5076 e1000_rev_polarity_normal; 5077 } else { 5078 /* For 10 Mbps, read the polarity bit in the status 5079 * register. (for 100 Mbps this bit is always 0) 5080 */ 5081 *polarity = 5082 (phy_data & IGP01E1000_PSSR_POLARITY_REVERSED) ? 5083 e1000_rev_polarity_reversed : 5084 e1000_rev_polarity_normal; 5085 } 5086 } 5087 return E1000_SUCCESS; 5088 } 5089 5090 /** 5091 * e1000_check_downshift - Check if Downshift occurred 5092 * @hw: Struct containing variables accessed by shared code 5093 * @downshift: output parameter : 0 - No Downshift occurred. 5094 * 1 - Downshift occurred. 5095 * 5096 * returns: - E1000_ERR_XXX 5097 * E1000_SUCCESS 5098 * 5099 * For phy's older than IGP, this function reads the Downshift bit in the Phy 5100 * Specific Status register. For IGP phy's, it reads the Downgrade bit in the 5101 * Link Health register. In IGP this bit is latched high, so the driver must 5102 * read it immediately after link is established. 5103 */ 5104 static s32 e1000_check_downshift(struct e1000_hw *hw) 5105 { 5106 s32 ret_val; 5107 u16 phy_data; 5108 5109 if (hw->phy_type == e1000_phy_igp) { 5110 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH, 5111 &phy_data); 5112 if (ret_val) 5113 return ret_val; 5114 5115 hw->speed_downgraded = 5116 (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0; 5117 } else if (hw->phy_type == e1000_phy_m88) { 5118 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, 5119 &phy_data); 5120 if (ret_val) 5121 return ret_val; 5122 5123 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >> 5124 M88E1000_PSSR_DOWNSHIFT_SHIFT; 5125 } 5126 5127 return E1000_SUCCESS; 5128 } 5129 5130 static const u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = { 5131 IGP01E1000_PHY_AGC_PARAM_A, 5132 IGP01E1000_PHY_AGC_PARAM_B, 5133 IGP01E1000_PHY_AGC_PARAM_C, 5134 IGP01E1000_PHY_AGC_PARAM_D 5135 }; 5136 5137 static s32 e1000_1000Mb_check_cable_length(struct e1000_hw *hw) 5138 { 5139 u16 min_length, max_length; 5140 u16 phy_data, i; 5141 s32 ret_val; 5142 5143 ret_val = e1000_get_cable_length(hw, &min_length, &max_length); 5144 if (ret_val) 5145 return ret_val; 5146 5147 if (hw->dsp_config_state != e1000_dsp_config_enabled) 5148 return 0; 5149 5150 if (min_length >= e1000_igp_cable_length_50) { 5151 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 5152 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], 5153 &phy_data); 5154 if (ret_val) 5155 return ret_val; 5156 5157 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; 5158 5159 ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i], 5160 phy_data); 5161 if (ret_val) 5162 return ret_val; 5163 } 5164 hw->dsp_config_state = e1000_dsp_config_activated; 5165 } else { 5166 u16 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20; 5167 u32 idle_errs = 0; 5168 5169 /* clear previous idle error counts */ 5170 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); 5171 if (ret_val) 5172 return ret_val; 5173 5174 for (i = 0; i < ffe_idle_err_timeout; i++) { 5175 udelay(1000); 5176 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, 5177 &phy_data); 5178 if (ret_val) 5179 return ret_val; 5180 5181 idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT); 5182 if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) { 5183 hw->ffe_config_state = e1000_ffe_config_active; 5184 5185 ret_val = e1000_write_phy_reg(hw, 5186 IGP01E1000_PHY_DSP_FFE, 5187 IGP01E1000_PHY_DSP_FFE_CM_CP); 5188 if (ret_val) 5189 return ret_val; 5190 break; 5191 } 5192 5193 if (idle_errs) 5194 ffe_idle_err_timeout = 5195 FFE_IDLE_ERR_COUNT_TIMEOUT_100; 5196 } 5197 } 5198 5199 return 0; 5200 } 5201 5202 /** 5203 * e1000_config_dsp_after_link_change 5204 * @hw: Struct containing variables accessed by shared code 5205 * @link_up: was link up at the time this was called 5206 * 5207 * returns: - E1000_ERR_PHY if fail to read/write the PHY 5208 * E1000_SUCCESS at any other case. 5209 * 5210 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a 5211 * gigabit link is achieved to improve link quality. 5212 */ 5213 5214 static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, bool link_up) 5215 { 5216 s32 ret_val; 5217 u16 phy_data, phy_saved_data, speed, duplex, i; 5218 5219 if (hw->phy_type != e1000_phy_igp) 5220 return E1000_SUCCESS; 5221 5222 if (link_up) { 5223 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); 5224 if (ret_val) { 5225 e_dbg("Error getting link speed and duplex\n"); 5226 return ret_val; 5227 } 5228 5229 if (speed == SPEED_1000) { 5230 ret_val = e1000_1000Mb_check_cable_length(hw); 5231 if (ret_val) 5232 return ret_val; 5233 } 5234 } else { 5235 if (hw->dsp_config_state == e1000_dsp_config_activated) { 5236 /* Save off the current value of register 0x2F5B to be 5237 * restored at the end of the routines. 5238 */ 5239 ret_val = 5240 e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 5241 5242 if (ret_val) 5243 return ret_val; 5244 5245 /* Disable the PHY transmitter */ 5246 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003); 5247 5248 if (ret_val) 5249 return ret_val; 5250 5251 msleep(20); 5252 5253 ret_val = e1000_write_phy_reg(hw, 0x0000, 5254 IGP01E1000_IEEE_FORCE_GIGA); 5255 if (ret_val) 5256 return ret_val; 5257 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 5258 ret_val = 5259 e1000_read_phy_reg(hw, dsp_reg_array[i], 5260 &phy_data); 5261 if (ret_val) 5262 return ret_val; 5263 5264 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; 5265 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS; 5266 5267 ret_val = 5268 e1000_write_phy_reg(hw, dsp_reg_array[i], 5269 phy_data); 5270 if (ret_val) 5271 return ret_val; 5272 } 5273 5274 ret_val = e1000_write_phy_reg(hw, 0x0000, 5275 IGP01E1000_IEEE_RESTART_AUTONEG); 5276 if (ret_val) 5277 return ret_val; 5278 5279 msleep(20); 5280 5281 /* Now enable the transmitter */ 5282 ret_val = 5283 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); 5284 5285 if (ret_val) 5286 return ret_val; 5287 5288 hw->dsp_config_state = e1000_dsp_config_enabled; 5289 } 5290 5291 if (hw->ffe_config_state == e1000_ffe_config_active) { 5292 /* Save off the current value of register 0x2F5B to be 5293 * restored at the end of the routines. 5294 */ 5295 ret_val = 5296 e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 5297 5298 if (ret_val) 5299 return ret_val; 5300 5301 /* Disable the PHY transmitter */ 5302 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003); 5303 5304 if (ret_val) 5305 return ret_val; 5306 5307 msleep(20); 5308 5309 ret_val = e1000_write_phy_reg(hw, 0x0000, 5310 IGP01E1000_IEEE_FORCE_GIGA); 5311 if (ret_val) 5312 return ret_val; 5313 ret_val = 5314 e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE, 5315 IGP01E1000_PHY_DSP_FFE_DEFAULT); 5316 if (ret_val) 5317 return ret_val; 5318 5319 ret_val = e1000_write_phy_reg(hw, 0x0000, 5320 IGP01E1000_IEEE_RESTART_AUTONEG); 5321 if (ret_val) 5322 return ret_val; 5323 5324 msleep(20); 5325 5326 /* Now enable the transmitter */ 5327 ret_val = 5328 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); 5329 5330 if (ret_val) 5331 return ret_val; 5332 5333 hw->ffe_config_state = e1000_ffe_config_enabled; 5334 } 5335 } 5336 return E1000_SUCCESS; 5337 } 5338 5339 /** 5340 * e1000_set_phy_mode - Set PHY to class A mode 5341 * @hw: Struct containing variables accessed by shared code 5342 * 5343 * Assumes the following operations will follow to enable the new class mode. 5344 * 1. Do a PHY soft reset 5345 * 2. Restart auto-negotiation or force link. 5346 */ 5347 static s32 e1000_set_phy_mode(struct e1000_hw *hw) 5348 { 5349 s32 ret_val; 5350 u16 eeprom_data; 5351 5352 if ((hw->mac_type == e1000_82545_rev_3) && 5353 (hw->media_type == e1000_media_type_copper)) { 5354 ret_val = 5355 e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, 5356 &eeprom_data); 5357 if (ret_val) 5358 return ret_val; 5359 5360 if ((eeprom_data != EEPROM_RESERVED_WORD) && 5361 (eeprom_data & EEPROM_PHY_CLASS_A)) { 5362 ret_val = 5363 e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 5364 0x000B); 5365 if (ret_val) 5366 return ret_val; 5367 ret_val = 5368 e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 5369 0x8104); 5370 if (ret_val) 5371 return ret_val; 5372 5373 hw->phy_reset_disable = false; 5374 } 5375 } 5376 5377 return E1000_SUCCESS; 5378 } 5379 5380 /** 5381 * e1000_set_d3_lplu_state - set d3 link power state 5382 * @hw: Struct containing variables accessed by shared code 5383 * @active: true to enable lplu false to disable lplu. 5384 * 5385 * This function sets the lplu state according to the active flag. When 5386 * activating lplu this function also disables smart speed and vise versa. 5387 * lplu will not be activated unless the device autonegotiation advertisement 5388 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. 5389 * 5390 * returns: - E1000_ERR_PHY if fail to read/write the PHY 5391 * E1000_SUCCESS at any other case. 5392 */ 5393 static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active) 5394 { 5395 s32 ret_val; 5396 u16 phy_data; 5397 5398 if (hw->phy_type != e1000_phy_igp) 5399 return E1000_SUCCESS; 5400 5401 /* During driver activity LPLU should not be used or it will attain link 5402 * from the lowest speeds starting from 10Mbps. The capability is used 5403 * for Dx transitions and states 5404 */ 5405 if (hw->mac_type == e1000_82541_rev_2 || 5406 hw->mac_type == e1000_82547_rev_2) { 5407 ret_val = 5408 e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data); 5409 if (ret_val) 5410 return ret_val; 5411 } 5412 5413 if (!active) { 5414 if (hw->mac_type == e1000_82541_rev_2 || 5415 hw->mac_type == e1000_82547_rev_2) { 5416 phy_data &= ~IGP01E1000_GMII_FLEX_SPD; 5417 ret_val = 5418 e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, 5419 phy_data); 5420 if (ret_val) 5421 return ret_val; 5422 } 5423 5424 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 5425 * during Dx states where the power conservation is most 5426 * important. During driver activity we should enable 5427 * SmartSpeed, so performance is maintained. 5428 */ 5429 if (hw->smart_speed == e1000_smart_speed_on) { 5430 ret_val = 5431 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 5432 &phy_data); 5433 if (ret_val) 5434 return ret_val; 5435 5436 phy_data |= IGP01E1000_PSCFR_SMART_SPEED; 5437 ret_val = 5438 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 5439 phy_data); 5440 if (ret_val) 5441 return ret_val; 5442 } else if (hw->smart_speed == e1000_smart_speed_off) { 5443 ret_val = 5444 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 5445 &phy_data); 5446 if (ret_val) 5447 return ret_val; 5448 5449 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 5450 ret_val = 5451 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 5452 phy_data); 5453 if (ret_val) 5454 return ret_val; 5455 } 5456 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) || 5457 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) || 5458 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) { 5459 if (hw->mac_type == e1000_82541_rev_2 || 5460 hw->mac_type == e1000_82547_rev_2) { 5461 phy_data |= IGP01E1000_GMII_FLEX_SPD; 5462 ret_val = 5463 e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, 5464 phy_data); 5465 if (ret_val) 5466 return ret_val; 5467 } 5468 5469 /* When LPLU is enabled we should disable SmartSpeed */ 5470 ret_val = 5471 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 5472 &phy_data); 5473 if (ret_val) 5474 return ret_val; 5475 5476 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 5477 ret_val = 5478 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 5479 phy_data); 5480 if (ret_val) 5481 return ret_val; 5482 } 5483 return E1000_SUCCESS; 5484 } 5485 5486 /** 5487 * e1000_set_vco_speed 5488 * @hw: Struct containing variables accessed by shared code 5489 * 5490 * Change VCO speed register to improve Bit Error Rate performance of SERDES. 5491 */ 5492 static s32 e1000_set_vco_speed(struct e1000_hw *hw) 5493 { 5494 s32 ret_val; 5495 u16 default_page = 0; 5496 u16 phy_data; 5497 5498 switch (hw->mac_type) { 5499 case e1000_82545_rev_3: 5500 case e1000_82546_rev_3: 5501 break; 5502 default: 5503 return E1000_SUCCESS; 5504 } 5505 5506 /* Set PHY register 30, page 5, bit 8 to 0 */ 5507 5508 ret_val = 5509 e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page); 5510 if (ret_val) 5511 return ret_val; 5512 5513 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005); 5514 if (ret_val) 5515 return ret_val; 5516 5517 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); 5518 if (ret_val) 5519 return ret_val; 5520 5521 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8; 5522 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); 5523 if (ret_val) 5524 return ret_val; 5525 5526 /* Set PHY register 30, page 4, bit 11 to 1 */ 5527 5528 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004); 5529 if (ret_val) 5530 return ret_val; 5531 5532 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); 5533 if (ret_val) 5534 return ret_val; 5535 5536 phy_data |= M88E1000_PHY_VCO_REG_BIT11; 5537 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); 5538 if (ret_val) 5539 return ret_val; 5540 5541 ret_val = 5542 e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page); 5543 if (ret_val) 5544 return ret_val; 5545 5546 return E1000_SUCCESS; 5547 } 5548 5549 /** 5550 * e1000_enable_mng_pass_thru - check for bmc pass through 5551 * @hw: Struct containing variables accessed by shared code 5552 * 5553 * Verifies the hardware needs to allow ARPs to be processed by the host 5554 * returns: - true/false 5555 */ 5556 u32 e1000_enable_mng_pass_thru(struct e1000_hw *hw) 5557 { 5558 u32 manc; 5559 5560 if (hw->asf_firmware_present) { 5561 manc = er32(MANC); 5562 5563 if (!(manc & E1000_MANC_RCV_TCO_EN) || 5564 !(manc & E1000_MANC_EN_MAC_ADDR_FILTER)) 5565 return false; 5566 if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN)) 5567 return true; 5568 } 5569 return false; 5570 } 5571 5572 static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw) 5573 { 5574 s32 ret_val; 5575 u16 mii_status_reg; 5576 u16 i; 5577 5578 /* Polarity reversal workaround for forced 10F/10H links. */ 5579 5580 /* Disable the transmitter on the PHY */ 5581 5582 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 5583 if (ret_val) 5584 return ret_val; 5585 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF); 5586 if (ret_val) 5587 return ret_val; 5588 5589 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 5590 if (ret_val) 5591 return ret_val; 5592 5593 /* This loop will early-out if the NO link condition has been met. */ 5594 for (i = PHY_FORCE_TIME; i > 0; i--) { 5595 /* Read the MII Status Register and wait for Link Status bit 5596 * to be clear. 5597 */ 5598 5599 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 5600 if (ret_val) 5601 return ret_val; 5602 5603 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 5604 if (ret_val) 5605 return ret_val; 5606 5607 if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) 5608 break; 5609 msleep(100); 5610 } 5611 5612 /* Recommended delay time after link has been lost */ 5613 msleep(1000); 5614 5615 /* Now we will re-enable th transmitter on the PHY */ 5616 5617 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 5618 if (ret_val) 5619 return ret_val; 5620 msleep(50); 5621 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0); 5622 if (ret_val) 5623 return ret_val; 5624 msleep(50); 5625 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00); 5626 if (ret_val) 5627 return ret_val; 5628 msleep(50); 5629 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000); 5630 if (ret_val) 5631 return ret_val; 5632 5633 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 5634 if (ret_val) 5635 return ret_val; 5636 5637 /* This loop will early-out if the link condition has been met. */ 5638 for (i = PHY_FORCE_TIME; i > 0; i--) { 5639 /* Read the MII Status Register and wait for Link Status bit 5640 * to be set. 5641 */ 5642 5643 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 5644 if (ret_val) 5645 return ret_val; 5646 5647 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 5648 if (ret_val) 5649 return ret_val; 5650 5651 if (mii_status_reg & MII_SR_LINK_STATUS) 5652 break; 5653 msleep(100); 5654 } 5655 return E1000_SUCCESS; 5656 } 5657 5658 /** 5659 * e1000_get_auto_rd_done 5660 * @hw: Struct containing variables accessed by shared code 5661 * 5662 * Check for EEPROM Auto Read bit done. 5663 * returns: - E1000_ERR_RESET if fail to reset MAC 5664 * E1000_SUCCESS at any other case. 5665 */ 5666 static s32 e1000_get_auto_rd_done(struct e1000_hw *hw) 5667 { 5668 msleep(5); 5669 return E1000_SUCCESS; 5670 } 5671 5672 /** 5673 * e1000_get_phy_cfg_done 5674 * @hw: Struct containing variables accessed by shared code 5675 * 5676 * Checks if the PHY configuration is done 5677 * returns: - E1000_ERR_RESET if fail to reset MAC 5678 * E1000_SUCCESS at any other case. 5679 */ 5680 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw) 5681 { 5682 msleep(10); 5683 return E1000_SUCCESS; 5684 } 5685