1 /* 2 * Copyright © 2012-2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * Daniel Vetter <daniel.vetter@ffwll.ch> 26 * 27 */ 28 29 #include <linux/pm_runtime.h> 30 #include <linux/vgaarb.h> 31 32 #include "i915_drv.h" 33 #include "intel_drv.h" 34 35 /** 36 * DOC: runtime pm 37 * 38 * The i915 driver supports dynamic enabling and disabling of entire hardware 39 * blocks at runtime. This is especially important on the display side where 40 * software is supposed to control many power gates manually on recent hardware, 41 * since on the GT side a lot of the power management is done by the hardware. 42 * But even there some manual control at the device level is required. 43 * 44 * Since i915 supports a diverse set of platforms with a unified codebase and 45 * hardware engineers just love to shuffle functionality around between power 46 * domains there's a sizeable amount of indirection required. This file provides 47 * generic functions to the driver for grabbing and releasing references for 48 * abstract power domains. It then maps those to the actual power wells 49 * present for a given platform. 50 */ 51 52 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv, 53 enum i915_power_well_id power_well_id); 54 55 static struct i915_power_well * 56 lookup_power_well(struct drm_i915_private *dev_priv, 57 enum i915_power_well_id power_well_id); 58 59 const char * 60 intel_display_power_domain_str(enum intel_display_power_domain domain) 61 { 62 switch (domain) { 63 case POWER_DOMAIN_PIPE_A: 64 return "PIPE_A"; 65 case POWER_DOMAIN_PIPE_B: 66 return "PIPE_B"; 67 case POWER_DOMAIN_PIPE_C: 68 return "PIPE_C"; 69 case POWER_DOMAIN_PIPE_A_PANEL_FITTER: 70 return "PIPE_A_PANEL_FITTER"; 71 case POWER_DOMAIN_PIPE_B_PANEL_FITTER: 72 return "PIPE_B_PANEL_FITTER"; 73 case POWER_DOMAIN_PIPE_C_PANEL_FITTER: 74 return "PIPE_C_PANEL_FITTER"; 75 case POWER_DOMAIN_TRANSCODER_A: 76 return "TRANSCODER_A"; 77 case POWER_DOMAIN_TRANSCODER_B: 78 return "TRANSCODER_B"; 79 case POWER_DOMAIN_TRANSCODER_C: 80 return "TRANSCODER_C"; 81 case POWER_DOMAIN_TRANSCODER_EDP: 82 return "TRANSCODER_EDP"; 83 case POWER_DOMAIN_TRANSCODER_DSI_A: 84 return "TRANSCODER_DSI_A"; 85 case POWER_DOMAIN_TRANSCODER_DSI_C: 86 return "TRANSCODER_DSI_C"; 87 case POWER_DOMAIN_PORT_DDI_A_LANES: 88 return "PORT_DDI_A_LANES"; 89 case POWER_DOMAIN_PORT_DDI_B_LANES: 90 return "PORT_DDI_B_LANES"; 91 case POWER_DOMAIN_PORT_DDI_C_LANES: 92 return "PORT_DDI_C_LANES"; 93 case POWER_DOMAIN_PORT_DDI_D_LANES: 94 return "PORT_DDI_D_LANES"; 95 case POWER_DOMAIN_PORT_DDI_E_LANES: 96 return "PORT_DDI_E_LANES"; 97 case POWER_DOMAIN_PORT_DDI_F_LANES: 98 return "PORT_DDI_F_LANES"; 99 case POWER_DOMAIN_PORT_DDI_A_IO: 100 return "PORT_DDI_A_IO"; 101 case POWER_DOMAIN_PORT_DDI_B_IO: 102 return "PORT_DDI_B_IO"; 103 case POWER_DOMAIN_PORT_DDI_C_IO: 104 return "PORT_DDI_C_IO"; 105 case POWER_DOMAIN_PORT_DDI_D_IO: 106 return "PORT_DDI_D_IO"; 107 case POWER_DOMAIN_PORT_DDI_E_IO: 108 return "PORT_DDI_E_IO"; 109 case POWER_DOMAIN_PORT_DDI_F_IO: 110 return "PORT_DDI_F_IO"; 111 case POWER_DOMAIN_PORT_DSI: 112 return "PORT_DSI"; 113 case POWER_DOMAIN_PORT_CRT: 114 return "PORT_CRT"; 115 case POWER_DOMAIN_PORT_OTHER: 116 return "PORT_OTHER"; 117 case POWER_DOMAIN_VGA: 118 return "VGA"; 119 case POWER_DOMAIN_AUDIO: 120 return "AUDIO"; 121 case POWER_DOMAIN_PLLS: 122 return "PLLS"; 123 case POWER_DOMAIN_AUX_A: 124 return "AUX_A"; 125 case POWER_DOMAIN_AUX_B: 126 return "AUX_B"; 127 case POWER_DOMAIN_AUX_C: 128 return "AUX_C"; 129 case POWER_DOMAIN_AUX_D: 130 return "AUX_D"; 131 case POWER_DOMAIN_AUX_F: 132 return "AUX_F"; 133 case POWER_DOMAIN_AUX_IO_A: 134 return "AUX_IO_A"; 135 case POWER_DOMAIN_GMBUS: 136 return "GMBUS"; 137 case POWER_DOMAIN_INIT: 138 return "INIT"; 139 case POWER_DOMAIN_MODESET: 140 return "MODESET"; 141 case POWER_DOMAIN_GT_IRQ: 142 return "GT_IRQ"; 143 default: 144 MISSING_CASE(domain); 145 return "?"; 146 } 147 } 148 149 static void intel_power_well_enable(struct drm_i915_private *dev_priv, 150 struct i915_power_well *power_well) 151 { 152 DRM_DEBUG_KMS("enabling %s\n", power_well->name); 153 power_well->ops->enable(dev_priv, power_well); 154 power_well->hw_enabled = true; 155 } 156 157 static void intel_power_well_disable(struct drm_i915_private *dev_priv, 158 struct i915_power_well *power_well) 159 { 160 DRM_DEBUG_KMS("disabling %s\n", power_well->name); 161 power_well->hw_enabled = false; 162 power_well->ops->disable(dev_priv, power_well); 163 } 164 165 static void intel_power_well_get(struct drm_i915_private *dev_priv, 166 struct i915_power_well *power_well) 167 { 168 if (!power_well->count++) 169 intel_power_well_enable(dev_priv, power_well); 170 } 171 172 static void intel_power_well_put(struct drm_i915_private *dev_priv, 173 struct i915_power_well *power_well) 174 { 175 WARN(!power_well->count, "Use count on power well %s is already zero", 176 power_well->name); 177 178 if (!--power_well->count) 179 intel_power_well_disable(dev_priv, power_well); 180 } 181 182 /** 183 * __intel_display_power_is_enabled - unlocked check for a power domain 184 * @dev_priv: i915 device instance 185 * @domain: power domain to check 186 * 187 * This is the unlocked version of intel_display_power_is_enabled() and should 188 * only be used from error capture and recovery code where deadlocks are 189 * possible. 190 * 191 * Returns: 192 * True when the power domain is enabled, false otherwise. 193 */ 194 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 195 enum intel_display_power_domain domain) 196 { 197 struct i915_power_well *power_well; 198 bool is_enabled; 199 200 if (dev_priv->runtime_pm.suspended) 201 return false; 202 203 is_enabled = true; 204 205 for_each_power_domain_well_rev(dev_priv, power_well, BIT_ULL(domain)) { 206 if (power_well->always_on) 207 continue; 208 209 if (!power_well->hw_enabled) { 210 is_enabled = false; 211 break; 212 } 213 } 214 215 return is_enabled; 216 } 217 218 /** 219 * intel_display_power_is_enabled - check for a power domain 220 * @dev_priv: i915 device instance 221 * @domain: power domain to check 222 * 223 * This function can be used to check the hw power domain state. It is mostly 224 * used in hardware state readout functions. Everywhere else code should rely 225 * upon explicit power domain reference counting to ensure that the hardware 226 * block is powered up before accessing it. 227 * 228 * Callers must hold the relevant modesetting locks to ensure that concurrent 229 * threads can't disable the power well while the caller tries to read a few 230 * registers. 231 * 232 * Returns: 233 * True when the power domain is enabled, false otherwise. 234 */ 235 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 236 enum intel_display_power_domain domain) 237 { 238 struct i915_power_domains *power_domains; 239 bool ret; 240 241 power_domains = &dev_priv->power_domains; 242 243 mutex_lock(&power_domains->lock); 244 ret = __intel_display_power_is_enabled(dev_priv, domain); 245 mutex_unlock(&power_domains->lock); 246 247 return ret; 248 } 249 250 /** 251 * intel_display_set_init_power - set the initial power domain state 252 * @dev_priv: i915 device instance 253 * @enable: whether to enable or disable the initial power domain state 254 * 255 * For simplicity our driver load/unload and system suspend/resume code assumes 256 * that all power domains are always enabled. This functions controls the state 257 * of this little hack. While the initial power domain state is enabled runtime 258 * pm is effectively disabled. 259 */ 260 void intel_display_set_init_power(struct drm_i915_private *dev_priv, 261 bool enable) 262 { 263 if (dev_priv->power_domains.init_power_on == enable) 264 return; 265 266 if (enable) 267 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); 268 else 269 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); 270 271 dev_priv->power_domains.init_power_on = enable; 272 } 273 274 /* 275 * Starting with Haswell, we have a "Power Down Well" that can be turned off 276 * when not needed anymore. We have 4 registers that can request the power well 277 * to be enabled, and it will only be disabled if none of the registers is 278 * requesting it to be enabled. 279 */ 280 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv, 281 u8 irq_pipe_mask, bool has_vga) 282 { 283 struct pci_dev *pdev = dev_priv->drm.pdev; 284 285 /* 286 * After we re-enable the power well, if we touch VGA register 0x3d5 287 * we'll get unclaimed register interrupts. This stops after we write 288 * anything to the VGA MSR register. The vgacon module uses this 289 * register all the time, so if we unbind our driver and, as a 290 * consequence, bind vgacon, we'll get stuck in an infinite loop at 291 * console_unlock(). So make here we touch the VGA MSR register, making 292 * sure vgacon can keep working normally without triggering interrupts 293 * and error messages. 294 */ 295 if (has_vga) { 296 vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO); 297 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE); 298 vga_put(pdev, VGA_RSRC_LEGACY_IO); 299 } 300 301 if (irq_pipe_mask) 302 gen8_irq_power_well_post_enable(dev_priv, irq_pipe_mask); 303 } 304 305 static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv, 306 u8 irq_pipe_mask) 307 { 308 if (irq_pipe_mask) 309 gen8_irq_power_well_pre_disable(dev_priv, irq_pipe_mask); 310 } 311 312 313 static void hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv, 314 struct i915_power_well *power_well) 315 { 316 enum i915_power_well_id id = power_well->id; 317 318 /* Timeout for PW1:10 us, AUX:not specified, other PWs:20 us. */ 319 WARN_ON(intel_wait_for_register(dev_priv, 320 HSW_PWR_WELL_CTL_DRIVER(id), 321 HSW_PWR_WELL_CTL_STATE(id), 322 HSW_PWR_WELL_CTL_STATE(id), 323 1)); 324 } 325 326 static u32 hsw_power_well_requesters(struct drm_i915_private *dev_priv, 327 enum i915_power_well_id id) 328 { 329 u32 req_mask = HSW_PWR_WELL_CTL_REQ(id); 330 u32 ret; 331 332 ret = I915_READ(HSW_PWR_WELL_CTL_BIOS(id)) & req_mask ? 1 : 0; 333 ret |= I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)) & req_mask ? 2 : 0; 334 ret |= I915_READ(HSW_PWR_WELL_CTL_KVMR) & req_mask ? 4 : 0; 335 ret |= I915_READ(HSW_PWR_WELL_CTL_DEBUG(id)) & req_mask ? 8 : 0; 336 337 return ret; 338 } 339 340 static void hsw_wait_for_power_well_disable(struct drm_i915_private *dev_priv, 341 struct i915_power_well *power_well) 342 { 343 enum i915_power_well_id id = power_well->id; 344 bool disabled; 345 u32 reqs; 346 347 /* 348 * Bspec doesn't require waiting for PWs to get disabled, but still do 349 * this for paranoia. The known cases where a PW will be forced on: 350 * - a KVMR request on any power well via the KVMR request register 351 * - a DMC request on PW1 and MISC_IO power wells via the BIOS and 352 * DEBUG request registers 353 * Skip the wait in case any of the request bits are set and print a 354 * diagnostic message. 355 */ 356 wait_for((disabled = !(I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)) & 357 HSW_PWR_WELL_CTL_STATE(id))) || 358 (reqs = hsw_power_well_requesters(dev_priv, id)), 1); 359 if (disabled) 360 return; 361 362 DRM_DEBUG_KMS("%s forced on (bios:%d driver:%d kvmr:%d debug:%d)\n", 363 power_well->name, 364 !!(reqs & 1), !!(reqs & 2), !!(reqs & 4), !!(reqs & 8)); 365 } 366 367 static void gen9_wait_for_power_well_fuses(struct drm_i915_private *dev_priv, 368 enum skl_power_gate pg) 369 { 370 /* Timeout 5us for PG#0, for other PGs 1us */ 371 WARN_ON(intel_wait_for_register(dev_priv, SKL_FUSE_STATUS, 372 SKL_FUSE_PG_DIST_STATUS(pg), 373 SKL_FUSE_PG_DIST_STATUS(pg), 1)); 374 } 375 376 static void hsw_power_well_enable(struct drm_i915_private *dev_priv, 377 struct i915_power_well *power_well) 378 { 379 enum i915_power_well_id id = power_well->id; 380 bool wait_fuses = power_well->hsw.has_fuses; 381 enum skl_power_gate uninitialized_var(pg); 382 u32 val; 383 384 if (wait_fuses) { 385 pg = SKL_PW_TO_PG(id); 386 /* 387 * For PW1 we have to wait both for the PW0/PG0 fuse state 388 * before enabling the power well and PW1/PG1's own fuse 389 * state after the enabling. For all other power wells with 390 * fuses we only have to wait for that PW/PG's fuse state 391 * after the enabling. 392 */ 393 if (pg == SKL_PG1) 394 gen9_wait_for_power_well_fuses(dev_priv, SKL_PG0); 395 } 396 397 val = I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)); 398 I915_WRITE(HSW_PWR_WELL_CTL_DRIVER(id), val | HSW_PWR_WELL_CTL_REQ(id)); 399 hsw_wait_for_power_well_enable(dev_priv, power_well); 400 401 /* Display WA #1178: cnl */ 402 if (IS_CANNONLAKE(dev_priv) && 403 (id == CNL_DISP_PW_AUX_B || id == CNL_DISP_PW_AUX_C || 404 id == CNL_DISP_PW_AUX_D || id == CNL_DISP_PW_AUX_F)) { 405 val = I915_READ(CNL_AUX_ANAOVRD1(id)); 406 val |= CNL_AUX_ANAOVRD1_ENABLE | CNL_AUX_ANAOVRD1_LDO_BYPASS; 407 I915_WRITE(CNL_AUX_ANAOVRD1(id), val); 408 } 409 410 if (wait_fuses) 411 gen9_wait_for_power_well_fuses(dev_priv, pg); 412 413 hsw_power_well_post_enable(dev_priv, power_well->hsw.irq_pipe_mask, 414 power_well->hsw.has_vga); 415 } 416 417 static void hsw_power_well_disable(struct drm_i915_private *dev_priv, 418 struct i915_power_well *power_well) 419 { 420 enum i915_power_well_id id = power_well->id; 421 u32 val; 422 423 hsw_power_well_pre_disable(dev_priv, power_well->hsw.irq_pipe_mask); 424 425 val = I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)); 426 I915_WRITE(HSW_PWR_WELL_CTL_DRIVER(id), 427 val & ~HSW_PWR_WELL_CTL_REQ(id)); 428 hsw_wait_for_power_well_disable(dev_priv, power_well); 429 } 430 431 /* 432 * We should only use the power well if we explicitly asked the hardware to 433 * enable it, so check if it's enabled and also check if we've requested it to 434 * be enabled. 435 */ 436 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv, 437 struct i915_power_well *power_well) 438 { 439 enum i915_power_well_id id = power_well->id; 440 u32 mask = HSW_PWR_WELL_CTL_REQ(id) | HSW_PWR_WELL_CTL_STATE(id); 441 442 return (I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)) & mask) == mask; 443 } 444 445 static void assert_can_enable_dc9(struct drm_i915_private *dev_priv) 446 { 447 enum i915_power_well_id id = SKL_DISP_PW_2; 448 449 WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9), 450 "DC9 already programmed to be enabled.\n"); 451 WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5, 452 "DC5 still not disabled to enable DC9.\n"); 453 WARN_ONCE(I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)) & 454 HSW_PWR_WELL_CTL_REQ(id), 455 "Power well 2 on.\n"); 456 WARN_ONCE(intel_irqs_enabled(dev_priv), 457 "Interrupts not disabled yet.\n"); 458 459 /* 460 * TODO: check for the following to verify the conditions to enter DC9 461 * state are satisfied: 462 * 1] Check relevant display engine registers to verify if mode set 463 * disable sequence was followed. 464 * 2] Check if display uninitialize sequence is initialized. 465 */ 466 } 467 468 static void assert_can_disable_dc9(struct drm_i915_private *dev_priv) 469 { 470 WARN_ONCE(intel_irqs_enabled(dev_priv), 471 "Interrupts not disabled yet.\n"); 472 WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5, 473 "DC5 still not disabled.\n"); 474 475 /* 476 * TODO: check for the following to verify DC9 state was indeed 477 * entered before programming to disable it: 478 * 1] Check relevant display engine registers to verify if mode 479 * set disable sequence was followed. 480 * 2] Check if display uninitialize sequence is initialized. 481 */ 482 } 483 484 static void gen9_write_dc_state(struct drm_i915_private *dev_priv, 485 u32 state) 486 { 487 int rewrites = 0; 488 int rereads = 0; 489 u32 v; 490 491 I915_WRITE(DC_STATE_EN, state); 492 493 /* It has been observed that disabling the dc6 state sometimes 494 * doesn't stick and dmc keeps returning old value. Make sure 495 * the write really sticks enough times and also force rewrite until 496 * we are confident that state is exactly what we want. 497 */ 498 do { 499 v = I915_READ(DC_STATE_EN); 500 501 if (v != state) { 502 I915_WRITE(DC_STATE_EN, state); 503 rewrites++; 504 rereads = 0; 505 } else if (rereads++ > 5) { 506 break; 507 } 508 509 } while (rewrites < 100); 510 511 if (v != state) 512 DRM_ERROR("Writing dc state to 0x%x failed, now 0x%x\n", 513 state, v); 514 515 /* Most of the times we need one retry, avoid spam */ 516 if (rewrites > 1) 517 DRM_DEBUG_KMS("Rewrote dc state to 0x%x %d times\n", 518 state, rewrites); 519 } 520 521 static u32 gen9_dc_mask(struct drm_i915_private *dev_priv) 522 { 523 u32 mask; 524 525 mask = DC_STATE_EN_UPTO_DC5; 526 if (IS_GEN9_LP(dev_priv)) 527 mask |= DC_STATE_EN_DC9; 528 else 529 mask |= DC_STATE_EN_UPTO_DC6; 530 531 return mask; 532 } 533 534 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv) 535 { 536 u32 val; 537 538 val = I915_READ(DC_STATE_EN) & gen9_dc_mask(dev_priv); 539 540 DRM_DEBUG_KMS("Resetting DC state tracking from %02x to %02x\n", 541 dev_priv->csr.dc_state, val); 542 dev_priv->csr.dc_state = val; 543 } 544 545 static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state) 546 { 547 uint32_t val; 548 uint32_t mask; 549 550 if (WARN_ON_ONCE(state & ~dev_priv->csr.allowed_dc_mask)) 551 state &= dev_priv->csr.allowed_dc_mask; 552 553 val = I915_READ(DC_STATE_EN); 554 mask = gen9_dc_mask(dev_priv); 555 DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n", 556 val & mask, state); 557 558 /* Check if DMC is ignoring our DC state requests */ 559 if ((val & mask) != dev_priv->csr.dc_state) 560 DRM_ERROR("DC state mismatch (0x%x -> 0x%x)\n", 561 dev_priv->csr.dc_state, val & mask); 562 563 val &= ~mask; 564 val |= state; 565 566 gen9_write_dc_state(dev_priv, val); 567 568 dev_priv->csr.dc_state = val & mask; 569 } 570 571 void bxt_enable_dc9(struct drm_i915_private *dev_priv) 572 { 573 assert_can_enable_dc9(dev_priv); 574 575 DRM_DEBUG_KMS("Enabling DC9\n"); 576 577 intel_power_sequencer_reset(dev_priv); 578 gen9_set_dc_state(dev_priv, DC_STATE_EN_DC9); 579 } 580 581 void bxt_disable_dc9(struct drm_i915_private *dev_priv) 582 { 583 assert_can_disable_dc9(dev_priv); 584 585 DRM_DEBUG_KMS("Disabling DC9\n"); 586 587 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 588 589 intel_pps_unlock_regs_wa(dev_priv); 590 } 591 592 static void assert_csr_loaded(struct drm_i915_private *dev_priv) 593 { 594 WARN_ONCE(!I915_READ(CSR_PROGRAM(0)), 595 "CSR program storage start is NULL\n"); 596 WARN_ONCE(!I915_READ(CSR_SSP_BASE), "CSR SSP Base Not fine\n"); 597 WARN_ONCE(!I915_READ(CSR_HTP_SKL), "CSR HTP Not fine\n"); 598 } 599 600 static void assert_can_enable_dc5(struct drm_i915_private *dev_priv) 601 { 602 bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv, 603 SKL_DISP_PW_2); 604 605 WARN_ONCE(pg2_enabled, "PG2 not disabled to enable DC5.\n"); 606 607 WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5), 608 "DC5 already programmed to be enabled.\n"); 609 assert_rpm_wakelock_held(dev_priv); 610 611 assert_csr_loaded(dev_priv); 612 } 613 614 void gen9_enable_dc5(struct drm_i915_private *dev_priv) 615 { 616 assert_can_enable_dc5(dev_priv); 617 618 DRM_DEBUG_KMS("Enabling DC5\n"); 619 620 /* Wa Display #1183: skl,kbl,cfl */ 621 if (IS_GEN9_BC(dev_priv)) 622 I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) | 623 SKL_SELECT_ALTERNATE_DC_EXIT); 624 625 gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5); 626 } 627 628 static void assert_can_enable_dc6(struct drm_i915_private *dev_priv) 629 { 630 WARN_ONCE(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, 631 "Backlight is not disabled.\n"); 632 WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6), 633 "DC6 already programmed to be enabled.\n"); 634 635 assert_csr_loaded(dev_priv); 636 } 637 638 void skl_enable_dc6(struct drm_i915_private *dev_priv) 639 { 640 assert_can_enable_dc6(dev_priv); 641 642 DRM_DEBUG_KMS("Enabling DC6\n"); 643 644 gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6); 645 646 } 647 648 void skl_disable_dc6(struct drm_i915_private *dev_priv) 649 { 650 DRM_DEBUG_KMS("Disabling DC6\n"); 651 652 /* Wa Display #1183: skl,kbl,cfl */ 653 if (IS_GEN9_BC(dev_priv)) 654 I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) | 655 SKL_SELECT_ALTERNATE_DC_EXIT); 656 657 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 658 } 659 660 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv, 661 struct i915_power_well *power_well) 662 { 663 enum i915_power_well_id id = power_well->id; 664 u32 mask = HSW_PWR_WELL_CTL_REQ(id); 665 u32 bios_req = I915_READ(HSW_PWR_WELL_CTL_BIOS(id)); 666 667 /* Take over the request bit if set by BIOS. */ 668 if (bios_req & mask) { 669 u32 drv_req = I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)); 670 671 if (!(drv_req & mask)) 672 I915_WRITE(HSW_PWR_WELL_CTL_DRIVER(id), drv_req | mask); 673 I915_WRITE(HSW_PWR_WELL_CTL_BIOS(id), bios_req & ~mask); 674 } 675 } 676 677 static void bxt_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, 678 struct i915_power_well *power_well) 679 { 680 bxt_ddi_phy_init(dev_priv, power_well->bxt.phy); 681 } 682 683 static void bxt_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, 684 struct i915_power_well *power_well) 685 { 686 bxt_ddi_phy_uninit(dev_priv, power_well->bxt.phy); 687 } 688 689 static bool bxt_dpio_cmn_power_well_enabled(struct drm_i915_private *dev_priv, 690 struct i915_power_well *power_well) 691 { 692 return bxt_ddi_phy_is_enabled(dev_priv, power_well->bxt.phy); 693 } 694 695 static void bxt_verify_ddi_phy_power_wells(struct drm_i915_private *dev_priv) 696 { 697 struct i915_power_well *power_well; 698 699 power_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_A); 700 if (power_well->count > 0) 701 bxt_ddi_phy_verify_state(dev_priv, power_well->bxt.phy); 702 703 power_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_BC); 704 if (power_well->count > 0) 705 bxt_ddi_phy_verify_state(dev_priv, power_well->bxt.phy); 706 707 if (IS_GEMINILAKE(dev_priv)) { 708 power_well = lookup_power_well(dev_priv, GLK_DPIO_CMN_C); 709 if (power_well->count > 0) 710 bxt_ddi_phy_verify_state(dev_priv, power_well->bxt.phy); 711 } 712 } 713 714 static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv, 715 struct i915_power_well *power_well) 716 { 717 return (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0; 718 } 719 720 static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv) 721 { 722 u32 tmp = I915_READ(DBUF_CTL); 723 724 WARN((tmp & (DBUF_POWER_STATE | DBUF_POWER_REQUEST)) != 725 (DBUF_POWER_STATE | DBUF_POWER_REQUEST), 726 "Unexpected DBuf power power state (0x%08x)\n", tmp); 727 } 728 729 static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv, 730 struct i915_power_well *power_well) 731 { 732 struct intel_cdclk_state cdclk_state = {}; 733 734 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 735 736 dev_priv->display.get_cdclk(dev_priv, &cdclk_state); 737 /* Can't read out voltage_level so can't use intel_cdclk_changed() */ 738 WARN_ON(intel_cdclk_needs_modeset(&dev_priv->cdclk.hw, &cdclk_state)); 739 740 gen9_assert_dbuf_enabled(dev_priv); 741 742 if (IS_GEN9_LP(dev_priv)) 743 bxt_verify_ddi_phy_power_wells(dev_priv); 744 } 745 746 static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv, 747 struct i915_power_well *power_well) 748 { 749 if (!dev_priv->csr.dmc_payload) 750 return; 751 752 if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC6) 753 skl_enable_dc6(dev_priv); 754 else if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5) 755 gen9_enable_dc5(dev_priv); 756 } 757 758 static void i9xx_power_well_sync_hw_noop(struct drm_i915_private *dev_priv, 759 struct i915_power_well *power_well) 760 { 761 } 762 763 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv, 764 struct i915_power_well *power_well) 765 { 766 } 767 768 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv, 769 struct i915_power_well *power_well) 770 { 771 return true; 772 } 773 774 static void i830_pipes_power_well_enable(struct drm_i915_private *dev_priv, 775 struct i915_power_well *power_well) 776 { 777 if ((I915_READ(PIPECONF(PIPE_A)) & PIPECONF_ENABLE) == 0) 778 i830_enable_pipe(dev_priv, PIPE_A); 779 if ((I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE) == 0) 780 i830_enable_pipe(dev_priv, PIPE_B); 781 } 782 783 static void i830_pipes_power_well_disable(struct drm_i915_private *dev_priv, 784 struct i915_power_well *power_well) 785 { 786 i830_disable_pipe(dev_priv, PIPE_B); 787 i830_disable_pipe(dev_priv, PIPE_A); 788 } 789 790 static bool i830_pipes_power_well_enabled(struct drm_i915_private *dev_priv, 791 struct i915_power_well *power_well) 792 { 793 return I915_READ(PIPECONF(PIPE_A)) & PIPECONF_ENABLE && 794 I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE; 795 } 796 797 static void i830_pipes_power_well_sync_hw(struct drm_i915_private *dev_priv, 798 struct i915_power_well *power_well) 799 { 800 if (power_well->count > 0) 801 i830_pipes_power_well_enable(dev_priv, power_well); 802 else 803 i830_pipes_power_well_disable(dev_priv, power_well); 804 } 805 806 static void vlv_set_power_well(struct drm_i915_private *dev_priv, 807 struct i915_power_well *power_well, bool enable) 808 { 809 enum i915_power_well_id power_well_id = power_well->id; 810 u32 mask; 811 u32 state; 812 u32 ctrl; 813 814 mask = PUNIT_PWRGT_MASK(power_well_id); 815 state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) : 816 PUNIT_PWRGT_PWR_GATE(power_well_id); 817 818 mutex_lock(&dev_priv->pcu_lock); 819 820 #define COND \ 821 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state) 822 823 if (COND) 824 goto out; 825 826 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL); 827 ctrl &= ~mask; 828 ctrl |= state; 829 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl); 830 831 if (wait_for(COND, 100)) 832 DRM_ERROR("timeout setting power well state %08x (%08x)\n", 833 state, 834 vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL)); 835 836 #undef COND 837 838 out: 839 mutex_unlock(&dev_priv->pcu_lock); 840 } 841 842 static void vlv_power_well_enable(struct drm_i915_private *dev_priv, 843 struct i915_power_well *power_well) 844 { 845 vlv_set_power_well(dev_priv, power_well, true); 846 } 847 848 static void vlv_power_well_disable(struct drm_i915_private *dev_priv, 849 struct i915_power_well *power_well) 850 { 851 vlv_set_power_well(dev_priv, power_well, false); 852 } 853 854 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv, 855 struct i915_power_well *power_well) 856 { 857 enum i915_power_well_id power_well_id = power_well->id; 858 bool enabled = false; 859 u32 mask; 860 u32 state; 861 u32 ctrl; 862 863 mask = PUNIT_PWRGT_MASK(power_well_id); 864 ctrl = PUNIT_PWRGT_PWR_ON(power_well_id); 865 866 mutex_lock(&dev_priv->pcu_lock); 867 868 state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask; 869 /* 870 * We only ever set the power-on and power-gate states, anything 871 * else is unexpected. 872 */ 873 WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) && 874 state != PUNIT_PWRGT_PWR_GATE(power_well_id)); 875 if (state == ctrl) 876 enabled = true; 877 878 /* 879 * A transient state at this point would mean some unexpected party 880 * is poking at the power controls too. 881 */ 882 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask; 883 WARN_ON(ctrl != state); 884 885 mutex_unlock(&dev_priv->pcu_lock); 886 887 return enabled; 888 } 889 890 static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv) 891 { 892 u32 val; 893 894 /* 895 * On driver load, a pipe may be active and driving a DSI display. 896 * Preserve DPOUNIT_CLOCK_GATE_DISABLE to avoid the pipe getting stuck 897 * (and never recovering) in this case. intel_dsi_post_disable() will 898 * clear it when we turn off the display. 899 */ 900 val = I915_READ(DSPCLK_GATE_D); 901 val &= DPOUNIT_CLOCK_GATE_DISABLE; 902 val |= VRHUNIT_CLOCK_GATE_DISABLE; 903 I915_WRITE(DSPCLK_GATE_D, val); 904 905 /* 906 * Disable trickle feed and enable pnd deadline calculation 907 */ 908 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); 909 I915_WRITE(CBR1_VLV, 0); 910 911 WARN_ON(dev_priv->rawclk_freq == 0); 912 913 I915_WRITE(RAWCLK_FREQ_VLV, 914 DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 1000)); 915 } 916 917 static void vlv_display_power_well_init(struct drm_i915_private *dev_priv) 918 { 919 struct intel_encoder *encoder; 920 enum pipe pipe; 921 922 /* 923 * Enable the CRI clock source so we can get at the 924 * display and the reference clock for VGA 925 * hotplug / manual detection. Supposedly DSI also 926 * needs the ref clock up and running. 927 * 928 * CHV DPLL B/C have some issues if VGA mode is enabled. 929 */ 930 for_each_pipe(dev_priv, pipe) { 931 u32 val = I915_READ(DPLL(pipe)); 932 933 val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; 934 if (pipe != PIPE_A) 935 val |= DPLL_INTEGRATED_CRI_CLK_VLV; 936 937 I915_WRITE(DPLL(pipe), val); 938 } 939 940 vlv_init_display_clock_gating(dev_priv); 941 942 spin_lock_irq(&dev_priv->irq_lock); 943 valleyview_enable_display_irqs(dev_priv); 944 spin_unlock_irq(&dev_priv->irq_lock); 945 946 /* 947 * During driver initialization/resume we can avoid restoring the 948 * part of the HW/SW state that will be inited anyway explicitly. 949 */ 950 if (dev_priv->power_domains.initializing) 951 return; 952 953 intel_hpd_init(dev_priv); 954 955 /* Re-enable the ADPA, if we have one */ 956 for_each_intel_encoder(&dev_priv->drm, encoder) { 957 if (encoder->type == INTEL_OUTPUT_ANALOG) 958 intel_crt_reset(&encoder->base); 959 } 960 961 i915_redisable_vga_power_on(dev_priv); 962 963 intel_pps_unlock_regs_wa(dev_priv); 964 } 965 966 static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv) 967 { 968 spin_lock_irq(&dev_priv->irq_lock); 969 valleyview_disable_display_irqs(dev_priv); 970 spin_unlock_irq(&dev_priv->irq_lock); 971 972 /* make sure we're done processing display irqs */ 973 synchronize_irq(dev_priv->drm.irq); 974 975 intel_power_sequencer_reset(dev_priv); 976 977 /* Prevent us from re-enabling polling on accident in late suspend */ 978 if (!dev_priv->drm.dev->power.is_suspended) 979 intel_hpd_poll_init(dev_priv); 980 } 981 982 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv, 983 struct i915_power_well *power_well) 984 { 985 WARN_ON_ONCE(power_well->id != PUNIT_POWER_WELL_DISP2D); 986 987 vlv_set_power_well(dev_priv, power_well, true); 988 989 vlv_display_power_well_init(dev_priv); 990 } 991 992 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv, 993 struct i915_power_well *power_well) 994 { 995 WARN_ON_ONCE(power_well->id != PUNIT_POWER_WELL_DISP2D); 996 997 vlv_display_power_well_deinit(dev_priv); 998 999 vlv_set_power_well(dev_priv, power_well, false); 1000 } 1001 1002 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, 1003 struct i915_power_well *power_well) 1004 { 1005 WARN_ON_ONCE(power_well->id != PUNIT_POWER_WELL_DPIO_CMN_BC); 1006 1007 /* since ref/cri clock was enabled */ 1008 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ 1009 1010 vlv_set_power_well(dev_priv, power_well, true); 1011 1012 /* 1013 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx - 1014 * 6. De-assert cmn_reset/side_reset. Same as VLV X0. 1015 * a. GUnit 0x2110 bit[0] set to 1 (def 0) 1016 * b. The other bits such as sfr settings / modesel may all 1017 * be set to 0. 1018 * 1019 * This should only be done on init and resume from S3 with 1020 * both PLLs disabled, or we risk losing DPIO and PLL 1021 * synchronization. 1022 */ 1023 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST); 1024 } 1025 1026 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, 1027 struct i915_power_well *power_well) 1028 { 1029 enum pipe pipe; 1030 1031 WARN_ON_ONCE(power_well->id != PUNIT_POWER_WELL_DPIO_CMN_BC); 1032 1033 for_each_pipe(dev_priv, pipe) 1034 assert_pll_disabled(dev_priv, pipe); 1035 1036 /* Assert common reset */ 1037 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST); 1038 1039 vlv_set_power_well(dev_priv, power_well, false); 1040 } 1041 1042 #define POWER_DOMAIN_MASK (GENMASK_ULL(POWER_DOMAIN_NUM - 1, 0)) 1043 1044 static struct i915_power_well * 1045 lookup_power_well(struct drm_i915_private *dev_priv, 1046 enum i915_power_well_id power_well_id) 1047 { 1048 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1049 int i; 1050 1051 for (i = 0; i < power_domains->power_well_count; i++) { 1052 struct i915_power_well *power_well; 1053 1054 power_well = &power_domains->power_wells[i]; 1055 if (power_well->id == power_well_id) 1056 return power_well; 1057 } 1058 1059 return NULL; 1060 } 1061 1062 #define BITS_SET(val, bits) (((val) & (bits)) == (bits)) 1063 1064 static void assert_chv_phy_status(struct drm_i915_private *dev_priv) 1065 { 1066 struct i915_power_well *cmn_bc = 1067 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC); 1068 struct i915_power_well *cmn_d = 1069 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D); 1070 u32 phy_control = dev_priv->chv_phy_control; 1071 u32 phy_status = 0; 1072 u32 phy_status_mask = 0xffffffff; 1073 1074 /* 1075 * The BIOS can leave the PHY is some weird state 1076 * where it doesn't fully power down some parts. 1077 * Disable the asserts until the PHY has been fully 1078 * reset (ie. the power well has been disabled at 1079 * least once). 1080 */ 1081 if (!dev_priv->chv_phy_assert[DPIO_PHY0]) 1082 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) | 1083 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) | 1084 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) | 1085 PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) | 1086 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) | 1087 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1)); 1088 1089 if (!dev_priv->chv_phy_assert[DPIO_PHY1]) 1090 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) | 1091 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) | 1092 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1)); 1093 1094 if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) { 1095 phy_status |= PHY_POWERGOOD(DPIO_PHY0); 1096 1097 /* this assumes override is only used to enable lanes */ 1098 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0) 1099 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0); 1100 1101 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)) == 0) 1102 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1); 1103 1104 /* CL1 is on whenever anything is on in either channel */ 1105 if (BITS_SET(phy_control, 1106 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0) | 1107 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1))) 1108 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0); 1109 1110 /* 1111 * The DPLLB check accounts for the pipe B + port A usage 1112 * with CL2 powered up but all the lanes in the second channel 1113 * powered down. 1114 */ 1115 if (BITS_SET(phy_control, 1116 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) && 1117 (I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0) 1118 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1); 1119 1120 if (BITS_SET(phy_control, 1121 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH0))) 1122 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0); 1123 if (BITS_SET(phy_control, 1124 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH0))) 1125 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1); 1126 1127 if (BITS_SET(phy_control, 1128 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH1))) 1129 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0); 1130 if (BITS_SET(phy_control, 1131 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH1))) 1132 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1); 1133 } 1134 1135 if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) { 1136 phy_status |= PHY_POWERGOOD(DPIO_PHY1); 1137 1138 /* this assumes override is only used to enable lanes */ 1139 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)) == 0) 1140 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0); 1141 1142 if (BITS_SET(phy_control, 1143 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0))) 1144 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0); 1145 1146 if (BITS_SET(phy_control, 1147 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0))) 1148 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0); 1149 if (BITS_SET(phy_control, 1150 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1, DPIO_CH0))) 1151 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1); 1152 } 1153 1154 phy_status &= phy_status_mask; 1155 1156 /* 1157 * The PHY may be busy with some initial calibration and whatnot, 1158 * so the power state can take a while to actually change. 1159 */ 1160 if (intel_wait_for_register(dev_priv, 1161 DISPLAY_PHY_STATUS, 1162 phy_status_mask, 1163 phy_status, 1164 10)) 1165 DRM_ERROR("Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n", 1166 I915_READ(DISPLAY_PHY_STATUS) & phy_status_mask, 1167 phy_status, dev_priv->chv_phy_control); 1168 } 1169 1170 #undef BITS_SET 1171 1172 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, 1173 struct i915_power_well *power_well) 1174 { 1175 enum dpio_phy phy; 1176 enum pipe pipe; 1177 uint32_t tmp; 1178 1179 WARN_ON_ONCE(power_well->id != PUNIT_POWER_WELL_DPIO_CMN_BC && 1180 power_well->id != PUNIT_POWER_WELL_DPIO_CMN_D); 1181 1182 if (power_well->id == PUNIT_POWER_WELL_DPIO_CMN_BC) { 1183 pipe = PIPE_A; 1184 phy = DPIO_PHY0; 1185 } else { 1186 pipe = PIPE_C; 1187 phy = DPIO_PHY1; 1188 } 1189 1190 /* since ref/cri clock was enabled */ 1191 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ 1192 vlv_set_power_well(dev_priv, power_well, true); 1193 1194 /* Poll for phypwrgood signal */ 1195 if (intel_wait_for_register(dev_priv, 1196 DISPLAY_PHY_STATUS, 1197 PHY_POWERGOOD(phy), 1198 PHY_POWERGOOD(phy), 1199 1)) 1200 DRM_ERROR("Display PHY %d is not power up\n", phy); 1201 1202 mutex_lock(&dev_priv->sb_lock); 1203 1204 /* Enable dynamic power down */ 1205 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28); 1206 tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN | 1207 DPIO_SUS_CLK_CONFIG_GATE_CLKREQ; 1208 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp); 1209 1210 if (power_well->id == PUNIT_POWER_WELL_DPIO_CMN_BC) { 1211 tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1); 1212 tmp |= DPIO_DYNPWRDOWNEN_CH1; 1213 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp); 1214 } else { 1215 /* 1216 * Force the non-existing CL2 off. BXT does this 1217 * too, so maybe it saves some power even though 1218 * CL2 doesn't exist? 1219 */ 1220 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30); 1221 tmp |= DPIO_CL2_LDOFUSE_PWRENB; 1222 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp); 1223 } 1224 1225 mutex_unlock(&dev_priv->sb_lock); 1226 1227 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy); 1228 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); 1229 1230 DRM_DEBUG_KMS("Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n", 1231 phy, dev_priv->chv_phy_control); 1232 1233 assert_chv_phy_status(dev_priv); 1234 } 1235 1236 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, 1237 struct i915_power_well *power_well) 1238 { 1239 enum dpio_phy phy; 1240 1241 WARN_ON_ONCE(power_well->id != PUNIT_POWER_WELL_DPIO_CMN_BC && 1242 power_well->id != PUNIT_POWER_WELL_DPIO_CMN_D); 1243 1244 if (power_well->id == PUNIT_POWER_WELL_DPIO_CMN_BC) { 1245 phy = DPIO_PHY0; 1246 assert_pll_disabled(dev_priv, PIPE_A); 1247 assert_pll_disabled(dev_priv, PIPE_B); 1248 } else { 1249 phy = DPIO_PHY1; 1250 assert_pll_disabled(dev_priv, PIPE_C); 1251 } 1252 1253 dev_priv->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy); 1254 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); 1255 1256 vlv_set_power_well(dev_priv, power_well, false); 1257 1258 DRM_DEBUG_KMS("Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n", 1259 phy, dev_priv->chv_phy_control); 1260 1261 /* PHY is fully reset now, so we can enable the PHY state asserts */ 1262 dev_priv->chv_phy_assert[phy] = true; 1263 1264 assert_chv_phy_status(dev_priv); 1265 } 1266 1267 static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy, 1268 enum dpio_channel ch, bool override, unsigned int mask) 1269 { 1270 enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C; 1271 u32 reg, val, expected, actual; 1272 1273 /* 1274 * The BIOS can leave the PHY is some weird state 1275 * where it doesn't fully power down some parts. 1276 * Disable the asserts until the PHY has been fully 1277 * reset (ie. the power well has been disabled at 1278 * least once). 1279 */ 1280 if (!dev_priv->chv_phy_assert[phy]) 1281 return; 1282 1283 if (ch == DPIO_CH0) 1284 reg = _CHV_CMN_DW0_CH0; 1285 else 1286 reg = _CHV_CMN_DW6_CH1; 1287 1288 mutex_lock(&dev_priv->sb_lock); 1289 val = vlv_dpio_read(dev_priv, pipe, reg); 1290 mutex_unlock(&dev_priv->sb_lock); 1291 1292 /* 1293 * This assumes !override is only used when the port is disabled. 1294 * All lanes should power down even without the override when 1295 * the port is disabled. 1296 */ 1297 if (!override || mask == 0xf) { 1298 expected = DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN; 1299 /* 1300 * If CH1 common lane is not active anymore 1301 * (eg. for pipe B DPLL) the entire channel will 1302 * shut down, which causes the common lane registers 1303 * to read as 0. That means we can't actually check 1304 * the lane power down status bits, but as the entire 1305 * register reads as 0 it's a good indication that the 1306 * channel is indeed entirely powered down. 1307 */ 1308 if (ch == DPIO_CH1 && val == 0) 1309 expected = 0; 1310 } else if (mask != 0x0) { 1311 expected = DPIO_ANYDL_POWERDOWN; 1312 } else { 1313 expected = 0; 1314 } 1315 1316 if (ch == DPIO_CH0) 1317 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH0; 1318 else 1319 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH1; 1320 actual &= DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN; 1321 1322 WARN(actual != expected, 1323 "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n", 1324 !!(actual & DPIO_ALLDL_POWERDOWN), !!(actual & DPIO_ANYDL_POWERDOWN), 1325 !!(expected & DPIO_ALLDL_POWERDOWN), !!(expected & DPIO_ANYDL_POWERDOWN), 1326 reg, val); 1327 } 1328 1329 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy, 1330 enum dpio_channel ch, bool override) 1331 { 1332 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1333 bool was_override; 1334 1335 mutex_lock(&power_domains->lock); 1336 1337 was_override = dev_priv->chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1338 1339 if (override == was_override) 1340 goto out; 1341 1342 if (override) 1343 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1344 else 1345 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1346 1347 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); 1348 1349 DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n", 1350 phy, ch, dev_priv->chv_phy_control); 1351 1352 assert_chv_phy_status(dev_priv); 1353 1354 out: 1355 mutex_unlock(&power_domains->lock); 1356 1357 return was_override; 1358 } 1359 1360 void chv_phy_powergate_lanes(struct intel_encoder *encoder, 1361 bool override, unsigned int mask) 1362 { 1363 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1364 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1365 enum dpio_phy phy = vlv_dport_to_phy(enc_to_dig_port(&encoder->base)); 1366 enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base)); 1367 1368 mutex_lock(&power_domains->lock); 1369 1370 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch); 1371 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch); 1372 1373 if (override) 1374 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1375 else 1376 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1377 1378 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); 1379 1380 DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n", 1381 phy, ch, mask, dev_priv->chv_phy_control); 1382 1383 assert_chv_phy_status(dev_priv); 1384 1385 assert_chv_phy_powergate(dev_priv, phy, ch, override, mask); 1386 1387 mutex_unlock(&power_domains->lock); 1388 } 1389 1390 static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv, 1391 struct i915_power_well *power_well) 1392 { 1393 enum pipe pipe = PIPE_A; 1394 bool enabled; 1395 u32 state, ctrl; 1396 1397 mutex_lock(&dev_priv->pcu_lock); 1398 1399 state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe); 1400 /* 1401 * We only ever set the power-on and power-gate states, anything 1402 * else is unexpected. 1403 */ 1404 WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe)); 1405 enabled = state == DP_SSS_PWR_ON(pipe); 1406 1407 /* 1408 * A transient state at this point would mean some unexpected party 1409 * is poking at the power controls too. 1410 */ 1411 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe); 1412 WARN_ON(ctrl << 16 != state); 1413 1414 mutex_unlock(&dev_priv->pcu_lock); 1415 1416 return enabled; 1417 } 1418 1419 static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv, 1420 struct i915_power_well *power_well, 1421 bool enable) 1422 { 1423 enum pipe pipe = PIPE_A; 1424 u32 state; 1425 u32 ctrl; 1426 1427 state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe); 1428 1429 mutex_lock(&dev_priv->pcu_lock); 1430 1431 #define COND \ 1432 ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state) 1433 1434 if (COND) 1435 goto out; 1436 1437 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); 1438 ctrl &= ~DP_SSC_MASK(pipe); 1439 ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe); 1440 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl); 1441 1442 if (wait_for(COND, 100)) 1443 DRM_ERROR("timeout setting power well state %08x (%08x)\n", 1444 state, 1445 vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ)); 1446 1447 #undef COND 1448 1449 out: 1450 mutex_unlock(&dev_priv->pcu_lock); 1451 } 1452 1453 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv, 1454 struct i915_power_well *power_well) 1455 { 1456 WARN_ON_ONCE(power_well->id != CHV_DISP_PW_PIPE_A); 1457 1458 chv_set_pipe_power_well(dev_priv, power_well, true); 1459 1460 vlv_display_power_well_init(dev_priv); 1461 } 1462 1463 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv, 1464 struct i915_power_well *power_well) 1465 { 1466 WARN_ON_ONCE(power_well->id != CHV_DISP_PW_PIPE_A); 1467 1468 vlv_display_power_well_deinit(dev_priv); 1469 1470 chv_set_pipe_power_well(dev_priv, power_well, false); 1471 } 1472 1473 static void 1474 __intel_display_power_get_domain(struct drm_i915_private *dev_priv, 1475 enum intel_display_power_domain domain) 1476 { 1477 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1478 struct i915_power_well *power_well; 1479 1480 for_each_power_domain_well(dev_priv, power_well, BIT_ULL(domain)) 1481 intel_power_well_get(dev_priv, power_well); 1482 1483 power_domains->domain_use_count[domain]++; 1484 } 1485 1486 /** 1487 * intel_display_power_get - grab a power domain reference 1488 * @dev_priv: i915 device instance 1489 * @domain: power domain to reference 1490 * 1491 * This function grabs a power domain reference for @domain and ensures that the 1492 * power domain and all its parents are powered up. Therefore users should only 1493 * grab a reference to the innermost power domain they need. 1494 * 1495 * Any power domain reference obtained by this function must have a symmetric 1496 * call to intel_display_power_put() to release the reference again. 1497 */ 1498 void intel_display_power_get(struct drm_i915_private *dev_priv, 1499 enum intel_display_power_domain domain) 1500 { 1501 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1502 1503 intel_runtime_pm_get(dev_priv); 1504 1505 mutex_lock(&power_domains->lock); 1506 1507 __intel_display_power_get_domain(dev_priv, domain); 1508 1509 mutex_unlock(&power_domains->lock); 1510 } 1511 1512 /** 1513 * intel_display_power_get_if_enabled - grab a reference for an enabled display power domain 1514 * @dev_priv: i915 device instance 1515 * @domain: power domain to reference 1516 * 1517 * This function grabs a power domain reference for @domain and ensures that the 1518 * power domain and all its parents are powered up. Therefore users should only 1519 * grab a reference to the innermost power domain they need. 1520 * 1521 * Any power domain reference obtained by this function must have a symmetric 1522 * call to intel_display_power_put() to release the reference again. 1523 */ 1524 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv, 1525 enum intel_display_power_domain domain) 1526 { 1527 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1528 bool is_enabled; 1529 1530 if (!intel_runtime_pm_get_if_in_use(dev_priv)) 1531 return false; 1532 1533 mutex_lock(&power_domains->lock); 1534 1535 if (__intel_display_power_is_enabled(dev_priv, domain)) { 1536 __intel_display_power_get_domain(dev_priv, domain); 1537 is_enabled = true; 1538 } else { 1539 is_enabled = false; 1540 } 1541 1542 mutex_unlock(&power_domains->lock); 1543 1544 if (!is_enabled) 1545 intel_runtime_pm_put(dev_priv); 1546 1547 return is_enabled; 1548 } 1549 1550 /** 1551 * intel_display_power_put - release a power domain reference 1552 * @dev_priv: i915 device instance 1553 * @domain: power domain to reference 1554 * 1555 * This function drops the power domain reference obtained by 1556 * intel_display_power_get() and might power down the corresponding hardware 1557 * block right away if this is the last reference. 1558 */ 1559 void intel_display_power_put(struct drm_i915_private *dev_priv, 1560 enum intel_display_power_domain domain) 1561 { 1562 struct i915_power_domains *power_domains; 1563 struct i915_power_well *power_well; 1564 1565 power_domains = &dev_priv->power_domains; 1566 1567 mutex_lock(&power_domains->lock); 1568 1569 WARN(!power_domains->domain_use_count[domain], 1570 "Use count on domain %s is already zero\n", 1571 intel_display_power_domain_str(domain)); 1572 power_domains->domain_use_count[domain]--; 1573 1574 for_each_power_domain_well_rev(dev_priv, power_well, BIT_ULL(domain)) 1575 intel_power_well_put(dev_priv, power_well); 1576 1577 mutex_unlock(&power_domains->lock); 1578 1579 intel_runtime_pm_put(dev_priv); 1580 } 1581 1582 #define I830_PIPES_POWER_DOMAINS ( \ 1583 BIT_ULL(POWER_DOMAIN_PIPE_A) | \ 1584 BIT_ULL(POWER_DOMAIN_PIPE_B) | \ 1585 BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \ 1586 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 1587 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ 1588 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ 1589 BIT_ULL(POWER_DOMAIN_INIT)) 1590 1591 #define VLV_DISPLAY_POWER_DOMAINS ( \ 1592 BIT_ULL(POWER_DOMAIN_PIPE_A) | \ 1593 BIT_ULL(POWER_DOMAIN_PIPE_B) | \ 1594 BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \ 1595 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 1596 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ 1597 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ 1598 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1599 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1600 BIT_ULL(POWER_DOMAIN_PORT_DSI) | \ 1601 BIT_ULL(POWER_DOMAIN_PORT_CRT) | \ 1602 BIT_ULL(POWER_DOMAIN_VGA) | \ 1603 BIT_ULL(POWER_DOMAIN_AUDIO) | \ 1604 BIT_ULL(POWER_DOMAIN_AUX_B) | \ 1605 BIT_ULL(POWER_DOMAIN_AUX_C) | \ 1606 BIT_ULL(POWER_DOMAIN_GMBUS) | \ 1607 BIT_ULL(POWER_DOMAIN_INIT)) 1608 1609 #define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \ 1610 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1611 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1612 BIT_ULL(POWER_DOMAIN_PORT_CRT) | \ 1613 BIT_ULL(POWER_DOMAIN_AUX_B) | \ 1614 BIT_ULL(POWER_DOMAIN_AUX_C) | \ 1615 BIT_ULL(POWER_DOMAIN_INIT)) 1616 1617 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \ 1618 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1619 BIT_ULL(POWER_DOMAIN_AUX_B) | \ 1620 BIT_ULL(POWER_DOMAIN_INIT)) 1621 1622 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \ 1623 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1624 BIT_ULL(POWER_DOMAIN_AUX_B) | \ 1625 BIT_ULL(POWER_DOMAIN_INIT)) 1626 1627 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \ 1628 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1629 BIT_ULL(POWER_DOMAIN_AUX_C) | \ 1630 BIT_ULL(POWER_DOMAIN_INIT)) 1631 1632 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \ 1633 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1634 BIT_ULL(POWER_DOMAIN_AUX_C) | \ 1635 BIT_ULL(POWER_DOMAIN_INIT)) 1636 1637 #define CHV_DISPLAY_POWER_DOMAINS ( \ 1638 BIT_ULL(POWER_DOMAIN_PIPE_A) | \ 1639 BIT_ULL(POWER_DOMAIN_PIPE_B) | \ 1640 BIT_ULL(POWER_DOMAIN_PIPE_C) | \ 1641 BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \ 1642 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 1643 BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ 1644 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ 1645 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ 1646 BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ 1647 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1648 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1649 BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \ 1650 BIT_ULL(POWER_DOMAIN_PORT_DSI) | \ 1651 BIT_ULL(POWER_DOMAIN_VGA) | \ 1652 BIT_ULL(POWER_DOMAIN_AUDIO) | \ 1653 BIT_ULL(POWER_DOMAIN_AUX_B) | \ 1654 BIT_ULL(POWER_DOMAIN_AUX_C) | \ 1655 BIT_ULL(POWER_DOMAIN_AUX_D) | \ 1656 BIT_ULL(POWER_DOMAIN_GMBUS) | \ 1657 BIT_ULL(POWER_DOMAIN_INIT)) 1658 1659 #define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \ 1660 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1661 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1662 BIT_ULL(POWER_DOMAIN_AUX_B) | \ 1663 BIT_ULL(POWER_DOMAIN_AUX_C) | \ 1664 BIT_ULL(POWER_DOMAIN_INIT)) 1665 1666 #define CHV_DPIO_CMN_D_POWER_DOMAINS ( \ 1667 BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \ 1668 BIT_ULL(POWER_DOMAIN_AUX_D) | \ 1669 BIT_ULL(POWER_DOMAIN_INIT)) 1670 1671 #define HSW_DISPLAY_POWER_DOMAINS ( \ 1672 BIT_ULL(POWER_DOMAIN_PIPE_B) | \ 1673 BIT_ULL(POWER_DOMAIN_PIPE_C) | \ 1674 BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \ 1675 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 1676 BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ 1677 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ 1678 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ 1679 BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ 1680 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1681 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1682 BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \ 1683 BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \ 1684 BIT_ULL(POWER_DOMAIN_VGA) | \ 1685 BIT_ULL(POWER_DOMAIN_AUDIO) | \ 1686 BIT_ULL(POWER_DOMAIN_INIT)) 1687 1688 #define BDW_DISPLAY_POWER_DOMAINS ( \ 1689 BIT_ULL(POWER_DOMAIN_PIPE_B) | \ 1690 BIT_ULL(POWER_DOMAIN_PIPE_C) | \ 1691 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 1692 BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ 1693 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ 1694 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ 1695 BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ 1696 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1697 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1698 BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \ 1699 BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \ 1700 BIT_ULL(POWER_DOMAIN_VGA) | \ 1701 BIT_ULL(POWER_DOMAIN_AUDIO) | \ 1702 BIT_ULL(POWER_DOMAIN_INIT)) 1703 1704 #define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ 1705 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ 1706 BIT_ULL(POWER_DOMAIN_PIPE_B) | \ 1707 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ 1708 BIT_ULL(POWER_DOMAIN_PIPE_C) | \ 1709 BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ 1710 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 1711 BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ 1712 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1713 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1714 BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \ 1715 BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) | \ 1716 BIT_ULL(POWER_DOMAIN_AUX_B) | \ 1717 BIT_ULL(POWER_DOMAIN_AUX_C) | \ 1718 BIT_ULL(POWER_DOMAIN_AUX_D) | \ 1719 BIT_ULL(POWER_DOMAIN_AUDIO) | \ 1720 BIT_ULL(POWER_DOMAIN_VGA) | \ 1721 BIT_ULL(POWER_DOMAIN_INIT)) 1722 #define SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS ( \ 1723 BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO) | \ 1724 BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO) | \ 1725 BIT_ULL(POWER_DOMAIN_INIT)) 1726 #define SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS ( \ 1727 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO) | \ 1728 BIT_ULL(POWER_DOMAIN_INIT)) 1729 #define SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS ( \ 1730 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO) | \ 1731 BIT_ULL(POWER_DOMAIN_INIT)) 1732 #define SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS ( \ 1733 BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO) | \ 1734 BIT_ULL(POWER_DOMAIN_INIT)) 1735 #define SKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \ 1736 SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ 1737 BIT_ULL(POWER_DOMAIN_GT_IRQ) | \ 1738 BIT_ULL(POWER_DOMAIN_MODESET) | \ 1739 BIT_ULL(POWER_DOMAIN_AUX_A) | \ 1740 BIT_ULL(POWER_DOMAIN_INIT)) 1741 1742 #define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ 1743 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ 1744 BIT_ULL(POWER_DOMAIN_PIPE_B) | \ 1745 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ 1746 BIT_ULL(POWER_DOMAIN_PIPE_C) | \ 1747 BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ 1748 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 1749 BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ 1750 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1751 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1752 BIT_ULL(POWER_DOMAIN_AUX_B) | \ 1753 BIT_ULL(POWER_DOMAIN_AUX_C) | \ 1754 BIT_ULL(POWER_DOMAIN_AUDIO) | \ 1755 BIT_ULL(POWER_DOMAIN_VGA) | \ 1756 BIT_ULL(POWER_DOMAIN_INIT)) 1757 #define BXT_DISPLAY_DC_OFF_POWER_DOMAINS ( \ 1758 BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ 1759 BIT_ULL(POWER_DOMAIN_GT_IRQ) | \ 1760 BIT_ULL(POWER_DOMAIN_MODESET) | \ 1761 BIT_ULL(POWER_DOMAIN_AUX_A) | \ 1762 BIT_ULL(POWER_DOMAIN_GMBUS) | \ 1763 BIT_ULL(POWER_DOMAIN_INIT)) 1764 #define BXT_DPIO_CMN_A_POWER_DOMAINS ( \ 1765 BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) | \ 1766 BIT_ULL(POWER_DOMAIN_AUX_A) | \ 1767 BIT_ULL(POWER_DOMAIN_INIT)) 1768 #define BXT_DPIO_CMN_BC_POWER_DOMAINS ( \ 1769 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1770 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1771 BIT_ULL(POWER_DOMAIN_AUX_B) | \ 1772 BIT_ULL(POWER_DOMAIN_AUX_C) | \ 1773 BIT_ULL(POWER_DOMAIN_INIT)) 1774 1775 #define GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ 1776 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ 1777 BIT_ULL(POWER_DOMAIN_PIPE_B) | \ 1778 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ 1779 BIT_ULL(POWER_DOMAIN_PIPE_C) | \ 1780 BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ 1781 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 1782 BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ 1783 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1784 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1785 BIT_ULL(POWER_DOMAIN_AUX_B) | \ 1786 BIT_ULL(POWER_DOMAIN_AUX_C) | \ 1787 BIT_ULL(POWER_DOMAIN_AUDIO) | \ 1788 BIT_ULL(POWER_DOMAIN_VGA) | \ 1789 BIT_ULL(POWER_DOMAIN_INIT)) 1790 #define GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS ( \ 1791 BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO)) 1792 #define GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS ( \ 1793 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO)) 1794 #define GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS ( \ 1795 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO)) 1796 #define GLK_DPIO_CMN_A_POWER_DOMAINS ( \ 1797 BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) | \ 1798 BIT_ULL(POWER_DOMAIN_AUX_A) | \ 1799 BIT_ULL(POWER_DOMAIN_INIT)) 1800 #define GLK_DPIO_CMN_B_POWER_DOMAINS ( \ 1801 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1802 BIT_ULL(POWER_DOMAIN_AUX_B) | \ 1803 BIT_ULL(POWER_DOMAIN_INIT)) 1804 #define GLK_DPIO_CMN_C_POWER_DOMAINS ( \ 1805 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1806 BIT_ULL(POWER_DOMAIN_AUX_C) | \ 1807 BIT_ULL(POWER_DOMAIN_INIT)) 1808 #define GLK_DISPLAY_AUX_A_POWER_DOMAINS ( \ 1809 BIT_ULL(POWER_DOMAIN_AUX_A) | \ 1810 BIT_ULL(POWER_DOMAIN_INIT)) 1811 #define GLK_DISPLAY_AUX_B_POWER_DOMAINS ( \ 1812 BIT_ULL(POWER_DOMAIN_AUX_B) | \ 1813 BIT_ULL(POWER_DOMAIN_INIT)) 1814 #define GLK_DISPLAY_AUX_C_POWER_DOMAINS ( \ 1815 BIT_ULL(POWER_DOMAIN_AUX_C) | \ 1816 BIT_ULL(POWER_DOMAIN_INIT)) 1817 #define GLK_DISPLAY_DC_OFF_POWER_DOMAINS ( \ 1818 GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ 1819 BIT_ULL(POWER_DOMAIN_GT_IRQ) | \ 1820 BIT_ULL(POWER_DOMAIN_MODESET) | \ 1821 BIT_ULL(POWER_DOMAIN_AUX_A) | \ 1822 BIT_ULL(POWER_DOMAIN_GMBUS) | \ 1823 BIT_ULL(POWER_DOMAIN_INIT)) 1824 1825 #define CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ 1826 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ 1827 BIT_ULL(POWER_DOMAIN_PIPE_B) | \ 1828 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ 1829 BIT_ULL(POWER_DOMAIN_PIPE_C) | \ 1830 BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ 1831 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 1832 BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ 1833 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1834 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1835 BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \ 1836 BIT_ULL(POWER_DOMAIN_PORT_DDI_F_LANES) | \ 1837 BIT_ULL(POWER_DOMAIN_AUX_B) | \ 1838 BIT_ULL(POWER_DOMAIN_AUX_C) | \ 1839 BIT_ULL(POWER_DOMAIN_AUX_D) | \ 1840 BIT_ULL(POWER_DOMAIN_AUX_F) | \ 1841 BIT_ULL(POWER_DOMAIN_AUDIO) | \ 1842 BIT_ULL(POWER_DOMAIN_VGA) | \ 1843 BIT_ULL(POWER_DOMAIN_INIT)) 1844 #define CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS ( \ 1845 BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO) | \ 1846 BIT_ULL(POWER_DOMAIN_INIT)) 1847 #define CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS ( \ 1848 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO) | \ 1849 BIT_ULL(POWER_DOMAIN_INIT)) 1850 #define CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS ( \ 1851 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO) | \ 1852 BIT_ULL(POWER_DOMAIN_INIT)) 1853 #define CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS ( \ 1854 BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO) | \ 1855 BIT_ULL(POWER_DOMAIN_INIT)) 1856 #define CNL_DISPLAY_AUX_A_POWER_DOMAINS ( \ 1857 BIT_ULL(POWER_DOMAIN_AUX_A) | \ 1858 BIT_ULL(POWER_DOMAIN_AUX_IO_A) | \ 1859 BIT_ULL(POWER_DOMAIN_INIT)) 1860 #define CNL_DISPLAY_AUX_B_POWER_DOMAINS ( \ 1861 BIT_ULL(POWER_DOMAIN_AUX_B) | \ 1862 BIT_ULL(POWER_DOMAIN_INIT)) 1863 #define CNL_DISPLAY_AUX_C_POWER_DOMAINS ( \ 1864 BIT_ULL(POWER_DOMAIN_AUX_C) | \ 1865 BIT_ULL(POWER_DOMAIN_INIT)) 1866 #define CNL_DISPLAY_AUX_D_POWER_DOMAINS ( \ 1867 BIT_ULL(POWER_DOMAIN_AUX_D) | \ 1868 BIT_ULL(POWER_DOMAIN_INIT)) 1869 #define CNL_DISPLAY_AUX_F_POWER_DOMAINS ( \ 1870 BIT_ULL(POWER_DOMAIN_AUX_F) | \ 1871 BIT_ULL(POWER_DOMAIN_INIT)) 1872 #define CNL_DISPLAY_DDI_F_IO_POWER_DOMAINS ( \ 1873 BIT_ULL(POWER_DOMAIN_PORT_DDI_F_IO) | \ 1874 BIT_ULL(POWER_DOMAIN_INIT)) 1875 #define CNL_DISPLAY_DC_OFF_POWER_DOMAINS ( \ 1876 CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ 1877 BIT_ULL(POWER_DOMAIN_GT_IRQ) | \ 1878 BIT_ULL(POWER_DOMAIN_MODESET) | \ 1879 BIT_ULL(POWER_DOMAIN_AUX_A) | \ 1880 BIT_ULL(POWER_DOMAIN_INIT)) 1881 1882 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = { 1883 .sync_hw = i9xx_power_well_sync_hw_noop, 1884 .enable = i9xx_always_on_power_well_noop, 1885 .disable = i9xx_always_on_power_well_noop, 1886 .is_enabled = i9xx_always_on_power_well_enabled, 1887 }; 1888 1889 static const struct i915_power_well_ops chv_pipe_power_well_ops = { 1890 .sync_hw = i9xx_power_well_sync_hw_noop, 1891 .enable = chv_pipe_power_well_enable, 1892 .disable = chv_pipe_power_well_disable, 1893 .is_enabled = chv_pipe_power_well_enabled, 1894 }; 1895 1896 static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = { 1897 .sync_hw = i9xx_power_well_sync_hw_noop, 1898 .enable = chv_dpio_cmn_power_well_enable, 1899 .disable = chv_dpio_cmn_power_well_disable, 1900 .is_enabled = vlv_power_well_enabled, 1901 }; 1902 1903 static struct i915_power_well i9xx_always_on_power_well[] = { 1904 { 1905 .name = "always-on", 1906 .always_on = 1, 1907 .domains = POWER_DOMAIN_MASK, 1908 .ops = &i9xx_always_on_power_well_ops, 1909 .id = I915_DISP_PW_ALWAYS_ON, 1910 }, 1911 }; 1912 1913 static const struct i915_power_well_ops i830_pipes_power_well_ops = { 1914 .sync_hw = i830_pipes_power_well_sync_hw, 1915 .enable = i830_pipes_power_well_enable, 1916 .disable = i830_pipes_power_well_disable, 1917 .is_enabled = i830_pipes_power_well_enabled, 1918 }; 1919 1920 static struct i915_power_well i830_power_wells[] = { 1921 { 1922 .name = "always-on", 1923 .always_on = 1, 1924 .domains = POWER_DOMAIN_MASK, 1925 .ops = &i9xx_always_on_power_well_ops, 1926 .id = I915_DISP_PW_ALWAYS_ON, 1927 }, 1928 { 1929 .name = "pipes", 1930 .domains = I830_PIPES_POWER_DOMAINS, 1931 .ops = &i830_pipes_power_well_ops, 1932 .id = I830_DISP_PW_PIPES, 1933 }, 1934 }; 1935 1936 static const struct i915_power_well_ops hsw_power_well_ops = { 1937 .sync_hw = hsw_power_well_sync_hw, 1938 .enable = hsw_power_well_enable, 1939 .disable = hsw_power_well_disable, 1940 .is_enabled = hsw_power_well_enabled, 1941 }; 1942 1943 static const struct i915_power_well_ops gen9_dc_off_power_well_ops = { 1944 .sync_hw = i9xx_power_well_sync_hw_noop, 1945 .enable = gen9_dc_off_power_well_enable, 1946 .disable = gen9_dc_off_power_well_disable, 1947 .is_enabled = gen9_dc_off_power_well_enabled, 1948 }; 1949 1950 static const struct i915_power_well_ops bxt_dpio_cmn_power_well_ops = { 1951 .sync_hw = i9xx_power_well_sync_hw_noop, 1952 .enable = bxt_dpio_cmn_power_well_enable, 1953 .disable = bxt_dpio_cmn_power_well_disable, 1954 .is_enabled = bxt_dpio_cmn_power_well_enabled, 1955 }; 1956 1957 static struct i915_power_well hsw_power_wells[] = { 1958 { 1959 .name = "always-on", 1960 .always_on = 1, 1961 .domains = POWER_DOMAIN_MASK, 1962 .ops = &i9xx_always_on_power_well_ops, 1963 .id = I915_DISP_PW_ALWAYS_ON, 1964 }, 1965 { 1966 .name = "display", 1967 .domains = HSW_DISPLAY_POWER_DOMAINS, 1968 .ops = &hsw_power_well_ops, 1969 .id = HSW_DISP_PW_GLOBAL, 1970 { 1971 .hsw.has_vga = true, 1972 }, 1973 }, 1974 }; 1975 1976 static struct i915_power_well bdw_power_wells[] = { 1977 { 1978 .name = "always-on", 1979 .always_on = 1, 1980 .domains = POWER_DOMAIN_MASK, 1981 .ops = &i9xx_always_on_power_well_ops, 1982 .id = I915_DISP_PW_ALWAYS_ON, 1983 }, 1984 { 1985 .name = "display", 1986 .domains = BDW_DISPLAY_POWER_DOMAINS, 1987 .ops = &hsw_power_well_ops, 1988 .id = HSW_DISP_PW_GLOBAL, 1989 { 1990 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), 1991 .hsw.has_vga = true, 1992 }, 1993 }, 1994 }; 1995 1996 static const struct i915_power_well_ops vlv_display_power_well_ops = { 1997 .sync_hw = i9xx_power_well_sync_hw_noop, 1998 .enable = vlv_display_power_well_enable, 1999 .disable = vlv_display_power_well_disable, 2000 .is_enabled = vlv_power_well_enabled, 2001 }; 2002 2003 static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = { 2004 .sync_hw = i9xx_power_well_sync_hw_noop, 2005 .enable = vlv_dpio_cmn_power_well_enable, 2006 .disable = vlv_dpio_cmn_power_well_disable, 2007 .is_enabled = vlv_power_well_enabled, 2008 }; 2009 2010 static const struct i915_power_well_ops vlv_dpio_power_well_ops = { 2011 .sync_hw = i9xx_power_well_sync_hw_noop, 2012 .enable = vlv_power_well_enable, 2013 .disable = vlv_power_well_disable, 2014 .is_enabled = vlv_power_well_enabled, 2015 }; 2016 2017 static struct i915_power_well vlv_power_wells[] = { 2018 { 2019 .name = "always-on", 2020 .always_on = 1, 2021 .domains = POWER_DOMAIN_MASK, 2022 .ops = &i9xx_always_on_power_well_ops, 2023 .id = I915_DISP_PW_ALWAYS_ON, 2024 }, 2025 { 2026 .name = "display", 2027 .domains = VLV_DISPLAY_POWER_DOMAINS, 2028 .id = PUNIT_POWER_WELL_DISP2D, 2029 .ops = &vlv_display_power_well_ops, 2030 }, 2031 { 2032 .name = "dpio-tx-b-01", 2033 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 2034 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | 2035 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | 2036 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, 2037 .ops = &vlv_dpio_power_well_ops, 2038 .id = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01, 2039 }, 2040 { 2041 .name = "dpio-tx-b-23", 2042 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 2043 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | 2044 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | 2045 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, 2046 .ops = &vlv_dpio_power_well_ops, 2047 .id = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23, 2048 }, 2049 { 2050 .name = "dpio-tx-c-01", 2051 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 2052 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | 2053 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | 2054 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, 2055 .ops = &vlv_dpio_power_well_ops, 2056 .id = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01, 2057 }, 2058 { 2059 .name = "dpio-tx-c-23", 2060 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 2061 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | 2062 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | 2063 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, 2064 .ops = &vlv_dpio_power_well_ops, 2065 .id = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23, 2066 }, 2067 { 2068 .name = "dpio-common", 2069 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS, 2070 .id = PUNIT_POWER_WELL_DPIO_CMN_BC, 2071 .ops = &vlv_dpio_cmn_power_well_ops, 2072 }, 2073 }; 2074 2075 static struct i915_power_well chv_power_wells[] = { 2076 { 2077 .name = "always-on", 2078 .always_on = 1, 2079 .domains = POWER_DOMAIN_MASK, 2080 .ops = &i9xx_always_on_power_well_ops, 2081 .id = I915_DISP_PW_ALWAYS_ON, 2082 }, 2083 { 2084 .name = "display", 2085 /* 2086 * Pipe A power well is the new disp2d well. Pipe B and C 2087 * power wells don't actually exist. Pipe A power well is 2088 * required for any pipe to work. 2089 */ 2090 .domains = CHV_DISPLAY_POWER_DOMAINS, 2091 .id = CHV_DISP_PW_PIPE_A, 2092 .ops = &chv_pipe_power_well_ops, 2093 }, 2094 { 2095 .name = "dpio-common-bc", 2096 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS, 2097 .id = PUNIT_POWER_WELL_DPIO_CMN_BC, 2098 .ops = &chv_dpio_cmn_power_well_ops, 2099 }, 2100 { 2101 .name = "dpio-common-d", 2102 .domains = CHV_DPIO_CMN_D_POWER_DOMAINS, 2103 .id = PUNIT_POWER_WELL_DPIO_CMN_D, 2104 .ops = &chv_dpio_cmn_power_well_ops, 2105 }, 2106 }; 2107 2108 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv, 2109 enum i915_power_well_id power_well_id) 2110 { 2111 struct i915_power_well *power_well; 2112 bool ret; 2113 2114 power_well = lookup_power_well(dev_priv, power_well_id); 2115 ret = power_well->ops->is_enabled(dev_priv, power_well); 2116 2117 return ret; 2118 } 2119 2120 static struct i915_power_well skl_power_wells[] = { 2121 { 2122 .name = "always-on", 2123 .always_on = 1, 2124 .domains = POWER_DOMAIN_MASK, 2125 .ops = &i9xx_always_on_power_well_ops, 2126 .id = I915_DISP_PW_ALWAYS_ON, 2127 }, 2128 { 2129 .name = "power well 1", 2130 /* Handled by the DMC firmware */ 2131 .domains = 0, 2132 .ops = &hsw_power_well_ops, 2133 .id = SKL_DISP_PW_1, 2134 { 2135 .hsw.has_fuses = true, 2136 }, 2137 }, 2138 { 2139 .name = "MISC IO power well", 2140 /* Handled by the DMC firmware */ 2141 .domains = 0, 2142 .ops = &hsw_power_well_ops, 2143 .id = SKL_DISP_PW_MISC_IO, 2144 }, 2145 { 2146 .name = "DC off", 2147 .domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS, 2148 .ops = &gen9_dc_off_power_well_ops, 2149 .id = SKL_DISP_PW_DC_OFF, 2150 }, 2151 { 2152 .name = "power well 2", 2153 .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS, 2154 .ops = &hsw_power_well_ops, 2155 .id = SKL_DISP_PW_2, 2156 { 2157 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), 2158 .hsw.has_vga = true, 2159 .hsw.has_fuses = true, 2160 }, 2161 }, 2162 { 2163 .name = "DDI A/E IO power well", 2164 .domains = SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS, 2165 .ops = &hsw_power_well_ops, 2166 .id = SKL_DISP_PW_DDI_A_E, 2167 }, 2168 { 2169 .name = "DDI B IO power well", 2170 .domains = SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS, 2171 .ops = &hsw_power_well_ops, 2172 .id = SKL_DISP_PW_DDI_B, 2173 }, 2174 { 2175 .name = "DDI C IO power well", 2176 .domains = SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS, 2177 .ops = &hsw_power_well_ops, 2178 .id = SKL_DISP_PW_DDI_C, 2179 }, 2180 { 2181 .name = "DDI D IO power well", 2182 .domains = SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS, 2183 .ops = &hsw_power_well_ops, 2184 .id = SKL_DISP_PW_DDI_D, 2185 }, 2186 }; 2187 2188 static struct i915_power_well bxt_power_wells[] = { 2189 { 2190 .name = "always-on", 2191 .always_on = 1, 2192 .domains = POWER_DOMAIN_MASK, 2193 .ops = &i9xx_always_on_power_well_ops, 2194 .id = I915_DISP_PW_ALWAYS_ON, 2195 }, 2196 { 2197 .name = "power well 1", 2198 .domains = 0, 2199 .ops = &hsw_power_well_ops, 2200 .id = SKL_DISP_PW_1, 2201 { 2202 .hsw.has_fuses = true, 2203 }, 2204 }, 2205 { 2206 .name = "DC off", 2207 .domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS, 2208 .ops = &gen9_dc_off_power_well_ops, 2209 .id = SKL_DISP_PW_DC_OFF, 2210 }, 2211 { 2212 .name = "power well 2", 2213 .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS, 2214 .ops = &hsw_power_well_ops, 2215 .id = SKL_DISP_PW_2, 2216 { 2217 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), 2218 .hsw.has_vga = true, 2219 .hsw.has_fuses = true, 2220 }, 2221 }, 2222 { 2223 .name = "dpio-common-a", 2224 .domains = BXT_DPIO_CMN_A_POWER_DOMAINS, 2225 .ops = &bxt_dpio_cmn_power_well_ops, 2226 .id = BXT_DPIO_CMN_A, 2227 { 2228 .bxt.phy = DPIO_PHY1, 2229 }, 2230 }, 2231 { 2232 .name = "dpio-common-bc", 2233 .domains = BXT_DPIO_CMN_BC_POWER_DOMAINS, 2234 .ops = &bxt_dpio_cmn_power_well_ops, 2235 .id = BXT_DPIO_CMN_BC, 2236 { 2237 .bxt.phy = DPIO_PHY0, 2238 }, 2239 }, 2240 }; 2241 2242 static struct i915_power_well glk_power_wells[] = { 2243 { 2244 .name = "always-on", 2245 .always_on = 1, 2246 .domains = POWER_DOMAIN_MASK, 2247 .ops = &i9xx_always_on_power_well_ops, 2248 .id = I915_DISP_PW_ALWAYS_ON, 2249 }, 2250 { 2251 .name = "power well 1", 2252 /* Handled by the DMC firmware */ 2253 .domains = 0, 2254 .ops = &hsw_power_well_ops, 2255 .id = SKL_DISP_PW_1, 2256 { 2257 .hsw.has_fuses = true, 2258 }, 2259 }, 2260 { 2261 .name = "DC off", 2262 .domains = GLK_DISPLAY_DC_OFF_POWER_DOMAINS, 2263 .ops = &gen9_dc_off_power_well_ops, 2264 .id = SKL_DISP_PW_DC_OFF, 2265 }, 2266 { 2267 .name = "power well 2", 2268 .domains = GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS, 2269 .ops = &hsw_power_well_ops, 2270 .id = SKL_DISP_PW_2, 2271 { 2272 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), 2273 .hsw.has_vga = true, 2274 .hsw.has_fuses = true, 2275 }, 2276 }, 2277 { 2278 .name = "dpio-common-a", 2279 .domains = GLK_DPIO_CMN_A_POWER_DOMAINS, 2280 .ops = &bxt_dpio_cmn_power_well_ops, 2281 .id = BXT_DPIO_CMN_A, 2282 { 2283 .bxt.phy = DPIO_PHY1, 2284 }, 2285 }, 2286 { 2287 .name = "dpio-common-b", 2288 .domains = GLK_DPIO_CMN_B_POWER_DOMAINS, 2289 .ops = &bxt_dpio_cmn_power_well_ops, 2290 .id = BXT_DPIO_CMN_BC, 2291 { 2292 .bxt.phy = DPIO_PHY0, 2293 }, 2294 }, 2295 { 2296 .name = "dpio-common-c", 2297 .domains = GLK_DPIO_CMN_C_POWER_DOMAINS, 2298 .ops = &bxt_dpio_cmn_power_well_ops, 2299 .id = GLK_DPIO_CMN_C, 2300 { 2301 .bxt.phy = DPIO_PHY2, 2302 }, 2303 }, 2304 { 2305 .name = "AUX A", 2306 .domains = GLK_DISPLAY_AUX_A_POWER_DOMAINS, 2307 .ops = &hsw_power_well_ops, 2308 .id = GLK_DISP_PW_AUX_A, 2309 }, 2310 { 2311 .name = "AUX B", 2312 .domains = GLK_DISPLAY_AUX_B_POWER_DOMAINS, 2313 .ops = &hsw_power_well_ops, 2314 .id = GLK_DISP_PW_AUX_B, 2315 }, 2316 { 2317 .name = "AUX C", 2318 .domains = GLK_DISPLAY_AUX_C_POWER_DOMAINS, 2319 .ops = &hsw_power_well_ops, 2320 .id = GLK_DISP_PW_AUX_C, 2321 }, 2322 { 2323 .name = "DDI A IO power well", 2324 .domains = GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS, 2325 .ops = &hsw_power_well_ops, 2326 .id = GLK_DISP_PW_DDI_A, 2327 }, 2328 { 2329 .name = "DDI B IO power well", 2330 .domains = GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS, 2331 .ops = &hsw_power_well_ops, 2332 .id = SKL_DISP_PW_DDI_B, 2333 }, 2334 { 2335 .name = "DDI C IO power well", 2336 .domains = GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS, 2337 .ops = &hsw_power_well_ops, 2338 .id = SKL_DISP_PW_DDI_C, 2339 }, 2340 }; 2341 2342 static struct i915_power_well cnl_power_wells[] = { 2343 { 2344 .name = "always-on", 2345 .always_on = 1, 2346 .domains = POWER_DOMAIN_MASK, 2347 .ops = &i9xx_always_on_power_well_ops, 2348 .id = I915_DISP_PW_ALWAYS_ON, 2349 }, 2350 { 2351 .name = "power well 1", 2352 /* Handled by the DMC firmware */ 2353 .domains = 0, 2354 .ops = &hsw_power_well_ops, 2355 .id = SKL_DISP_PW_1, 2356 { 2357 .hsw.has_fuses = true, 2358 }, 2359 }, 2360 { 2361 .name = "AUX A", 2362 .domains = CNL_DISPLAY_AUX_A_POWER_DOMAINS, 2363 .ops = &hsw_power_well_ops, 2364 .id = CNL_DISP_PW_AUX_A, 2365 }, 2366 { 2367 .name = "AUX B", 2368 .domains = CNL_DISPLAY_AUX_B_POWER_DOMAINS, 2369 .ops = &hsw_power_well_ops, 2370 .id = CNL_DISP_PW_AUX_B, 2371 }, 2372 { 2373 .name = "AUX C", 2374 .domains = CNL_DISPLAY_AUX_C_POWER_DOMAINS, 2375 .ops = &hsw_power_well_ops, 2376 .id = CNL_DISP_PW_AUX_C, 2377 }, 2378 { 2379 .name = "AUX D", 2380 .domains = CNL_DISPLAY_AUX_D_POWER_DOMAINS, 2381 .ops = &hsw_power_well_ops, 2382 .id = CNL_DISP_PW_AUX_D, 2383 }, 2384 { 2385 .name = "DC off", 2386 .domains = CNL_DISPLAY_DC_OFF_POWER_DOMAINS, 2387 .ops = &gen9_dc_off_power_well_ops, 2388 .id = SKL_DISP_PW_DC_OFF, 2389 }, 2390 { 2391 .name = "power well 2", 2392 .domains = CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS, 2393 .ops = &hsw_power_well_ops, 2394 .id = SKL_DISP_PW_2, 2395 { 2396 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), 2397 .hsw.has_vga = true, 2398 .hsw.has_fuses = true, 2399 }, 2400 }, 2401 { 2402 .name = "DDI A IO power well", 2403 .domains = CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS, 2404 .ops = &hsw_power_well_ops, 2405 .id = CNL_DISP_PW_DDI_A, 2406 }, 2407 { 2408 .name = "DDI B IO power well", 2409 .domains = CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS, 2410 .ops = &hsw_power_well_ops, 2411 .id = SKL_DISP_PW_DDI_B, 2412 }, 2413 { 2414 .name = "DDI C IO power well", 2415 .domains = CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS, 2416 .ops = &hsw_power_well_ops, 2417 .id = SKL_DISP_PW_DDI_C, 2418 }, 2419 { 2420 .name = "DDI D IO power well", 2421 .domains = CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS, 2422 .ops = &hsw_power_well_ops, 2423 .id = SKL_DISP_PW_DDI_D, 2424 }, 2425 { 2426 .name = "DDI F IO power well", 2427 .domains = CNL_DISPLAY_DDI_F_IO_POWER_DOMAINS, 2428 .ops = &hsw_power_well_ops, 2429 .id = CNL_DISP_PW_DDI_F, 2430 }, 2431 { 2432 .name = "AUX F", 2433 .domains = CNL_DISPLAY_AUX_F_POWER_DOMAINS, 2434 .ops = &hsw_power_well_ops, 2435 .id = CNL_DISP_PW_AUX_F, 2436 }, 2437 }; 2438 2439 static int 2440 sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv, 2441 int disable_power_well) 2442 { 2443 if (disable_power_well >= 0) 2444 return !!disable_power_well; 2445 2446 return 1; 2447 } 2448 2449 static uint32_t get_allowed_dc_mask(const struct drm_i915_private *dev_priv, 2450 int enable_dc) 2451 { 2452 uint32_t mask; 2453 int requested_dc; 2454 int max_dc; 2455 2456 if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) { 2457 max_dc = 2; 2458 mask = 0; 2459 } else if (IS_GEN9_LP(dev_priv)) { 2460 max_dc = 1; 2461 /* 2462 * DC9 has a separate HW flow from the rest of the DC states, 2463 * not depending on the DMC firmware. It's needed by system 2464 * suspend/resume, so allow it unconditionally. 2465 */ 2466 mask = DC_STATE_EN_DC9; 2467 } else { 2468 max_dc = 0; 2469 mask = 0; 2470 } 2471 2472 if (!i915_modparams.disable_power_well) 2473 max_dc = 0; 2474 2475 if (enable_dc >= 0 && enable_dc <= max_dc) { 2476 requested_dc = enable_dc; 2477 } else if (enable_dc == -1) { 2478 requested_dc = max_dc; 2479 } else if (enable_dc > max_dc && enable_dc <= 2) { 2480 DRM_DEBUG_KMS("Adjusting requested max DC state (%d->%d)\n", 2481 enable_dc, max_dc); 2482 requested_dc = max_dc; 2483 } else { 2484 DRM_ERROR("Unexpected value for enable_dc (%d)\n", enable_dc); 2485 requested_dc = max_dc; 2486 } 2487 2488 if (requested_dc > 1) 2489 mask |= DC_STATE_EN_UPTO_DC6; 2490 if (requested_dc > 0) 2491 mask |= DC_STATE_EN_UPTO_DC5; 2492 2493 DRM_DEBUG_KMS("Allowed DC state mask %02x\n", mask); 2494 2495 return mask; 2496 } 2497 2498 static void assert_power_well_ids_unique(struct drm_i915_private *dev_priv) 2499 { 2500 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2501 u64 power_well_ids; 2502 int i; 2503 2504 power_well_ids = 0; 2505 for (i = 0; i < power_domains->power_well_count; i++) { 2506 enum i915_power_well_id id = power_domains->power_wells[i].id; 2507 2508 WARN_ON(id >= sizeof(power_well_ids) * 8); 2509 WARN_ON(power_well_ids & BIT_ULL(id)); 2510 power_well_ids |= BIT_ULL(id); 2511 } 2512 } 2513 2514 #define set_power_wells(power_domains, __power_wells) ({ \ 2515 (power_domains)->power_wells = (__power_wells); \ 2516 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \ 2517 }) 2518 2519 /** 2520 * intel_power_domains_init - initializes the power domain structures 2521 * @dev_priv: i915 device instance 2522 * 2523 * Initializes the power domain structures for @dev_priv depending upon the 2524 * supported platform. 2525 */ 2526 int intel_power_domains_init(struct drm_i915_private *dev_priv) 2527 { 2528 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2529 2530 i915_modparams.disable_power_well = 2531 sanitize_disable_power_well_option(dev_priv, 2532 i915_modparams.disable_power_well); 2533 dev_priv->csr.allowed_dc_mask = 2534 get_allowed_dc_mask(dev_priv, i915_modparams.enable_dc); 2535 2536 BUILD_BUG_ON(POWER_DOMAIN_NUM > 64); 2537 2538 mutex_init(&power_domains->lock); 2539 2540 /* 2541 * The enabling order will be from lower to higher indexed wells, 2542 * the disabling order is reversed. 2543 */ 2544 if (IS_HASWELL(dev_priv)) { 2545 set_power_wells(power_domains, hsw_power_wells); 2546 } else if (IS_BROADWELL(dev_priv)) { 2547 set_power_wells(power_domains, bdw_power_wells); 2548 } else if (IS_GEN9_BC(dev_priv)) { 2549 set_power_wells(power_domains, skl_power_wells); 2550 } else if (IS_CANNONLAKE(dev_priv)) { 2551 set_power_wells(power_domains, cnl_power_wells); 2552 2553 /* 2554 * DDI and Aux IO are getting enabled for all ports 2555 * regardless the presence or use. So, in order to avoid 2556 * timeouts, lets remove them from the list 2557 * for the SKUs without port F. 2558 */ 2559 if (!IS_CNL_WITH_PORT_F(dev_priv)) 2560 power_domains->power_well_count -= 2; 2561 2562 } else if (IS_BROXTON(dev_priv)) { 2563 set_power_wells(power_domains, bxt_power_wells); 2564 } else if (IS_GEMINILAKE(dev_priv)) { 2565 set_power_wells(power_domains, glk_power_wells); 2566 } else if (IS_CHERRYVIEW(dev_priv)) { 2567 set_power_wells(power_domains, chv_power_wells); 2568 } else if (IS_VALLEYVIEW(dev_priv)) { 2569 set_power_wells(power_domains, vlv_power_wells); 2570 } else if (IS_I830(dev_priv)) { 2571 set_power_wells(power_domains, i830_power_wells); 2572 } else { 2573 set_power_wells(power_domains, i9xx_always_on_power_well); 2574 } 2575 2576 assert_power_well_ids_unique(dev_priv); 2577 2578 return 0; 2579 } 2580 2581 /** 2582 * intel_power_domains_fini - finalizes the power domain structures 2583 * @dev_priv: i915 device instance 2584 * 2585 * Finalizes the power domain structures for @dev_priv depending upon the 2586 * supported platform. This function also disables runtime pm and ensures that 2587 * the device stays powered up so that the driver can be reloaded. 2588 */ 2589 void intel_power_domains_fini(struct drm_i915_private *dev_priv) 2590 { 2591 struct device *kdev = &dev_priv->drm.pdev->dev; 2592 2593 /* 2594 * The i915.ko module is still not prepared to be loaded when 2595 * the power well is not enabled, so just enable it in case 2596 * we're going to unload/reload. 2597 * The following also reacquires the RPM reference the core passed 2598 * to the driver during loading, which is dropped in 2599 * intel_runtime_pm_enable(). We have to hand back the control of the 2600 * device to the core with this reference held. 2601 */ 2602 intel_display_set_init_power(dev_priv, true); 2603 2604 /* Remove the refcount we took to keep power well support disabled. */ 2605 if (!i915_modparams.disable_power_well) 2606 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); 2607 2608 /* 2609 * Remove the refcount we took in intel_runtime_pm_enable() in case 2610 * the platform doesn't support runtime PM. 2611 */ 2612 if (!HAS_RUNTIME_PM(dev_priv)) 2613 pm_runtime_put(kdev); 2614 } 2615 2616 static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv) 2617 { 2618 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2619 struct i915_power_well *power_well; 2620 2621 mutex_lock(&power_domains->lock); 2622 for_each_power_well(dev_priv, power_well) { 2623 power_well->ops->sync_hw(dev_priv, power_well); 2624 power_well->hw_enabled = power_well->ops->is_enabled(dev_priv, 2625 power_well); 2626 } 2627 mutex_unlock(&power_domains->lock); 2628 } 2629 2630 static void gen9_dbuf_enable(struct drm_i915_private *dev_priv) 2631 { 2632 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); 2633 POSTING_READ(DBUF_CTL); 2634 2635 udelay(10); 2636 2637 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) 2638 DRM_ERROR("DBuf power enable timeout\n"); 2639 } 2640 2641 static void gen9_dbuf_disable(struct drm_i915_private *dev_priv) 2642 { 2643 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); 2644 POSTING_READ(DBUF_CTL); 2645 2646 udelay(10); 2647 2648 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) 2649 DRM_ERROR("DBuf power disable timeout!\n"); 2650 } 2651 2652 /* 2653 * TODO: we shouldn't always enable DBUF_CTL_S2, we should only enable it when 2654 * needed and keep it disabled as much as possible. 2655 */ 2656 static void icl_dbuf_enable(struct drm_i915_private *dev_priv) 2657 { 2658 I915_WRITE(DBUF_CTL_S1, I915_READ(DBUF_CTL_S1) | DBUF_POWER_REQUEST); 2659 I915_WRITE(DBUF_CTL_S2, I915_READ(DBUF_CTL_S2) | DBUF_POWER_REQUEST); 2660 POSTING_READ(DBUF_CTL_S2); 2661 2662 udelay(10); 2663 2664 if (!(I915_READ(DBUF_CTL_S1) & DBUF_POWER_STATE) || 2665 !(I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE)) 2666 DRM_ERROR("DBuf power enable timeout\n"); 2667 } 2668 2669 static void icl_dbuf_disable(struct drm_i915_private *dev_priv) 2670 { 2671 I915_WRITE(DBUF_CTL_S1, I915_READ(DBUF_CTL_S1) & ~DBUF_POWER_REQUEST); 2672 I915_WRITE(DBUF_CTL_S2, I915_READ(DBUF_CTL_S2) & ~DBUF_POWER_REQUEST); 2673 POSTING_READ(DBUF_CTL_S2); 2674 2675 udelay(10); 2676 2677 if ((I915_READ(DBUF_CTL_S1) & DBUF_POWER_STATE) || 2678 (I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE)) 2679 DRM_ERROR("DBuf power disable timeout!\n"); 2680 } 2681 2682 static void icl_mbus_init(struct drm_i915_private *dev_priv) 2683 { 2684 uint32_t val; 2685 2686 val = MBUS_ABOX_BT_CREDIT_POOL1(16) | 2687 MBUS_ABOX_BT_CREDIT_POOL2(16) | 2688 MBUS_ABOX_B_CREDIT(1) | 2689 MBUS_ABOX_BW_CREDIT(1); 2690 2691 I915_WRITE(MBUS_ABOX_CTL, val); 2692 } 2693 2694 static void skl_display_core_init(struct drm_i915_private *dev_priv, 2695 bool resume) 2696 { 2697 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2698 struct i915_power_well *well; 2699 uint32_t val; 2700 2701 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 2702 2703 /* enable PCH reset handshake */ 2704 val = I915_READ(HSW_NDE_RSTWRN_OPT); 2705 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE); 2706 2707 /* enable PG1 and Misc I/O */ 2708 mutex_lock(&power_domains->lock); 2709 2710 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 2711 intel_power_well_enable(dev_priv, well); 2712 2713 well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO); 2714 intel_power_well_enable(dev_priv, well); 2715 2716 mutex_unlock(&power_domains->lock); 2717 2718 skl_init_cdclk(dev_priv); 2719 2720 gen9_dbuf_enable(dev_priv); 2721 2722 if (resume && dev_priv->csr.dmc_payload) 2723 intel_csr_load_program(dev_priv); 2724 } 2725 2726 static void skl_display_core_uninit(struct drm_i915_private *dev_priv) 2727 { 2728 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2729 struct i915_power_well *well; 2730 2731 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 2732 2733 gen9_dbuf_disable(dev_priv); 2734 2735 skl_uninit_cdclk(dev_priv); 2736 2737 /* The spec doesn't call for removing the reset handshake flag */ 2738 /* disable PG1 and Misc I/O */ 2739 2740 mutex_lock(&power_domains->lock); 2741 2742 /* 2743 * BSpec says to keep the MISC IO power well enabled here, only 2744 * remove our request for power well 1. 2745 * Note that even though the driver's request is removed power well 1 2746 * may stay enabled after this due to DMC's own request on it. 2747 */ 2748 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 2749 intel_power_well_disable(dev_priv, well); 2750 2751 mutex_unlock(&power_domains->lock); 2752 2753 usleep_range(10, 30); /* 10 us delay per Bspec */ 2754 } 2755 2756 void bxt_display_core_init(struct drm_i915_private *dev_priv, 2757 bool resume) 2758 { 2759 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2760 struct i915_power_well *well; 2761 uint32_t val; 2762 2763 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 2764 2765 /* 2766 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT 2767 * or else the reset will hang because there is no PCH to respond. 2768 * Move the handshake programming to initialization sequence. 2769 * Previously was left up to BIOS. 2770 */ 2771 val = I915_READ(HSW_NDE_RSTWRN_OPT); 2772 val &= ~RESET_PCH_HANDSHAKE_ENABLE; 2773 I915_WRITE(HSW_NDE_RSTWRN_OPT, val); 2774 2775 /* Enable PG1 */ 2776 mutex_lock(&power_domains->lock); 2777 2778 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 2779 intel_power_well_enable(dev_priv, well); 2780 2781 mutex_unlock(&power_domains->lock); 2782 2783 bxt_init_cdclk(dev_priv); 2784 2785 gen9_dbuf_enable(dev_priv); 2786 2787 if (resume && dev_priv->csr.dmc_payload) 2788 intel_csr_load_program(dev_priv); 2789 } 2790 2791 void bxt_display_core_uninit(struct drm_i915_private *dev_priv) 2792 { 2793 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2794 struct i915_power_well *well; 2795 2796 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 2797 2798 gen9_dbuf_disable(dev_priv); 2799 2800 bxt_uninit_cdclk(dev_priv); 2801 2802 /* The spec doesn't call for removing the reset handshake flag */ 2803 2804 /* 2805 * Disable PW1 (PG1). 2806 * Note that even though the driver's request is removed power well 1 2807 * may stay enabled after this due to DMC's own request on it. 2808 */ 2809 mutex_lock(&power_domains->lock); 2810 2811 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 2812 intel_power_well_disable(dev_priv, well); 2813 2814 mutex_unlock(&power_domains->lock); 2815 2816 usleep_range(10, 30); /* 10 us delay per Bspec */ 2817 } 2818 2819 enum { 2820 PROCMON_0_85V_DOT_0, 2821 PROCMON_0_95V_DOT_0, 2822 PROCMON_0_95V_DOT_1, 2823 PROCMON_1_05V_DOT_0, 2824 PROCMON_1_05V_DOT_1, 2825 }; 2826 2827 static const struct cnl_procmon { 2828 u32 dw1, dw9, dw10; 2829 } cnl_procmon_values[] = { 2830 [PROCMON_0_85V_DOT_0] = 2831 { .dw1 = 0x00000000, .dw9 = 0x62AB67BB, .dw10 = 0x51914F96, }, 2832 [PROCMON_0_95V_DOT_0] = 2833 { .dw1 = 0x00000000, .dw9 = 0x86E172C7, .dw10 = 0x77CA5EAB, }, 2834 [PROCMON_0_95V_DOT_1] = 2835 { .dw1 = 0x00000000, .dw9 = 0x93F87FE1, .dw10 = 0x8AE871C5, }, 2836 [PROCMON_1_05V_DOT_0] = 2837 { .dw1 = 0x00000000, .dw9 = 0x98FA82DD, .dw10 = 0x89E46DC1, }, 2838 [PROCMON_1_05V_DOT_1] = 2839 { .dw1 = 0x00440000, .dw9 = 0x9A00AB25, .dw10 = 0x8AE38FF1, }, 2840 }; 2841 2842 /* 2843 * CNL has just one set of registers, while ICL has two sets: one for port A and 2844 * the other for port B. The CNL registers are equivalent to the ICL port A 2845 * registers, that's why we call the ICL macros even though the function has CNL 2846 * on its name. 2847 */ 2848 static void cnl_set_procmon_ref_values(struct drm_i915_private *dev_priv, 2849 enum port port) 2850 { 2851 const struct cnl_procmon *procmon; 2852 u32 val; 2853 2854 val = I915_READ(ICL_PORT_COMP_DW3(port)); 2855 switch (val & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) { 2856 default: 2857 MISSING_CASE(val); 2858 case VOLTAGE_INFO_0_85V | PROCESS_INFO_DOT_0: 2859 procmon = &cnl_procmon_values[PROCMON_0_85V_DOT_0]; 2860 break; 2861 case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_0: 2862 procmon = &cnl_procmon_values[PROCMON_0_95V_DOT_0]; 2863 break; 2864 case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_1: 2865 procmon = &cnl_procmon_values[PROCMON_0_95V_DOT_1]; 2866 break; 2867 case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_0: 2868 procmon = &cnl_procmon_values[PROCMON_1_05V_DOT_0]; 2869 break; 2870 case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_1: 2871 procmon = &cnl_procmon_values[PROCMON_1_05V_DOT_1]; 2872 break; 2873 } 2874 2875 val = I915_READ(ICL_PORT_COMP_DW1(port)); 2876 val &= ~((0xff << 16) | 0xff); 2877 val |= procmon->dw1; 2878 I915_WRITE(ICL_PORT_COMP_DW1(port), val); 2879 2880 I915_WRITE(ICL_PORT_COMP_DW9(port), procmon->dw9); 2881 I915_WRITE(ICL_PORT_COMP_DW10(port), procmon->dw10); 2882 } 2883 2884 static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume) 2885 { 2886 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2887 struct i915_power_well *well; 2888 u32 val; 2889 2890 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 2891 2892 /* 1. Enable PCH Reset Handshake */ 2893 val = I915_READ(HSW_NDE_RSTWRN_OPT); 2894 val |= RESET_PCH_HANDSHAKE_ENABLE; 2895 I915_WRITE(HSW_NDE_RSTWRN_OPT, val); 2896 2897 /* 2. Enable Comp */ 2898 val = I915_READ(CHICKEN_MISC_2); 2899 val &= ~CNL_COMP_PWR_DOWN; 2900 I915_WRITE(CHICKEN_MISC_2, val); 2901 2902 /* Dummy PORT_A to get the correct CNL register from the ICL macro */ 2903 cnl_set_procmon_ref_values(dev_priv, PORT_A); 2904 2905 val = I915_READ(CNL_PORT_COMP_DW0); 2906 val |= COMP_INIT; 2907 I915_WRITE(CNL_PORT_COMP_DW0, val); 2908 2909 /* 3. */ 2910 val = I915_READ(CNL_PORT_CL1CM_DW5); 2911 val |= CL_POWER_DOWN_ENABLE; 2912 I915_WRITE(CNL_PORT_CL1CM_DW5, val); 2913 2914 /* 2915 * 4. Enable Power Well 1 (PG1). 2916 * The AUX IO power wells will be enabled on demand. 2917 */ 2918 mutex_lock(&power_domains->lock); 2919 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 2920 intel_power_well_enable(dev_priv, well); 2921 mutex_unlock(&power_domains->lock); 2922 2923 /* 5. Enable CD clock */ 2924 cnl_init_cdclk(dev_priv); 2925 2926 /* 6. Enable DBUF */ 2927 gen9_dbuf_enable(dev_priv); 2928 2929 if (resume && dev_priv->csr.dmc_payload) 2930 intel_csr_load_program(dev_priv); 2931 } 2932 2933 static void cnl_display_core_uninit(struct drm_i915_private *dev_priv) 2934 { 2935 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2936 struct i915_power_well *well; 2937 u32 val; 2938 2939 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 2940 2941 /* 1. Disable all display engine functions -> aready done */ 2942 2943 /* 2. Disable DBUF */ 2944 gen9_dbuf_disable(dev_priv); 2945 2946 /* 3. Disable CD clock */ 2947 cnl_uninit_cdclk(dev_priv); 2948 2949 /* 2950 * 4. Disable Power Well 1 (PG1). 2951 * The AUX IO power wells are toggled on demand, so they are already 2952 * disabled at this point. 2953 */ 2954 mutex_lock(&power_domains->lock); 2955 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 2956 intel_power_well_disable(dev_priv, well); 2957 mutex_unlock(&power_domains->lock); 2958 2959 usleep_range(10, 30); /* 10 us delay per Bspec */ 2960 2961 /* 5. Disable Comp */ 2962 val = I915_READ(CHICKEN_MISC_2); 2963 val |= CNL_COMP_PWR_DOWN; 2964 I915_WRITE(CHICKEN_MISC_2, val); 2965 } 2966 2967 static void icl_display_core_init(struct drm_i915_private *dev_priv, 2968 bool resume) 2969 { 2970 enum port port; 2971 u32 val; 2972 2973 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 2974 2975 /* 1. Enable PCH reset handshake. */ 2976 val = I915_READ(HSW_NDE_RSTWRN_OPT); 2977 val |= RESET_PCH_HANDSHAKE_ENABLE; 2978 I915_WRITE(HSW_NDE_RSTWRN_OPT, val); 2979 2980 for (port = PORT_A; port <= PORT_B; port++) { 2981 /* 2. Enable DDI combo PHY comp. */ 2982 val = I915_READ(ICL_PHY_MISC(port)); 2983 val &= ~ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN; 2984 I915_WRITE(ICL_PHY_MISC(port), val); 2985 2986 cnl_set_procmon_ref_values(dev_priv, port); 2987 2988 val = I915_READ(ICL_PORT_COMP_DW0(port)); 2989 val |= COMP_INIT; 2990 I915_WRITE(ICL_PORT_COMP_DW0(port), val); 2991 2992 /* 3. Set power down enable. */ 2993 val = I915_READ(ICL_PORT_CL_DW5(port)); 2994 val |= CL_POWER_DOWN_ENABLE; 2995 I915_WRITE(ICL_PORT_CL_DW5(port), val); 2996 } 2997 2998 /* 4. Enable power well 1 (PG1) and aux IO power. */ 2999 /* FIXME: ICL power wells code not here yet. */ 3000 3001 /* 5. Enable CDCLK. */ 3002 icl_init_cdclk(dev_priv); 3003 3004 /* 6. Enable DBUF. */ 3005 icl_dbuf_enable(dev_priv); 3006 3007 /* 7. Setup MBUS. */ 3008 icl_mbus_init(dev_priv); 3009 3010 /* 8. CHICKEN_DCPR_1 */ 3011 I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) | 3012 CNL_DDI_CLOCK_REG_ACCESS_ON); 3013 } 3014 3015 static void icl_display_core_uninit(struct drm_i915_private *dev_priv) 3016 { 3017 enum port port; 3018 u32 val; 3019 3020 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 3021 3022 /* 1. Disable all display engine functions -> aready done */ 3023 3024 /* 2. Disable DBUF */ 3025 icl_dbuf_disable(dev_priv); 3026 3027 /* 3. Disable CD clock */ 3028 icl_uninit_cdclk(dev_priv); 3029 3030 /* 4. Disable Power Well 1 (PG1) and Aux IO Power */ 3031 /* FIXME: ICL power wells code not here yet. */ 3032 3033 /* 5. Disable Comp */ 3034 for (port = PORT_A; port <= PORT_B; port++) { 3035 val = I915_READ(ICL_PHY_MISC(port)); 3036 val |= ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN; 3037 I915_WRITE(ICL_PHY_MISC(port), val); 3038 } 3039 } 3040 3041 static void chv_phy_control_init(struct drm_i915_private *dev_priv) 3042 { 3043 struct i915_power_well *cmn_bc = 3044 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC); 3045 struct i915_power_well *cmn_d = 3046 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D); 3047 3048 /* 3049 * DISPLAY_PHY_CONTROL can get corrupted if read. As a 3050 * workaround never ever read DISPLAY_PHY_CONTROL, and 3051 * instead maintain a shadow copy ourselves. Use the actual 3052 * power well state and lane status to reconstruct the 3053 * expected initial value. 3054 */ 3055 dev_priv->chv_phy_control = 3056 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) | 3057 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) | 3058 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) | 3059 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH1) | 3060 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY1, DPIO_CH0); 3061 3062 /* 3063 * If all lanes are disabled we leave the override disabled 3064 * with all power down bits cleared to match the state we 3065 * would use after disabling the port. Otherwise enable the 3066 * override and set the lane powerdown bits accding to the 3067 * current lane status. 3068 */ 3069 if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) { 3070 uint32_t status = I915_READ(DPLL(PIPE_A)); 3071 unsigned int mask; 3072 3073 mask = status & DPLL_PORTB_READY_MASK; 3074 if (mask == 0xf) 3075 mask = 0x0; 3076 else 3077 dev_priv->chv_phy_control |= 3078 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0); 3079 3080 dev_priv->chv_phy_control |= 3081 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0); 3082 3083 mask = (status & DPLL_PORTC_READY_MASK) >> 4; 3084 if (mask == 0xf) 3085 mask = 0x0; 3086 else 3087 dev_priv->chv_phy_control |= 3088 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1); 3089 3090 dev_priv->chv_phy_control |= 3091 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1); 3092 3093 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0); 3094 3095 dev_priv->chv_phy_assert[DPIO_PHY0] = false; 3096 } else { 3097 dev_priv->chv_phy_assert[DPIO_PHY0] = true; 3098 } 3099 3100 if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) { 3101 uint32_t status = I915_READ(DPIO_PHY_STATUS); 3102 unsigned int mask; 3103 3104 mask = status & DPLL_PORTD_READY_MASK; 3105 3106 if (mask == 0xf) 3107 mask = 0x0; 3108 else 3109 dev_priv->chv_phy_control |= 3110 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0); 3111 3112 dev_priv->chv_phy_control |= 3113 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0); 3114 3115 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1); 3116 3117 dev_priv->chv_phy_assert[DPIO_PHY1] = false; 3118 } else { 3119 dev_priv->chv_phy_assert[DPIO_PHY1] = true; 3120 } 3121 3122 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); 3123 3124 DRM_DEBUG_KMS("Initial PHY_CONTROL=0x%08x\n", 3125 dev_priv->chv_phy_control); 3126 } 3127 3128 static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv) 3129 { 3130 struct i915_power_well *cmn = 3131 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC); 3132 struct i915_power_well *disp2d = 3133 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D); 3134 3135 /* If the display might be already active skip this */ 3136 if (cmn->ops->is_enabled(dev_priv, cmn) && 3137 disp2d->ops->is_enabled(dev_priv, disp2d) && 3138 I915_READ(DPIO_CTL) & DPIO_CMNRST) 3139 return; 3140 3141 DRM_DEBUG_KMS("toggling display PHY side reset\n"); 3142 3143 /* cmnlane needs DPLL registers */ 3144 disp2d->ops->enable(dev_priv, disp2d); 3145 3146 /* 3147 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx: 3148 * Need to assert and de-assert PHY SB reset by gating the 3149 * common lane power, then un-gating it. 3150 * Simply ungating isn't enough to reset the PHY enough to get 3151 * ports and lanes running. 3152 */ 3153 cmn->ops->disable(dev_priv, cmn); 3154 } 3155 3156 /** 3157 * intel_power_domains_init_hw - initialize hardware power domain state 3158 * @dev_priv: i915 device instance 3159 * @resume: Called from resume code paths or not 3160 * 3161 * This function initializes the hardware power domain state and enables all 3162 * power wells belonging to the INIT power domain. Power wells in other 3163 * domains (and not in the INIT domain) are referenced or disabled during the 3164 * modeset state HW readout. After that the reference count of each power well 3165 * must match its HW enabled state, see intel_power_domains_verify_state(). 3166 */ 3167 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume) 3168 { 3169 struct i915_power_domains *power_domains = &dev_priv->power_domains; 3170 3171 power_domains->initializing = true; 3172 3173 if (IS_ICELAKE(dev_priv)) { 3174 icl_display_core_init(dev_priv, resume); 3175 } else if (IS_CANNONLAKE(dev_priv)) { 3176 cnl_display_core_init(dev_priv, resume); 3177 } else if (IS_GEN9_BC(dev_priv)) { 3178 skl_display_core_init(dev_priv, resume); 3179 } else if (IS_GEN9_LP(dev_priv)) { 3180 bxt_display_core_init(dev_priv, resume); 3181 } else if (IS_CHERRYVIEW(dev_priv)) { 3182 mutex_lock(&power_domains->lock); 3183 chv_phy_control_init(dev_priv); 3184 mutex_unlock(&power_domains->lock); 3185 } else if (IS_VALLEYVIEW(dev_priv)) { 3186 mutex_lock(&power_domains->lock); 3187 vlv_cmnlane_wa(dev_priv); 3188 mutex_unlock(&power_domains->lock); 3189 } 3190 3191 /* For now, we need the power well to be always enabled. */ 3192 intel_display_set_init_power(dev_priv, true); 3193 /* Disable power support if the user asked so. */ 3194 if (!i915_modparams.disable_power_well) 3195 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); 3196 intel_power_domains_sync_hw(dev_priv); 3197 power_domains->initializing = false; 3198 } 3199 3200 /** 3201 * intel_power_domains_suspend - suspend power domain state 3202 * @dev_priv: i915 device instance 3203 * 3204 * This function prepares the hardware power domain state before entering 3205 * system suspend. It must be paired with intel_power_domains_init_hw(). 3206 */ 3207 void intel_power_domains_suspend(struct drm_i915_private *dev_priv) 3208 { 3209 /* 3210 * Even if power well support was disabled we still want to disable 3211 * power wells while we are system suspended. 3212 */ 3213 if (!i915_modparams.disable_power_well) 3214 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); 3215 3216 if (IS_ICELAKE(dev_priv)) 3217 icl_display_core_uninit(dev_priv); 3218 else if (IS_CANNONLAKE(dev_priv)) 3219 cnl_display_core_uninit(dev_priv); 3220 else if (IS_GEN9_BC(dev_priv)) 3221 skl_display_core_uninit(dev_priv); 3222 else if (IS_GEN9_LP(dev_priv)) 3223 bxt_display_core_uninit(dev_priv); 3224 } 3225 3226 static void intel_power_domains_dump_info(struct drm_i915_private *dev_priv) 3227 { 3228 struct i915_power_domains *power_domains = &dev_priv->power_domains; 3229 struct i915_power_well *power_well; 3230 3231 for_each_power_well(dev_priv, power_well) { 3232 enum intel_display_power_domain domain; 3233 3234 DRM_DEBUG_DRIVER("%-25s %d\n", 3235 power_well->name, power_well->count); 3236 3237 for_each_power_domain(domain, power_well->domains) 3238 DRM_DEBUG_DRIVER(" %-23s %d\n", 3239 intel_display_power_domain_str(domain), 3240 power_domains->domain_use_count[domain]); 3241 } 3242 } 3243 3244 /** 3245 * intel_power_domains_verify_state - verify the HW/SW state for all power wells 3246 * @dev_priv: i915 device instance 3247 * 3248 * Verify if the reference count of each power well matches its HW enabled 3249 * state and the total refcount of the domains it belongs to. This must be 3250 * called after modeset HW state sanitization, which is responsible for 3251 * acquiring reference counts for any power wells in use and disabling the 3252 * ones left on by BIOS but not required by any active output. 3253 */ 3254 void intel_power_domains_verify_state(struct drm_i915_private *dev_priv) 3255 { 3256 struct i915_power_domains *power_domains = &dev_priv->power_domains; 3257 struct i915_power_well *power_well; 3258 bool dump_domain_info; 3259 3260 mutex_lock(&power_domains->lock); 3261 3262 dump_domain_info = false; 3263 for_each_power_well(dev_priv, power_well) { 3264 enum intel_display_power_domain domain; 3265 int domains_count; 3266 bool enabled; 3267 3268 /* 3269 * Power wells not belonging to any domain (like the MISC_IO 3270 * and PW1 power wells) are under FW control, so ignore them, 3271 * since their state can change asynchronously. 3272 */ 3273 if (!power_well->domains) 3274 continue; 3275 3276 enabled = power_well->ops->is_enabled(dev_priv, power_well); 3277 if ((power_well->count || power_well->always_on) != enabled) 3278 DRM_ERROR("power well %s state mismatch (refcount %d/enabled %d)", 3279 power_well->name, power_well->count, enabled); 3280 3281 domains_count = 0; 3282 for_each_power_domain(domain, power_well->domains) 3283 domains_count += power_domains->domain_use_count[domain]; 3284 3285 if (power_well->count != domains_count) { 3286 DRM_ERROR("power well %s refcount/domain refcount mismatch " 3287 "(refcount %d/domains refcount %d)\n", 3288 power_well->name, power_well->count, 3289 domains_count); 3290 dump_domain_info = true; 3291 } 3292 } 3293 3294 if (dump_domain_info) { 3295 static bool dumped; 3296 3297 if (!dumped) { 3298 intel_power_domains_dump_info(dev_priv); 3299 dumped = true; 3300 } 3301 } 3302 3303 mutex_unlock(&power_domains->lock); 3304 } 3305 3306 /** 3307 * intel_runtime_pm_get - grab a runtime pm reference 3308 * @dev_priv: i915 device instance 3309 * 3310 * This function grabs a device-level runtime pm reference (mostly used for GEM 3311 * code to ensure the GTT or GT is on) and ensures that it is powered up. 3312 * 3313 * Any runtime pm reference obtained by this function must have a symmetric 3314 * call to intel_runtime_pm_put() to release the reference again. 3315 */ 3316 void intel_runtime_pm_get(struct drm_i915_private *dev_priv) 3317 { 3318 struct pci_dev *pdev = dev_priv->drm.pdev; 3319 struct device *kdev = &pdev->dev; 3320 int ret; 3321 3322 ret = pm_runtime_get_sync(kdev); 3323 WARN_ONCE(ret < 0, "pm_runtime_get_sync() failed: %d\n", ret); 3324 3325 atomic_inc(&dev_priv->runtime_pm.wakeref_count); 3326 assert_rpm_wakelock_held(dev_priv); 3327 } 3328 3329 /** 3330 * intel_runtime_pm_get_if_in_use - grab a runtime pm reference if device in use 3331 * @dev_priv: i915 device instance 3332 * 3333 * This function grabs a device-level runtime pm reference if the device is 3334 * already in use and ensures that it is powered up. It is illegal to try 3335 * and access the HW should intel_runtime_pm_get_if_in_use() report failure. 3336 * 3337 * Any runtime pm reference obtained by this function must have a symmetric 3338 * call to intel_runtime_pm_put() to release the reference again. 3339 * 3340 * Returns: True if the wakeref was acquired, or False otherwise. 3341 */ 3342 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv) 3343 { 3344 if (IS_ENABLED(CONFIG_PM)) { 3345 struct pci_dev *pdev = dev_priv->drm.pdev; 3346 struct device *kdev = &pdev->dev; 3347 3348 /* 3349 * In cases runtime PM is disabled by the RPM core and we get 3350 * an -EINVAL return value we are not supposed to call this 3351 * function, since the power state is undefined. This applies 3352 * atm to the late/early system suspend/resume handlers. 3353 */ 3354 if (pm_runtime_get_if_in_use(kdev) <= 0) 3355 return false; 3356 } 3357 3358 atomic_inc(&dev_priv->runtime_pm.wakeref_count); 3359 assert_rpm_wakelock_held(dev_priv); 3360 3361 return true; 3362 } 3363 3364 /** 3365 * intel_runtime_pm_get_noresume - grab a runtime pm reference 3366 * @dev_priv: i915 device instance 3367 * 3368 * This function grabs a device-level runtime pm reference (mostly used for GEM 3369 * code to ensure the GTT or GT is on). 3370 * 3371 * It will _not_ power up the device but instead only check that it's powered 3372 * on. Therefore it is only valid to call this functions from contexts where 3373 * the device is known to be powered up and where trying to power it up would 3374 * result in hilarity and deadlocks. That pretty much means only the system 3375 * suspend/resume code where this is used to grab runtime pm references for 3376 * delayed setup down in work items. 3377 * 3378 * Any runtime pm reference obtained by this function must have a symmetric 3379 * call to intel_runtime_pm_put() to release the reference again. 3380 */ 3381 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv) 3382 { 3383 struct pci_dev *pdev = dev_priv->drm.pdev; 3384 struct device *kdev = &pdev->dev; 3385 3386 assert_rpm_wakelock_held(dev_priv); 3387 pm_runtime_get_noresume(kdev); 3388 3389 atomic_inc(&dev_priv->runtime_pm.wakeref_count); 3390 } 3391 3392 /** 3393 * intel_runtime_pm_put - release a runtime pm reference 3394 * @dev_priv: i915 device instance 3395 * 3396 * This function drops the device-level runtime pm reference obtained by 3397 * intel_runtime_pm_get() and might power down the corresponding 3398 * hardware block right away if this is the last reference. 3399 */ 3400 void intel_runtime_pm_put(struct drm_i915_private *dev_priv) 3401 { 3402 struct pci_dev *pdev = dev_priv->drm.pdev; 3403 struct device *kdev = &pdev->dev; 3404 3405 assert_rpm_wakelock_held(dev_priv); 3406 atomic_dec(&dev_priv->runtime_pm.wakeref_count); 3407 3408 pm_runtime_mark_last_busy(kdev); 3409 pm_runtime_put_autosuspend(kdev); 3410 } 3411 3412 /** 3413 * intel_runtime_pm_enable - enable runtime pm 3414 * @dev_priv: i915 device instance 3415 * 3416 * This function enables runtime pm at the end of the driver load sequence. 3417 * 3418 * Note that this function does currently not enable runtime pm for the 3419 * subordinate display power domains. That is only done on the first modeset 3420 * using intel_display_set_init_power(). 3421 */ 3422 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv) 3423 { 3424 struct pci_dev *pdev = dev_priv->drm.pdev; 3425 struct device *kdev = &pdev->dev; 3426 3427 pm_runtime_set_autosuspend_delay(kdev, 10000); /* 10s */ 3428 pm_runtime_mark_last_busy(kdev); 3429 3430 /* 3431 * Take a permanent reference to disable the RPM functionality and drop 3432 * it only when unloading the driver. Use the low level get/put helpers, 3433 * so the driver's own RPM reference tracking asserts also work on 3434 * platforms without RPM support. 3435 */ 3436 if (!HAS_RUNTIME_PM(dev_priv)) { 3437 int ret; 3438 3439 pm_runtime_dont_use_autosuspend(kdev); 3440 ret = pm_runtime_get_sync(kdev); 3441 WARN(ret < 0, "pm_runtime_get_sync() failed: %d\n", ret); 3442 } else { 3443 pm_runtime_use_autosuspend(kdev); 3444 } 3445 3446 /* 3447 * The core calls the driver load handler with an RPM reference held. 3448 * We drop that here and will reacquire it during unloading in 3449 * intel_power_domains_fini(). 3450 */ 3451 pm_runtime_put_autosuspend(kdev); 3452 } 3453