1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ 3 #define _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ 4 5 #include <asm-generic/5level-fixup.h> 6 7 #ifndef __ASSEMBLY__ 8 #include <linux/mmdebug.h> 9 #include <linux/bug.h> 10 #endif 11 12 /* 13 * Common bits between hash and Radix page table 14 */ 15 #define _PAGE_BIT_SWAP_TYPE 0 16 17 #define _PAGE_NA 0 18 #define _PAGE_RO 0 19 #define _PAGE_USER 0 20 21 #define _PAGE_EXEC 0x00001 /* execute permission */ 22 #define _PAGE_WRITE 0x00002 /* write access allowed */ 23 #define _PAGE_READ 0x00004 /* read access allowed */ 24 #define _PAGE_RW (_PAGE_READ | _PAGE_WRITE) 25 #define _PAGE_RWX (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC) 26 #define _PAGE_PRIVILEGED 0x00008 /* kernel access only */ 27 #define _PAGE_SAO 0x00010 /* Strong access order */ 28 #define _PAGE_NON_IDEMPOTENT 0x00020 /* non idempotent memory */ 29 #define _PAGE_TOLERANT 0x00030 /* tolerant memory, cache inhibited */ 30 #define _PAGE_DIRTY 0x00080 /* C: page changed */ 31 #define _PAGE_ACCESSED 0x00100 /* R: page referenced */ 32 /* 33 * Software bits 34 */ 35 #define _RPAGE_SW0 0x2000000000000000UL 36 #define _RPAGE_SW1 0x00800 37 #define _RPAGE_SW2 0x00400 38 #define _RPAGE_SW3 0x00200 39 #define _RPAGE_RSV1 0x1000000000000000UL 40 #define _RPAGE_RSV2 0x0800000000000000UL 41 #define _RPAGE_RSV3 0x0400000000000000UL 42 #define _RPAGE_RSV4 0x0200000000000000UL 43 #define _RPAGE_RSV5 0x00040UL 44 45 #define _PAGE_PTE 0x4000000000000000UL /* distinguishes PTEs from pointers */ 46 #define _PAGE_PRESENT 0x8000000000000000UL /* pte contains a translation */ 47 48 /* 49 * Top and bottom bits of RPN which can be used by hash 50 * translation mode, because we expect them to be zero 51 * otherwise. 52 */ 53 #define _RPAGE_RPN0 0x01000 54 #define _RPAGE_RPN1 0x02000 55 #define _RPAGE_RPN44 0x0100000000000000UL 56 #define _RPAGE_RPN43 0x0080000000000000UL 57 #define _RPAGE_RPN42 0x0040000000000000UL 58 #define _RPAGE_RPN41 0x0020000000000000UL 59 60 /* Max physical address bit as per radix table */ 61 #define _RPAGE_PA_MAX 57 62 63 #ifdef CONFIG_PPC_MEM_KEYS 64 #ifdef CONFIG_PPC_64K_PAGES 65 #define H_PTE_PKEY_BIT0 _RPAGE_RSV1 66 #define H_PTE_PKEY_BIT1 _RPAGE_RSV2 67 #else /* CONFIG_PPC_64K_PAGES */ 68 #define H_PTE_PKEY_BIT0 0 /* _RPAGE_RSV1 is not available */ 69 #define H_PTE_PKEY_BIT1 0 /* _RPAGE_RSV2 is not available */ 70 #endif /* CONFIG_PPC_64K_PAGES */ 71 #define H_PTE_PKEY_BIT2 _RPAGE_RSV3 72 #define H_PTE_PKEY_BIT3 _RPAGE_RSV4 73 #define H_PTE_PKEY_BIT4 _RPAGE_RSV5 74 #else /* CONFIG_PPC_MEM_KEYS */ 75 #define H_PTE_PKEY_BIT0 0 76 #define H_PTE_PKEY_BIT1 0 77 #define H_PTE_PKEY_BIT2 0 78 #define H_PTE_PKEY_BIT3 0 79 #define H_PTE_PKEY_BIT4 0 80 #endif /* CONFIG_PPC_MEM_KEYS */ 81 82 /* 83 * Max physical address bit we will use for now. 84 * 85 * This is mostly a hardware limitation and for now Power9 has 86 * a 51 bit limit. 87 * 88 * This is different from the number of physical bit required to address 89 * the last byte of memory. That is defined by MAX_PHYSMEM_BITS. 90 * MAX_PHYSMEM_BITS is a linux limitation imposed by the maximum 91 * number of sections we can support (SECTIONS_SHIFT). 92 * 93 * This is different from Radix page table limitation above and 94 * should always be less than that. The limit is done such that 95 * we can overload the bits between _RPAGE_PA_MAX and _PAGE_PA_MAX 96 * for hash linux page table specific bits. 97 * 98 * In order to be compatible with future hardware generations we keep 99 * some offsets and limit this for now to 53 100 */ 101 #define _PAGE_PA_MAX 53 102 103 #define _PAGE_SOFT_DIRTY _RPAGE_SW3 /* software: software dirty tracking */ 104 #define _PAGE_SPECIAL _RPAGE_SW2 /* software: special page */ 105 #define _PAGE_DEVMAP _RPAGE_SW1 /* software: ZONE_DEVICE page */ 106 #define __HAVE_ARCH_PTE_DEVMAP 107 108 /* 109 * Drivers request for cache inhibited pte mapping using _PAGE_NO_CACHE 110 * Instead of fixing all of them, add an alternate define which 111 * maps CI pte mapping. 112 */ 113 #define _PAGE_NO_CACHE _PAGE_TOLERANT 114 /* 115 * We support _RPAGE_PA_MAX bit real address in pte. On the linux side 116 * we are limited by _PAGE_PA_MAX. Clear everything above _PAGE_PA_MAX 117 * and every thing below PAGE_SHIFT; 118 */ 119 #define PTE_RPN_MASK (((1UL << _PAGE_PA_MAX) - 1) & (PAGE_MASK)) 120 /* 121 * set of bits not changed in pmd_modify. Even though we have hash specific bits 122 * in here, on radix we expect them to be zero. 123 */ 124 #define _HPAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ 125 _PAGE_ACCESSED | H_PAGE_THP_HUGE | _PAGE_PTE | \ 126 _PAGE_SOFT_DIRTY) 127 /* 128 * user access blocked by key 129 */ 130 #define _PAGE_KERNEL_RW (_PAGE_PRIVILEGED | _PAGE_RW | _PAGE_DIRTY) 131 #define _PAGE_KERNEL_RO (_PAGE_PRIVILEGED | _PAGE_READ) 132 #define _PAGE_KERNEL_RWX (_PAGE_PRIVILEGED | _PAGE_DIRTY | \ 133 _PAGE_RW | _PAGE_EXEC) 134 /* 135 * No page size encoding in the linux PTE 136 */ 137 #define _PAGE_PSIZE 0 138 /* 139 * _PAGE_CHG_MASK masks of bits that are to be preserved across 140 * pgprot changes 141 */ 142 #define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ 143 _PAGE_ACCESSED | _PAGE_SPECIAL | _PAGE_PTE | \ 144 _PAGE_SOFT_DIRTY) 145 146 #define H_PTE_PKEY (H_PTE_PKEY_BIT0 | H_PTE_PKEY_BIT1 | H_PTE_PKEY_BIT2 | \ 147 H_PTE_PKEY_BIT3 | H_PTE_PKEY_BIT4) 148 /* 149 * Mask of bits returned by pte_pgprot() 150 */ 151 #define PAGE_PROT_BITS (_PAGE_SAO | _PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT | \ 152 H_PAGE_4K_PFN | _PAGE_PRIVILEGED | _PAGE_ACCESSED | \ 153 _PAGE_READ | _PAGE_WRITE | _PAGE_DIRTY | _PAGE_EXEC | \ 154 _PAGE_SOFT_DIRTY | H_PTE_PKEY) 155 /* 156 * We define 2 sets of base prot bits, one for basic pages (ie, 157 * cacheable kernel and user pages) and one for non cacheable 158 * pages. We always set _PAGE_COHERENT when SMP is enabled or 159 * the processor might need it for DMA coherency. 160 */ 161 #define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_PSIZE) 162 #define _PAGE_BASE (_PAGE_BASE_NC) 163 164 /* Permission masks used to generate the __P and __S table, 165 * 166 * Note:__pgprot is defined in arch/powerpc/include/asm/page.h 167 * 168 * Write permissions imply read permissions for now (we could make write-only 169 * pages on BookE but we don't bother for now). Execute permission control is 170 * possible on platforms that define _PAGE_EXEC 171 * 172 * Note due to the way vm flags are laid out, the bits are XWR 173 */ 174 #define PAGE_NONE __pgprot(_PAGE_BASE | _PAGE_PRIVILEGED) 175 #define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_RW) 176 #define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_EXEC) 177 #define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_READ) 178 #define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) 179 #define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_READ) 180 #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) 181 182 #define __P000 PAGE_NONE 183 #define __P001 PAGE_READONLY 184 #define __P010 PAGE_COPY 185 #define __P011 PAGE_COPY 186 #define __P100 PAGE_READONLY_X 187 #define __P101 PAGE_READONLY_X 188 #define __P110 PAGE_COPY_X 189 #define __P111 PAGE_COPY_X 190 191 #define __S000 PAGE_NONE 192 #define __S001 PAGE_READONLY 193 #define __S010 PAGE_SHARED 194 #define __S011 PAGE_SHARED 195 #define __S100 PAGE_READONLY_X 196 #define __S101 PAGE_READONLY_X 197 #define __S110 PAGE_SHARED_X 198 #define __S111 PAGE_SHARED_X 199 200 /* Permission masks used for kernel mappings */ 201 #define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW) 202 #define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \ 203 _PAGE_TOLERANT) 204 #define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \ 205 _PAGE_NON_IDEMPOTENT) 206 #define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX) 207 #define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO) 208 #define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX) 209 210 /* 211 * Protection used for kernel text. We want the debuggers to be able to 212 * set breakpoints anywhere, so don't write protect the kernel text 213 * on platforms where such control is possible. 214 */ 215 #if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) || \ 216 defined(CONFIG_KPROBES) || defined(CONFIG_DYNAMIC_FTRACE) 217 #define PAGE_KERNEL_TEXT PAGE_KERNEL_X 218 #else 219 #define PAGE_KERNEL_TEXT PAGE_KERNEL_ROX 220 #endif 221 222 /* Make modules code happy. We don't set RO yet */ 223 #define PAGE_KERNEL_EXEC PAGE_KERNEL_X 224 #define PAGE_AGP (PAGE_KERNEL_NC) 225 226 #ifndef __ASSEMBLY__ 227 /* 228 * page table defines 229 */ 230 extern unsigned long __pte_index_size; 231 extern unsigned long __pmd_index_size; 232 extern unsigned long __pud_index_size; 233 extern unsigned long __pgd_index_size; 234 extern unsigned long __pmd_cache_index; 235 #define PTE_INDEX_SIZE __pte_index_size 236 #define PMD_INDEX_SIZE __pmd_index_size 237 #define PUD_INDEX_SIZE __pud_index_size 238 #define PGD_INDEX_SIZE __pgd_index_size 239 #define PMD_CACHE_INDEX __pmd_cache_index 240 /* 241 * Because of use of pte fragments and THP, size of page table 242 * are not always derived out of index size above. 243 */ 244 extern unsigned long __pte_table_size; 245 extern unsigned long __pmd_table_size; 246 extern unsigned long __pud_table_size; 247 extern unsigned long __pgd_table_size; 248 #define PTE_TABLE_SIZE __pte_table_size 249 #define PMD_TABLE_SIZE __pmd_table_size 250 #define PUD_TABLE_SIZE __pud_table_size 251 #define PGD_TABLE_SIZE __pgd_table_size 252 253 extern unsigned long __pmd_val_bits; 254 extern unsigned long __pud_val_bits; 255 extern unsigned long __pgd_val_bits; 256 #define PMD_VAL_BITS __pmd_val_bits 257 #define PUD_VAL_BITS __pud_val_bits 258 #define PGD_VAL_BITS __pgd_val_bits 259 260 extern unsigned long __pte_frag_nr; 261 #define PTE_FRAG_NR __pte_frag_nr 262 extern unsigned long __pte_frag_size_shift; 263 #define PTE_FRAG_SIZE_SHIFT __pte_frag_size_shift 264 #define PTE_FRAG_SIZE (1UL << PTE_FRAG_SIZE_SHIFT) 265 266 #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE) 267 #define PTRS_PER_PMD (1 << PMD_INDEX_SIZE) 268 #define PTRS_PER_PUD (1 << PUD_INDEX_SIZE) 269 #define PTRS_PER_PGD (1 << PGD_INDEX_SIZE) 270 271 /* PMD_SHIFT determines what a second-level page table entry can map */ 272 #define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE) 273 #define PMD_SIZE (1UL << PMD_SHIFT) 274 #define PMD_MASK (~(PMD_SIZE-1)) 275 276 /* PUD_SHIFT determines what a third-level page table entry can map */ 277 #define PUD_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE) 278 #define PUD_SIZE (1UL << PUD_SHIFT) 279 #define PUD_MASK (~(PUD_SIZE-1)) 280 281 /* PGDIR_SHIFT determines what a fourth-level page table entry can map */ 282 #define PGDIR_SHIFT (PUD_SHIFT + PUD_INDEX_SIZE) 283 #define PGDIR_SIZE (1UL << PGDIR_SHIFT) 284 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 285 286 /* Bits to mask out from a PMD to get to the PTE page */ 287 #define PMD_MASKED_BITS 0xc0000000000000ffUL 288 /* Bits to mask out from a PUD to get to the PMD page */ 289 #define PUD_MASKED_BITS 0xc0000000000000ffUL 290 /* Bits to mask out from a PGD to get to the PUD page */ 291 #define PGD_MASKED_BITS 0xc0000000000000ffUL 292 293 extern unsigned long __vmalloc_start; 294 extern unsigned long __vmalloc_end; 295 #define VMALLOC_START __vmalloc_start 296 #define VMALLOC_END __vmalloc_end 297 298 extern unsigned long __kernel_virt_start; 299 extern unsigned long __kernel_virt_size; 300 extern unsigned long __kernel_io_start; 301 #define KERN_VIRT_START __kernel_virt_start 302 #define KERN_VIRT_SIZE __kernel_virt_size 303 #define KERN_IO_START __kernel_io_start 304 extern struct page *vmemmap; 305 extern unsigned long ioremap_bot; 306 extern unsigned long pci_io_base; 307 #endif /* __ASSEMBLY__ */ 308 309 #include <asm/book3s/64/hash.h> 310 #include <asm/book3s/64/radix.h> 311 312 #ifdef CONFIG_PPC_64K_PAGES 313 #include <asm/book3s/64/pgtable-64k.h> 314 #else 315 #include <asm/book3s/64/pgtable-4k.h> 316 #endif 317 318 #include <asm/barrier.h> 319 /* 320 * The second half of the kernel virtual space is used for IO mappings, 321 * it's itself carved into the PIO region (ISA and PHB IO space) and 322 * the ioremap space 323 * 324 * ISA_IO_BASE = KERN_IO_START, 64K reserved area 325 * PHB_IO_BASE = ISA_IO_BASE + 64K to ISA_IO_BASE + 2G, PHB IO spaces 326 * IOREMAP_BASE = ISA_IO_BASE + 2G to VMALLOC_START + PGTABLE_RANGE 327 */ 328 #define FULL_IO_SIZE 0x80000000ul 329 #define ISA_IO_BASE (KERN_IO_START) 330 #define ISA_IO_END (KERN_IO_START + 0x10000ul) 331 #define PHB_IO_BASE (ISA_IO_END) 332 #define PHB_IO_END (KERN_IO_START + FULL_IO_SIZE) 333 #define IOREMAP_BASE (PHB_IO_END) 334 #define IOREMAP_END (KERN_VIRT_START + KERN_VIRT_SIZE) 335 336 /* Advertise special mapping type for AGP */ 337 #define HAVE_PAGE_AGP 338 339 /* Advertise support for _PAGE_SPECIAL */ 340 #define __HAVE_ARCH_PTE_SPECIAL 341 342 #ifndef __ASSEMBLY__ 343 344 /* 345 * This is the default implementation of various PTE accessors, it's 346 * used in all cases except Book3S with 64K pages where we have a 347 * concept of sub-pages 348 */ 349 #ifndef __real_pte 350 351 #define __real_pte(e,p) ((real_pte_t){(e)}) 352 #define __rpte_to_pte(r) ((r).pte) 353 #define __rpte_to_hidx(r,index) (pte_val(__rpte_to_pte(r)) >> H_PAGE_F_GIX_SHIFT) 354 355 #define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \ 356 do { \ 357 index = 0; \ 358 shift = mmu_psize_defs[psize].shift; \ 359 360 #define pte_iterate_hashed_end() } while(0) 361 362 /* 363 * We expect this to be called only for user addresses or kernel virtual 364 * addresses other than the linear mapping. 365 */ 366 #define pte_pagesize_index(mm, addr, pte) MMU_PAGE_4K 367 368 #endif /* __real_pte */ 369 370 static inline unsigned long pte_update(struct mm_struct *mm, unsigned long addr, 371 pte_t *ptep, unsigned long clr, 372 unsigned long set, int huge) 373 { 374 if (radix_enabled()) 375 return radix__pte_update(mm, addr, ptep, clr, set, huge); 376 return hash__pte_update(mm, addr, ptep, clr, set, huge); 377 } 378 /* 379 * For hash even if we have _PAGE_ACCESSED = 0, we do a pte_update. 380 * We currently remove entries from the hashtable regardless of whether 381 * the entry was young or dirty. 382 * 383 * We should be more intelligent about this but for the moment we override 384 * these functions and force a tlb flush unconditionally 385 * For radix: H_PAGE_HASHPTE should be zero. Hence we can use the same 386 * function for both hash and radix. 387 */ 388 static inline int __ptep_test_and_clear_young(struct mm_struct *mm, 389 unsigned long addr, pte_t *ptep) 390 { 391 unsigned long old; 392 393 if ((pte_raw(*ptep) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) 394 return 0; 395 old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0); 396 return (old & _PAGE_ACCESSED) != 0; 397 } 398 399 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 400 #define ptep_test_and_clear_young(__vma, __addr, __ptep) \ 401 ({ \ 402 int __r; \ 403 __r = __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \ 404 __r; \ 405 }) 406 407 static inline int __pte_write(pte_t pte) 408 { 409 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_WRITE)); 410 } 411 412 #ifdef CONFIG_NUMA_BALANCING 413 #define pte_savedwrite pte_savedwrite 414 static inline bool pte_savedwrite(pte_t pte) 415 { 416 /* 417 * Saved write ptes are prot none ptes that doesn't have 418 * privileged bit sit. We mark prot none as one which has 419 * present and pviliged bit set and RWX cleared. To mark 420 * protnone which used to have _PAGE_WRITE set we clear 421 * the privileged bit. 422 */ 423 return !(pte_raw(pte) & cpu_to_be64(_PAGE_RWX | _PAGE_PRIVILEGED)); 424 } 425 #else 426 #define pte_savedwrite pte_savedwrite 427 static inline bool pte_savedwrite(pte_t pte) 428 { 429 return false; 430 } 431 #endif 432 433 static inline int pte_write(pte_t pte) 434 { 435 return __pte_write(pte) || pte_savedwrite(pte); 436 } 437 438 static inline int pte_read(pte_t pte) 439 { 440 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_READ)); 441 } 442 443 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 444 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, 445 pte_t *ptep) 446 { 447 if (__pte_write(*ptep)) 448 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 0); 449 else if (unlikely(pte_savedwrite(*ptep))) 450 pte_update(mm, addr, ptep, 0, _PAGE_PRIVILEGED, 0); 451 } 452 453 static inline void huge_ptep_set_wrprotect(struct mm_struct *mm, 454 unsigned long addr, pte_t *ptep) 455 { 456 /* 457 * We should not find protnone for hugetlb, but this complete the 458 * interface. 459 */ 460 if (__pte_write(*ptep)) 461 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 1); 462 else if (unlikely(pte_savedwrite(*ptep))) 463 pte_update(mm, addr, ptep, 0, _PAGE_PRIVILEGED, 1); 464 } 465 466 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 467 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 468 unsigned long addr, pte_t *ptep) 469 { 470 unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0, 0); 471 return __pte(old); 472 } 473 474 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL 475 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, 476 unsigned long addr, 477 pte_t *ptep, int full) 478 { 479 if (full && radix_enabled()) { 480 /* 481 * Let's skip the DD1 style pte update here. We know that 482 * this is a full mm pte clear and hence can be sure there is 483 * no parallel set_pte. 484 */ 485 return radix__ptep_get_and_clear_full(mm, addr, ptep, full); 486 } 487 return ptep_get_and_clear(mm, addr, ptep); 488 } 489 490 491 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, 492 pte_t * ptep) 493 { 494 pte_update(mm, addr, ptep, ~0UL, 0, 0); 495 } 496 497 static inline int pte_dirty(pte_t pte) 498 { 499 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_DIRTY)); 500 } 501 502 static inline int pte_young(pte_t pte) 503 { 504 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_ACCESSED)); 505 } 506 507 static inline int pte_special(pte_t pte) 508 { 509 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SPECIAL)); 510 } 511 512 static inline pgprot_t pte_pgprot(pte_t pte) { return __pgprot(pte_val(pte) & PAGE_PROT_BITS); } 513 514 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 515 static inline bool pte_soft_dirty(pte_t pte) 516 { 517 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SOFT_DIRTY)); 518 } 519 520 static inline pte_t pte_mksoft_dirty(pte_t pte) 521 { 522 return __pte(pte_val(pte) | _PAGE_SOFT_DIRTY); 523 } 524 525 static inline pte_t pte_clear_soft_dirty(pte_t pte) 526 { 527 return __pte(pte_val(pte) & ~_PAGE_SOFT_DIRTY); 528 } 529 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 530 531 #ifdef CONFIG_NUMA_BALANCING 532 static inline int pte_protnone(pte_t pte) 533 { 534 return (pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE | _PAGE_RWX)) == 535 cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE); 536 } 537 538 #define pte_mk_savedwrite pte_mk_savedwrite 539 static inline pte_t pte_mk_savedwrite(pte_t pte) 540 { 541 /* 542 * Used by Autonuma subsystem to preserve the write bit 543 * while marking the pte PROT_NONE. Only allow this 544 * on PROT_NONE pte 545 */ 546 VM_BUG_ON((pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_RWX | _PAGE_PRIVILEGED)) != 547 cpu_to_be64(_PAGE_PRESENT | _PAGE_PRIVILEGED)); 548 return __pte(pte_val(pte) & ~_PAGE_PRIVILEGED); 549 } 550 551 #define pte_clear_savedwrite pte_clear_savedwrite 552 static inline pte_t pte_clear_savedwrite(pte_t pte) 553 { 554 /* 555 * Used by KSM subsystem to make a protnone pte readonly. 556 */ 557 VM_BUG_ON(!pte_protnone(pte)); 558 return __pte(pte_val(pte) | _PAGE_PRIVILEGED); 559 } 560 #else 561 #define pte_clear_savedwrite pte_clear_savedwrite 562 static inline pte_t pte_clear_savedwrite(pte_t pte) 563 { 564 VM_WARN_ON(1); 565 return __pte(pte_val(pte) & ~_PAGE_WRITE); 566 } 567 #endif /* CONFIG_NUMA_BALANCING */ 568 569 static inline int pte_present(pte_t pte) 570 { 571 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT)); 572 } 573 574 #ifdef CONFIG_PPC_MEM_KEYS 575 extern bool arch_pte_access_permitted(u64 pte, bool write, bool execute); 576 #else 577 static inline bool arch_pte_access_permitted(u64 pte, bool write, bool execute) 578 { 579 return true; 580 } 581 #endif /* CONFIG_PPC_MEM_KEYS */ 582 583 #define pte_access_permitted pte_access_permitted 584 static inline bool pte_access_permitted(pte_t pte, bool write) 585 { 586 unsigned long pteval = pte_val(pte); 587 /* Also check for pte_user */ 588 unsigned long clear_pte_bits = _PAGE_PRIVILEGED; 589 /* 590 * _PAGE_READ is needed for any access and will be 591 * cleared for PROT_NONE 592 */ 593 unsigned long need_pte_bits = _PAGE_PRESENT | _PAGE_READ; 594 595 if (write) 596 need_pte_bits |= _PAGE_WRITE; 597 598 if ((pteval & need_pte_bits) != need_pte_bits) 599 return false; 600 601 if ((pteval & clear_pte_bits) == clear_pte_bits) 602 return false; 603 604 return arch_pte_access_permitted(pte_val(pte), write, 0); 605 } 606 607 /* 608 * Conversion functions: convert a page and protection to a page entry, 609 * and a page entry and page directory to the page they refer to. 610 * 611 * Even if PTEs can be unsigned long long, a PFN is always an unsigned 612 * long for now. 613 */ 614 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot) 615 { 616 return __pte((((pte_basic_t)(pfn) << PAGE_SHIFT) & PTE_RPN_MASK) | 617 pgprot_val(pgprot)); 618 } 619 620 static inline unsigned long pte_pfn(pte_t pte) 621 { 622 return (pte_val(pte) & PTE_RPN_MASK) >> PAGE_SHIFT; 623 } 624 625 /* Generic modifiers for PTE bits */ 626 static inline pte_t pte_wrprotect(pte_t pte) 627 { 628 if (unlikely(pte_savedwrite(pte))) 629 return pte_clear_savedwrite(pte); 630 return __pte(pte_val(pte) & ~_PAGE_WRITE); 631 } 632 633 static inline pte_t pte_mkclean(pte_t pte) 634 { 635 return __pte(pte_val(pte) & ~_PAGE_DIRTY); 636 } 637 638 static inline pte_t pte_mkold(pte_t pte) 639 { 640 return __pte(pte_val(pte) & ~_PAGE_ACCESSED); 641 } 642 643 static inline pte_t pte_mkwrite(pte_t pte) 644 { 645 /* 646 * write implies read, hence set both 647 */ 648 return __pte(pte_val(pte) | _PAGE_RW); 649 } 650 651 static inline pte_t pte_mkdirty(pte_t pte) 652 { 653 return __pte(pte_val(pte) | _PAGE_DIRTY | _PAGE_SOFT_DIRTY); 654 } 655 656 static inline pte_t pte_mkyoung(pte_t pte) 657 { 658 return __pte(pte_val(pte) | _PAGE_ACCESSED); 659 } 660 661 static inline pte_t pte_mkspecial(pte_t pte) 662 { 663 return __pte(pte_val(pte) | _PAGE_SPECIAL); 664 } 665 666 static inline pte_t pte_mkhuge(pte_t pte) 667 { 668 return pte; 669 } 670 671 static inline pte_t pte_mkdevmap(pte_t pte) 672 { 673 return __pte(pte_val(pte) | _PAGE_SPECIAL|_PAGE_DEVMAP); 674 } 675 676 /* 677 * This is potentially called with a pmd as the argument, in which case it's not 678 * safe to check _PAGE_DEVMAP unless we also confirm that _PAGE_PTE is set. 679 * That's because the bit we use for _PAGE_DEVMAP is not reserved for software 680 * use in page directory entries (ie. non-ptes). 681 */ 682 static inline int pte_devmap(pte_t pte) 683 { 684 u64 mask = cpu_to_be64(_PAGE_DEVMAP | _PAGE_PTE); 685 686 return (pte_raw(pte) & mask) == mask; 687 } 688 689 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 690 { 691 /* FIXME!! check whether this need to be a conditional */ 692 return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot)); 693 } 694 695 static inline bool pte_user(pte_t pte) 696 { 697 return !(pte_raw(pte) & cpu_to_be64(_PAGE_PRIVILEGED)); 698 } 699 700 /* Encode and de-code a swap entry */ 701 #define MAX_SWAPFILES_CHECK() do { \ 702 BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS); \ 703 /* \ 704 * Don't have overlapping bits with _PAGE_HPTEFLAGS \ 705 * We filter HPTEFLAGS on set_pte. \ 706 */ \ 707 BUILD_BUG_ON(_PAGE_HPTEFLAGS & (0x1f << _PAGE_BIT_SWAP_TYPE)); \ 708 BUILD_BUG_ON(_PAGE_HPTEFLAGS & _PAGE_SWP_SOFT_DIRTY); \ 709 } while (0) 710 /* 711 * on pte we don't need handle RADIX_TREE_EXCEPTIONAL_SHIFT; 712 */ 713 #define SWP_TYPE_BITS 5 714 #define __swp_type(x) (((x).val >> _PAGE_BIT_SWAP_TYPE) \ 715 & ((1UL << SWP_TYPE_BITS) - 1)) 716 #define __swp_offset(x) (((x).val & PTE_RPN_MASK) >> PAGE_SHIFT) 717 #define __swp_entry(type, offset) ((swp_entry_t) { \ 718 ((type) << _PAGE_BIT_SWAP_TYPE) \ 719 | (((offset) << PAGE_SHIFT) & PTE_RPN_MASK)}) 720 /* 721 * swp_entry_t must be independent of pte bits. We build a swp_entry_t from 722 * swap type and offset we get from swap and convert that to pte to find a 723 * matching pte in linux page table. 724 * Clear bits not found in swap entries here. 725 */ 726 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val((pte)) & ~_PAGE_PTE }) 727 #define __swp_entry_to_pte(x) __pte((x).val | _PAGE_PTE) 728 729 #ifdef CONFIG_MEM_SOFT_DIRTY 730 #define _PAGE_SWP_SOFT_DIRTY (1UL << (SWP_TYPE_BITS + _PAGE_BIT_SWAP_TYPE)) 731 #else 732 #define _PAGE_SWP_SOFT_DIRTY 0UL 733 #endif /* CONFIG_MEM_SOFT_DIRTY */ 734 735 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 736 static inline pte_t pte_swp_mksoft_dirty(pte_t pte) 737 { 738 return __pte(pte_val(pte) | _PAGE_SWP_SOFT_DIRTY); 739 } 740 741 static inline bool pte_swp_soft_dirty(pte_t pte) 742 { 743 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SWP_SOFT_DIRTY)); 744 } 745 746 static inline pte_t pte_swp_clear_soft_dirty(pte_t pte) 747 { 748 return __pte(pte_val(pte) & ~_PAGE_SWP_SOFT_DIRTY); 749 } 750 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 751 752 static inline bool check_pte_access(unsigned long access, unsigned long ptev) 753 { 754 /* 755 * This check for _PAGE_RWX and _PAGE_PRESENT bits 756 */ 757 if (access & ~ptev) 758 return false; 759 /* 760 * This check for access to privilege space 761 */ 762 if ((access & _PAGE_PRIVILEGED) != (ptev & _PAGE_PRIVILEGED)) 763 return false; 764 765 return true; 766 } 767 /* 768 * Generic functions with hash/radix callbacks 769 */ 770 771 static inline void __ptep_set_access_flags(struct mm_struct *mm, 772 pte_t *ptep, pte_t entry, 773 unsigned long address) 774 { 775 if (radix_enabled()) 776 return radix__ptep_set_access_flags(mm, ptep, entry, address); 777 return hash__ptep_set_access_flags(ptep, entry); 778 } 779 780 #define __HAVE_ARCH_PTE_SAME 781 static inline int pte_same(pte_t pte_a, pte_t pte_b) 782 { 783 if (radix_enabled()) 784 return radix__pte_same(pte_a, pte_b); 785 return hash__pte_same(pte_a, pte_b); 786 } 787 788 static inline int pte_none(pte_t pte) 789 { 790 if (radix_enabled()) 791 return radix__pte_none(pte); 792 return hash__pte_none(pte); 793 } 794 795 static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr, 796 pte_t *ptep, pte_t pte, int percpu) 797 { 798 if (radix_enabled()) 799 return radix__set_pte_at(mm, addr, ptep, pte, percpu); 800 return hash__set_pte_at(mm, addr, ptep, pte, percpu); 801 } 802 803 #define _PAGE_CACHE_CTL (_PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT) 804 805 #define pgprot_noncached pgprot_noncached 806 static inline pgprot_t pgprot_noncached(pgprot_t prot) 807 { 808 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | 809 _PAGE_NON_IDEMPOTENT); 810 } 811 812 #define pgprot_noncached_wc pgprot_noncached_wc 813 static inline pgprot_t pgprot_noncached_wc(pgprot_t prot) 814 { 815 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | 816 _PAGE_TOLERANT); 817 } 818 819 #define pgprot_cached pgprot_cached 820 static inline pgprot_t pgprot_cached(pgprot_t prot) 821 { 822 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL)); 823 } 824 825 #define pgprot_writecombine pgprot_writecombine 826 static inline pgprot_t pgprot_writecombine(pgprot_t prot) 827 { 828 return pgprot_noncached_wc(prot); 829 } 830 /* 831 * check a pte mapping have cache inhibited property 832 */ 833 static inline bool pte_ci(pte_t pte) 834 { 835 unsigned long pte_v = pte_val(pte); 836 837 if (((pte_v & _PAGE_CACHE_CTL) == _PAGE_TOLERANT) || 838 ((pte_v & _PAGE_CACHE_CTL) == _PAGE_NON_IDEMPOTENT)) 839 return true; 840 return false; 841 } 842 843 static inline void pmd_set(pmd_t *pmdp, unsigned long val) 844 { 845 *pmdp = __pmd(val); 846 } 847 848 static inline void pmd_clear(pmd_t *pmdp) 849 { 850 *pmdp = __pmd(0); 851 } 852 853 static inline int pmd_none(pmd_t pmd) 854 { 855 return !pmd_raw(pmd); 856 } 857 858 static inline int pmd_present(pmd_t pmd) 859 { 860 861 return !pmd_none(pmd); 862 } 863 864 static inline int pmd_bad(pmd_t pmd) 865 { 866 if (radix_enabled()) 867 return radix__pmd_bad(pmd); 868 return hash__pmd_bad(pmd); 869 } 870 871 static inline void pud_set(pud_t *pudp, unsigned long val) 872 { 873 *pudp = __pud(val); 874 } 875 876 static inline void pud_clear(pud_t *pudp) 877 { 878 *pudp = __pud(0); 879 } 880 881 static inline int pud_none(pud_t pud) 882 { 883 return !pud_raw(pud); 884 } 885 886 static inline int pud_present(pud_t pud) 887 { 888 return !pud_none(pud); 889 } 890 891 extern struct page *pud_page(pud_t pud); 892 extern struct page *pmd_page(pmd_t pmd); 893 static inline pte_t pud_pte(pud_t pud) 894 { 895 return __pte_raw(pud_raw(pud)); 896 } 897 898 static inline pud_t pte_pud(pte_t pte) 899 { 900 return __pud_raw(pte_raw(pte)); 901 } 902 #define pud_write(pud) pte_write(pud_pte(pud)) 903 904 static inline int pud_bad(pud_t pud) 905 { 906 if (radix_enabled()) 907 return radix__pud_bad(pud); 908 return hash__pud_bad(pud); 909 } 910 911 #define pud_access_permitted pud_access_permitted 912 static inline bool pud_access_permitted(pud_t pud, bool write) 913 { 914 return pte_access_permitted(pud_pte(pud), write); 915 } 916 917 #define pgd_write(pgd) pte_write(pgd_pte(pgd)) 918 static inline void pgd_set(pgd_t *pgdp, unsigned long val) 919 { 920 *pgdp = __pgd(val); 921 } 922 923 static inline void pgd_clear(pgd_t *pgdp) 924 { 925 *pgdp = __pgd(0); 926 } 927 928 static inline int pgd_none(pgd_t pgd) 929 { 930 return !pgd_raw(pgd); 931 } 932 933 static inline int pgd_present(pgd_t pgd) 934 { 935 return !pgd_none(pgd); 936 } 937 938 static inline pte_t pgd_pte(pgd_t pgd) 939 { 940 return __pte_raw(pgd_raw(pgd)); 941 } 942 943 static inline pgd_t pte_pgd(pte_t pte) 944 { 945 return __pgd_raw(pte_raw(pte)); 946 } 947 948 static inline int pgd_bad(pgd_t pgd) 949 { 950 if (radix_enabled()) 951 return radix__pgd_bad(pgd); 952 return hash__pgd_bad(pgd); 953 } 954 955 #define pgd_access_permitted pgd_access_permitted 956 static inline bool pgd_access_permitted(pgd_t pgd, bool write) 957 { 958 return pte_access_permitted(pgd_pte(pgd), write); 959 } 960 961 extern struct page *pgd_page(pgd_t pgd); 962 963 /* Pointers in the page table tree are physical addresses */ 964 #define __pgtable_ptr_val(ptr) __pa(ptr) 965 966 #define pmd_page_vaddr(pmd) __va(pmd_val(pmd) & ~PMD_MASKED_BITS) 967 #define pud_page_vaddr(pud) __va(pud_val(pud) & ~PUD_MASKED_BITS) 968 #define pgd_page_vaddr(pgd) __va(pgd_val(pgd) & ~PGD_MASKED_BITS) 969 970 #define pgd_index(address) (((address) >> (PGDIR_SHIFT)) & (PTRS_PER_PGD - 1)) 971 #define pud_index(address) (((address) >> (PUD_SHIFT)) & (PTRS_PER_PUD - 1)) 972 #define pmd_index(address) (((address) >> (PMD_SHIFT)) & (PTRS_PER_PMD - 1)) 973 #define pte_index(address) (((address) >> (PAGE_SHIFT)) & (PTRS_PER_PTE - 1)) 974 975 /* 976 * Find an entry in a page-table-directory. We combine the address region 977 * (the high order N bits) and the pgd portion of the address. 978 */ 979 980 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) 981 982 #define pud_offset(pgdp, addr) \ 983 (((pud_t *) pgd_page_vaddr(*(pgdp))) + pud_index(addr)) 984 #define pmd_offset(pudp,addr) \ 985 (((pmd_t *) pud_page_vaddr(*(pudp))) + pmd_index(addr)) 986 #define pte_offset_kernel(dir,addr) \ 987 (((pte_t *) pmd_page_vaddr(*(dir))) + pte_index(addr)) 988 989 #define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr)) 990 #define pte_unmap(pte) do { } while(0) 991 992 /* to find an entry in a kernel page-table-directory */ 993 /* This now only contains the vmalloc pages */ 994 #define pgd_offset_k(address) pgd_offset(&init_mm, address) 995 996 #define pte_ERROR(e) \ 997 pr_err("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e)) 998 #define pmd_ERROR(e) \ 999 pr_err("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e)) 1000 #define pud_ERROR(e) \ 1001 pr_err("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e)) 1002 #define pgd_ERROR(e) \ 1003 pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) 1004 1005 static inline int map_kernel_page(unsigned long ea, unsigned long pa, 1006 unsigned long flags) 1007 { 1008 if (radix_enabled()) { 1009 #if defined(CONFIG_PPC_RADIX_MMU) && defined(DEBUG_VM) 1010 unsigned long page_size = 1 << mmu_psize_defs[mmu_io_psize].shift; 1011 WARN((page_size != PAGE_SIZE), "I/O page size != PAGE_SIZE"); 1012 #endif 1013 return radix__map_kernel_page(ea, pa, __pgprot(flags), PAGE_SIZE); 1014 } 1015 return hash__map_kernel_page(ea, pa, flags); 1016 } 1017 1018 static inline int __meminit vmemmap_create_mapping(unsigned long start, 1019 unsigned long page_size, 1020 unsigned long phys) 1021 { 1022 if (radix_enabled()) 1023 return radix__vmemmap_create_mapping(start, page_size, phys); 1024 return hash__vmemmap_create_mapping(start, page_size, phys); 1025 } 1026 1027 #ifdef CONFIG_MEMORY_HOTPLUG 1028 static inline void vmemmap_remove_mapping(unsigned long start, 1029 unsigned long page_size) 1030 { 1031 if (radix_enabled()) 1032 return radix__vmemmap_remove_mapping(start, page_size); 1033 return hash__vmemmap_remove_mapping(start, page_size); 1034 } 1035 #endif 1036 struct page *realmode_pfn_to_page(unsigned long pfn); 1037 1038 static inline pte_t pmd_pte(pmd_t pmd) 1039 { 1040 return __pte_raw(pmd_raw(pmd)); 1041 } 1042 1043 static inline pmd_t pte_pmd(pte_t pte) 1044 { 1045 return __pmd_raw(pte_raw(pte)); 1046 } 1047 1048 static inline pte_t *pmdp_ptep(pmd_t *pmd) 1049 { 1050 return (pte_t *)pmd; 1051 } 1052 #define pmd_pfn(pmd) pte_pfn(pmd_pte(pmd)) 1053 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) 1054 #define pmd_young(pmd) pte_young(pmd_pte(pmd)) 1055 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) 1056 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) 1057 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) 1058 #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) 1059 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) 1060 #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd))) 1061 #define pmd_mk_savedwrite(pmd) pte_pmd(pte_mk_savedwrite(pmd_pte(pmd))) 1062 #define pmd_clear_savedwrite(pmd) pte_pmd(pte_clear_savedwrite(pmd_pte(pmd))) 1063 1064 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 1065 #define pmd_soft_dirty(pmd) pte_soft_dirty(pmd_pte(pmd)) 1066 #define pmd_mksoft_dirty(pmd) pte_pmd(pte_mksoft_dirty(pmd_pte(pmd))) 1067 #define pmd_clear_soft_dirty(pmd) pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd))) 1068 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 1069 1070 #ifdef CONFIG_NUMA_BALANCING 1071 static inline int pmd_protnone(pmd_t pmd) 1072 { 1073 return pte_protnone(pmd_pte(pmd)); 1074 } 1075 #endif /* CONFIG_NUMA_BALANCING */ 1076 1077 #define pmd_write(pmd) pte_write(pmd_pte(pmd)) 1078 #define __pmd_write(pmd) __pte_write(pmd_pte(pmd)) 1079 #define pmd_savedwrite(pmd) pte_savedwrite(pmd_pte(pmd)) 1080 1081 #define pmd_access_permitted pmd_access_permitted 1082 static inline bool pmd_access_permitted(pmd_t pmd, bool write) 1083 { 1084 return pte_access_permitted(pmd_pte(pmd), write); 1085 } 1086 1087 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1088 extern pmd_t pfn_pmd(unsigned long pfn, pgprot_t pgprot); 1089 extern pmd_t mk_pmd(struct page *page, pgprot_t pgprot); 1090 extern pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot); 1091 extern void set_pmd_at(struct mm_struct *mm, unsigned long addr, 1092 pmd_t *pmdp, pmd_t pmd); 1093 extern void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr, 1094 pmd_t *pmd); 1095 extern int hash__has_transparent_hugepage(void); 1096 static inline int has_transparent_hugepage(void) 1097 { 1098 if (radix_enabled()) 1099 return radix__has_transparent_hugepage(); 1100 return hash__has_transparent_hugepage(); 1101 } 1102 #define has_transparent_hugepage has_transparent_hugepage 1103 1104 static inline unsigned long 1105 pmd_hugepage_update(struct mm_struct *mm, unsigned long addr, pmd_t *pmdp, 1106 unsigned long clr, unsigned long set) 1107 { 1108 if (radix_enabled()) 1109 return radix__pmd_hugepage_update(mm, addr, pmdp, clr, set); 1110 return hash__pmd_hugepage_update(mm, addr, pmdp, clr, set); 1111 } 1112 1113 static inline int pmd_large(pmd_t pmd) 1114 { 1115 return !!(pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE)); 1116 } 1117 1118 static inline pmd_t pmd_mknotpresent(pmd_t pmd) 1119 { 1120 return __pmd(pmd_val(pmd) & ~_PAGE_PRESENT); 1121 } 1122 /* 1123 * For radix we should always find H_PAGE_HASHPTE zero. Hence 1124 * the below will work for radix too 1125 */ 1126 static inline int __pmdp_test_and_clear_young(struct mm_struct *mm, 1127 unsigned long addr, pmd_t *pmdp) 1128 { 1129 unsigned long old; 1130 1131 if ((pmd_raw(*pmdp) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) 1132 return 0; 1133 old = pmd_hugepage_update(mm, addr, pmdp, _PAGE_ACCESSED, 0); 1134 return ((old & _PAGE_ACCESSED) != 0); 1135 } 1136 1137 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 1138 static inline void pmdp_set_wrprotect(struct mm_struct *mm, unsigned long addr, 1139 pmd_t *pmdp) 1140 { 1141 if (__pmd_write((*pmdp))) 1142 pmd_hugepage_update(mm, addr, pmdp, _PAGE_WRITE, 0); 1143 else if (unlikely(pmd_savedwrite(*pmdp))) 1144 pmd_hugepage_update(mm, addr, pmdp, 0, _PAGE_PRIVILEGED); 1145 } 1146 1147 static inline int pmd_trans_huge(pmd_t pmd) 1148 { 1149 if (radix_enabled()) 1150 return radix__pmd_trans_huge(pmd); 1151 return hash__pmd_trans_huge(pmd); 1152 } 1153 1154 #define __HAVE_ARCH_PMD_SAME 1155 static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b) 1156 { 1157 if (radix_enabled()) 1158 return radix__pmd_same(pmd_a, pmd_b); 1159 return hash__pmd_same(pmd_a, pmd_b); 1160 } 1161 1162 static inline pmd_t pmd_mkhuge(pmd_t pmd) 1163 { 1164 if (radix_enabled()) 1165 return radix__pmd_mkhuge(pmd); 1166 return hash__pmd_mkhuge(pmd); 1167 } 1168 1169 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 1170 extern int pmdp_set_access_flags(struct vm_area_struct *vma, 1171 unsigned long address, pmd_t *pmdp, 1172 pmd_t entry, int dirty); 1173 1174 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 1175 extern int pmdp_test_and_clear_young(struct vm_area_struct *vma, 1176 unsigned long address, pmd_t *pmdp); 1177 1178 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 1179 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 1180 unsigned long addr, pmd_t *pmdp) 1181 { 1182 if (radix_enabled()) 1183 return radix__pmdp_huge_get_and_clear(mm, addr, pmdp); 1184 return hash__pmdp_huge_get_and_clear(mm, addr, pmdp); 1185 } 1186 1187 static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, 1188 unsigned long address, pmd_t *pmdp) 1189 { 1190 if (radix_enabled()) 1191 return radix__pmdp_collapse_flush(vma, address, pmdp); 1192 return hash__pmdp_collapse_flush(vma, address, pmdp); 1193 } 1194 #define pmdp_collapse_flush pmdp_collapse_flush 1195 1196 #define __HAVE_ARCH_PGTABLE_DEPOSIT 1197 static inline void pgtable_trans_huge_deposit(struct mm_struct *mm, 1198 pmd_t *pmdp, pgtable_t pgtable) 1199 { 1200 if (radix_enabled()) 1201 return radix__pgtable_trans_huge_deposit(mm, pmdp, pgtable); 1202 return hash__pgtable_trans_huge_deposit(mm, pmdp, pgtable); 1203 } 1204 1205 #define __HAVE_ARCH_PGTABLE_WITHDRAW 1206 static inline pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, 1207 pmd_t *pmdp) 1208 { 1209 if (radix_enabled()) 1210 return radix__pgtable_trans_huge_withdraw(mm, pmdp); 1211 return hash__pgtable_trans_huge_withdraw(mm, pmdp); 1212 } 1213 1214 #define __HAVE_ARCH_PMDP_INVALIDATE 1215 extern pmd_t pmdp_invalidate(struct vm_area_struct *vma, unsigned long address, 1216 pmd_t *pmdp); 1217 1218 #define pmd_move_must_withdraw pmd_move_must_withdraw 1219 struct spinlock; 1220 static inline int pmd_move_must_withdraw(struct spinlock *new_pmd_ptl, 1221 struct spinlock *old_pmd_ptl, 1222 struct vm_area_struct *vma) 1223 { 1224 if (radix_enabled()) 1225 return false; 1226 /* 1227 * Archs like ppc64 use pgtable to store per pmd 1228 * specific information. So when we switch the pmd, 1229 * we should also withdraw and deposit the pgtable 1230 */ 1231 return true; 1232 } 1233 1234 1235 #define arch_needs_pgtable_deposit arch_needs_pgtable_deposit 1236 static inline bool arch_needs_pgtable_deposit(void) 1237 { 1238 if (radix_enabled()) 1239 return false; 1240 return true; 1241 } 1242 extern void serialize_against_pte_lookup(struct mm_struct *mm); 1243 1244 1245 static inline pmd_t pmd_mkdevmap(pmd_t pmd) 1246 { 1247 return __pmd(pmd_val(pmd) | (_PAGE_PTE | _PAGE_DEVMAP)); 1248 } 1249 1250 static inline int pmd_devmap(pmd_t pmd) 1251 { 1252 return pte_devmap(pmd_pte(pmd)); 1253 } 1254 1255 static inline int pud_devmap(pud_t pud) 1256 { 1257 return 0; 1258 } 1259 1260 static inline int pgd_devmap(pgd_t pgd) 1261 { 1262 return 0; 1263 } 1264 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1265 1266 static inline const int pud_pfn(pud_t pud) 1267 { 1268 /* 1269 * Currently all calls to pud_pfn() are gated around a pud_devmap() 1270 * check so this should never be used. If it grows another user we 1271 * want to know about it. 1272 */ 1273 BUILD_BUG(); 1274 return 0; 1275 } 1276 1277 #endif /* __ASSEMBLY__ */ 1278 #endif /* _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ */ 1279