1 /* 2 * Copyright (c) 2016~2017 Hisilicon Limited. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 */ 9 10 #include <linux/etherdevice.h> 11 12 #include "hclge_cmd.h" 13 #include "hclge_main.h" 14 #include "hclge_tm.h" 15 16 enum hclge_shaper_level { 17 HCLGE_SHAPER_LVL_PRI = 0, 18 HCLGE_SHAPER_LVL_PG = 1, 19 HCLGE_SHAPER_LVL_PORT = 2, 20 HCLGE_SHAPER_LVL_QSET = 3, 21 HCLGE_SHAPER_LVL_CNT = 4, 22 HCLGE_SHAPER_LVL_VF = 0, 23 HCLGE_SHAPER_LVL_PF = 1, 24 }; 25 26 #define HCLGE_TM_PFC_PKT_GET_CMD_NUM 3 27 #define HCLGE_TM_PFC_NUM_GET_PER_CMD 3 28 29 #define HCLGE_SHAPER_BS_U_DEF 5 30 #define HCLGE_SHAPER_BS_S_DEF 20 31 32 #define HCLGE_ETHER_MAX_RATE 100000 33 34 /* hclge_shaper_para_calc: calculate ir parameter for the shaper 35 * @ir: Rate to be config, its unit is Mbps 36 * @shaper_level: the shaper level. eg: port, pg, priority, queueset 37 * @ir_b: IR_B parameter of IR shaper 38 * @ir_u: IR_U parameter of IR shaper 39 * @ir_s: IR_S parameter of IR shaper 40 * 41 * the formula: 42 * 43 * IR_b * (2 ^ IR_u) * 8 44 * IR(Mbps) = ------------------------- * CLOCK(1000Mbps) 45 * Tick * (2 ^ IR_s) 46 * 47 * @return: 0: calculate sucessful, negative: fail 48 */ 49 static int hclge_shaper_para_calc(u32 ir, u8 shaper_level, 50 u8 *ir_b, u8 *ir_u, u8 *ir_s) 51 { 52 const u16 tick_array[HCLGE_SHAPER_LVL_CNT] = { 53 6 * 256, /* Prioriy level */ 54 6 * 32, /* Prioriy group level */ 55 6 * 8, /* Port level */ 56 6 * 256 /* Qset level */ 57 }; 58 u8 ir_u_calc = 0, ir_s_calc = 0; 59 u32 ir_calc; 60 u32 tick; 61 62 /* Calc tick */ 63 if (shaper_level >= HCLGE_SHAPER_LVL_CNT) 64 return -EINVAL; 65 66 tick = tick_array[shaper_level]; 67 68 /** 69 * Calc the speed if ir_b = 126, ir_u = 0 and ir_s = 0 70 * the formula is changed to: 71 * 126 * 1 * 8 72 * ir_calc = ---------------- * 1000 73 * tick * 1 74 */ 75 ir_calc = (1008000 + (tick >> 1) - 1) / tick; 76 77 if (ir_calc == ir) { 78 *ir_b = 126; 79 *ir_u = 0; 80 *ir_s = 0; 81 82 return 0; 83 } else if (ir_calc > ir) { 84 /* Increasing the denominator to select ir_s value */ 85 while (ir_calc > ir) { 86 ir_s_calc++; 87 ir_calc = 1008000 / (tick * (1 << ir_s_calc)); 88 } 89 90 if (ir_calc == ir) 91 *ir_b = 126; 92 else 93 *ir_b = (ir * tick * (1 << ir_s_calc) + 4000) / 8000; 94 } else { 95 /* Increasing the numerator to select ir_u value */ 96 u32 numerator; 97 98 while (ir_calc < ir) { 99 ir_u_calc++; 100 numerator = 1008000 * (1 << ir_u_calc); 101 ir_calc = (numerator + (tick >> 1)) / tick; 102 } 103 104 if (ir_calc == ir) { 105 *ir_b = 126; 106 } else { 107 u32 denominator = (8000 * (1 << --ir_u_calc)); 108 *ir_b = (ir * tick + (denominator >> 1)) / denominator; 109 } 110 } 111 112 *ir_u = ir_u_calc; 113 *ir_s = ir_s_calc; 114 115 return 0; 116 } 117 118 static int hclge_pfc_stats_get(struct hclge_dev *hdev, 119 enum hclge_opcode_type opcode, u64 *stats) 120 { 121 struct hclge_desc desc[HCLGE_TM_PFC_PKT_GET_CMD_NUM]; 122 int ret, i, j; 123 124 if (!(opcode == HCLGE_OPC_QUERY_PFC_RX_PKT_CNT || 125 opcode == HCLGE_OPC_QUERY_PFC_TX_PKT_CNT)) 126 return -EINVAL; 127 128 for (i = 0; i < HCLGE_TM_PFC_PKT_GET_CMD_NUM; i++) { 129 hclge_cmd_setup_basic_desc(&desc[i], opcode, true); 130 if (i != (HCLGE_TM_PFC_PKT_GET_CMD_NUM - 1)) 131 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 132 else 133 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 134 } 135 136 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_TM_PFC_PKT_GET_CMD_NUM); 137 if (ret) { 138 dev_err(&hdev->pdev->dev, 139 "Get pfc pause stats fail, ret = %d.\n", ret); 140 return ret; 141 } 142 143 for (i = 0; i < HCLGE_TM_PFC_PKT_GET_CMD_NUM; i++) { 144 struct hclge_pfc_stats_cmd *pfc_stats = 145 (struct hclge_pfc_stats_cmd *)desc[i].data; 146 147 for (j = 0; j < HCLGE_TM_PFC_NUM_GET_PER_CMD; j++) { 148 u32 index = i * HCLGE_TM_PFC_PKT_GET_CMD_NUM + j; 149 150 if (index < HCLGE_MAX_TC_NUM) 151 stats[index] = 152 le64_to_cpu(pfc_stats->pkt_num[j]); 153 } 154 } 155 return 0; 156 } 157 158 int hclge_pfc_rx_stats_get(struct hclge_dev *hdev, u64 *stats) 159 { 160 return hclge_pfc_stats_get(hdev, HCLGE_OPC_QUERY_PFC_RX_PKT_CNT, stats); 161 } 162 163 int hclge_pfc_tx_stats_get(struct hclge_dev *hdev, u64 *stats) 164 { 165 return hclge_pfc_stats_get(hdev, HCLGE_OPC_QUERY_PFC_TX_PKT_CNT, stats); 166 } 167 168 int hclge_mac_pause_en_cfg(struct hclge_dev *hdev, bool tx, bool rx) 169 { 170 struct hclge_desc desc; 171 172 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_MAC_PAUSE_EN, false); 173 174 desc.data[0] = cpu_to_le32((tx ? HCLGE_TX_MAC_PAUSE_EN_MSK : 0) | 175 (rx ? HCLGE_RX_MAC_PAUSE_EN_MSK : 0)); 176 177 return hclge_cmd_send(&hdev->hw, &desc, 1); 178 } 179 180 static int hclge_pfc_pause_en_cfg(struct hclge_dev *hdev, u8 tx_rx_bitmap, 181 u8 pfc_bitmap) 182 { 183 struct hclge_desc desc; 184 struct hclge_pfc_en_cmd *pfc = (struct hclge_pfc_en_cmd *)&desc.data; 185 186 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PFC_PAUSE_EN, false); 187 188 pfc->tx_rx_en_bitmap = tx_rx_bitmap; 189 pfc->pri_en_bitmap = pfc_bitmap; 190 191 return hclge_cmd_send(&hdev->hw, &desc, 1); 192 } 193 194 static int hclge_pause_param_cfg(struct hclge_dev *hdev, const u8 *addr, 195 u8 pause_trans_gap, u16 pause_trans_time) 196 { 197 struct hclge_cfg_pause_param_cmd *pause_param; 198 struct hclge_desc desc; 199 200 pause_param = (struct hclge_cfg_pause_param_cmd *)&desc.data; 201 202 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_MAC_PARA, false); 203 204 ether_addr_copy(pause_param->mac_addr, addr); 205 pause_param->pause_trans_gap = pause_trans_gap; 206 pause_param->pause_trans_time = cpu_to_le16(pause_trans_time); 207 208 return hclge_cmd_send(&hdev->hw, &desc, 1); 209 } 210 211 int hclge_pause_addr_cfg(struct hclge_dev *hdev, const u8 *mac_addr) 212 { 213 struct hclge_cfg_pause_param_cmd *pause_param; 214 struct hclge_desc desc; 215 u16 trans_time; 216 u8 trans_gap; 217 int ret; 218 219 pause_param = (struct hclge_cfg_pause_param_cmd *)&desc.data; 220 221 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_MAC_PARA, true); 222 223 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 224 if (ret) 225 return ret; 226 227 trans_gap = pause_param->pause_trans_gap; 228 trans_time = le16_to_cpu(pause_param->pause_trans_time); 229 230 return hclge_pause_param_cfg(hdev, mac_addr, trans_gap, 231 trans_time); 232 } 233 234 static int hclge_fill_pri_array(struct hclge_dev *hdev, u8 *pri, u8 pri_id) 235 { 236 u8 tc; 237 238 tc = hdev->tm_info.prio_tc[pri_id]; 239 240 if (tc >= hdev->tm_info.num_tc) 241 return -EINVAL; 242 243 /** 244 * the register for priority has four bytes, the first bytes includes 245 * priority0 and priority1, the higher 4bit stands for priority1 246 * while the lower 4bit stands for priority0, as below: 247 * first byte: | pri_1 | pri_0 | 248 * second byte: | pri_3 | pri_2 | 249 * third byte: | pri_5 | pri_4 | 250 * fourth byte: | pri_7 | pri_6 | 251 */ 252 pri[pri_id >> 1] |= tc << ((pri_id & 1) * 4); 253 254 return 0; 255 } 256 257 static int hclge_up_to_tc_map(struct hclge_dev *hdev) 258 { 259 struct hclge_desc desc; 260 u8 *pri = (u8 *)desc.data; 261 u8 pri_id; 262 int ret; 263 264 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PRI_TO_TC_MAPPING, false); 265 266 for (pri_id = 0; pri_id < HNAE3_MAX_USER_PRIO; pri_id++) { 267 ret = hclge_fill_pri_array(hdev, pri, pri_id); 268 if (ret) 269 return ret; 270 } 271 272 return hclge_cmd_send(&hdev->hw, &desc, 1); 273 } 274 275 static int hclge_tm_pg_to_pri_map_cfg(struct hclge_dev *hdev, 276 u8 pg_id, u8 pri_bit_map) 277 { 278 struct hclge_pg_to_pri_link_cmd *map; 279 struct hclge_desc desc; 280 281 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PG_TO_PRI_LINK, false); 282 283 map = (struct hclge_pg_to_pri_link_cmd *)desc.data; 284 285 map->pg_id = pg_id; 286 map->pri_bit_map = pri_bit_map; 287 288 return hclge_cmd_send(&hdev->hw, &desc, 1); 289 } 290 291 static int hclge_tm_qs_to_pri_map_cfg(struct hclge_dev *hdev, 292 u16 qs_id, u8 pri) 293 { 294 struct hclge_qs_to_pri_link_cmd *map; 295 struct hclge_desc desc; 296 297 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_QS_TO_PRI_LINK, false); 298 299 map = (struct hclge_qs_to_pri_link_cmd *)desc.data; 300 301 map->qs_id = cpu_to_le16(qs_id); 302 map->priority = pri; 303 map->link_vld = HCLGE_TM_QS_PRI_LINK_VLD_MSK; 304 305 return hclge_cmd_send(&hdev->hw, &desc, 1); 306 } 307 308 static int hclge_tm_q_to_qs_map_cfg(struct hclge_dev *hdev, 309 u8 q_id, u16 qs_id) 310 { 311 struct hclge_nq_to_qs_link_cmd *map; 312 struct hclge_desc desc; 313 314 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_NQ_TO_QS_LINK, false); 315 316 map = (struct hclge_nq_to_qs_link_cmd *)desc.data; 317 318 map->nq_id = cpu_to_le16(q_id); 319 map->qset_id = cpu_to_le16(qs_id | HCLGE_TM_Q_QS_LINK_VLD_MSK); 320 321 return hclge_cmd_send(&hdev->hw, &desc, 1); 322 } 323 324 static int hclge_tm_pg_weight_cfg(struct hclge_dev *hdev, u8 pg_id, 325 u8 dwrr) 326 { 327 struct hclge_pg_weight_cmd *weight; 328 struct hclge_desc desc; 329 330 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PG_WEIGHT, false); 331 332 weight = (struct hclge_pg_weight_cmd *)desc.data; 333 334 weight->pg_id = pg_id; 335 weight->dwrr = dwrr; 336 337 return hclge_cmd_send(&hdev->hw, &desc, 1); 338 } 339 340 static int hclge_tm_pri_weight_cfg(struct hclge_dev *hdev, u8 pri_id, 341 u8 dwrr) 342 { 343 struct hclge_priority_weight_cmd *weight; 344 struct hclge_desc desc; 345 346 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PRI_WEIGHT, false); 347 348 weight = (struct hclge_priority_weight_cmd *)desc.data; 349 350 weight->pri_id = pri_id; 351 weight->dwrr = dwrr; 352 353 return hclge_cmd_send(&hdev->hw, &desc, 1); 354 } 355 356 static int hclge_tm_qs_weight_cfg(struct hclge_dev *hdev, u16 qs_id, 357 u8 dwrr) 358 { 359 struct hclge_qs_weight_cmd *weight; 360 struct hclge_desc desc; 361 362 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_QS_WEIGHT, false); 363 364 weight = (struct hclge_qs_weight_cmd *)desc.data; 365 366 weight->qs_id = cpu_to_le16(qs_id); 367 weight->dwrr = dwrr; 368 369 return hclge_cmd_send(&hdev->hw, &desc, 1); 370 } 371 372 static int hclge_tm_pg_shapping_cfg(struct hclge_dev *hdev, 373 enum hclge_shap_bucket bucket, u8 pg_id, 374 u8 ir_b, u8 ir_u, u8 ir_s, u8 bs_b, u8 bs_s) 375 { 376 struct hclge_pg_shapping_cmd *shap_cfg_cmd; 377 enum hclge_opcode_type opcode; 378 struct hclge_desc desc; 379 u32 shapping_para = 0; 380 381 opcode = bucket ? HCLGE_OPC_TM_PG_P_SHAPPING : 382 HCLGE_OPC_TM_PG_C_SHAPPING; 383 hclge_cmd_setup_basic_desc(&desc, opcode, false); 384 385 shap_cfg_cmd = (struct hclge_pg_shapping_cmd *)desc.data; 386 387 shap_cfg_cmd->pg_id = pg_id; 388 389 hclge_tm_set_field(shapping_para, IR_B, ir_b); 390 hclge_tm_set_field(shapping_para, IR_U, ir_u); 391 hclge_tm_set_field(shapping_para, IR_S, ir_s); 392 hclge_tm_set_field(shapping_para, BS_B, bs_b); 393 hclge_tm_set_field(shapping_para, BS_S, bs_s); 394 395 shap_cfg_cmd->pg_shapping_para = cpu_to_le32(shapping_para); 396 397 return hclge_cmd_send(&hdev->hw, &desc, 1); 398 } 399 400 static int hclge_tm_port_shaper_cfg(struct hclge_dev *hdev) 401 { 402 struct hclge_port_shapping_cmd *shap_cfg_cmd; 403 struct hclge_desc desc; 404 u32 shapping_para = 0; 405 u8 ir_u, ir_b, ir_s; 406 int ret; 407 408 ret = hclge_shaper_para_calc(HCLGE_ETHER_MAX_RATE, 409 HCLGE_SHAPER_LVL_PORT, 410 &ir_b, &ir_u, &ir_s); 411 if (ret) 412 return ret; 413 414 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PORT_SHAPPING, false); 415 shap_cfg_cmd = (struct hclge_port_shapping_cmd *)desc.data; 416 417 hclge_tm_set_field(shapping_para, IR_B, ir_b); 418 hclge_tm_set_field(shapping_para, IR_U, ir_u); 419 hclge_tm_set_field(shapping_para, IR_S, ir_s); 420 hclge_tm_set_field(shapping_para, BS_B, HCLGE_SHAPER_BS_U_DEF); 421 hclge_tm_set_field(shapping_para, BS_S, HCLGE_SHAPER_BS_S_DEF); 422 423 shap_cfg_cmd->port_shapping_para = cpu_to_le32(shapping_para); 424 425 return hclge_cmd_send(&hdev->hw, &desc, 1); 426 } 427 428 static int hclge_tm_pri_shapping_cfg(struct hclge_dev *hdev, 429 enum hclge_shap_bucket bucket, u8 pri_id, 430 u8 ir_b, u8 ir_u, u8 ir_s, 431 u8 bs_b, u8 bs_s) 432 { 433 struct hclge_pri_shapping_cmd *shap_cfg_cmd; 434 enum hclge_opcode_type opcode; 435 struct hclge_desc desc; 436 u32 shapping_para = 0; 437 438 opcode = bucket ? HCLGE_OPC_TM_PRI_P_SHAPPING : 439 HCLGE_OPC_TM_PRI_C_SHAPPING; 440 441 hclge_cmd_setup_basic_desc(&desc, opcode, false); 442 443 shap_cfg_cmd = (struct hclge_pri_shapping_cmd *)desc.data; 444 445 shap_cfg_cmd->pri_id = pri_id; 446 447 hclge_tm_set_field(shapping_para, IR_B, ir_b); 448 hclge_tm_set_field(shapping_para, IR_U, ir_u); 449 hclge_tm_set_field(shapping_para, IR_S, ir_s); 450 hclge_tm_set_field(shapping_para, BS_B, bs_b); 451 hclge_tm_set_field(shapping_para, BS_S, bs_s); 452 453 shap_cfg_cmd->pri_shapping_para = cpu_to_le32(shapping_para); 454 455 return hclge_cmd_send(&hdev->hw, &desc, 1); 456 } 457 458 static int hclge_tm_pg_schd_mode_cfg(struct hclge_dev *hdev, u8 pg_id) 459 { 460 struct hclge_desc desc; 461 462 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PG_SCH_MODE_CFG, false); 463 464 if (hdev->tm_info.pg_info[pg_id].pg_sch_mode == HCLGE_SCH_MODE_DWRR) 465 desc.data[1] = cpu_to_le32(HCLGE_TM_TX_SCHD_DWRR_MSK); 466 else 467 desc.data[1] = 0; 468 469 desc.data[0] = cpu_to_le32(pg_id); 470 471 return hclge_cmd_send(&hdev->hw, &desc, 1); 472 } 473 474 static int hclge_tm_pri_schd_mode_cfg(struct hclge_dev *hdev, u8 pri_id) 475 { 476 struct hclge_desc desc; 477 478 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PRI_SCH_MODE_CFG, false); 479 480 if (hdev->tm_info.tc_info[pri_id].tc_sch_mode == HCLGE_SCH_MODE_DWRR) 481 desc.data[1] = cpu_to_le32(HCLGE_TM_TX_SCHD_DWRR_MSK); 482 else 483 desc.data[1] = 0; 484 485 desc.data[0] = cpu_to_le32(pri_id); 486 487 return hclge_cmd_send(&hdev->hw, &desc, 1); 488 } 489 490 static int hclge_tm_qs_schd_mode_cfg(struct hclge_dev *hdev, u16 qs_id, u8 mode) 491 { 492 struct hclge_desc desc; 493 494 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_QS_SCH_MODE_CFG, false); 495 496 if (mode == HCLGE_SCH_MODE_DWRR) 497 desc.data[1] = cpu_to_le32(HCLGE_TM_TX_SCHD_DWRR_MSK); 498 else 499 desc.data[1] = 0; 500 501 desc.data[0] = cpu_to_le32(qs_id); 502 503 return hclge_cmd_send(&hdev->hw, &desc, 1); 504 } 505 506 static int hclge_tm_qs_bp_cfg(struct hclge_dev *hdev, u8 tc) 507 { 508 struct hclge_bp_to_qs_map_cmd *bp_to_qs_map_cmd; 509 struct hclge_desc desc; 510 511 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_BP_TO_QSET_MAPPING, 512 false); 513 514 bp_to_qs_map_cmd = (struct hclge_bp_to_qs_map_cmd *)desc.data; 515 516 bp_to_qs_map_cmd->tc_id = tc; 517 518 /* Qset and tc is one by one mapping */ 519 bp_to_qs_map_cmd->qs_bit_map = cpu_to_le32(1 << tc); 520 521 return hclge_cmd_send(&hdev->hw, &desc, 1); 522 } 523 524 static void hclge_tm_vport_tc_info_update(struct hclge_vport *vport) 525 { 526 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 527 struct hclge_dev *hdev = vport->back; 528 u8 i; 529 530 vport->bw_limit = hdev->tm_info.pg_info[0].bw_limit; 531 kinfo->num_tc = 532 min_t(u16, kinfo->num_tqps, hdev->tm_info.num_tc); 533 kinfo->rss_size 534 = min_t(u16, hdev->rss_size_max, 535 kinfo->num_tqps / kinfo->num_tc); 536 vport->qs_offset = hdev->tm_info.num_tc * vport->vport_id; 537 vport->dwrr = 100; /* 100 percent as init */ 538 vport->alloc_rss_size = kinfo->rss_size; 539 540 for (i = 0; i < kinfo->num_tc; i++) { 541 if (hdev->hw_tc_map & BIT(i)) { 542 kinfo->tc_info[i].enable = true; 543 kinfo->tc_info[i].tqp_offset = i * kinfo->rss_size; 544 kinfo->tc_info[i].tqp_count = kinfo->rss_size; 545 kinfo->tc_info[i].tc = i; 546 } else { 547 /* Set to default queue if TC is disable */ 548 kinfo->tc_info[i].enable = false; 549 kinfo->tc_info[i].tqp_offset = 0; 550 kinfo->tc_info[i].tqp_count = 1; 551 kinfo->tc_info[i].tc = 0; 552 } 553 } 554 555 memcpy(kinfo->prio_tc, hdev->tm_info.prio_tc, 556 FIELD_SIZEOF(struct hnae3_knic_private_info, prio_tc)); 557 } 558 559 static void hclge_tm_vport_info_update(struct hclge_dev *hdev) 560 { 561 struct hclge_vport *vport = hdev->vport; 562 u32 i; 563 564 for (i = 0; i < hdev->num_alloc_vport; i++) { 565 hclge_tm_vport_tc_info_update(vport); 566 567 vport++; 568 } 569 } 570 571 static void hclge_tm_tc_info_init(struct hclge_dev *hdev) 572 { 573 u8 i; 574 575 for (i = 0; i < hdev->tm_info.num_tc; i++) { 576 hdev->tm_info.tc_info[i].tc_id = i; 577 hdev->tm_info.tc_info[i].tc_sch_mode = HCLGE_SCH_MODE_DWRR; 578 hdev->tm_info.tc_info[i].pgid = 0; 579 hdev->tm_info.tc_info[i].bw_limit = 580 hdev->tm_info.pg_info[0].bw_limit; 581 } 582 583 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) 584 hdev->tm_info.prio_tc[i] = 585 (i >= hdev->tm_info.num_tc) ? 0 : i; 586 587 /* DCB is enabled if we have more than 1 TC */ 588 if (hdev->tm_info.num_tc > 1) 589 hdev->flag |= HCLGE_FLAG_DCB_ENABLE; 590 else 591 hdev->flag &= ~HCLGE_FLAG_DCB_ENABLE; 592 } 593 594 static void hclge_tm_pg_info_init(struct hclge_dev *hdev) 595 { 596 u8 i; 597 598 for (i = 0; i < hdev->tm_info.num_pg; i++) { 599 int k; 600 601 hdev->tm_info.pg_dwrr[i] = i ? 0 : 100; 602 603 hdev->tm_info.pg_info[i].pg_id = i; 604 hdev->tm_info.pg_info[i].pg_sch_mode = HCLGE_SCH_MODE_DWRR; 605 606 hdev->tm_info.pg_info[i].bw_limit = HCLGE_ETHER_MAX_RATE; 607 608 if (i != 0) 609 continue; 610 611 hdev->tm_info.pg_info[i].tc_bit_map = hdev->hw_tc_map; 612 for (k = 0; k < hdev->tm_info.num_tc; k++) 613 hdev->tm_info.pg_info[i].tc_dwrr[k] = 100; 614 } 615 } 616 617 static void hclge_pfc_info_init(struct hclge_dev *hdev) 618 { 619 if (!(hdev->flag & HCLGE_FLAG_DCB_ENABLE)) { 620 if (hdev->fc_mode_last_time == HCLGE_FC_PFC) 621 dev_warn(&hdev->pdev->dev, 622 "DCB is disable, but last mode is FC_PFC\n"); 623 624 hdev->tm_info.fc_mode = hdev->fc_mode_last_time; 625 } else if (hdev->tm_info.fc_mode != HCLGE_FC_PFC) { 626 /* fc_mode_last_time record the last fc_mode when 627 * DCB is enabled, so that fc_mode can be set to 628 * the correct value when DCB is disabled. 629 */ 630 hdev->fc_mode_last_time = hdev->tm_info.fc_mode; 631 hdev->tm_info.fc_mode = HCLGE_FC_PFC; 632 } 633 } 634 635 static int hclge_tm_schd_info_init(struct hclge_dev *hdev) 636 { 637 if ((hdev->tx_sch_mode != HCLGE_FLAG_TC_BASE_SCH_MODE) && 638 (hdev->tm_info.num_pg != 1)) 639 return -EINVAL; 640 641 hclge_tm_pg_info_init(hdev); 642 643 hclge_tm_tc_info_init(hdev); 644 645 hclge_tm_vport_info_update(hdev); 646 647 hclge_pfc_info_init(hdev); 648 649 return 0; 650 } 651 652 static int hclge_tm_pg_to_pri_map(struct hclge_dev *hdev) 653 { 654 int ret; 655 u32 i; 656 657 if (hdev->tx_sch_mode != HCLGE_FLAG_TC_BASE_SCH_MODE) 658 return 0; 659 660 for (i = 0; i < hdev->tm_info.num_pg; i++) { 661 /* Cfg mapping */ 662 ret = hclge_tm_pg_to_pri_map_cfg( 663 hdev, i, hdev->tm_info.pg_info[i].tc_bit_map); 664 if (ret) 665 return ret; 666 } 667 668 return 0; 669 } 670 671 static int hclge_tm_pg_shaper_cfg(struct hclge_dev *hdev) 672 { 673 u8 ir_u, ir_b, ir_s; 674 int ret; 675 u32 i; 676 677 /* Cfg pg schd */ 678 if (hdev->tx_sch_mode != HCLGE_FLAG_TC_BASE_SCH_MODE) 679 return 0; 680 681 /* Pg to pri */ 682 for (i = 0; i < hdev->tm_info.num_pg; i++) { 683 /* Calc shaper para */ 684 ret = hclge_shaper_para_calc( 685 hdev->tm_info.pg_info[i].bw_limit, 686 HCLGE_SHAPER_LVL_PG, 687 &ir_b, &ir_u, &ir_s); 688 if (ret) 689 return ret; 690 691 ret = hclge_tm_pg_shapping_cfg(hdev, 692 HCLGE_TM_SHAP_C_BUCKET, i, 693 0, 0, 0, HCLGE_SHAPER_BS_U_DEF, 694 HCLGE_SHAPER_BS_S_DEF); 695 if (ret) 696 return ret; 697 698 ret = hclge_tm_pg_shapping_cfg(hdev, 699 HCLGE_TM_SHAP_P_BUCKET, i, 700 ir_b, ir_u, ir_s, 701 HCLGE_SHAPER_BS_U_DEF, 702 HCLGE_SHAPER_BS_S_DEF); 703 if (ret) 704 return ret; 705 } 706 707 return 0; 708 } 709 710 static int hclge_tm_pg_dwrr_cfg(struct hclge_dev *hdev) 711 { 712 int ret; 713 u32 i; 714 715 /* cfg pg schd */ 716 if (hdev->tx_sch_mode != HCLGE_FLAG_TC_BASE_SCH_MODE) 717 return 0; 718 719 /* pg to prio */ 720 for (i = 0; i < hdev->tm_info.num_pg; i++) { 721 /* Cfg dwrr */ 722 ret = hclge_tm_pg_weight_cfg(hdev, i, 723 hdev->tm_info.pg_dwrr[i]); 724 if (ret) 725 return ret; 726 } 727 728 return 0; 729 } 730 731 static int hclge_vport_q_to_qs_map(struct hclge_dev *hdev, 732 struct hclge_vport *vport) 733 { 734 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 735 struct hnae3_queue **tqp = kinfo->tqp; 736 struct hnae3_tc_info *v_tc_info; 737 u32 i, j; 738 int ret; 739 740 for (i = 0; i < kinfo->num_tc; i++) { 741 v_tc_info = &kinfo->tc_info[i]; 742 for (j = 0; j < v_tc_info->tqp_count; j++) { 743 struct hnae3_queue *q = tqp[v_tc_info->tqp_offset + j]; 744 745 ret = hclge_tm_q_to_qs_map_cfg(hdev, 746 hclge_get_queue_id(q), 747 vport->qs_offset + i); 748 if (ret) 749 return ret; 750 } 751 } 752 753 return 0; 754 } 755 756 static int hclge_tm_pri_q_qs_cfg(struct hclge_dev *hdev) 757 { 758 struct hclge_vport *vport = hdev->vport; 759 int ret; 760 u32 i, k; 761 762 if (hdev->tx_sch_mode == HCLGE_FLAG_TC_BASE_SCH_MODE) { 763 /* Cfg qs -> pri mapping, one by one mapping */ 764 for (k = 0; k < hdev->num_alloc_vport; k++) 765 for (i = 0; i < hdev->tm_info.num_tc; i++) { 766 ret = hclge_tm_qs_to_pri_map_cfg( 767 hdev, vport[k].qs_offset + i, i); 768 if (ret) 769 return ret; 770 } 771 } else if (hdev->tx_sch_mode == HCLGE_FLAG_VNET_BASE_SCH_MODE) { 772 /* Cfg qs -> pri mapping, qs = tc, pri = vf, 8 qs -> 1 pri */ 773 for (k = 0; k < hdev->num_alloc_vport; k++) 774 for (i = 0; i < HNAE3_MAX_TC; i++) { 775 ret = hclge_tm_qs_to_pri_map_cfg( 776 hdev, vport[k].qs_offset + i, k); 777 if (ret) 778 return ret; 779 } 780 } else { 781 return -EINVAL; 782 } 783 784 /* Cfg q -> qs mapping */ 785 for (i = 0; i < hdev->num_alloc_vport; i++) { 786 ret = hclge_vport_q_to_qs_map(hdev, vport); 787 if (ret) 788 return ret; 789 790 vport++; 791 } 792 793 return 0; 794 } 795 796 static int hclge_tm_pri_tc_base_shaper_cfg(struct hclge_dev *hdev) 797 { 798 u8 ir_u, ir_b, ir_s; 799 int ret; 800 u32 i; 801 802 for (i = 0; i < hdev->tm_info.num_tc; i++) { 803 ret = hclge_shaper_para_calc( 804 hdev->tm_info.tc_info[i].bw_limit, 805 HCLGE_SHAPER_LVL_PRI, 806 &ir_b, &ir_u, &ir_s); 807 if (ret) 808 return ret; 809 810 ret = hclge_tm_pri_shapping_cfg( 811 hdev, HCLGE_TM_SHAP_C_BUCKET, i, 812 0, 0, 0, HCLGE_SHAPER_BS_U_DEF, 813 HCLGE_SHAPER_BS_S_DEF); 814 if (ret) 815 return ret; 816 817 ret = hclge_tm_pri_shapping_cfg( 818 hdev, HCLGE_TM_SHAP_P_BUCKET, i, 819 ir_b, ir_u, ir_s, HCLGE_SHAPER_BS_U_DEF, 820 HCLGE_SHAPER_BS_S_DEF); 821 if (ret) 822 return ret; 823 } 824 825 return 0; 826 } 827 828 static int hclge_tm_pri_vnet_base_shaper_pri_cfg(struct hclge_vport *vport) 829 { 830 struct hclge_dev *hdev = vport->back; 831 u8 ir_u, ir_b, ir_s; 832 int ret; 833 834 ret = hclge_shaper_para_calc(vport->bw_limit, HCLGE_SHAPER_LVL_VF, 835 &ir_b, &ir_u, &ir_s); 836 if (ret) 837 return ret; 838 839 ret = hclge_tm_pri_shapping_cfg(hdev, HCLGE_TM_SHAP_C_BUCKET, 840 vport->vport_id, 841 0, 0, 0, HCLGE_SHAPER_BS_U_DEF, 842 HCLGE_SHAPER_BS_S_DEF); 843 if (ret) 844 return ret; 845 846 ret = hclge_tm_pri_shapping_cfg(hdev, HCLGE_TM_SHAP_P_BUCKET, 847 vport->vport_id, 848 ir_b, ir_u, ir_s, 849 HCLGE_SHAPER_BS_U_DEF, 850 HCLGE_SHAPER_BS_S_DEF); 851 if (ret) 852 return ret; 853 854 return 0; 855 } 856 857 static int hclge_tm_pri_vnet_base_shaper_qs_cfg(struct hclge_vport *vport) 858 { 859 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 860 struct hclge_dev *hdev = vport->back; 861 u8 ir_u, ir_b, ir_s; 862 u32 i; 863 int ret; 864 865 for (i = 0; i < kinfo->num_tc; i++) { 866 ret = hclge_shaper_para_calc( 867 hdev->tm_info.tc_info[i].bw_limit, 868 HCLGE_SHAPER_LVL_QSET, 869 &ir_b, &ir_u, &ir_s); 870 if (ret) 871 return ret; 872 } 873 874 return 0; 875 } 876 877 static int hclge_tm_pri_vnet_base_shaper_cfg(struct hclge_dev *hdev) 878 { 879 struct hclge_vport *vport = hdev->vport; 880 int ret; 881 u32 i; 882 883 /* Need config vport shaper */ 884 for (i = 0; i < hdev->num_alloc_vport; i++) { 885 ret = hclge_tm_pri_vnet_base_shaper_pri_cfg(vport); 886 if (ret) 887 return ret; 888 889 ret = hclge_tm_pri_vnet_base_shaper_qs_cfg(vport); 890 if (ret) 891 return ret; 892 893 vport++; 894 } 895 896 return 0; 897 } 898 899 static int hclge_tm_pri_shaper_cfg(struct hclge_dev *hdev) 900 { 901 int ret; 902 903 if (hdev->tx_sch_mode == HCLGE_FLAG_TC_BASE_SCH_MODE) { 904 ret = hclge_tm_pri_tc_base_shaper_cfg(hdev); 905 if (ret) 906 return ret; 907 } else { 908 ret = hclge_tm_pri_vnet_base_shaper_cfg(hdev); 909 if (ret) 910 return ret; 911 } 912 913 return 0; 914 } 915 916 static int hclge_tm_pri_tc_base_dwrr_cfg(struct hclge_dev *hdev) 917 { 918 struct hclge_vport *vport = hdev->vport; 919 struct hclge_pg_info *pg_info; 920 u8 dwrr; 921 int ret; 922 u32 i, k; 923 924 for (i = 0; i < hdev->tm_info.num_tc; i++) { 925 pg_info = 926 &hdev->tm_info.pg_info[hdev->tm_info.tc_info[i].pgid]; 927 dwrr = pg_info->tc_dwrr[i]; 928 929 ret = hclge_tm_pri_weight_cfg(hdev, i, dwrr); 930 if (ret) 931 return ret; 932 933 for (k = 0; k < hdev->num_alloc_vport; k++) { 934 ret = hclge_tm_qs_weight_cfg( 935 hdev, vport[k].qs_offset + i, 936 vport[k].dwrr); 937 if (ret) 938 return ret; 939 } 940 } 941 942 return 0; 943 } 944 945 static int hclge_tm_pri_vnet_base_dwrr_pri_cfg(struct hclge_vport *vport) 946 { 947 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 948 struct hclge_dev *hdev = vport->back; 949 int ret; 950 u8 i; 951 952 /* Vf dwrr */ 953 ret = hclge_tm_pri_weight_cfg(hdev, vport->vport_id, vport->dwrr); 954 if (ret) 955 return ret; 956 957 /* Qset dwrr */ 958 for (i = 0; i < kinfo->num_tc; i++) { 959 ret = hclge_tm_qs_weight_cfg( 960 hdev, vport->qs_offset + i, 961 hdev->tm_info.pg_info[0].tc_dwrr[i]); 962 if (ret) 963 return ret; 964 } 965 966 return 0; 967 } 968 969 static int hclge_tm_pri_vnet_base_dwrr_cfg(struct hclge_dev *hdev) 970 { 971 struct hclge_vport *vport = hdev->vport; 972 int ret; 973 u32 i; 974 975 for (i = 0; i < hdev->num_alloc_vport; i++) { 976 ret = hclge_tm_pri_vnet_base_dwrr_pri_cfg(vport); 977 if (ret) 978 return ret; 979 980 vport++; 981 } 982 983 return 0; 984 } 985 986 static int hclge_tm_pri_dwrr_cfg(struct hclge_dev *hdev) 987 { 988 int ret; 989 990 if (hdev->tx_sch_mode == HCLGE_FLAG_TC_BASE_SCH_MODE) { 991 ret = hclge_tm_pri_tc_base_dwrr_cfg(hdev); 992 if (ret) 993 return ret; 994 } else { 995 ret = hclge_tm_pri_vnet_base_dwrr_cfg(hdev); 996 if (ret) 997 return ret; 998 } 999 1000 return 0; 1001 } 1002 1003 int hclge_tm_map_cfg(struct hclge_dev *hdev) 1004 { 1005 int ret; 1006 1007 ret = hclge_up_to_tc_map(hdev); 1008 if (ret) 1009 return ret; 1010 1011 ret = hclge_tm_pg_to_pri_map(hdev); 1012 if (ret) 1013 return ret; 1014 1015 return hclge_tm_pri_q_qs_cfg(hdev); 1016 } 1017 1018 static int hclge_tm_shaper_cfg(struct hclge_dev *hdev) 1019 { 1020 int ret; 1021 1022 ret = hclge_tm_port_shaper_cfg(hdev); 1023 if (ret) 1024 return ret; 1025 1026 ret = hclge_tm_pg_shaper_cfg(hdev); 1027 if (ret) 1028 return ret; 1029 1030 return hclge_tm_pri_shaper_cfg(hdev); 1031 } 1032 1033 int hclge_tm_dwrr_cfg(struct hclge_dev *hdev) 1034 { 1035 int ret; 1036 1037 ret = hclge_tm_pg_dwrr_cfg(hdev); 1038 if (ret) 1039 return ret; 1040 1041 return hclge_tm_pri_dwrr_cfg(hdev); 1042 } 1043 1044 static int hclge_tm_lvl2_schd_mode_cfg(struct hclge_dev *hdev) 1045 { 1046 int ret; 1047 u8 i; 1048 1049 /* Only being config on TC-Based scheduler mode */ 1050 if (hdev->tx_sch_mode == HCLGE_FLAG_VNET_BASE_SCH_MODE) 1051 return 0; 1052 1053 for (i = 0; i < hdev->tm_info.num_pg; i++) { 1054 ret = hclge_tm_pg_schd_mode_cfg(hdev, i); 1055 if (ret) 1056 return ret; 1057 } 1058 1059 return 0; 1060 } 1061 1062 static int hclge_tm_schd_mode_vnet_base_cfg(struct hclge_vport *vport) 1063 { 1064 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 1065 struct hclge_dev *hdev = vport->back; 1066 int ret; 1067 u8 i; 1068 1069 ret = hclge_tm_pri_schd_mode_cfg(hdev, vport->vport_id); 1070 if (ret) 1071 return ret; 1072 1073 for (i = 0; i < kinfo->num_tc; i++) { 1074 u8 sch_mode = hdev->tm_info.tc_info[i].tc_sch_mode; 1075 1076 ret = hclge_tm_qs_schd_mode_cfg(hdev, vport->qs_offset + i, 1077 sch_mode); 1078 if (ret) 1079 return ret; 1080 } 1081 1082 return 0; 1083 } 1084 1085 static int hclge_tm_lvl34_schd_mode_cfg(struct hclge_dev *hdev) 1086 { 1087 struct hclge_vport *vport = hdev->vport; 1088 int ret; 1089 u8 i, k; 1090 1091 if (hdev->tx_sch_mode == HCLGE_FLAG_TC_BASE_SCH_MODE) { 1092 for (i = 0; i < hdev->tm_info.num_tc; i++) { 1093 ret = hclge_tm_pri_schd_mode_cfg(hdev, i); 1094 if (ret) 1095 return ret; 1096 1097 for (k = 0; k < hdev->num_alloc_vport; k++) { 1098 ret = hclge_tm_qs_schd_mode_cfg( 1099 hdev, vport[k].qs_offset + i, 1100 HCLGE_SCH_MODE_DWRR); 1101 if (ret) 1102 return ret; 1103 } 1104 } 1105 } else { 1106 for (i = 0; i < hdev->num_alloc_vport; i++) { 1107 ret = hclge_tm_schd_mode_vnet_base_cfg(vport); 1108 if (ret) 1109 return ret; 1110 1111 vport++; 1112 } 1113 } 1114 1115 return 0; 1116 } 1117 1118 int hclge_tm_schd_mode_hw(struct hclge_dev *hdev) 1119 { 1120 int ret; 1121 1122 ret = hclge_tm_lvl2_schd_mode_cfg(hdev); 1123 if (ret) 1124 return ret; 1125 1126 return hclge_tm_lvl34_schd_mode_cfg(hdev); 1127 } 1128 1129 static int hclge_tm_schd_setup_hw(struct hclge_dev *hdev) 1130 { 1131 int ret; 1132 1133 /* Cfg tm mapping */ 1134 ret = hclge_tm_map_cfg(hdev); 1135 if (ret) 1136 return ret; 1137 1138 /* Cfg tm shaper */ 1139 ret = hclge_tm_shaper_cfg(hdev); 1140 if (ret) 1141 return ret; 1142 1143 /* Cfg dwrr */ 1144 ret = hclge_tm_dwrr_cfg(hdev); 1145 if (ret) 1146 return ret; 1147 1148 /* Cfg schd mode for each level schd */ 1149 return hclge_tm_schd_mode_hw(hdev); 1150 } 1151 1152 static int hclge_pause_param_setup_hw(struct hclge_dev *hdev) 1153 { 1154 struct hclge_mac *mac = &hdev->hw.mac; 1155 1156 return hclge_pause_param_cfg(hdev, mac->mac_addr, 1157 HCLGE_DEFAULT_PAUSE_TRANS_GAP, 1158 HCLGE_DEFAULT_PAUSE_TRANS_TIME); 1159 } 1160 1161 static int hclge_pfc_setup_hw(struct hclge_dev *hdev) 1162 { 1163 u8 enable_bitmap = 0; 1164 1165 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) 1166 enable_bitmap = HCLGE_TX_MAC_PAUSE_EN_MSK | 1167 HCLGE_RX_MAC_PAUSE_EN_MSK; 1168 1169 return hclge_pfc_pause_en_cfg(hdev, enable_bitmap, 1170 hdev->tm_info.hw_pfc_map); 1171 } 1172 1173 static int hclge_mac_pause_setup_hw(struct hclge_dev *hdev) 1174 { 1175 bool tx_en, rx_en; 1176 1177 switch (hdev->tm_info.fc_mode) { 1178 case HCLGE_FC_NONE: 1179 tx_en = false; 1180 rx_en = false; 1181 break; 1182 case HCLGE_FC_RX_PAUSE: 1183 tx_en = false; 1184 rx_en = true; 1185 break; 1186 case HCLGE_FC_TX_PAUSE: 1187 tx_en = true; 1188 rx_en = false; 1189 break; 1190 case HCLGE_FC_FULL: 1191 tx_en = true; 1192 rx_en = true; 1193 break; 1194 default: 1195 tx_en = true; 1196 rx_en = true; 1197 } 1198 1199 return hclge_mac_pause_en_cfg(hdev, tx_en, rx_en); 1200 } 1201 1202 int hclge_pause_setup_hw(struct hclge_dev *hdev) 1203 { 1204 int ret; 1205 u8 i; 1206 1207 ret = hclge_pause_param_setup_hw(hdev); 1208 if (ret) 1209 return ret; 1210 1211 if (hdev->tm_info.fc_mode != HCLGE_FC_PFC) 1212 return hclge_mac_pause_setup_hw(hdev); 1213 1214 /* Only DCB-supported dev supports qset back pressure and pfc cmd */ 1215 if (!hnae3_dev_dcb_supported(hdev)) 1216 return 0; 1217 1218 /* When MAC is GE Mode, hdev does not support pfc setting */ 1219 ret = hclge_pfc_setup_hw(hdev); 1220 if (ret) 1221 dev_warn(&hdev->pdev->dev, "set pfc pause failed:%d\n", ret); 1222 1223 for (i = 0; i < hdev->tm_info.num_tc; i++) { 1224 ret = hclge_tm_qs_bp_cfg(hdev, i); 1225 if (ret) 1226 return ret; 1227 } 1228 1229 return 0; 1230 } 1231 1232 int hclge_tm_prio_tc_info_update(struct hclge_dev *hdev, u8 *prio_tc) 1233 { 1234 struct hclge_vport *vport = hdev->vport; 1235 struct hnae3_knic_private_info *kinfo; 1236 u32 i, k; 1237 1238 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) { 1239 if (prio_tc[i] >= hdev->tm_info.num_tc) 1240 return -EINVAL; 1241 hdev->tm_info.prio_tc[i] = prio_tc[i]; 1242 1243 for (k = 0; k < hdev->num_alloc_vport; k++) { 1244 kinfo = &vport[k].nic.kinfo; 1245 kinfo->prio_tc[i] = prio_tc[i]; 1246 } 1247 } 1248 return 0; 1249 } 1250 1251 void hclge_tm_schd_info_update(struct hclge_dev *hdev, u8 num_tc) 1252 { 1253 u8 i, bit_map = 0; 1254 1255 hdev->tm_info.num_tc = num_tc; 1256 1257 for (i = 0; i < hdev->tm_info.num_tc; i++) 1258 bit_map |= BIT(i); 1259 1260 if (!bit_map) { 1261 bit_map = 1; 1262 hdev->tm_info.num_tc = 1; 1263 } 1264 1265 hdev->hw_tc_map = bit_map; 1266 1267 hclge_tm_schd_info_init(hdev); 1268 } 1269 1270 int hclge_tm_init_hw(struct hclge_dev *hdev) 1271 { 1272 int ret; 1273 1274 if ((hdev->tx_sch_mode != HCLGE_FLAG_TC_BASE_SCH_MODE) && 1275 (hdev->tx_sch_mode != HCLGE_FLAG_VNET_BASE_SCH_MODE)) 1276 return -ENOTSUPP; 1277 1278 ret = hclge_tm_schd_setup_hw(hdev); 1279 if (ret) 1280 return ret; 1281 1282 ret = hclge_pause_setup_hw(hdev); 1283 if (ret) 1284 return ret; 1285 1286 return 0; 1287 } 1288 1289 int hclge_tm_schd_init(struct hclge_dev *hdev) 1290 { 1291 int ret; 1292 1293 /* fc_mode is HCLGE_FC_FULL on reset */ 1294 hdev->tm_info.fc_mode = HCLGE_FC_FULL; 1295 hdev->fc_mode_last_time = hdev->tm_info.fc_mode; 1296 1297 ret = hclge_tm_schd_info_init(hdev); 1298 if (ret) 1299 return ret; 1300 1301 return hclge_tm_init_hw(hdev); 1302 } 1303