1 /** 2 * \file amdgpu_drv.c 3 * AMD Amdgpu driver 4 * 5 * \author Gareth Hughes <gareth@valinux.com> 6 */ 7 8 /* 9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 10 * All Rights Reserved. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a 13 * copy of this software and associated documentation files (the "Software"), 14 * to deal in the Software without restriction, including without limitation 15 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 16 * and/or sell copies of the Software, and to permit persons to whom the 17 * Software is furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice (including the next 20 * paragraph) shall be included in all copies or substantial portions of the 21 * Software. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 29 * OTHER DEALINGS IN THE SOFTWARE. 30 */ 31 32 #include <drm/drmP.h> 33 #include <drm/amdgpu_drm.h> 34 #include <drm/drm_gem.h> 35 #include "amdgpu_drv.h" 36 37 #include <drm/drm_pciids.h> 38 #include <linux/console.h> 39 #include <linux/module.h> 40 #include <linux/pm_runtime.h> 41 #include <linux/vga_switcheroo.h> 42 #include <drm/drm_crtc_helper.h> 43 44 #include "amdgpu.h" 45 #include "amdgpu_irq.h" 46 47 #include "amdgpu_amdkfd.h" 48 49 /* 50 * KMS wrapper. 51 * - 3.0.0 - initial driver 52 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 53 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 54 * at the end of IBs. 55 * - 3.3.0 - Add VM support for UVD on supported hardware. 56 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 57 * - 3.5.0 - Add support for new UVD_NO_OP register. 58 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 59 * - 3.7.0 - Add support for VCE clock list packet 60 * - 3.8.0 - Add support raster config init in the kernel 61 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 62 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 63 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 64 * - 3.12.0 - Add query for double offchip LDS buffers 65 * - 3.13.0 - Add PRT support 66 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 67 * - 3.15.0 - Export more gpu info for gfx9 68 * - 3.16.0 - Add reserved vmid support 69 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 70 * - 3.18.0 - Export gpu always on cu bitmap 71 * - 3.19.0 - Add support for UVD MJPEG decode 72 * - 3.20.0 - Add support for local BOs 73 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 74 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 75 * - 3.23.0 - Add query for VRAM lost counter 76 */ 77 #define KMS_DRIVER_MAJOR 3 78 #define KMS_DRIVER_MINOR 23 79 #define KMS_DRIVER_PATCHLEVEL 0 80 81 int amdgpu_vram_limit = 0; 82 int amdgpu_vis_vram_limit = 0; 83 int amdgpu_gart_size = -1; /* auto */ 84 int amdgpu_gtt_size = -1; /* auto */ 85 int amdgpu_moverate = -1; /* auto */ 86 int amdgpu_benchmarking = 0; 87 int amdgpu_testing = 0; 88 int amdgpu_audio = -1; 89 int amdgpu_disp_priority = 0; 90 int amdgpu_hw_i2c = 0; 91 int amdgpu_pcie_gen2 = -1; 92 int amdgpu_msi = -1; 93 int amdgpu_lockup_timeout = 10000; 94 int amdgpu_dpm = -1; 95 int amdgpu_fw_load_type = -1; 96 int amdgpu_aspm = -1; 97 int amdgpu_runtime_pm = -1; 98 uint amdgpu_ip_block_mask = 0xffffffff; 99 int amdgpu_bapm = -1; 100 int amdgpu_deep_color = 0; 101 int amdgpu_vm_size = -1; 102 int amdgpu_vm_fragment_size = -1; 103 int amdgpu_vm_block_size = -1; 104 int amdgpu_vm_fault_stop = 0; 105 int amdgpu_vm_debug = 0; 106 int amdgpu_vram_page_split = 512; 107 int amdgpu_vm_update_mode = -1; 108 int amdgpu_exp_hw_support = 0; 109 int amdgpu_dc = -1; 110 int amdgpu_dc_log = 0; 111 int amdgpu_sched_jobs = 32; 112 int amdgpu_sched_hw_submission = 2; 113 int amdgpu_no_evict = 0; 114 int amdgpu_direct_gma_size = 0; 115 uint amdgpu_pcie_gen_cap = 0; 116 uint amdgpu_pcie_lane_cap = 0; 117 uint amdgpu_cg_mask = 0xffffffff; 118 uint amdgpu_pg_mask = 0xffffffff; 119 uint amdgpu_sdma_phase_quantum = 32; 120 char *amdgpu_disable_cu = NULL; 121 char *amdgpu_virtual_display = NULL; 122 uint amdgpu_pp_feature_mask = 0xffffffff; 123 int amdgpu_ngg = 0; 124 int amdgpu_prim_buf_per_se = 0; 125 int amdgpu_pos_buf_per_se = 0; 126 int amdgpu_cntl_sb_buf_per_se = 0; 127 int amdgpu_param_buf_per_se = 0; 128 int amdgpu_job_hang_limit = 0; 129 int amdgpu_lbpw = -1; 130 int amdgpu_compute_multipipe = -1; 131 int amdgpu_gpu_recovery = -1; /* auto */ 132 133 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 134 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 135 136 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 137 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 138 139 MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)"); 140 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 141 142 MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)"); 143 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 144 145 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 146 module_param_named(moverate, amdgpu_moverate, int, 0600); 147 148 MODULE_PARM_DESC(benchmark, "Run benchmark"); 149 module_param_named(benchmark, amdgpu_benchmarking, int, 0444); 150 151 MODULE_PARM_DESC(test, "Run tests"); 152 module_param_named(test, amdgpu_testing, int, 0444); 153 154 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 155 module_param_named(audio, amdgpu_audio, int, 0444); 156 157 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 158 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 159 160 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 161 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 162 163 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 164 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 165 166 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 167 module_param_named(msi, amdgpu_msi, int, 0444); 168 169 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms > 0 (default 10000)"); 170 module_param_named(lockup_timeout, amdgpu_lockup_timeout, int, 0444); 171 172 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 173 module_param_named(dpm, amdgpu_dpm, int, 0444); 174 175 MODULE_PARM_DESC(fw_load_type, "firmware loading type (0 = direct, 1 = SMU, 2 = PSP, -1 = auto)"); 176 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 177 178 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 179 module_param_named(aspm, amdgpu_aspm, int, 0444); 180 181 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)"); 182 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 183 184 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 185 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 186 187 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 188 module_param_named(bapm, amdgpu_bapm, int, 0444); 189 190 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 191 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 192 193 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 194 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 195 196 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 197 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 198 199 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 200 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 201 202 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 203 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 204 205 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); 206 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); 207 208 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 209 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 210 211 MODULE_PARM_DESC(vram_page_split, "Number of pages after we split VRAM allocations (default 512, -1 = disable)"); 212 module_param_named(vram_page_split, amdgpu_vram_page_split, int, 0444); 213 214 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 215 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 216 217 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 218 module_param_named(dc, amdgpu_dc, int, 0444); 219 220 MODULE_PARM_DESC(dc_log, "Display Core Log Level (0 = minimal (default), 1 = chatty"); 221 module_param_named(dc_log, amdgpu_dc_log, int, 0444); 222 223 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 224 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 225 226 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 227 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 228 229 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 230 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, uint, 0444); 231 232 MODULE_PARM_DESC(no_evict, "Support pinning request from user space (1 = enable, 0 = disable (default))"); 233 module_param_named(no_evict, amdgpu_no_evict, int, 0444); 234 235 MODULE_PARM_DESC(direct_gma_size, "Direct GMA size in megabytes (max 96MB)"); 236 module_param_named(direct_gma_size, amdgpu_direct_gma_size, int, 0444); 237 238 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 239 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 240 241 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 242 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 243 244 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 245 module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444); 246 247 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 248 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 249 250 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 251 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 252 253 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 254 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 255 256 MODULE_PARM_DESC(virtual_display, 257 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 258 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 259 260 MODULE_PARM_DESC(ngg, "Next Generation Graphics (1 = enable, 0 = disable(default depending on gfx))"); 261 module_param_named(ngg, amdgpu_ngg, int, 0444); 262 263 MODULE_PARM_DESC(prim_buf_per_se, "the size of Primitive Buffer per Shader Engine (default depending on gfx)"); 264 module_param_named(prim_buf_per_se, amdgpu_prim_buf_per_se, int, 0444); 265 266 MODULE_PARM_DESC(pos_buf_per_se, "the size of Position Buffer per Shader Engine (default depending on gfx)"); 267 module_param_named(pos_buf_per_se, amdgpu_pos_buf_per_se, int, 0444); 268 269 MODULE_PARM_DESC(cntl_sb_buf_per_se, "the size of Control Sideband per Shader Engine (default depending on gfx)"); 270 module_param_named(cntl_sb_buf_per_se, amdgpu_cntl_sb_buf_per_se, int, 0444); 271 272 MODULE_PARM_DESC(param_buf_per_se, "the size of Off-Chip Pramater Cache per Shader Engine (default depending on gfx)"); 273 module_param_named(param_buf_per_se, amdgpu_param_buf_per_se, int, 0444); 274 275 MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)"); 276 module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444); 277 278 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 279 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 280 281 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 282 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 283 284 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto"); 285 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 286 287 #ifdef CONFIG_DRM_AMDGPU_SI 288 289 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 290 int amdgpu_si_support = 0; 291 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 292 #else 293 int amdgpu_si_support = 1; 294 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 295 #endif 296 297 module_param_named(si_support, amdgpu_si_support, int, 0444); 298 #endif 299 300 #ifdef CONFIG_DRM_AMDGPU_CIK 301 302 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 303 int amdgpu_cik_support = 0; 304 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 305 #else 306 int amdgpu_cik_support = 1; 307 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 308 #endif 309 310 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 311 #endif 312 313 static const struct pci_device_id pciidlist[] = { 314 #ifdef CONFIG_DRM_AMDGPU_SI 315 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 316 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 317 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 318 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 319 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 320 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 321 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 322 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 323 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 324 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 325 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 326 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 327 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 328 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 329 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 330 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 331 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 332 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 333 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 334 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 335 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 336 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 337 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 338 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 339 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 340 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 341 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 342 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 343 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 344 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 345 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 346 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 347 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 348 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 349 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 350 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 351 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 352 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 353 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 354 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 355 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 356 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 357 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 358 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 359 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 360 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 361 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 362 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 363 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 364 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 365 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 366 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 367 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 368 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 369 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 370 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 371 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 372 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 373 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 374 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 375 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 376 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 377 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 378 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 379 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 380 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 381 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 382 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 383 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 384 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 385 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 386 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 387 #endif 388 #ifdef CONFIG_DRM_AMDGPU_CIK 389 /* Kaveri */ 390 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 391 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 392 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 393 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 394 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 395 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 396 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 397 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 398 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 399 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 400 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 401 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 402 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 403 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 404 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 405 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 406 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 407 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 408 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 409 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 410 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 411 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 412 /* Bonaire */ 413 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 414 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 415 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 416 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 417 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 418 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 419 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 420 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 421 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 422 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 423 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 424 /* Hawaii */ 425 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 426 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 427 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 428 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 429 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 430 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 431 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 432 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 433 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 434 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 435 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 436 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 437 /* Kabini */ 438 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 439 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 440 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 441 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 442 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 443 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 444 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 445 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 446 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 447 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 448 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 449 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 450 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 451 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 452 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 453 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 454 /* mullins */ 455 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 456 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 457 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 458 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 459 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 460 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 461 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 462 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 463 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 464 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 465 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 466 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 467 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 468 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 469 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 470 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 471 #endif 472 /* topaz */ 473 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 474 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 475 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 476 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 477 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 478 /* tonga */ 479 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 480 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 481 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 482 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 483 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 484 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 485 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 486 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 487 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 488 /* fiji */ 489 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 490 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 491 /* carrizo */ 492 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 493 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 494 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 495 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 496 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 497 /* stoney */ 498 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 499 /* Polaris11 */ 500 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 501 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 502 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 503 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 504 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 505 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 506 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 507 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 508 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 509 /* Polaris10 */ 510 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 511 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 512 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 513 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 514 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 515 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 516 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 517 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 518 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 519 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 520 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 521 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 522 /* Polaris12 */ 523 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 524 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 525 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 526 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 527 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 528 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 529 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 530 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 531 /* Vega 10 */ 532 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 533 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 534 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 535 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 536 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 537 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 538 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 539 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 540 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 541 /* Raven */ 542 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 543 544 {0, 0, 0} 545 }; 546 547 MODULE_DEVICE_TABLE(pci, pciidlist); 548 549 static struct drm_driver kms_driver; 550 551 static int amdgpu_kick_out_firmware_fb(struct pci_dev *pdev) 552 { 553 struct apertures_struct *ap; 554 bool primary = false; 555 556 ap = alloc_apertures(1); 557 if (!ap) 558 return -ENOMEM; 559 560 ap->ranges[0].base = pci_resource_start(pdev, 0); 561 ap->ranges[0].size = pci_resource_len(pdev, 0); 562 563 #ifdef CONFIG_X86 564 primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; 565 #endif 566 drm_fb_helper_remove_conflicting_framebuffers(ap, "amdgpudrmfb", primary); 567 kfree(ap); 568 569 return 0; 570 } 571 572 573 static int amdgpu_pci_probe(struct pci_dev *pdev, 574 const struct pci_device_id *ent) 575 { 576 struct drm_device *dev; 577 unsigned long flags = ent->driver_data; 578 int ret, retry = 0; 579 580 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 581 DRM_INFO("This hardware requires experimental hardware support.\n" 582 "See modparam exp_hw_support\n"); 583 return -ENODEV; 584 } 585 586 /* 587 * Initialize amdkfd before starting radeon. If it was not loaded yet, 588 * defer radeon probing 589 */ 590 ret = amdgpu_amdkfd_init(); 591 if (ret == -EPROBE_DEFER) 592 return ret; 593 594 /* Get rid of things like offb */ 595 ret = amdgpu_kick_out_firmware_fb(pdev); 596 if (ret) 597 return ret; 598 599 dev = drm_dev_alloc(&kms_driver, &pdev->dev); 600 if (IS_ERR(dev)) 601 return PTR_ERR(dev); 602 603 ret = pci_enable_device(pdev); 604 if (ret) 605 goto err_free; 606 607 dev->pdev = pdev; 608 609 pci_set_drvdata(pdev, dev); 610 611 retry_init: 612 ret = drm_dev_register(dev, ent->driver_data); 613 if (ret == -EAGAIN && ++retry <= 3) { 614 DRM_INFO("retry init %d\n", retry); 615 /* Don't request EX mode too frequently which is attacking */ 616 msleep(5000); 617 goto retry_init; 618 } else if (ret) 619 goto err_pci; 620 621 return 0; 622 623 err_pci: 624 pci_disable_device(pdev); 625 err_free: 626 drm_dev_unref(dev); 627 return ret; 628 } 629 630 static void 631 amdgpu_pci_remove(struct pci_dev *pdev) 632 { 633 struct drm_device *dev = pci_get_drvdata(pdev); 634 635 drm_dev_unregister(dev); 636 drm_dev_unref(dev); 637 pci_disable_device(pdev); 638 pci_set_drvdata(pdev, NULL); 639 } 640 641 static void 642 amdgpu_pci_shutdown(struct pci_dev *pdev) 643 { 644 struct drm_device *dev = pci_get_drvdata(pdev); 645 struct amdgpu_device *adev = dev->dev_private; 646 647 /* if we are running in a VM, make sure the device 648 * torn down properly on reboot/shutdown. 649 * unfortunately we can't detect certain 650 * hypervisors so just do this all the time. 651 */ 652 amdgpu_device_ip_suspend(adev); 653 } 654 655 static int amdgpu_pmops_suspend(struct device *dev) 656 { 657 struct pci_dev *pdev = to_pci_dev(dev); 658 659 struct drm_device *drm_dev = pci_get_drvdata(pdev); 660 return amdgpu_device_suspend(drm_dev, true, true); 661 } 662 663 static int amdgpu_pmops_resume(struct device *dev) 664 { 665 struct pci_dev *pdev = to_pci_dev(dev); 666 struct drm_device *drm_dev = pci_get_drvdata(pdev); 667 668 /* GPU comes up enabled by the bios on resume */ 669 if (amdgpu_device_is_px(drm_dev)) { 670 pm_runtime_disable(dev); 671 pm_runtime_set_active(dev); 672 pm_runtime_enable(dev); 673 } 674 675 return amdgpu_device_resume(drm_dev, true, true); 676 } 677 678 static int amdgpu_pmops_freeze(struct device *dev) 679 { 680 struct pci_dev *pdev = to_pci_dev(dev); 681 682 struct drm_device *drm_dev = pci_get_drvdata(pdev); 683 return amdgpu_device_suspend(drm_dev, false, true); 684 } 685 686 static int amdgpu_pmops_thaw(struct device *dev) 687 { 688 struct pci_dev *pdev = to_pci_dev(dev); 689 690 struct drm_device *drm_dev = pci_get_drvdata(pdev); 691 return amdgpu_device_resume(drm_dev, false, true); 692 } 693 694 static int amdgpu_pmops_poweroff(struct device *dev) 695 { 696 struct pci_dev *pdev = to_pci_dev(dev); 697 698 struct drm_device *drm_dev = pci_get_drvdata(pdev); 699 return amdgpu_device_suspend(drm_dev, true, true); 700 } 701 702 static int amdgpu_pmops_restore(struct device *dev) 703 { 704 struct pci_dev *pdev = to_pci_dev(dev); 705 706 struct drm_device *drm_dev = pci_get_drvdata(pdev); 707 return amdgpu_device_resume(drm_dev, false, true); 708 } 709 710 static int amdgpu_pmops_runtime_suspend(struct device *dev) 711 { 712 struct pci_dev *pdev = to_pci_dev(dev); 713 struct drm_device *drm_dev = pci_get_drvdata(pdev); 714 int ret; 715 716 if (!amdgpu_device_is_px(drm_dev)) { 717 pm_runtime_forbid(dev); 718 return -EBUSY; 719 } 720 721 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 722 drm_kms_helper_poll_disable(drm_dev); 723 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF); 724 725 ret = amdgpu_device_suspend(drm_dev, false, false); 726 pci_save_state(pdev); 727 pci_disable_device(pdev); 728 pci_ignore_hotplug(pdev); 729 if (amdgpu_is_atpx_hybrid()) 730 pci_set_power_state(pdev, PCI_D3cold); 731 else if (!amdgpu_has_atpx_dgpu_power_cntl()) 732 pci_set_power_state(pdev, PCI_D3hot); 733 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 734 735 return 0; 736 } 737 738 static int amdgpu_pmops_runtime_resume(struct device *dev) 739 { 740 struct pci_dev *pdev = to_pci_dev(dev); 741 struct drm_device *drm_dev = pci_get_drvdata(pdev); 742 int ret; 743 744 if (!amdgpu_device_is_px(drm_dev)) 745 return -EINVAL; 746 747 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 748 749 if (amdgpu_is_atpx_hybrid() || 750 !amdgpu_has_atpx_dgpu_power_cntl()) 751 pci_set_power_state(pdev, PCI_D0); 752 pci_restore_state(pdev); 753 ret = pci_enable_device(pdev); 754 if (ret) 755 return ret; 756 pci_set_master(pdev); 757 758 ret = amdgpu_device_resume(drm_dev, false, false); 759 drm_kms_helper_poll_enable(drm_dev); 760 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON); 761 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 762 return 0; 763 } 764 765 static int amdgpu_pmops_runtime_idle(struct device *dev) 766 { 767 struct pci_dev *pdev = to_pci_dev(dev); 768 struct drm_device *drm_dev = pci_get_drvdata(pdev); 769 struct drm_crtc *crtc; 770 771 if (!amdgpu_device_is_px(drm_dev)) { 772 pm_runtime_forbid(dev); 773 return -EBUSY; 774 } 775 776 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) { 777 if (crtc->enabled) { 778 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 779 return -EBUSY; 780 } 781 } 782 783 pm_runtime_mark_last_busy(dev); 784 pm_runtime_autosuspend(dev); 785 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 786 return 1; 787 } 788 789 long amdgpu_drm_ioctl(struct file *filp, 790 unsigned int cmd, unsigned long arg) 791 { 792 struct drm_file *file_priv = filp->private_data; 793 struct drm_device *dev; 794 long ret; 795 dev = file_priv->minor->dev; 796 ret = pm_runtime_get_sync(dev->dev); 797 if (ret < 0) 798 return ret; 799 800 ret = drm_ioctl(filp, cmd, arg); 801 802 pm_runtime_mark_last_busy(dev->dev); 803 pm_runtime_put_autosuspend(dev->dev); 804 return ret; 805 } 806 807 static const struct dev_pm_ops amdgpu_pm_ops = { 808 .suspend = amdgpu_pmops_suspend, 809 .resume = amdgpu_pmops_resume, 810 .freeze = amdgpu_pmops_freeze, 811 .thaw = amdgpu_pmops_thaw, 812 .poweroff = amdgpu_pmops_poweroff, 813 .restore = amdgpu_pmops_restore, 814 .runtime_suspend = amdgpu_pmops_runtime_suspend, 815 .runtime_resume = amdgpu_pmops_runtime_resume, 816 .runtime_idle = amdgpu_pmops_runtime_idle, 817 }; 818 819 static const struct file_operations amdgpu_driver_kms_fops = { 820 .owner = THIS_MODULE, 821 .open = drm_open, 822 .release = drm_release, 823 .unlocked_ioctl = amdgpu_drm_ioctl, 824 .mmap = amdgpu_mmap, 825 .poll = drm_poll, 826 .read = drm_read, 827 #ifdef CONFIG_COMPAT 828 .compat_ioctl = amdgpu_kms_compat_ioctl, 829 #endif 830 }; 831 832 static bool 833 amdgpu_get_crtc_scanout_position(struct drm_device *dev, unsigned int pipe, 834 bool in_vblank_irq, int *vpos, int *hpos, 835 ktime_t *stime, ktime_t *etime, 836 const struct drm_display_mode *mode) 837 { 838 return amdgpu_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos, 839 stime, etime, mode); 840 } 841 842 static struct drm_driver kms_driver = { 843 .driver_features = 844 DRIVER_USE_AGP | 845 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | 846 DRIVER_PRIME | DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ, 847 .load = amdgpu_driver_load_kms, 848 .open = amdgpu_driver_open_kms, 849 .postclose = amdgpu_driver_postclose_kms, 850 .lastclose = amdgpu_driver_lastclose_kms, 851 .unload = amdgpu_driver_unload_kms, 852 .get_vblank_counter = amdgpu_get_vblank_counter_kms, 853 .enable_vblank = amdgpu_enable_vblank_kms, 854 .disable_vblank = amdgpu_disable_vblank_kms, 855 .get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos, 856 .get_scanout_position = amdgpu_get_crtc_scanout_position, 857 .irq_preinstall = amdgpu_irq_preinstall, 858 .irq_postinstall = amdgpu_irq_postinstall, 859 .irq_uninstall = amdgpu_irq_uninstall, 860 .irq_handler = amdgpu_irq_handler, 861 .ioctls = amdgpu_ioctls_kms, 862 .gem_free_object_unlocked = amdgpu_gem_object_free, 863 .gem_open_object = amdgpu_gem_object_open, 864 .gem_close_object = amdgpu_gem_object_close, 865 .dumb_create = amdgpu_mode_dumb_create, 866 .dumb_map_offset = amdgpu_mode_dumb_mmap, 867 .fops = &amdgpu_driver_kms_fops, 868 869 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 870 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 871 .gem_prime_export = amdgpu_gem_prime_export, 872 .gem_prime_import = drm_gem_prime_import, 873 .gem_prime_pin = amdgpu_gem_prime_pin, 874 .gem_prime_unpin = amdgpu_gem_prime_unpin, 875 .gem_prime_res_obj = amdgpu_gem_prime_res_obj, 876 .gem_prime_get_sg_table = amdgpu_gem_prime_get_sg_table, 877 .gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table, 878 .gem_prime_vmap = amdgpu_gem_prime_vmap, 879 .gem_prime_vunmap = amdgpu_gem_prime_vunmap, 880 .gem_prime_mmap = amdgpu_gem_prime_mmap, 881 882 .name = DRIVER_NAME, 883 .desc = DRIVER_DESC, 884 .date = DRIVER_DATE, 885 .major = KMS_DRIVER_MAJOR, 886 .minor = KMS_DRIVER_MINOR, 887 .patchlevel = KMS_DRIVER_PATCHLEVEL, 888 }; 889 890 static struct drm_driver *driver; 891 static struct pci_driver *pdriver; 892 893 static struct pci_driver amdgpu_kms_pci_driver = { 894 .name = DRIVER_NAME, 895 .id_table = pciidlist, 896 .probe = amdgpu_pci_probe, 897 .remove = amdgpu_pci_remove, 898 .shutdown = amdgpu_pci_shutdown, 899 .driver.pm = &amdgpu_pm_ops, 900 }; 901 902 903 904 static int __init amdgpu_init(void) 905 { 906 int r; 907 908 r = amdgpu_sync_init(); 909 if (r) 910 goto error_sync; 911 912 r = amdgpu_fence_slab_init(); 913 if (r) 914 goto error_fence; 915 916 if (vgacon_text_force()) { 917 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n"); 918 return -EINVAL; 919 } 920 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 921 driver = &kms_driver; 922 pdriver = &amdgpu_kms_pci_driver; 923 driver->num_ioctls = amdgpu_max_kms_ioctl; 924 amdgpu_register_atpx_handler(); 925 /* let modprobe override vga console setting */ 926 return pci_register_driver(pdriver); 927 928 error_fence: 929 amdgpu_sync_fini(); 930 931 error_sync: 932 return r; 933 } 934 935 static void __exit amdgpu_exit(void) 936 { 937 amdgpu_amdkfd_fini(); 938 pci_unregister_driver(pdriver); 939 amdgpu_unregister_atpx_handler(); 940 amdgpu_sync_fini(); 941 amdgpu_fence_slab_fini(); 942 } 943 944 module_init(amdgpu_init); 945 module_exit(amdgpu_exit); 946 947 MODULE_AUTHOR(DRIVER_AUTHOR); 948 MODULE_DESCRIPTION(DRIVER_DESC); 949 MODULE_LICENSE("GPL and additional rights"); 950