xref: /openbmc/linux/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts (revision b240b419db5d624ce7a5a397d6f62a1a686009ec) 
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * dts file for Xilinx ZynqMP ZCU111
4 *
5 * (C) Copyright 2017 - 2018, Xilinx, Inc.
6 *
7 * Michal Simek <michal.simek@xilinx.com>
8 */
9
10/dts-v1/;
11
12#include "zynqmp.dtsi"
13#include "zynqmp-clk.dtsi"
14#include <dt-bindings/input/input.h>
15#include <dt-bindings/gpio/gpio.h>
16
17/ {
18	model = "ZynqMP ZCU111 RevA";
19	compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp";
20
21	aliases {
22		ethernet0 = &gem3;
23		i2c0 = &i2c0;
24		i2c1 = &i2c1;
25		mmc0 = &sdhci1;
26		rtc0 = &rtc;
27		serial0 = &uart0;
28		serial1 = &dcc;
29	};
30
31	chosen {
32		bootargs = "earlycon";
33		stdout-path = "serial0:115200n8";
34	};
35
36	memory@0 {
37		device_type = "memory";
38		reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
39		/* Another 4GB connected to PL */
40	};
41
42	gpio-keys {
43		compatible = "gpio-keys";
44		#address-cells = <1>;
45		#size-cells = <0>;
46		autorepeat;
47		sw19 {
48			label = "sw19";
49			gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
50			linux,code = <KEY_DOWN>;
51			gpio-key,wakeup;
52			autorepeat;
53		};
54	};
55
56	leds {
57		compatible = "gpio-leds";
58		heartbeat_led {
59			label = "heartbeat";
60			gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
61			linux,default-trigger = "heartbeat";
62		};
63	};
64};
65
66&dcc {
67	status = "okay";
68};
69
70&fpd_dma_chan1 {
71	status = "okay";
72};
73
74&fpd_dma_chan2 {
75	status = "okay";
76};
77
78&fpd_dma_chan3 {
79	status = "okay";
80};
81
82&fpd_dma_chan4 {
83	status = "okay";
84};
85
86&fpd_dma_chan5 {
87	status = "okay";
88};
89
90&fpd_dma_chan6 {
91	status = "okay";
92};
93
94&fpd_dma_chan7 {
95	status = "okay";
96};
97
98&fpd_dma_chan8 {
99	status = "okay";
100};
101
102&gem3 {
103	status = "okay";
104	phy-handle = <&phy0>;
105	phy-mode = "rgmii-id";
106	phy0: phy@c {
107		reg = <0xc>;
108		ti,rx-internal-delay = <0x8>;
109		ti,tx-internal-delay = <0xa>;
110		ti,fifo-depth = <0x1>;
111	};
112};
113
114&gpio {
115	status = "okay";
116};
117
118&i2c0 {
119	status = "okay";
120	clock-frequency = <400000>;
121
122	tca6416_u22: gpio@20 {
123		compatible = "ti,tca6416";
124		reg = <0x20>;
125		gpio-controller; /* interrupt not connected */
126		#gpio-cells = <2>;
127		/*
128		 * IRQ not connected
129		 * Lines:
130		 * 0 - MAX6643_OT_B
131		 * 1 - MAX6643_FANFAIL_B
132		 * 2 - MIO26_PMU_INPUT_LS
133		 * 4 - SFP_SI5382_INT_ALM
134		 * 5 - IIC_MUX_RESET_B
135		 * 6 - GEM3_EXP_RESET_B
136		 * 10 - FMCP_HSPC_PRSNT_M2C_B
137		 * 11 - CLK_SPI_MUX_SEL0
138		 * 12 - CLK_SPI_MUX_SEL1
139		 * 16 - IRPS5401_ALERT_B
140		 * 17 - INA226_PMBUS_ALERT
141		 * 3, 7, 13-15 - not connected
142		 */
143	};
144
145	i2c-mux@75 { /* u23 */
146		compatible = "nxp,pca9544";
147		#address-cells = <1>;
148		#size-cells = <0>;
149		reg = <0x75>;
150		i2c@0 {
151			#address-cells = <1>;
152			#size-cells = <0>;
153			reg = <0>;
154			/* PS_PMBUS */
155			/* PMBUS_ALERT done via pca9544 */
156			ina226@40 { /* u67 */
157				compatible = "ti,ina226";
158				reg = <0x40>;
159				shunt-resistor = <2000>;
160			};
161			ina226@41 { /* u59 */
162				compatible = "ti,ina226";
163				reg = <0x41>;
164				shunt-resistor = <5000>;
165			};
166			ina226@42 { /* u61 */
167				compatible = "ti,ina226";
168				reg = <0x42>;
169				shunt-resistor = <5000>;
170			};
171			ina226@43 { /* u60 */
172				compatible = "ti,ina226";
173				reg = <0x43>;
174				shunt-resistor = <5000>;
175			};
176			ina226@45 { /* u64 */
177				compatible = "ti,ina226";
178				reg = <0x45>;
179				shunt-resistor = <5000>;
180			};
181			ina226@46 { /* u69 */
182				compatible = "ti,ina226";
183				reg = <0x46>;
184				shunt-resistor = <2000>;
185			};
186			ina226@47 { /* u66 */
187				compatible = "ti,ina226";
188				reg = <0x47>;
189				shunt-resistor = <5000>;
190			};
191			ina226@48 { /* u65 */
192				compatible = "ti,ina226";
193				reg = <0x48>;
194				shunt-resistor = <5000>;
195			};
196			ina226@49 { /* u63 */
197				compatible = "ti,ina226";
198				reg = <0x49>;
199				shunt-resistor = <5000>;
200			};
201			ina226@4a { /* u3 */
202				compatible = "ti,ina226";
203				reg = <0x4a>;
204				shunt-resistor = <5000>;
205			};
206			ina226@4b { /* u71 */
207				compatible = "ti,ina226";
208				reg = <0x4b>;
209				shunt-resistor = <5000>;
210			};
211			ina226@4c { /* u77 */
212				compatible = "ti,ina226";
213				reg = <0x4c>;
214				shunt-resistor = <5000>;
215			};
216			ina226@4d { /* u73 */
217				compatible = "ti,ina226";
218				reg = <0x4d>;
219				shunt-resistor = <5000>;
220			};
221			ina226@4e { /* u79 */
222				compatible = "ti,ina226";
223				reg = <0x4e>;
224				shunt-resistor = <5000>;
225			};
226		};
227		i2c@1 {
228			#address-cells = <1>;
229			#size-cells = <0>;
230			reg = <1>;
231			/* NC */
232		};
233		i2c@2 {
234			#address-cells = <1>;
235			#size-cells = <0>;
236			reg = <2>;
237			irps5401_43: irps54012@43 { /* IRPS5401 - u53 check these */
238				reg = <0x43>;
239			};
240			irps5401_44: irps54012@44 { /* IRPS5401 - u55 */
241				reg = <0x44>;
242			};
243			irps5401_45: irps54012@45 { /* IRPS5401 - u57 */
244				reg = <0x45>;
245			};
246			/* u68 IR38064 +0 */
247			/* u70 IR38060 +1 */
248			/* u74 IR38060 +2 */
249			/* u75 IR38060 +6 */
250			/* J19 header too */
251
252		};
253		i2c@3 {
254			#address-cells = <1>;
255			#size-cells = <0>;
256			reg = <3>;
257			/* SYSMON */
258		};
259	};
260};
261
262&i2c1 {
263	status = "okay";
264	clock-frequency = <400000>;
265
266	i2c-mux@74 { /* u26 */
267		compatible = "nxp,pca9548";
268		#address-cells = <1>;
269		#size-cells = <0>;
270		reg = <0x74>;
271		i2c@0 {
272			#address-cells = <1>;
273			#size-cells = <0>;
274			reg = <0>;
275			/*
276			 * IIC_EEPROM 1kB memory which uses 256B blocks
277			 * where every block has different address.
278			 *    0 - 256B address 0x54
279			 * 256B - 512B address 0x55
280			 * 512B - 768B address 0x56
281			 * 768B - 1024B address 0x57
282			 */
283			eeprom: eeprom@54 { /* u88 */
284				compatible = "atmel,24c08";
285				reg = <0x54>;
286			};
287		};
288		i2c@1 {
289			#address-cells = <1>;
290			#size-cells = <0>;
291			reg = <1>;
292			si5341: clock-generator@36 { /* SI5341 - u46 */
293				reg = <0x36>;
294			};
295
296		};
297		i2c@2 {
298			#address-cells = <1>;
299			#size-cells = <0>;
300			reg = <2>;
301			si570_1: clock-generator@5d { /* USER SI570 - u47 */
302				#clock-cells = <0>;
303				compatible = "silabs,si570";
304				reg = <0x5d>;
305				temperature-stability = <50>;
306				factory-fout = <300000000>;
307				clock-frequency = <300000000>;
308			};
309		};
310		i2c@3 {
311			#address-cells = <1>;
312			#size-cells = <0>;
313			reg = <3>;
314			si570_2: clock-generator@5d { /* USER MGT SI570 - u49 */
315				#clock-cells = <0>;
316				compatible = "silabs,si570";
317				reg = <0x5d>;
318				temperature-stability = <50>;
319				factory-fout = <156250000>;
320				clock-frequency = <148500000>;
321			};
322		};
323		i2c@4 {
324			#address-cells = <1>;
325			#size-cells = <0>;
326			reg = <4>;
327			si5328: clock-generator@69 { /* SI5328 - u48 */
328				reg = <0x69>;
329			};
330		};
331		i2c@5 {
332			#address-cells = <1>;
333			#size-cells = <0>;
334			reg = <5>;
335				sc18is603@2f { /* sc18is602 - u93 */
336					compatible = "nxp,sc18is603";
337					reg = <0x2f>;
338					/* 4 gpios for CS not handled by driver */
339					/*
340					 * USB2ANY cable or
341					 * LMK04208 - u90 or
342					 * LMX2594 - u102 or
343					 * LMX2594 - u103 or
344					 * LMX2594 - u104
345					 */
346				};
347		};
348		i2c@6 {
349			#address-cells = <1>;
350			#size-cells = <0>;
351			reg = <6>;
352			/* FMC connector */
353		};
354		/* 7 NC */
355	};
356
357	i2c-mux@75 {
358		compatible = "nxp,pca9548"; /* u27 */
359		#address-cells = <1>;
360		#size-cells = <0>;
361		reg = <0x75>;
362
363		i2c@0 {
364			#address-cells = <1>;
365			#size-cells = <0>;
366			reg = <0>;
367			/* FMCP_HSPC_IIC */
368		};
369		i2c@1 {
370			#address-cells = <1>;
371			#size-cells = <0>;
372			reg = <1>;
373			/* NC */
374		};
375		i2c@2 {
376			#address-cells = <1>;
377			#size-cells = <0>;
378			reg = <2>;
379			/* SYSMON */
380		};
381		i2c@3 {
382			#address-cells = <1>;
383			#size-cells = <0>;
384			reg = <3>;
385			/* DDR4 SODIMM */
386		};
387		i2c@4 {
388			#address-cells = <1>;
389			#size-cells = <0>;
390			reg = <4>;
391			/* SFP3 */
392		};
393		i2c@5 {
394			#address-cells = <1>;
395			#size-cells = <0>;
396			reg = <5>;
397			/* SFP2 */
398		};
399		i2c@6 {
400			#address-cells = <1>;
401			#size-cells = <0>;
402			reg = <6>;
403			/* SFP1 */
404		};
405		i2c@7 {
406			#address-cells = <1>;
407			#size-cells = <0>;
408			reg = <7>;
409			/* SFP0 */
410		};
411	};
412};
413
414&rtc {
415	status = "okay";
416};
417
418&sata {
419	status = "okay";
420	/* SATA OOB timing settings */
421	ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
422	ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
423	ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
424	ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
425	ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
426	ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
427	ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
428	ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
429};
430
431/* SD1 with level shifter */
432&sdhci1 {
433	status = "okay";
434	no-1-8-v;
435};
436
437&uart0 {
438	status = "okay";
439};
440
441/* ULPI SMSC USB3320 */
442&usb0 {
443	status = "okay";
444};
445