1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <drm/drmP.h> 26 #include "amdgpu.h" 27 #include "amdgpu_ucode.h" 28 #include "amdgpu_trace.h" 29 30 #include "sdma0/sdma0_4_0_offset.h" 31 #include "sdma0/sdma0_4_0_sh_mask.h" 32 #include "sdma1/sdma1_4_0_offset.h" 33 #include "sdma1/sdma1_4_0_sh_mask.h" 34 #include "hdp/hdp_4_0_offset.h" 35 #include "sdma0/sdma0_4_1_default.h" 36 37 #include "soc15_common.h" 38 #include "soc15.h" 39 #include "vega10_sdma_pkt_open.h" 40 41 MODULE_FIRMWARE("amdgpu/vega10_sdma.bin"); 42 MODULE_FIRMWARE("amdgpu/vega10_sdma1.bin"); 43 MODULE_FIRMWARE("amdgpu/vega12_sdma.bin"); 44 MODULE_FIRMWARE("amdgpu/vega12_sdma1.bin"); 45 MODULE_FIRMWARE("amdgpu/raven_sdma.bin"); 46 47 #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L 48 #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L 49 50 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev); 51 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev); 52 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev); 53 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev); 54 55 static const struct soc15_reg_golden golden_settings_sdma_4[] = { 56 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 57 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xff000ff0, 0x3f000100), 58 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0100, 0x00000100), 59 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 60 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_IB_CNTL, 0x800f0100, 0x00000100), 61 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 62 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003ff006, 0x0003c000), 63 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0100, 0x00000100), 64 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 65 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0100, 0x00000100), 66 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 67 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), 68 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 69 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100), 70 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_IB_CNTL, 0x800f0100, 0x00000100), 71 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 72 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_IB_CNTL, 0x800f0100, 0x00000100), 73 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 74 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_POWER_CNTL, 0x003ff000, 0x0003c000), 75 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_IB_CNTL, 0x800f0100, 0x00000100), 76 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 77 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_IB_CNTL, 0x800f0100, 0x00000100), 78 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 79 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0) 80 }; 81 82 static const struct soc15_reg_golden golden_settings_sdma_vg10[] = { 83 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 84 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), 85 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 86 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002) 87 }; 88 89 static const struct soc15_reg_golden golden_settings_sdma_vg12[] = { 90 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104001), 91 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001), 92 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104001), 93 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001) 94 }; 95 96 static const struct soc15_reg_golden golden_settings_sdma_4_1[] = 97 { 98 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 99 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100), 100 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100), 101 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 102 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0xfc3fffff, 0x40000051), 103 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100), 104 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 105 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100), 106 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 107 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0) 108 }; 109 110 static const struct soc15_reg_golden golden_settings_sdma_rv1[] = 111 { 112 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002), 113 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002) 114 }; 115 116 static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev, 117 u32 instance, u32 offset) 118 { 119 return ( 0 == instance ? (adev->reg_offset[SDMA0_HWIP][0][0] + offset) : 120 (adev->reg_offset[SDMA1_HWIP][0][0] + offset)); 121 } 122 123 static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev) 124 { 125 switch (adev->asic_type) { 126 case CHIP_VEGA10: 127 soc15_program_register_sequence(adev, 128 golden_settings_sdma_4, 129 ARRAY_SIZE(golden_settings_sdma_4)); 130 soc15_program_register_sequence(adev, 131 golden_settings_sdma_vg10, 132 ARRAY_SIZE(golden_settings_sdma_vg10)); 133 break; 134 case CHIP_VEGA12: 135 soc15_program_register_sequence(adev, 136 golden_settings_sdma_4, 137 ARRAY_SIZE(golden_settings_sdma_4)); 138 soc15_program_register_sequence(adev, 139 golden_settings_sdma_vg12, 140 ARRAY_SIZE(golden_settings_sdma_vg12)); 141 break; 142 case CHIP_RAVEN: 143 soc15_program_register_sequence(adev, 144 golden_settings_sdma_4_1, 145 ARRAY_SIZE(golden_settings_sdma_4_1)); 146 soc15_program_register_sequence(adev, 147 golden_settings_sdma_rv1, 148 ARRAY_SIZE(golden_settings_sdma_rv1)); 149 break; 150 default: 151 break; 152 } 153 } 154 155 /** 156 * sdma_v4_0_init_microcode - load ucode images from disk 157 * 158 * @adev: amdgpu_device pointer 159 * 160 * Use the firmware interface to load the ucode images into 161 * the driver (not loaded into hw). 162 * Returns 0 on success, error on failure. 163 */ 164 165 // emulation only, won't work on real chip 166 // vega10 real chip need to use PSP to load firmware 167 static int sdma_v4_0_init_microcode(struct amdgpu_device *adev) 168 { 169 const char *chip_name; 170 char fw_name[30]; 171 int err = 0, i; 172 struct amdgpu_firmware_info *info = NULL; 173 const struct common_firmware_header *header = NULL; 174 const struct sdma_firmware_header_v1_0 *hdr; 175 176 DRM_DEBUG("\n"); 177 178 switch (adev->asic_type) { 179 case CHIP_VEGA10: 180 chip_name = "vega10"; 181 break; 182 case CHIP_VEGA12: 183 chip_name = "vega12"; 184 break; 185 case CHIP_RAVEN: 186 chip_name = "raven"; 187 break; 188 default: 189 BUG(); 190 } 191 192 for (i = 0; i < adev->sdma.num_instances; i++) { 193 if (i == 0) 194 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); 195 else 196 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name); 197 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); 198 if (err) 199 goto out; 200 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw); 201 if (err) 202 goto out; 203 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 204 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version); 205 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); 206 if (adev->sdma.instance[i].feature_version >= 20) 207 adev->sdma.instance[i].burst_nop = true; 208 DRM_DEBUG("psp_load == '%s'\n", 209 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false"); 210 211 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 212 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; 213 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; 214 info->fw = adev->sdma.instance[i].fw; 215 header = (const struct common_firmware_header *)info->fw->data; 216 adev->firmware.fw_size += 217 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 218 } 219 } 220 out: 221 if (err) { 222 DRM_ERROR("sdma_v4_0: Failed to load firmware \"%s\"\n", fw_name); 223 for (i = 0; i < adev->sdma.num_instances; i++) { 224 release_firmware(adev->sdma.instance[i].fw); 225 adev->sdma.instance[i].fw = NULL; 226 } 227 } 228 return err; 229 } 230 231 /** 232 * sdma_v4_0_ring_get_rptr - get the current read pointer 233 * 234 * @ring: amdgpu ring pointer 235 * 236 * Get the current rptr from the hardware (VEGA10+). 237 */ 238 static uint64_t sdma_v4_0_ring_get_rptr(struct amdgpu_ring *ring) 239 { 240 u64 *rptr; 241 242 /* XXX check if swapping is necessary on BE */ 243 rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]); 244 245 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr); 246 return ((*rptr) >> 2); 247 } 248 249 /** 250 * sdma_v4_0_ring_get_wptr - get the current write pointer 251 * 252 * @ring: amdgpu ring pointer 253 * 254 * Get the current wptr from the hardware (VEGA10+). 255 */ 256 static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring) 257 { 258 struct amdgpu_device *adev = ring->adev; 259 u64 wptr; 260 261 if (ring->use_doorbell) { 262 /* XXX check if swapping is necessary on BE */ 263 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); 264 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); 265 } else { 266 u32 lowbit, highbit; 267 int me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1; 268 269 lowbit = RREG32(sdma_v4_0_get_reg_offset(adev, me, mmSDMA0_GFX_RB_WPTR)) >> 2; 270 highbit = RREG32(sdma_v4_0_get_reg_offset(adev, me, mmSDMA0_GFX_RB_WPTR_HI)) >> 2; 271 272 DRM_DEBUG("wptr [%i]high== 0x%08x low==0x%08x\n", 273 me, highbit, lowbit); 274 wptr = highbit; 275 wptr = wptr << 32; 276 wptr |= lowbit; 277 } 278 279 return wptr >> 2; 280 } 281 282 /** 283 * sdma_v4_0_ring_set_wptr - commit the write pointer 284 * 285 * @ring: amdgpu ring pointer 286 * 287 * Write the wptr back to the hardware (VEGA10+). 288 */ 289 static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring) 290 { 291 struct amdgpu_device *adev = ring->adev; 292 293 DRM_DEBUG("Setting write pointer\n"); 294 if (ring->use_doorbell) { 295 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs]; 296 297 DRM_DEBUG("Using doorbell -- " 298 "wptr_offs == 0x%08x " 299 "lower_32_bits(ring->wptr) << 2 == 0x%08x " 300 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n", 301 ring->wptr_offs, 302 lower_32_bits(ring->wptr << 2), 303 upper_32_bits(ring->wptr << 2)); 304 /* XXX check if swapping is necessary on BE */ 305 WRITE_ONCE(*wb, (ring->wptr << 2)); 306 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 307 ring->doorbell_index, ring->wptr << 2); 308 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 309 } else { 310 int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1; 311 312 DRM_DEBUG("Not using doorbell -- " 313 "mmSDMA%i_GFX_RB_WPTR == 0x%08x " 314 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 315 me, 316 lower_32_bits(ring->wptr << 2), 317 me, 318 upper_32_bits(ring->wptr << 2)); 319 WREG32(sdma_v4_0_get_reg_offset(adev, me, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2)); 320 WREG32(sdma_v4_0_get_reg_offset(adev, me, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2)); 321 } 322 } 323 324 static void sdma_v4_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 325 { 326 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring); 327 int i; 328 329 for (i = 0; i < count; i++) 330 if (sdma && sdma->burst_nop && (i == 0)) 331 amdgpu_ring_write(ring, ring->funcs->nop | 332 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 333 else 334 amdgpu_ring_write(ring, ring->funcs->nop); 335 } 336 337 /** 338 * sdma_v4_0_ring_emit_ib - Schedule an IB on the DMA engine 339 * 340 * @ring: amdgpu ring pointer 341 * @ib: IB object to schedule 342 * 343 * Schedule an IB in the DMA ring (VEGA10). 344 */ 345 static void sdma_v4_0_ring_emit_ib(struct amdgpu_ring *ring, 346 struct amdgpu_ib *ib, 347 unsigned vmid, bool ctx_switch) 348 { 349 /* IB packet must end on a 8 DW boundary */ 350 sdma_v4_0_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8); 351 352 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 353 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 354 /* base must be 32 byte aligned */ 355 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 356 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 357 amdgpu_ring_write(ring, ib->length_dw); 358 amdgpu_ring_write(ring, 0); 359 amdgpu_ring_write(ring, 0); 360 361 } 362 363 /** 364 * sdma_v4_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 365 * 366 * @ring: amdgpu ring pointer 367 * 368 * Emit an hdp flush packet on the requested DMA ring. 369 */ 370 static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 371 { 372 struct amdgpu_device *adev = ring->adev; 373 u32 ref_and_mask = 0; 374 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg; 375 376 if (ring == &ring->adev->sdma.instance[0].ring) 377 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0; 378 else 379 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1; 380 381 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 382 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | 383 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 384 amdgpu_ring_write(ring, (adev->nbio_funcs->get_hdp_flush_done_offset(adev)) << 2); 385 amdgpu_ring_write(ring, (adev->nbio_funcs->get_hdp_flush_req_offset(adev)) << 2); 386 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 387 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 388 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 389 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 390 } 391 392 /** 393 * sdma_v4_0_ring_emit_fence - emit a fence on the DMA ring 394 * 395 * @ring: amdgpu ring pointer 396 * @fence: amdgpu fence object 397 * 398 * Add a DMA fence packet to the ring to write 399 * the fence seq number and DMA trap packet to generate 400 * an interrupt if needed (VEGA10). 401 */ 402 static void sdma_v4_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 403 unsigned flags) 404 { 405 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 406 /* write the fence */ 407 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 408 /* zero in first two bits */ 409 BUG_ON(addr & 0x3); 410 amdgpu_ring_write(ring, lower_32_bits(addr)); 411 amdgpu_ring_write(ring, upper_32_bits(addr)); 412 amdgpu_ring_write(ring, lower_32_bits(seq)); 413 414 /* optionally write high bits as well */ 415 if (write64bit) { 416 addr += 4; 417 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 418 /* zero in first two bits */ 419 BUG_ON(addr & 0x3); 420 amdgpu_ring_write(ring, lower_32_bits(addr)); 421 amdgpu_ring_write(ring, upper_32_bits(addr)); 422 amdgpu_ring_write(ring, upper_32_bits(seq)); 423 } 424 425 /* generate an interrupt */ 426 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 427 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 428 } 429 430 431 /** 432 * sdma_v4_0_gfx_stop - stop the gfx async dma engines 433 * 434 * @adev: amdgpu_device pointer 435 * 436 * Stop the gfx async dma ring buffers (VEGA10). 437 */ 438 static void sdma_v4_0_gfx_stop(struct amdgpu_device *adev) 439 { 440 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; 441 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; 442 u32 rb_cntl, ib_cntl; 443 int i; 444 445 if ((adev->mman.buffer_funcs_ring == sdma0) || 446 (adev->mman.buffer_funcs_ring == sdma1)) 447 amdgpu_ttm_set_buffer_funcs_status(adev, false); 448 449 for (i = 0; i < adev->sdma.num_instances; i++) { 450 rb_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); 451 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 452 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 453 ib_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); 454 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 455 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); 456 } 457 458 sdma0->ready = false; 459 sdma1->ready = false; 460 } 461 462 /** 463 * sdma_v4_0_rlc_stop - stop the compute async dma engines 464 * 465 * @adev: amdgpu_device pointer 466 * 467 * Stop the compute async dma queues (VEGA10). 468 */ 469 static void sdma_v4_0_rlc_stop(struct amdgpu_device *adev) 470 { 471 /* XXX todo */ 472 } 473 474 /** 475 * sdma_v_0_ctx_switch_enable - stop the async dma engines context switch 476 * 477 * @adev: amdgpu_device pointer 478 * @enable: enable/disable the DMA MEs context switch. 479 * 480 * Halt or unhalt the async dma engines context switch (VEGA10). 481 */ 482 static void sdma_v4_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 483 { 484 u32 f32_cntl, phase_quantum = 0; 485 int i; 486 487 if (amdgpu_sdma_phase_quantum) { 488 unsigned value = amdgpu_sdma_phase_quantum; 489 unsigned unit = 0; 490 491 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 492 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) { 493 value = (value + 1) >> 1; 494 unit++; 495 } 496 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 497 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) { 498 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 499 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT); 500 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 501 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT); 502 WARN_ONCE(1, 503 "clamping sdma_phase_quantum to %uK clock cycles\n", 504 value << unit); 505 } 506 phase_quantum = 507 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | 508 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT; 509 } 510 511 for (i = 0; i < adev->sdma.num_instances; i++) { 512 f32_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL)); 513 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 514 AUTO_CTXSW_ENABLE, enable ? 1 : 0); 515 if (enable && amdgpu_sdma_phase_quantum) { 516 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM), 517 phase_quantum); 518 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM), 519 phase_quantum); 520 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM), 521 phase_quantum); 522 } 523 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl); 524 } 525 526 } 527 528 /** 529 * sdma_v4_0_enable - stop the async dma engines 530 * 531 * @adev: amdgpu_device pointer 532 * @enable: enable/disable the DMA MEs. 533 * 534 * Halt or unhalt the async dma engines (VEGA10). 535 */ 536 static void sdma_v4_0_enable(struct amdgpu_device *adev, bool enable) 537 { 538 u32 f32_cntl; 539 int i; 540 541 if (enable == false) { 542 sdma_v4_0_gfx_stop(adev); 543 sdma_v4_0_rlc_stop(adev); 544 } 545 546 for (i = 0; i < adev->sdma.num_instances; i++) { 547 f32_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); 548 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); 549 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl); 550 } 551 } 552 553 /** 554 * sdma_v4_0_gfx_resume - setup and start the async dma engines 555 * 556 * @adev: amdgpu_device pointer 557 * 558 * Set up the gfx DMA ring buffers and enable them (VEGA10). 559 * Returns 0 for success, error for failure. 560 */ 561 static int sdma_v4_0_gfx_resume(struct amdgpu_device *adev) 562 { 563 struct amdgpu_ring *ring; 564 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 565 u32 rb_bufsz; 566 u32 wb_offset; 567 u32 doorbell; 568 u32 doorbell_offset; 569 u32 temp; 570 u64 wptr_gpu_addr; 571 int i, r; 572 573 for (i = 0; i < adev->sdma.num_instances; i++) { 574 ring = &adev->sdma.instance[i].ring; 575 wb_offset = (ring->rptr_offs * 4); 576 577 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); 578 579 /* Set ring buffer size in dwords */ 580 rb_bufsz = order_base_2(ring->ring_size / 4); 581 rb_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); 582 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 583 #ifdef __BIG_ENDIAN 584 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 585 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 586 RPTR_WRITEBACK_SWAP_ENABLE, 1); 587 #endif 588 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 589 590 /* Initialize the ring buffer's read and write pointers */ 591 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0); 592 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0); 593 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0); 594 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0); 595 596 /* set the wb address whether it's enabled or not */ 597 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI), 598 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 599 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO), 600 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 601 602 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 603 604 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8); 605 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40); 606 607 ring->wptr = 0; 608 609 /* before programing wptr to a less value, need set minor_ptr_update first */ 610 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1); 611 612 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ 613 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2); 614 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2); 615 } 616 617 doorbell = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL)); 618 doorbell_offset = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET)); 619 620 if (ring->use_doorbell) { 621 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1); 622 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET, 623 OFFSET, ring->doorbell_index); 624 } else { 625 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0); 626 } 627 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell); 628 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset); 629 adev->nbio_funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, 630 ring->doorbell_index); 631 632 if (amdgpu_sriov_vf(adev)) 633 sdma_v4_0_ring_set_wptr(ring); 634 635 /* set minor_ptr_update to 0 after wptr programed */ 636 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0); 637 638 /* set utc l1 enable flag always to 1 */ 639 temp = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL)); 640 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1); 641 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp); 642 643 if (!amdgpu_sriov_vf(adev)) { 644 /* unhalt engine */ 645 temp = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); 646 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); 647 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp); 648 } 649 650 /* setup the wptr shadow polling */ 651 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 652 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO), 653 lower_32_bits(wptr_gpu_addr)); 654 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI), 655 upper_32_bits(wptr_gpu_addr)); 656 wptr_poll_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL)); 657 if (amdgpu_sriov_vf(adev)) 658 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 1); 659 else 660 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 0); 661 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), wptr_poll_cntl); 662 663 /* enable DMA RB */ 664 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 665 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 666 667 ib_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); 668 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 669 #ifdef __BIG_ENDIAN 670 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 671 #endif 672 /* enable DMA IBs */ 673 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); 674 675 ring->ready = true; 676 677 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */ 678 sdma_v4_0_ctx_switch_enable(adev, true); 679 sdma_v4_0_enable(adev, true); 680 } 681 682 r = amdgpu_ring_test_ring(ring); 683 if (r) { 684 ring->ready = false; 685 return r; 686 } 687 688 if (adev->mman.buffer_funcs_ring == ring) 689 amdgpu_ttm_set_buffer_funcs_status(adev, true); 690 691 } 692 693 return 0; 694 } 695 696 static void 697 sdma_v4_1_update_power_gating(struct amdgpu_device *adev, bool enable) 698 { 699 uint32_t def, data; 700 701 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_SDMA)) { 702 /* disable idle interrupt */ 703 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 704 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 705 706 if (data != def) 707 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 708 } else { 709 /* disable idle interrupt */ 710 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 711 data &= ~SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 712 if (data != def) 713 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 714 } 715 } 716 717 static void sdma_v4_1_init_power_gating(struct amdgpu_device *adev) 718 { 719 uint32_t def, data; 720 721 /* Enable HW based PG. */ 722 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 723 data |= SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK; 724 if (data != def) 725 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 726 727 /* enable interrupt */ 728 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 729 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 730 if (data != def) 731 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 732 733 /* Configure hold time to filter in-valid power on/off request. Use default right now */ 734 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 735 data &= ~SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK; 736 data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK); 737 /* Configure switch time for hysteresis purpose. Use default right now */ 738 data &= ~SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK; 739 data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK); 740 if(data != def) 741 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 742 } 743 744 static void sdma_v4_0_init_pg(struct amdgpu_device *adev) 745 { 746 if (!(adev->pg_flags & AMD_PG_SUPPORT_SDMA)) 747 return; 748 749 switch (adev->asic_type) { 750 case CHIP_RAVEN: 751 sdma_v4_1_init_power_gating(adev); 752 sdma_v4_1_update_power_gating(adev, true); 753 break; 754 default: 755 break; 756 } 757 } 758 759 /** 760 * sdma_v4_0_rlc_resume - setup and start the async dma engines 761 * 762 * @adev: amdgpu_device pointer 763 * 764 * Set up the compute DMA queues and enable them (VEGA10). 765 * Returns 0 for success, error for failure. 766 */ 767 static int sdma_v4_0_rlc_resume(struct amdgpu_device *adev) 768 { 769 sdma_v4_0_init_pg(adev); 770 771 return 0; 772 } 773 774 /** 775 * sdma_v4_0_load_microcode - load the sDMA ME ucode 776 * 777 * @adev: amdgpu_device pointer 778 * 779 * Loads the sDMA0/1 ucode. 780 * Returns 0 for success, -EINVAL if the ucode is not available. 781 */ 782 static int sdma_v4_0_load_microcode(struct amdgpu_device *adev) 783 { 784 const struct sdma_firmware_header_v1_0 *hdr; 785 const __le32 *fw_data; 786 u32 fw_size; 787 int i, j; 788 789 /* halt the MEs */ 790 sdma_v4_0_enable(adev, false); 791 792 for (i = 0; i < adev->sdma.num_instances; i++) { 793 if (!adev->sdma.instance[i].fw) 794 return -EINVAL; 795 796 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 797 amdgpu_ucode_print_sdma_hdr(&hdr->header); 798 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 799 800 fw_data = (const __le32 *) 801 (adev->sdma.instance[i].fw->data + 802 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 803 804 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0); 805 806 for (j = 0; j < fw_size; j++) 807 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++)); 808 809 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version); 810 } 811 812 return 0; 813 } 814 815 /** 816 * sdma_v4_0_start - setup and start the async dma engines 817 * 818 * @adev: amdgpu_device pointer 819 * 820 * Set up the DMA engines and enable them (VEGA10). 821 * Returns 0 for success, error for failure. 822 */ 823 static int sdma_v4_0_start(struct amdgpu_device *adev) 824 { 825 int r = 0; 826 827 if (amdgpu_sriov_vf(adev)) { 828 sdma_v4_0_ctx_switch_enable(adev, false); 829 sdma_v4_0_enable(adev, false); 830 831 /* set RB registers */ 832 r = sdma_v4_0_gfx_resume(adev); 833 return r; 834 } 835 836 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 837 r = sdma_v4_0_load_microcode(adev); 838 if (r) 839 return r; 840 } 841 842 /* unhalt the MEs */ 843 sdma_v4_0_enable(adev, true); 844 /* enable sdma ring preemption */ 845 sdma_v4_0_ctx_switch_enable(adev, true); 846 847 /* start the gfx rings and rlc compute queues */ 848 r = sdma_v4_0_gfx_resume(adev); 849 if (r) 850 return r; 851 r = sdma_v4_0_rlc_resume(adev); 852 853 return r; 854 } 855 856 /** 857 * sdma_v4_0_ring_test_ring - simple async dma engine test 858 * 859 * @ring: amdgpu_ring structure holding ring information 860 * 861 * Test the DMA engine by writing using it to write an 862 * value to memory. (VEGA10). 863 * Returns 0 for success, error for failure. 864 */ 865 static int sdma_v4_0_ring_test_ring(struct amdgpu_ring *ring) 866 { 867 struct amdgpu_device *adev = ring->adev; 868 unsigned i; 869 unsigned index; 870 int r; 871 u32 tmp; 872 u64 gpu_addr; 873 874 r = amdgpu_device_wb_get(adev, &index); 875 if (r) { 876 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); 877 return r; 878 } 879 880 gpu_addr = adev->wb.gpu_addr + (index * 4); 881 tmp = 0xCAFEDEAD; 882 adev->wb.wb[index] = cpu_to_le32(tmp); 883 884 r = amdgpu_ring_alloc(ring, 5); 885 if (r) { 886 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); 887 amdgpu_device_wb_free(adev, index); 888 return r; 889 } 890 891 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 892 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 893 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 894 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 895 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 896 amdgpu_ring_write(ring, 0xDEADBEEF); 897 amdgpu_ring_commit(ring); 898 899 for (i = 0; i < adev->usec_timeout; i++) { 900 tmp = le32_to_cpu(adev->wb.wb[index]); 901 if (tmp == 0xDEADBEEF) 902 break; 903 DRM_UDELAY(1); 904 } 905 906 if (i < adev->usec_timeout) { 907 DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i); 908 } else { 909 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", 910 ring->idx, tmp); 911 r = -EINVAL; 912 } 913 amdgpu_device_wb_free(adev, index); 914 915 return r; 916 } 917 918 /** 919 * sdma_v4_0_ring_test_ib - test an IB on the DMA engine 920 * 921 * @ring: amdgpu_ring structure holding ring information 922 * 923 * Test a simple IB in the DMA ring (VEGA10). 924 * Returns 0 on success, error on failure. 925 */ 926 static int sdma_v4_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 927 { 928 struct amdgpu_device *adev = ring->adev; 929 struct amdgpu_ib ib; 930 struct dma_fence *f = NULL; 931 unsigned index; 932 long r; 933 u32 tmp = 0; 934 u64 gpu_addr; 935 936 r = amdgpu_device_wb_get(adev, &index); 937 if (r) { 938 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); 939 return r; 940 } 941 942 gpu_addr = adev->wb.gpu_addr + (index * 4); 943 tmp = 0xCAFEDEAD; 944 adev->wb.wb[index] = cpu_to_le32(tmp); 945 memset(&ib, 0, sizeof(ib)); 946 r = amdgpu_ib_get(adev, NULL, 256, &ib); 947 if (r) { 948 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 949 goto err0; 950 } 951 952 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 953 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 954 ib.ptr[1] = lower_32_bits(gpu_addr); 955 ib.ptr[2] = upper_32_bits(gpu_addr); 956 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 957 ib.ptr[4] = 0xDEADBEEF; 958 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 959 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 960 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 961 ib.length_dw = 8; 962 963 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 964 if (r) 965 goto err1; 966 967 r = dma_fence_wait_timeout(f, false, timeout); 968 if (r == 0) { 969 DRM_ERROR("amdgpu: IB test timed out\n"); 970 r = -ETIMEDOUT; 971 goto err1; 972 } else if (r < 0) { 973 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 974 goto err1; 975 } 976 tmp = le32_to_cpu(adev->wb.wb[index]); 977 if (tmp == 0xDEADBEEF) { 978 DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx); 979 r = 0; 980 } else { 981 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp); 982 r = -EINVAL; 983 } 984 err1: 985 amdgpu_ib_free(adev, &ib, NULL); 986 dma_fence_put(f); 987 err0: 988 amdgpu_device_wb_free(adev, index); 989 return r; 990 } 991 992 993 /** 994 * sdma_v4_0_vm_copy_pte - update PTEs by copying them from the GART 995 * 996 * @ib: indirect buffer to fill with commands 997 * @pe: addr of the page entry 998 * @src: src addr to copy from 999 * @count: number of page entries to update 1000 * 1001 * Update PTEs by copying them from the GART using sDMA (VEGA10). 1002 */ 1003 static void sdma_v4_0_vm_copy_pte(struct amdgpu_ib *ib, 1004 uint64_t pe, uint64_t src, 1005 unsigned count) 1006 { 1007 unsigned bytes = count * 8; 1008 1009 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1010 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1011 ib->ptr[ib->length_dw++] = bytes - 1; 1012 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1013 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1014 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1015 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1016 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1017 1018 } 1019 1020 /** 1021 * sdma_v4_0_vm_write_pte - update PTEs by writing them manually 1022 * 1023 * @ib: indirect buffer to fill with commands 1024 * @pe: addr of the page entry 1025 * @addr: dst addr to write into pe 1026 * @count: number of page entries to update 1027 * @incr: increase next addr by incr bytes 1028 * @flags: access flags 1029 * 1030 * Update PTEs by writing them manually using sDMA (VEGA10). 1031 */ 1032 static void sdma_v4_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1033 uint64_t value, unsigned count, 1034 uint32_t incr) 1035 { 1036 unsigned ndw = count * 2; 1037 1038 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1039 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1040 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1041 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1042 ib->ptr[ib->length_dw++] = ndw - 1; 1043 for (; ndw > 0; ndw -= 2) { 1044 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1045 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1046 value += incr; 1047 } 1048 } 1049 1050 /** 1051 * sdma_v4_0_vm_set_pte_pde - update the page tables using sDMA 1052 * 1053 * @ib: indirect buffer to fill with commands 1054 * @pe: addr of the page entry 1055 * @addr: dst addr to write into pe 1056 * @count: number of page entries to update 1057 * @incr: increase next addr by incr bytes 1058 * @flags: access flags 1059 * 1060 * Update the page tables using sDMA (VEGA10). 1061 */ 1062 static void sdma_v4_0_vm_set_pte_pde(struct amdgpu_ib *ib, 1063 uint64_t pe, 1064 uint64_t addr, unsigned count, 1065 uint32_t incr, uint64_t flags) 1066 { 1067 /* for physically contiguous pages (vram) */ 1068 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE); 1069 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1070 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1071 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1072 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1073 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1074 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1075 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1076 ib->ptr[ib->length_dw++] = 0; 1077 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1078 } 1079 1080 /** 1081 * sdma_v4_0_ring_pad_ib - pad the IB to the required number of dw 1082 * 1083 * @ib: indirect buffer to fill with padding 1084 * 1085 */ 1086 static void sdma_v4_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1087 { 1088 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring); 1089 u32 pad_count; 1090 int i; 1091 1092 pad_count = (8 - (ib->length_dw & 0x7)) % 8; 1093 for (i = 0; i < pad_count; i++) 1094 if (sdma && sdma->burst_nop && (i == 0)) 1095 ib->ptr[ib->length_dw++] = 1096 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1097 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1098 else 1099 ib->ptr[ib->length_dw++] = 1100 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1101 } 1102 1103 1104 /** 1105 * sdma_v4_0_ring_emit_pipeline_sync - sync the pipeline 1106 * 1107 * @ring: amdgpu_ring pointer 1108 * 1109 * Make sure all previous operations are completed (CIK). 1110 */ 1111 static void sdma_v4_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1112 { 1113 uint32_t seq = ring->fence_drv.sync_seq; 1114 uint64_t addr = ring->fence_drv.gpu_addr; 1115 1116 /* wait for idle */ 1117 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1118 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1119 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 1120 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)); 1121 amdgpu_ring_write(ring, addr & 0xfffffffc); 1122 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 1123 amdgpu_ring_write(ring, seq); /* reference */ 1124 amdgpu_ring_write(ring, 0xffffffff); /* mask */ 1125 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1126 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ 1127 } 1128 1129 1130 /** 1131 * sdma_v4_0_ring_emit_vm_flush - vm flush using sDMA 1132 * 1133 * @ring: amdgpu_ring pointer 1134 * @vm: amdgpu_vm pointer 1135 * 1136 * Update the page table base and flush the VM TLB 1137 * using sDMA (VEGA10). 1138 */ 1139 static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1140 unsigned vmid, uint64_t pd_addr) 1141 { 1142 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1143 } 1144 1145 static void sdma_v4_0_ring_emit_wreg(struct amdgpu_ring *ring, 1146 uint32_t reg, uint32_t val) 1147 { 1148 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1149 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1150 amdgpu_ring_write(ring, reg); 1151 amdgpu_ring_write(ring, val); 1152 } 1153 1154 static void sdma_v4_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1155 uint32_t val, uint32_t mask) 1156 { 1157 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1158 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1159 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */ 1160 amdgpu_ring_write(ring, reg << 2); 1161 amdgpu_ring_write(ring, 0); 1162 amdgpu_ring_write(ring, val); /* reference */ 1163 amdgpu_ring_write(ring, mask); /* mask */ 1164 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1165 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); 1166 } 1167 1168 static int sdma_v4_0_early_init(void *handle) 1169 { 1170 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1171 1172 if (adev->asic_type == CHIP_RAVEN) 1173 adev->sdma.num_instances = 1; 1174 else 1175 adev->sdma.num_instances = 2; 1176 1177 sdma_v4_0_set_ring_funcs(adev); 1178 sdma_v4_0_set_buffer_funcs(adev); 1179 sdma_v4_0_set_vm_pte_funcs(adev); 1180 sdma_v4_0_set_irq_funcs(adev); 1181 1182 return 0; 1183 } 1184 1185 1186 static int sdma_v4_0_sw_init(void *handle) 1187 { 1188 struct amdgpu_ring *ring; 1189 int r, i; 1190 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1191 1192 /* SDMA trap event */ 1193 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0, 224, 1194 &adev->sdma.trap_irq); 1195 if (r) 1196 return r; 1197 1198 /* SDMA trap event */ 1199 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA1, 224, 1200 &adev->sdma.trap_irq); 1201 if (r) 1202 return r; 1203 1204 r = sdma_v4_0_init_microcode(adev); 1205 if (r) { 1206 DRM_ERROR("Failed to load sdma firmware!\n"); 1207 return r; 1208 } 1209 1210 for (i = 0; i < adev->sdma.num_instances; i++) { 1211 ring = &adev->sdma.instance[i].ring; 1212 ring->ring_obj = NULL; 1213 ring->use_doorbell = true; 1214 1215 DRM_INFO("use_doorbell being set to: [%s]\n", 1216 ring->use_doorbell?"true":"false"); 1217 1218 ring->doorbell_index = (i == 0) ? 1219 (AMDGPU_DOORBELL64_sDMA_ENGINE0 << 1) //get DWORD offset 1220 : (AMDGPU_DOORBELL64_sDMA_ENGINE1 << 1); // get DWORD offset 1221 1222 sprintf(ring->name, "sdma%d", i); 1223 r = amdgpu_ring_init(adev, ring, 1024, 1224 &adev->sdma.trap_irq, 1225 (i == 0) ? 1226 AMDGPU_SDMA_IRQ_TRAP0 : 1227 AMDGPU_SDMA_IRQ_TRAP1); 1228 if (r) 1229 return r; 1230 } 1231 1232 return r; 1233 } 1234 1235 static int sdma_v4_0_sw_fini(void *handle) 1236 { 1237 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1238 int i; 1239 1240 for (i = 0; i < adev->sdma.num_instances; i++) 1241 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1242 1243 for (i = 0; i < adev->sdma.num_instances; i++) { 1244 release_firmware(adev->sdma.instance[i].fw); 1245 adev->sdma.instance[i].fw = NULL; 1246 } 1247 1248 return 0; 1249 } 1250 1251 static int sdma_v4_0_hw_init(void *handle) 1252 { 1253 int r; 1254 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1255 1256 sdma_v4_0_init_golden_registers(adev); 1257 1258 r = sdma_v4_0_start(adev); 1259 1260 return r; 1261 } 1262 1263 static int sdma_v4_0_hw_fini(void *handle) 1264 { 1265 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1266 1267 if (amdgpu_sriov_vf(adev)) 1268 return 0; 1269 1270 sdma_v4_0_ctx_switch_enable(adev, false); 1271 sdma_v4_0_enable(adev, false); 1272 1273 return 0; 1274 } 1275 1276 static int sdma_v4_0_suspend(void *handle) 1277 { 1278 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1279 1280 return sdma_v4_0_hw_fini(adev); 1281 } 1282 1283 static int sdma_v4_0_resume(void *handle) 1284 { 1285 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1286 1287 return sdma_v4_0_hw_init(adev); 1288 } 1289 1290 static bool sdma_v4_0_is_idle(void *handle) 1291 { 1292 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1293 u32 i; 1294 1295 for (i = 0; i < adev->sdma.num_instances; i++) { 1296 u32 tmp = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_STATUS_REG)); 1297 1298 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) 1299 return false; 1300 } 1301 1302 return true; 1303 } 1304 1305 static int sdma_v4_0_wait_for_idle(void *handle) 1306 { 1307 unsigned i; 1308 u32 sdma0, sdma1; 1309 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1310 1311 for (i = 0; i < adev->usec_timeout; i++) { 1312 sdma0 = RREG32(sdma_v4_0_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG)); 1313 sdma1 = RREG32(sdma_v4_0_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG)); 1314 1315 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK) 1316 return 0; 1317 udelay(1); 1318 } 1319 return -ETIMEDOUT; 1320 } 1321 1322 static int sdma_v4_0_soft_reset(void *handle) 1323 { 1324 /* todo */ 1325 1326 return 0; 1327 } 1328 1329 static int sdma_v4_0_set_trap_irq_state(struct amdgpu_device *adev, 1330 struct amdgpu_irq_src *source, 1331 unsigned type, 1332 enum amdgpu_interrupt_state state) 1333 { 1334 u32 sdma_cntl; 1335 1336 u32 reg_offset = (type == AMDGPU_SDMA_IRQ_TRAP0) ? 1337 sdma_v4_0_get_reg_offset(adev, 0, mmSDMA0_CNTL) : 1338 sdma_v4_0_get_reg_offset(adev, 1, mmSDMA0_CNTL); 1339 1340 sdma_cntl = RREG32(reg_offset); 1341 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1342 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1343 WREG32(reg_offset, sdma_cntl); 1344 1345 return 0; 1346 } 1347 1348 static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev, 1349 struct amdgpu_irq_src *source, 1350 struct amdgpu_iv_entry *entry) 1351 { 1352 DRM_DEBUG("IH: SDMA trap\n"); 1353 switch (entry->client_id) { 1354 case SOC15_IH_CLIENTID_SDMA0: 1355 switch (entry->ring_id) { 1356 case 0: 1357 amdgpu_fence_process(&adev->sdma.instance[0].ring); 1358 break; 1359 case 1: 1360 /* XXX compute */ 1361 break; 1362 case 2: 1363 /* XXX compute */ 1364 break; 1365 case 3: 1366 /* XXX page queue*/ 1367 break; 1368 } 1369 break; 1370 case SOC15_IH_CLIENTID_SDMA1: 1371 switch (entry->ring_id) { 1372 case 0: 1373 amdgpu_fence_process(&adev->sdma.instance[1].ring); 1374 break; 1375 case 1: 1376 /* XXX compute */ 1377 break; 1378 case 2: 1379 /* XXX compute */ 1380 break; 1381 case 3: 1382 /* XXX page queue*/ 1383 break; 1384 } 1385 break; 1386 } 1387 return 0; 1388 } 1389 1390 static int sdma_v4_0_process_illegal_inst_irq(struct amdgpu_device *adev, 1391 struct amdgpu_irq_src *source, 1392 struct amdgpu_iv_entry *entry) 1393 { 1394 DRM_ERROR("Illegal instruction in SDMA command stream\n"); 1395 schedule_work(&adev->reset_work); 1396 return 0; 1397 } 1398 1399 1400 static void sdma_v4_0_update_medium_grain_clock_gating( 1401 struct amdgpu_device *adev, 1402 bool enable) 1403 { 1404 uint32_t data, def; 1405 1406 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { 1407 /* enable sdma0 clock gating */ 1408 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL)); 1409 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1410 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1411 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1412 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1413 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1414 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1415 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1416 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1417 if (def != data) 1418 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data); 1419 1420 if (adev->sdma.num_instances > 1) { 1421 def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL)); 1422 data &= ~(SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1423 SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1424 SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1425 SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1426 SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1427 SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1428 SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1429 SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1430 if (def != data) 1431 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), data); 1432 } 1433 } else { 1434 /* disable sdma0 clock gating */ 1435 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL)); 1436 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1437 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1438 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1439 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1440 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1441 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1442 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1443 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1444 1445 if (def != data) 1446 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data); 1447 1448 if (adev->sdma.num_instances > 1) { 1449 def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL)); 1450 data |= (SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1451 SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1452 SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1453 SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1454 SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1455 SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1456 SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1457 SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1458 if (def != data) 1459 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), data); 1460 } 1461 } 1462 } 1463 1464 1465 static void sdma_v4_0_update_medium_grain_light_sleep( 1466 struct amdgpu_device *adev, 1467 bool enable) 1468 { 1469 uint32_t data, def; 1470 1471 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { 1472 /* 1-not override: enable sdma0 mem light sleep */ 1473 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 1474 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1475 if (def != data) 1476 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 1477 1478 /* 1-not override: enable sdma1 mem light sleep */ 1479 if (adev->sdma.num_instances > 1) { 1480 def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL)); 1481 data |= SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1482 if (def != data) 1483 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), data); 1484 } 1485 } else { 1486 /* 0-override:disable sdma0 mem light sleep */ 1487 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 1488 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1489 if (def != data) 1490 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 1491 1492 /* 0-override:disable sdma1 mem light sleep */ 1493 if (adev->sdma.num_instances > 1) { 1494 def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL)); 1495 data &= ~SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1496 if (def != data) 1497 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), data); 1498 } 1499 } 1500 } 1501 1502 static int sdma_v4_0_set_clockgating_state(void *handle, 1503 enum amd_clockgating_state state) 1504 { 1505 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1506 1507 if (amdgpu_sriov_vf(adev)) 1508 return 0; 1509 1510 switch (adev->asic_type) { 1511 case CHIP_VEGA10: 1512 case CHIP_VEGA12: 1513 case CHIP_RAVEN: 1514 sdma_v4_0_update_medium_grain_clock_gating(adev, 1515 state == AMD_CG_STATE_GATE ? true : false); 1516 sdma_v4_0_update_medium_grain_light_sleep(adev, 1517 state == AMD_CG_STATE_GATE ? true : false); 1518 break; 1519 default: 1520 break; 1521 } 1522 return 0; 1523 } 1524 1525 static int sdma_v4_0_set_powergating_state(void *handle, 1526 enum amd_powergating_state state) 1527 { 1528 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1529 1530 switch (adev->asic_type) { 1531 case CHIP_RAVEN: 1532 sdma_v4_1_update_power_gating(adev, 1533 state == AMD_PG_STATE_GATE ? true : false); 1534 break; 1535 default: 1536 break; 1537 } 1538 1539 return 0; 1540 } 1541 1542 static void sdma_v4_0_get_clockgating_state(void *handle, u32 *flags) 1543 { 1544 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1545 int data; 1546 1547 if (amdgpu_sriov_vf(adev)) 1548 *flags = 0; 1549 1550 /* AMD_CG_SUPPORT_SDMA_MGCG */ 1551 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL)); 1552 if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK)) 1553 *flags |= AMD_CG_SUPPORT_SDMA_MGCG; 1554 1555 /* AMD_CG_SUPPORT_SDMA_LS */ 1556 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 1557 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 1558 *flags |= AMD_CG_SUPPORT_SDMA_LS; 1559 } 1560 1561 const struct amd_ip_funcs sdma_v4_0_ip_funcs = { 1562 .name = "sdma_v4_0", 1563 .early_init = sdma_v4_0_early_init, 1564 .late_init = NULL, 1565 .sw_init = sdma_v4_0_sw_init, 1566 .sw_fini = sdma_v4_0_sw_fini, 1567 .hw_init = sdma_v4_0_hw_init, 1568 .hw_fini = sdma_v4_0_hw_fini, 1569 .suspend = sdma_v4_0_suspend, 1570 .resume = sdma_v4_0_resume, 1571 .is_idle = sdma_v4_0_is_idle, 1572 .wait_for_idle = sdma_v4_0_wait_for_idle, 1573 .soft_reset = sdma_v4_0_soft_reset, 1574 .set_clockgating_state = sdma_v4_0_set_clockgating_state, 1575 .set_powergating_state = sdma_v4_0_set_powergating_state, 1576 .get_clockgating_state = sdma_v4_0_get_clockgating_state, 1577 }; 1578 1579 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = { 1580 .type = AMDGPU_RING_TYPE_SDMA, 1581 .align_mask = 0xf, 1582 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1583 .support_64bit_ptrs = true, 1584 .vmhub = AMDGPU_MMHUB, 1585 .get_rptr = sdma_v4_0_ring_get_rptr, 1586 .get_wptr = sdma_v4_0_ring_get_wptr, 1587 .set_wptr = sdma_v4_0_ring_set_wptr, 1588 .emit_frame_size = 1589 6 + /* sdma_v4_0_ring_emit_hdp_flush */ 1590 3 + /* hdp invalidate */ 1591 6 + /* sdma_v4_0_ring_emit_pipeline_sync */ 1592 /* sdma_v4_0_ring_emit_vm_flush */ 1593 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1594 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 1595 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */ 1596 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */ 1597 .emit_ib = sdma_v4_0_ring_emit_ib, 1598 .emit_fence = sdma_v4_0_ring_emit_fence, 1599 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync, 1600 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush, 1601 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush, 1602 .test_ring = sdma_v4_0_ring_test_ring, 1603 .test_ib = sdma_v4_0_ring_test_ib, 1604 .insert_nop = sdma_v4_0_ring_insert_nop, 1605 .pad_ib = sdma_v4_0_ring_pad_ib, 1606 .emit_wreg = sdma_v4_0_ring_emit_wreg, 1607 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait, 1608 }; 1609 1610 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev) 1611 { 1612 int i; 1613 1614 for (i = 0; i < adev->sdma.num_instances; i++) 1615 adev->sdma.instance[i].ring.funcs = &sdma_v4_0_ring_funcs; 1616 } 1617 1618 static const struct amdgpu_irq_src_funcs sdma_v4_0_trap_irq_funcs = { 1619 .set = sdma_v4_0_set_trap_irq_state, 1620 .process = sdma_v4_0_process_trap_irq, 1621 }; 1622 1623 static const struct amdgpu_irq_src_funcs sdma_v4_0_illegal_inst_irq_funcs = { 1624 .process = sdma_v4_0_process_illegal_inst_irq, 1625 }; 1626 1627 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev) 1628 { 1629 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; 1630 adev->sdma.trap_irq.funcs = &sdma_v4_0_trap_irq_funcs; 1631 adev->sdma.illegal_inst_irq.funcs = &sdma_v4_0_illegal_inst_irq_funcs; 1632 } 1633 1634 /** 1635 * sdma_v4_0_emit_copy_buffer - copy buffer using the sDMA engine 1636 * 1637 * @ring: amdgpu_ring structure holding ring information 1638 * @src_offset: src GPU address 1639 * @dst_offset: dst GPU address 1640 * @byte_count: number of bytes to xfer 1641 * 1642 * Copy GPU buffers using the DMA engine (VEGA10/12). 1643 * Used by the amdgpu ttm implementation to move pages if 1644 * registered as the asic copy callback. 1645 */ 1646 static void sdma_v4_0_emit_copy_buffer(struct amdgpu_ib *ib, 1647 uint64_t src_offset, 1648 uint64_t dst_offset, 1649 uint32_t byte_count) 1650 { 1651 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1652 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1653 ib->ptr[ib->length_dw++] = byte_count - 1; 1654 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1655 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1656 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1657 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1658 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1659 } 1660 1661 /** 1662 * sdma_v4_0_emit_fill_buffer - fill buffer using the sDMA engine 1663 * 1664 * @ring: amdgpu_ring structure holding ring information 1665 * @src_data: value to write to buffer 1666 * @dst_offset: dst GPU address 1667 * @byte_count: number of bytes to xfer 1668 * 1669 * Fill GPU buffers using the DMA engine (VEGA10/12). 1670 */ 1671 static void sdma_v4_0_emit_fill_buffer(struct amdgpu_ib *ib, 1672 uint32_t src_data, 1673 uint64_t dst_offset, 1674 uint32_t byte_count) 1675 { 1676 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 1677 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1678 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1679 ib->ptr[ib->length_dw++] = src_data; 1680 ib->ptr[ib->length_dw++] = byte_count - 1; 1681 } 1682 1683 static const struct amdgpu_buffer_funcs sdma_v4_0_buffer_funcs = { 1684 .copy_max_bytes = 0x400000, 1685 .copy_num_dw = 7, 1686 .emit_copy_buffer = sdma_v4_0_emit_copy_buffer, 1687 1688 .fill_max_bytes = 0x400000, 1689 .fill_num_dw = 5, 1690 .emit_fill_buffer = sdma_v4_0_emit_fill_buffer, 1691 }; 1692 1693 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev) 1694 { 1695 if (adev->mman.buffer_funcs == NULL) { 1696 adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs; 1697 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1698 } 1699 } 1700 1701 static const struct amdgpu_vm_pte_funcs sdma_v4_0_vm_pte_funcs = { 1702 .copy_pte_num_dw = 7, 1703 .copy_pte = sdma_v4_0_vm_copy_pte, 1704 1705 .write_pte = sdma_v4_0_vm_write_pte, 1706 .set_pte_pde = sdma_v4_0_vm_set_pte_pde, 1707 }; 1708 1709 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev) 1710 { 1711 unsigned i; 1712 1713 if (adev->vm_manager.vm_pte_funcs == NULL) { 1714 adev->vm_manager.vm_pte_funcs = &sdma_v4_0_vm_pte_funcs; 1715 for (i = 0; i < adev->sdma.num_instances; i++) 1716 adev->vm_manager.vm_pte_rings[i] = 1717 &adev->sdma.instance[i].ring; 1718 1719 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances; 1720 } 1721 } 1722 1723 const struct amdgpu_ip_block_version sdma_v4_0_ip_block = { 1724 .type = AMD_IP_BLOCK_TYPE_SDMA, 1725 .major = 4, 1726 .minor = 0, 1727 .rev = 0, 1728 .funcs = &sdma_v4_0_ip_funcs, 1729 }; 1730