1 /* 2 * Copyright (c) 2016-2017 Hisilicon Limited. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 */ 9 10 #include <linux/acpi.h> 11 #include <linux/device.h> 12 #include <linux/etherdevice.h> 13 #include <linux/init.h> 14 #include <linux/interrupt.h> 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/netdevice.h> 18 #include <linux/pci.h> 19 #include <linux/platform_device.h> 20 #include <linux/if_vlan.h> 21 #include <net/rtnetlink.h> 22 #include "hclge_cmd.h" 23 #include "hclge_dcb.h" 24 #include "hclge_main.h" 25 #include "hclge_mbx.h" 26 #include "hclge_mdio.h" 27 #include "hclge_tm.h" 28 #include "hnae3.h" 29 30 #define HCLGE_NAME "hclge" 31 #define HCLGE_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset)))) 32 #define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f)) 33 #define HCLGE_64BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_64_bit_stats, f)) 34 #define HCLGE_32BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_32_bit_stats, f)) 35 36 static int hclge_set_mta_filter_mode(struct hclge_dev *hdev, 37 enum hclge_mta_dmac_sel_type mta_mac_sel, 38 bool enable); 39 static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu); 40 static int hclge_init_vlan_config(struct hclge_dev *hdev); 41 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev); 42 static int hclge_update_led_status(struct hclge_dev *hdev); 43 44 static struct hnae3_ae_algo ae_algo; 45 46 static const struct pci_device_id ae_algo_pci_tbl[] = { 47 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0}, 48 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0}, 49 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0}, 50 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0}, 51 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0}, 52 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0}, 53 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0}, 54 /* required last entry */ 55 {0, } 56 }; 57 58 MODULE_DEVICE_TABLE(pci, ae_algo_pci_tbl); 59 60 static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = { 61 "Mac Loopback test", 62 "Serdes Loopback test", 63 "Phy Loopback test" 64 }; 65 66 static const struct hclge_comm_stats_str g_all_64bit_stats_string[] = { 67 {"igu_rx_oversize_pkt", 68 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_oversize_pkt)}, 69 {"igu_rx_undersize_pkt", 70 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_undersize_pkt)}, 71 {"igu_rx_out_all_pkt", 72 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_out_all_pkt)}, 73 {"igu_rx_uni_pkt", 74 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_uni_pkt)}, 75 {"igu_rx_multi_pkt", 76 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_multi_pkt)}, 77 {"igu_rx_broad_pkt", 78 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_broad_pkt)}, 79 {"egu_tx_out_all_pkt", 80 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_out_all_pkt)}, 81 {"egu_tx_uni_pkt", 82 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_uni_pkt)}, 83 {"egu_tx_multi_pkt", 84 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_multi_pkt)}, 85 {"egu_tx_broad_pkt", 86 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_broad_pkt)}, 87 {"ssu_ppp_mac_key_num", 88 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_mac_key_num)}, 89 {"ssu_ppp_host_key_num", 90 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_host_key_num)}, 91 {"ppp_ssu_mac_rlt_num", 92 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_mac_rlt_num)}, 93 {"ppp_ssu_host_rlt_num", 94 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_host_rlt_num)}, 95 {"ssu_tx_in_num", 96 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_in_num)}, 97 {"ssu_tx_out_num", 98 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_out_num)}, 99 {"ssu_rx_in_num", 100 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_in_num)}, 101 {"ssu_rx_out_num", 102 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_out_num)} 103 }; 104 105 static const struct hclge_comm_stats_str g_all_32bit_stats_string[] = { 106 {"igu_rx_err_pkt", 107 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_err_pkt)}, 108 {"igu_rx_no_eof_pkt", 109 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_eof_pkt)}, 110 {"igu_rx_no_sof_pkt", 111 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_sof_pkt)}, 112 {"egu_tx_1588_pkt", 113 HCLGE_32BIT_STATS_FIELD_OFF(egu_tx_1588_pkt)}, 114 {"ssu_full_drop_num", 115 HCLGE_32BIT_STATS_FIELD_OFF(ssu_full_drop_num)}, 116 {"ssu_part_drop_num", 117 HCLGE_32BIT_STATS_FIELD_OFF(ssu_part_drop_num)}, 118 {"ppp_key_drop_num", 119 HCLGE_32BIT_STATS_FIELD_OFF(ppp_key_drop_num)}, 120 {"ppp_rlt_drop_num", 121 HCLGE_32BIT_STATS_FIELD_OFF(ppp_rlt_drop_num)}, 122 {"ssu_key_drop_num", 123 HCLGE_32BIT_STATS_FIELD_OFF(ssu_key_drop_num)}, 124 {"pkt_curr_buf_cnt", 125 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_cnt)}, 126 {"qcn_fb_rcv_cnt", 127 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_rcv_cnt)}, 128 {"qcn_fb_drop_cnt", 129 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_drop_cnt)}, 130 {"qcn_fb_invaild_cnt", 131 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_invaild_cnt)}, 132 {"rx_packet_tc0_in_cnt", 133 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_in_cnt)}, 134 {"rx_packet_tc1_in_cnt", 135 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_in_cnt)}, 136 {"rx_packet_tc2_in_cnt", 137 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_in_cnt)}, 138 {"rx_packet_tc3_in_cnt", 139 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_in_cnt)}, 140 {"rx_packet_tc4_in_cnt", 141 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_in_cnt)}, 142 {"rx_packet_tc5_in_cnt", 143 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_in_cnt)}, 144 {"rx_packet_tc6_in_cnt", 145 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_in_cnt)}, 146 {"rx_packet_tc7_in_cnt", 147 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_in_cnt)}, 148 {"rx_packet_tc0_out_cnt", 149 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_out_cnt)}, 150 {"rx_packet_tc1_out_cnt", 151 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_out_cnt)}, 152 {"rx_packet_tc2_out_cnt", 153 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_out_cnt)}, 154 {"rx_packet_tc3_out_cnt", 155 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_out_cnt)}, 156 {"rx_packet_tc4_out_cnt", 157 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_out_cnt)}, 158 {"rx_packet_tc5_out_cnt", 159 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_out_cnt)}, 160 {"rx_packet_tc6_out_cnt", 161 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_out_cnt)}, 162 {"rx_packet_tc7_out_cnt", 163 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_out_cnt)}, 164 {"tx_packet_tc0_in_cnt", 165 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_in_cnt)}, 166 {"tx_packet_tc1_in_cnt", 167 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_in_cnt)}, 168 {"tx_packet_tc2_in_cnt", 169 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_in_cnt)}, 170 {"tx_packet_tc3_in_cnt", 171 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_in_cnt)}, 172 {"tx_packet_tc4_in_cnt", 173 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_in_cnt)}, 174 {"tx_packet_tc5_in_cnt", 175 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_in_cnt)}, 176 {"tx_packet_tc6_in_cnt", 177 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_in_cnt)}, 178 {"tx_packet_tc7_in_cnt", 179 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_in_cnt)}, 180 {"tx_packet_tc0_out_cnt", 181 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_out_cnt)}, 182 {"tx_packet_tc1_out_cnt", 183 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_out_cnt)}, 184 {"tx_packet_tc2_out_cnt", 185 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_out_cnt)}, 186 {"tx_packet_tc3_out_cnt", 187 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_out_cnt)}, 188 {"tx_packet_tc4_out_cnt", 189 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_out_cnt)}, 190 {"tx_packet_tc5_out_cnt", 191 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_out_cnt)}, 192 {"tx_packet_tc6_out_cnt", 193 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_out_cnt)}, 194 {"tx_packet_tc7_out_cnt", 195 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_out_cnt)}, 196 {"pkt_curr_buf_tc0_cnt", 197 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc0_cnt)}, 198 {"pkt_curr_buf_tc1_cnt", 199 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc1_cnt)}, 200 {"pkt_curr_buf_tc2_cnt", 201 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc2_cnt)}, 202 {"pkt_curr_buf_tc3_cnt", 203 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc3_cnt)}, 204 {"pkt_curr_buf_tc4_cnt", 205 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc4_cnt)}, 206 {"pkt_curr_buf_tc5_cnt", 207 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc5_cnt)}, 208 {"pkt_curr_buf_tc6_cnt", 209 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc6_cnt)}, 210 {"pkt_curr_buf_tc7_cnt", 211 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc7_cnt)}, 212 {"mb_uncopy_num", 213 HCLGE_32BIT_STATS_FIELD_OFF(mb_uncopy_num)}, 214 {"lo_pri_unicast_rlt_drop_num", 215 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_unicast_rlt_drop_num)}, 216 {"hi_pri_multicast_rlt_drop_num", 217 HCLGE_32BIT_STATS_FIELD_OFF(hi_pri_multicast_rlt_drop_num)}, 218 {"lo_pri_multicast_rlt_drop_num", 219 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_multicast_rlt_drop_num)}, 220 {"rx_oq_drop_pkt_cnt", 221 HCLGE_32BIT_STATS_FIELD_OFF(rx_oq_drop_pkt_cnt)}, 222 {"tx_oq_drop_pkt_cnt", 223 HCLGE_32BIT_STATS_FIELD_OFF(tx_oq_drop_pkt_cnt)}, 224 {"nic_l2_err_drop_pkt_cnt", 225 HCLGE_32BIT_STATS_FIELD_OFF(nic_l2_err_drop_pkt_cnt)}, 226 {"roc_l2_err_drop_pkt_cnt", 227 HCLGE_32BIT_STATS_FIELD_OFF(roc_l2_err_drop_pkt_cnt)} 228 }; 229 230 static const struct hclge_comm_stats_str g_mac_stats_string[] = { 231 {"mac_tx_mac_pause_num", 232 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)}, 233 {"mac_rx_mac_pause_num", 234 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)}, 235 {"mac_tx_pfc_pri0_pkt_num", 236 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)}, 237 {"mac_tx_pfc_pri1_pkt_num", 238 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)}, 239 {"mac_tx_pfc_pri2_pkt_num", 240 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)}, 241 {"mac_tx_pfc_pri3_pkt_num", 242 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)}, 243 {"mac_tx_pfc_pri4_pkt_num", 244 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)}, 245 {"mac_tx_pfc_pri5_pkt_num", 246 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)}, 247 {"mac_tx_pfc_pri6_pkt_num", 248 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)}, 249 {"mac_tx_pfc_pri7_pkt_num", 250 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)}, 251 {"mac_rx_pfc_pri0_pkt_num", 252 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)}, 253 {"mac_rx_pfc_pri1_pkt_num", 254 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)}, 255 {"mac_rx_pfc_pri2_pkt_num", 256 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)}, 257 {"mac_rx_pfc_pri3_pkt_num", 258 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)}, 259 {"mac_rx_pfc_pri4_pkt_num", 260 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)}, 261 {"mac_rx_pfc_pri5_pkt_num", 262 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)}, 263 {"mac_rx_pfc_pri6_pkt_num", 264 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)}, 265 {"mac_rx_pfc_pri7_pkt_num", 266 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)}, 267 {"mac_tx_total_pkt_num", 268 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)}, 269 {"mac_tx_total_oct_num", 270 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)}, 271 {"mac_tx_good_pkt_num", 272 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)}, 273 {"mac_tx_bad_pkt_num", 274 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)}, 275 {"mac_tx_good_oct_num", 276 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)}, 277 {"mac_tx_bad_oct_num", 278 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)}, 279 {"mac_tx_uni_pkt_num", 280 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)}, 281 {"mac_tx_multi_pkt_num", 282 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)}, 283 {"mac_tx_broad_pkt_num", 284 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)}, 285 {"mac_tx_undersize_pkt_num", 286 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)}, 287 {"mac_tx_oversize_pkt_num", 288 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num)}, 289 {"mac_tx_64_oct_pkt_num", 290 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)}, 291 {"mac_tx_65_127_oct_pkt_num", 292 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)}, 293 {"mac_tx_128_255_oct_pkt_num", 294 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)}, 295 {"mac_tx_256_511_oct_pkt_num", 296 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)}, 297 {"mac_tx_512_1023_oct_pkt_num", 298 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)}, 299 {"mac_tx_1024_1518_oct_pkt_num", 300 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)}, 301 {"mac_tx_1519_2047_oct_pkt_num", 302 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_2047_oct_pkt_num)}, 303 {"mac_tx_2048_4095_oct_pkt_num", 304 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_2048_4095_oct_pkt_num)}, 305 {"mac_tx_4096_8191_oct_pkt_num", 306 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_4096_8191_oct_pkt_num)}, 307 {"mac_tx_8192_12287_oct_pkt_num", 308 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_12287_oct_pkt_num)}, 309 {"mac_tx_8192_9216_oct_pkt_num", 310 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_9216_oct_pkt_num)}, 311 {"mac_tx_9217_12287_oct_pkt_num", 312 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_9217_12287_oct_pkt_num)}, 313 {"mac_tx_12288_16383_oct_pkt_num", 314 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_12288_16383_oct_pkt_num)}, 315 {"mac_tx_1519_max_good_pkt_num", 316 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_good_oct_pkt_num)}, 317 {"mac_tx_1519_max_bad_pkt_num", 318 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_bad_oct_pkt_num)}, 319 {"mac_rx_total_pkt_num", 320 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)}, 321 {"mac_rx_total_oct_num", 322 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)}, 323 {"mac_rx_good_pkt_num", 324 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)}, 325 {"mac_rx_bad_pkt_num", 326 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)}, 327 {"mac_rx_good_oct_num", 328 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)}, 329 {"mac_rx_bad_oct_num", 330 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)}, 331 {"mac_rx_uni_pkt_num", 332 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)}, 333 {"mac_rx_multi_pkt_num", 334 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)}, 335 {"mac_rx_broad_pkt_num", 336 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)}, 337 {"mac_rx_undersize_pkt_num", 338 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)}, 339 {"mac_rx_oversize_pkt_num", 340 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num)}, 341 {"mac_rx_64_oct_pkt_num", 342 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)}, 343 {"mac_rx_65_127_oct_pkt_num", 344 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)}, 345 {"mac_rx_128_255_oct_pkt_num", 346 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)}, 347 {"mac_rx_256_511_oct_pkt_num", 348 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)}, 349 {"mac_rx_512_1023_oct_pkt_num", 350 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)}, 351 {"mac_rx_1024_1518_oct_pkt_num", 352 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)}, 353 {"mac_rx_1519_2047_oct_pkt_num", 354 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_2047_oct_pkt_num)}, 355 {"mac_rx_2048_4095_oct_pkt_num", 356 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_2048_4095_oct_pkt_num)}, 357 {"mac_rx_4096_8191_oct_pkt_num", 358 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_4096_8191_oct_pkt_num)}, 359 {"mac_rx_8192_12287_oct_pkt_num", 360 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_12287_oct_pkt_num)}, 361 {"mac_rx_8192_9216_oct_pkt_num", 362 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_9216_oct_pkt_num)}, 363 {"mac_rx_9217_12287_oct_pkt_num", 364 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_9217_12287_oct_pkt_num)}, 365 {"mac_rx_12288_16383_oct_pkt_num", 366 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_12288_16383_oct_pkt_num)}, 367 {"mac_rx_1519_max_good_pkt_num", 368 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_good_oct_pkt_num)}, 369 {"mac_rx_1519_max_bad_pkt_num", 370 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_bad_oct_pkt_num)}, 371 372 {"mac_tx_fragment_pkt_num", 373 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num)}, 374 {"mac_tx_undermin_pkt_num", 375 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num)}, 376 {"mac_tx_jabber_pkt_num", 377 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num)}, 378 {"mac_tx_err_all_pkt_num", 379 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num)}, 380 {"mac_tx_from_app_good_pkt_num", 381 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num)}, 382 {"mac_tx_from_app_bad_pkt_num", 383 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num)}, 384 {"mac_rx_fragment_pkt_num", 385 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num)}, 386 {"mac_rx_undermin_pkt_num", 387 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num)}, 388 {"mac_rx_jabber_pkt_num", 389 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num)}, 390 {"mac_rx_fcs_err_pkt_num", 391 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num)}, 392 {"mac_rx_send_app_good_pkt_num", 393 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num)}, 394 {"mac_rx_send_app_bad_pkt_num", 395 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num)} 396 }; 397 398 static const struct hclge_mac_mgr_tbl_entry_cmd hclge_mgr_table[] = { 399 { 400 .flags = HCLGE_MAC_MGR_MASK_VLAN_B, 401 .ethter_type = cpu_to_le16(HCLGE_MAC_ETHERTYPE_LLDP), 402 .mac_addr_hi32 = cpu_to_le32(htonl(0x0180C200)), 403 .mac_addr_lo16 = cpu_to_le16(htons(0x000E)), 404 .i_port_bitmap = 0x1, 405 }, 406 }; 407 408 static int hclge_64_bit_update_stats(struct hclge_dev *hdev) 409 { 410 #define HCLGE_64_BIT_CMD_NUM 5 411 #define HCLGE_64_BIT_RTN_DATANUM 4 412 u64 *data = (u64 *)(&hdev->hw_stats.all_64_bit_stats); 413 struct hclge_desc desc[HCLGE_64_BIT_CMD_NUM]; 414 __le64 *desc_data; 415 int i, k, n; 416 int ret; 417 418 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_64_BIT, true); 419 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_64_BIT_CMD_NUM); 420 if (ret) { 421 dev_err(&hdev->pdev->dev, 422 "Get 64 bit pkt stats fail, status = %d.\n", ret); 423 return ret; 424 } 425 426 for (i = 0; i < HCLGE_64_BIT_CMD_NUM; i++) { 427 if (unlikely(i == 0)) { 428 desc_data = (__le64 *)(&desc[i].data[0]); 429 n = HCLGE_64_BIT_RTN_DATANUM - 1; 430 } else { 431 desc_data = (__le64 *)(&desc[i]); 432 n = HCLGE_64_BIT_RTN_DATANUM; 433 } 434 for (k = 0; k < n; k++) { 435 *data++ += le64_to_cpu(*desc_data); 436 desc_data++; 437 } 438 } 439 440 return 0; 441 } 442 443 static void hclge_reset_partial_32bit_counter(struct hclge_32_bit_stats *stats) 444 { 445 stats->pkt_curr_buf_cnt = 0; 446 stats->pkt_curr_buf_tc0_cnt = 0; 447 stats->pkt_curr_buf_tc1_cnt = 0; 448 stats->pkt_curr_buf_tc2_cnt = 0; 449 stats->pkt_curr_buf_tc3_cnt = 0; 450 stats->pkt_curr_buf_tc4_cnt = 0; 451 stats->pkt_curr_buf_tc5_cnt = 0; 452 stats->pkt_curr_buf_tc6_cnt = 0; 453 stats->pkt_curr_buf_tc7_cnt = 0; 454 } 455 456 static int hclge_32_bit_update_stats(struct hclge_dev *hdev) 457 { 458 #define HCLGE_32_BIT_CMD_NUM 8 459 #define HCLGE_32_BIT_RTN_DATANUM 8 460 461 struct hclge_desc desc[HCLGE_32_BIT_CMD_NUM]; 462 struct hclge_32_bit_stats *all_32_bit_stats; 463 __le32 *desc_data; 464 int i, k, n; 465 u64 *data; 466 int ret; 467 468 all_32_bit_stats = &hdev->hw_stats.all_32_bit_stats; 469 data = (u64 *)(&all_32_bit_stats->egu_tx_1588_pkt); 470 471 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_32_BIT, true); 472 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_32_BIT_CMD_NUM); 473 if (ret) { 474 dev_err(&hdev->pdev->dev, 475 "Get 32 bit pkt stats fail, status = %d.\n", ret); 476 477 return ret; 478 } 479 480 hclge_reset_partial_32bit_counter(all_32_bit_stats); 481 for (i = 0; i < HCLGE_32_BIT_CMD_NUM; i++) { 482 if (unlikely(i == 0)) { 483 __le16 *desc_data_16bit; 484 485 all_32_bit_stats->igu_rx_err_pkt += 486 le32_to_cpu(desc[i].data[0]); 487 488 desc_data_16bit = (__le16 *)&desc[i].data[1]; 489 all_32_bit_stats->igu_rx_no_eof_pkt += 490 le16_to_cpu(*desc_data_16bit); 491 492 desc_data_16bit++; 493 all_32_bit_stats->igu_rx_no_sof_pkt += 494 le16_to_cpu(*desc_data_16bit); 495 496 desc_data = &desc[i].data[2]; 497 n = HCLGE_32_BIT_RTN_DATANUM - 4; 498 } else { 499 desc_data = (__le32 *)&desc[i]; 500 n = HCLGE_32_BIT_RTN_DATANUM; 501 } 502 for (k = 0; k < n; k++) { 503 *data++ += le32_to_cpu(*desc_data); 504 desc_data++; 505 } 506 } 507 508 return 0; 509 } 510 511 static int hclge_mac_get_traffic_stats(struct hclge_dev *hdev) 512 { 513 struct hclge_mac_stats *mac_stats = &hdev->hw_stats.mac_stats; 514 struct hclge_desc desc; 515 __le64 *desc_data; 516 int ret; 517 518 /* for fiber port, need to query the total rx/tx packets statstics, 519 * used for data transferring checking. 520 */ 521 if (hdev->hw.mac.media_type != HNAE3_MEDIA_TYPE_FIBER) 522 return 0; 523 524 if (test_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state)) 525 return 0; 526 527 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_STATS_MAC_TRAFFIC, true); 528 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 529 if (ret) { 530 dev_err(&hdev->pdev->dev, 531 "Get MAC total pkt stats fail, ret = %d\n", ret); 532 533 return ret; 534 } 535 536 desc_data = (__le64 *)(&desc.data[0]); 537 mac_stats->mac_tx_total_pkt_num += le64_to_cpu(*desc_data++); 538 mac_stats->mac_rx_total_pkt_num += le64_to_cpu(*desc_data); 539 540 return 0; 541 } 542 543 static int hclge_mac_update_stats(struct hclge_dev *hdev) 544 { 545 #define HCLGE_MAC_CMD_NUM 21 546 #define HCLGE_RTN_DATA_NUM 4 547 548 u64 *data = (u64 *)(&hdev->hw_stats.mac_stats); 549 struct hclge_desc desc[HCLGE_MAC_CMD_NUM]; 550 __le64 *desc_data; 551 int i, k, n; 552 int ret; 553 554 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true); 555 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM); 556 if (ret) { 557 dev_err(&hdev->pdev->dev, 558 "Get MAC pkt stats fail, status = %d.\n", ret); 559 560 return ret; 561 } 562 563 for (i = 0; i < HCLGE_MAC_CMD_NUM; i++) { 564 if (unlikely(i == 0)) { 565 desc_data = (__le64 *)(&desc[i].data[0]); 566 n = HCLGE_RTN_DATA_NUM - 2; 567 } else { 568 desc_data = (__le64 *)(&desc[i]); 569 n = HCLGE_RTN_DATA_NUM; 570 } 571 for (k = 0; k < n; k++) { 572 *data++ += le64_to_cpu(*desc_data); 573 desc_data++; 574 } 575 } 576 577 return 0; 578 } 579 580 static int hclge_tqps_update_stats(struct hnae3_handle *handle) 581 { 582 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 583 struct hclge_vport *vport = hclge_get_vport(handle); 584 struct hclge_dev *hdev = vport->back; 585 struct hnae3_queue *queue; 586 struct hclge_desc desc[1]; 587 struct hclge_tqp *tqp; 588 int ret, i; 589 590 for (i = 0; i < kinfo->num_tqps; i++) { 591 queue = handle->kinfo.tqp[i]; 592 tqp = container_of(queue, struct hclge_tqp, q); 593 /* command : HCLGE_OPC_QUERY_IGU_STAT */ 594 hclge_cmd_setup_basic_desc(&desc[0], 595 HCLGE_OPC_QUERY_RX_STATUS, 596 true); 597 598 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff)); 599 ret = hclge_cmd_send(&hdev->hw, desc, 1); 600 if (ret) { 601 dev_err(&hdev->pdev->dev, 602 "Query tqp stat fail, status = %d,queue = %d\n", 603 ret, i); 604 return ret; 605 } 606 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd += 607 le32_to_cpu(desc[0].data[1]); 608 } 609 610 for (i = 0; i < kinfo->num_tqps; i++) { 611 queue = handle->kinfo.tqp[i]; 612 tqp = container_of(queue, struct hclge_tqp, q); 613 /* command : HCLGE_OPC_QUERY_IGU_STAT */ 614 hclge_cmd_setup_basic_desc(&desc[0], 615 HCLGE_OPC_QUERY_TX_STATUS, 616 true); 617 618 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff)); 619 ret = hclge_cmd_send(&hdev->hw, desc, 1); 620 if (ret) { 621 dev_err(&hdev->pdev->dev, 622 "Query tqp stat fail, status = %d,queue = %d\n", 623 ret, i); 624 return ret; 625 } 626 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd += 627 le32_to_cpu(desc[0].data[1]); 628 } 629 630 return 0; 631 } 632 633 static u64 *hclge_tqps_get_stats(struct hnae3_handle *handle, u64 *data) 634 { 635 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 636 struct hclge_tqp *tqp; 637 u64 *buff = data; 638 int i; 639 640 for (i = 0; i < kinfo->num_tqps; i++) { 641 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q); 642 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd; 643 } 644 645 for (i = 0; i < kinfo->num_tqps; i++) { 646 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q); 647 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd; 648 } 649 650 return buff; 651 } 652 653 static int hclge_tqps_get_sset_count(struct hnae3_handle *handle, int stringset) 654 { 655 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 656 657 return kinfo->num_tqps * (2); 658 } 659 660 static u8 *hclge_tqps_get_strings(struct hnae3_handle *handle, u8 *data) 661 { 662 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 663 u8 *buff = data; 664 int i = 0; 665 666 for (i = 0; i < kinfo->num_tqps; i++) { 667 struct hclge_tqp *tqp = container_of(handle->kinfo.tqp[i], 668 struct hclge_tqp, q); 669 snprintf(buff, ETH_GSTRING_LEN, "txq#%d_pktnum_rcd", 670 tqp->index); 671 buff = buff + ETH_GSTRING_LEN; 672 } 673 674 for (i = 0; i < kinfo->num_tqps; i++) { 675 struct hclge_tqp *tqp = container_of(kinfo->tqp[i], 676 struct hclge_tqp, q); 677 snprintf(buff, ETH_GSTRING_LEN, "rxq#%d_pktnum_rcd", 678 tqp->index); 679 buff = buff + ETH_GSTRING_LEN; 680 } 681 682 return buff; 683 } 684 685 static u64 *hclge_comm_get_stats(void *comm_stats, 686 const struct hclge_comm_stats_str strs[], 687 int size, u64 *data) 688 { 689 u64 *buf = data; 690 u32 i; 691 692 for (i = 0; i < size; i++) 693 buf[i] = HCLGE_STATS_READ(comm_stats, strs[i].offset); 694 695 return buf + size; 696 } 697 698 static u8 *hclge_comm_get_strings(u32 stringset, 699 const struct hclge_comm_stats_str strs[], 700 int size, u8 *data) 701 { 702 char *buff = (char *)data; 703 u32 i; 704 705 if (stringset != ETH_SS_STATS) 706 return buff; 707 708 for (i = 0; i < size; i++) { 709 snprintf(buff, ETH_GSTRING_LEN, 710 strs[i].desc); 711 buff = buff + ETH_GSTRING_LEN; 712 } 713 714 return (u8 *)buff; 715 } 716 717 static void hclge_update_netstat(struct hclge_hw_stats *hw_stats, 718 struct net_device_stats *net_stats) 719 { 720 net_stats->tx_dropped = 0; 721 net_stats->rx_dropped = hw_stats->all_32_bit_stats.ssu_full_drop_num; 722 net_stats->rx_dropped += hw_stats->all_32_bit_stats.ppp_key_drop_num; 723 net_stats->rx_dropped += hw_stats->all_32_bit_stats.ssu_key_drop_num; 724 725 net_stats->rx_errors = hw_stats->mac_stats.mac_rx_oversize_pkt_num; 726 net_stats->rx_errors += hw_stats->mac_stats.mac_rx_undersize_pkt_num; 727 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_eof_pkt; 728 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_sof_pkt; 729 net_stats->rx_errors += hw_stats->mac_stats.mac_rx_fcs_err_pkt_num; 730 731 net_stats->multicast = hw_stats->mac_stats.mac_tx_multi_pkt_num; 732 net_stats->multicast += hw_stats->mac_stats.mac_rx_multi_pkt_num; 733 734 net_stats->rx_crc_errors = hw_stats->mac_stats.mac_rx_fcs_err_pkt_num; 735 net_stats->rx_length_errors = 736 hw_stats->mac_stats.mac_rx_undersize_pkt_num; 737 net_stats->rx_length_errors += 738 hw_stats->mac_stats.mac_rx_oversize_pkt_num; 739 net_stats->rx_over_errors = 740 hw_stats->mac_stats.mac_rx_oversize_pkt_num; 741 } 742 743 static void hclge_update_stats_for_all(struct hclge_dev *hdev) 744 { 745 struct hnae3_handle *handle; 746 int status; 747 748 handle = &hdev->vport[0].nic; 749 if (handle->client) { 750 status = hclge_tqps_update_stats(handle); 751 if (status) { 752 dev_err(&hdev->pdev->dev, 753 "Update TQPS stats fail, status = %d.\n", 754 status); 755 } 756 } 757 758 status = hclge_mac_update_stats(hdev); 759 if (status) 760 dev_err(&hdev->pdev->dev, 761 "Update MAC stats fail, status = %d.\n", status); 762 763 status = hclge_32_bit_update_stats(hdev); 764 if (status) 765 dev_err(&hdev->pdev->dev, 766 "Update 32 bit stats fail, status = %d.\n", 767 status); 768 769 hclge_update_netstat(&hdev->hw_stats, &handle->kinfo.netdev->stats); 770 } 771 772 static void hclge_update_stats(struct hnae3_handle *handle, 773 struct net_device_stats *net_stats) 774 { 775 struct hclge_vport *vport = hclge_get_vport(handle); 776 struct hclge_dev *hdev = vport->back; 777 struct hclge_hw_stats *hw_stats = &hdev->hw_stats; 778 int status; 779 780 if (test_and_set_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state)) 781 return; 782 783 status = hclge_mac_update_stats(hdev); 784 if (status) 785 dev_err(&hdev->pdev->dev, 786 "Update MAC stats fail, status = %d.\n", 787 status); 788 789 status = hclge_32_bit_update_stats(hdev); 790 if (status) 791 dev_err(&hdev->pdev->dev, 792 "Update 32 bit stats fail, status = %d.\n", 793 status); 794 795 status = hclge_64_bit_update_stats(hdev); 796 if (status) 797 dev_err(&hdev->pdev->dev, 798 "Update 64 bit stats fail, status = %d.\n", 799 status); 800 801 status = hclge_tqps_update_stats(handle); 802 if (status) 803 dev_err(&hdev->pdev->dev, 804 "Update TQPS stats fail, status = %d.\n", 805 status); 806 807 hclge_update_netstat(hw_stats, net_stats); 808 809 clear_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state); 810 } 811 812 static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset) 813 { 814 #define HCLGE_LOOPBACK_TEST_FLAGS 0x7 815 816 struct hclge_vport *vport = hclge_get_vport(handle); 817 struct hclge_dev *hdev = vport->back; 818 int count = 0; 819 820 /* Loopback test support rules: 821 * mac: only GE mode support 822 * serdes: all mac mode will support include GE/XGE/LGE/CGE 823 * phy: only support when phy device exist on board 824 */ 825 if (stringset == ETH_SS_TEST) { 826 /* clear loopback bit flags at first */ 827 handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS)); 828 if (hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M || 829 hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M || 830 hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) { 831 count += 1; 832 handle->flags |= HNAE3_SUPPORT_MAC_LOOPBACK; 833 } else { 834 count = -EOPNOTSUPP; 835 } 836 } else if (stringset == ETH_SS_STATS) { 837 count = ARRAY_SIZE(g_mac_stats_string) + 838 ARRAY_SIZE(g_all_32bit_stats_string) + 839 ARRAY_SIZE(g_all_64bit_stats_string) + 840 hclge_tqps_get_sset_count(handle, stringset); 841 } 842 843 return count; 844 } 845 846 static void hclge_get_strings(struct hnae3_handle *handle, 847 u32 stringset, 848 u8 *data) 849 { 850 u8 *p = (char *)data; 851 int size; 852 853 if (stringset == ETH_SS_STATS) { 854 size = ARRAY_SIZE(g_mac_stats_string); 855 p = hclge_comm_get_strings(stringset, 856 g_mac_stats_string, 857 size, 858 p); 859 size = ARRAY_SIZE(g_all_32bit_stats_string); 860 p = hclge_comm_get_strings(stringset, 861 g_all_32bit_stats_string, 862 size, 863 p); 864 size = ARRAY_SIZE(g_all_64bit_stats_string); 865 p = hclge_comm_get_strings(stringset, 866 g_all_64bit_stats_string, 867 size, 868 p); 869 p = hclge_tqps_get_strings(handle, p); 870 } else if (stringset == ETH_SS_TEST) { 871 if (handle->flags & HNAE3_SUPPORT_MAC_LOOPBACK) { 872 memcpy(p, 873 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_MAC], 874 ETH_GSTRING_LEN); 875 p += ETH_GSTRING_LEN; 876 } 877 if (handle->flags & HNAE3_SUPPORT_SERDES_LOOPBACK) { 878 memcpy(p, 879 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_SERDES], 880 ETH_GSTRING_LEN); 881 p += ETH_GSTRING_LEN; 882 } 883 if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) { 884 memcpy(p, 885 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_PHY], 886 ETH_GSTRING_LEN); 887 p += ETH_GSTRING_LEN; 888 } 889 } 890 } 891 892 static void hclge_get_stats(struct hnae3_handle *handle, u64 *data) 893 { 894 struct hclge_vport *vport = hclge_get_vport(handle); 895 struct hclge_dev *hdev = vport->back; 896 u64 *p; 897 898 p = hclge_comm_get_stats(&hdev->hw_stats.mac_stats, 899 g_mac_stats_string, 900 ARRAY_SIZE(g_mac_stats_string), 901 data); 902 p = hclge_comm_get_stats(&hdev->hw_stats.all_32_bit_stats, 903 g_all_32bit_stats_string, 904 ARRAY_SIZE(g_all_32bit_stats_string), 905 p); 906 p = hclge_comm_get_stats(&hdev->hw_stats.all_64_bit_stats, 907 g_all_64bit_stats_string, 908 ARRAY_SIZE(g_all_64bit_stats_string), 909 p); 910 p = hclge_tqps_get_stats(handle, p); 911 } 912 913 static int hclge_parse_func_status(struct hclge_dev *hdev, 914 struct hclge_func_status_cmd *status) 915 { 916 if (!(status->pf_state & HCLGE_PF_STATE_DONE)) 917 return -EINVAL; 918 919 /* Set the pf to main pf */ 920 if (status->pf_state & HCLGE_PF_STATE_MAIN) 921 hdev->flag |= HCLGE_FLAG_MAIN; 922 else 923 hdev->flag &= ~HCLGE_FLAG_MAIN; 924 925 return 0; 926 } 927 928 static int hclge_query_function_status(struct hclge_dev *hdev) 929 { 930 struct hclge_func_status_cmd *req; 931 struct hclge_desc desc; 932 int timeout = 0; 933 int ret; 934 935 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true); 936 req = (struct hclge_func_status_cmd *)desc.data; 937 938 do { 939 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 940 if (ret) { 941 dev_err(&hdev->pdev->dev, 942 "query function status failed %d.\n", 943 ret); 944 945 return ret; 946 } 947 948 /* Check pf reset is done */ 949 if (req->pf_state) 950 break; 951 usleep_range(1000, 2000); 952 } while (timeout++ < 5); 953 954 ret = hclge_parse_func_status(hdev, req); 955 956 return ret; 957 } 958 959 static int hclge_query_pf_resource(struct hclge_dev *hdev) 960 { 961 struct hclge_pf_res_cmd *req; 962 struct hclge_desc desc; 963 int ret; 964 965 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true); 966 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 967 if (ret) { 968 dev_err(&hdev->pdev->dev, 969 "query pf resource failed %d.\n", ret); 970 return ret; 971 } 972 973 req = (struct hclge_pf_res_cmd *)desc.data; 974 hdev->num_tqps = __le16_to_cpu(req->tqp_num); 975 hdev->pkt_buf_size = __le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S; 976 977 if (hnae3_dev_roce_supported(hdev)) { 978 hdev->num_roce_msi = 979 hnae_get_field(__le16_to_cpu(req->pf_intr_vector_number), 980 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S); 981 982 /* PF should have NIC vectors and Roce vectors, 983 * NIC vectors are queued before Roce vectors. 984 */ 985 hdev->num_msi = hdev->num_roce_msi + HCLGE_ROCE_VECTOR_OFFSET; 986 } else { 987 hdev->num_msi = 988 hnae_get_field(__le16_to_cpu(req->pf_intr_vector_number), 989 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S); 990 } 991 992 return 0; 993 } 994 995 static int hclge_parse_speed(int speed_cmd, int *speed) 996 { 997 switch (speed_cmd) { 998 case 6: 999 *speed = HCLGE_MAC_SPEED_10M; 1000 break; 1001 case 7: 1002 *speed = HCLGE_MAC_SPEED_100M; 1003 break; 1004 case 0: 1005 *speed = HCLGE_MAC_SPEED_1G; 1006 break; 1007 case 1: 1008 *speed = HCLGE_MAC_SPEED_10G; 1009 break; 1010 case 2: 1011 *speed = HCLGE_MAC_SPEED_25G; 1012 break; 1013 case 3: 1014 *speed = HCLGE_MAC_SPEED_40G; 1015 break; 1016 case 4: 1017 *speed = HCLGE_MAC_SPEED_50G; 1018 break; 1019 case 5: 1020 *speed = HCLGE_MAC_SPEED_100G; 1021 break; 1022 default: 1023 return -EINVAL; 1024 } 1025 1026 return 0; 1027 } 1028 1029 static void hclge_parse_fiber_link_mode(struct hclge_dev *hdev, 1030 u8 speed_ability) 1031 { 1032 unsigned long *supported = hdev->hw.mac.supported; 1033 1034 if (speed_ability & HCLGE_SUPPORT_1G_BIT) 1035 set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 1036 supported); 1037 1038 if (speed_ability & HCLGE_SUPPORT_10G_BIT) 1039 set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, 1040 supported); 1041 1042 if (speed_ability & HCLGE_SUPPORT_25G_BIT) 1043 set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, 1044 supported); 1045 1046 if (speed_ability & HCLGE_SUPPORT_50G_BIT) 1047 set_bit(ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT, 1048 supported); 1049 1050 if (speed_ability & HCLGE_SUPPORT_100G_BIT) 1051 set_bit(ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT, 1052 supported); 1053 1054 set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, supported); 1055 set_bit(ETHTOOL_LINK_MODE_Pause_BIT, supported); 1056 } 1057 1058 static void hclge_parse_link_mode(struct hclge_dev *hdev, u8 speed_ability) 1059 { 1060 u8 media_type = hdev->hw.mac.media_type; 1061 1062 if (media_type != HNAE3_MEDIA_TYPE_FIBER) 1063 return; 1064 1065 hclge_parse_fiber_link_mode(hdev, speed_ability); 1066 } 1067 1068 static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc) 1069 { 1070 struct hclge_cfg_param_cmd *req; 1071 u64 mac_addr_tmp_high; 1072 u64 mac_addr_tmp; 1073 int i; 1074 1075 req = (struct hclge_cfg_param_cmd *)desc[0].data; 1076 1077 /* get the configuration */ 1078 cfg->vmdq_vport_num = hnae_get_field(__le32_to_cpu(req->param[0]), 1079 HCLGE_CFG_VMDQ_M, 1080 HCLGE_CFG_VMDQ_S); 1081 cfg->tc_num = hnae_get_field(__le32_to_cpu(req->param[0]), 1082 HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S); 1083 cfg->tqp_desc_num = hnae_get_field(__le32_to_cpu(req->param[0]), 1084 HCLGE_CFG_TQP_DESC_N_M, 1085 HCLGE_CFG_TQP_DESC_N_S); 1086 1087 cfg->phy_addr = hnae_get_field(__le32_to_cpu(req->param[1]), 1088 HCLGE_CFG_PHY_ADDR_M, 1089 HCLGE_CFG_PHY_ADDR_S); 1090 cfg->media_type = hnae_get_field(__le32_to_cpu(req->param[1]), 1091 HCLGE_CFG_MEDIA_TP_M, 1092 HCLGE_CFG_MEDIA_TP_S); 1093 cfg->rx_buf_len = hnae_get_field(__le32_to_cpu(req->param[1]), 1094 HCLGE_CFG_RX_BUF_LEN_M, 1095 HCLGE_CFG_RX_BUF_LEN_S); 1096 /* get mac_address */ 1097 mac_addr_tmp = __le32_to_cpu(req->param[2]); 1098 mac_addr_tmp_high = hnae_get_field(__le32_to_cpu(req->param[3]), 1099 HCLGE_CFG_MAC_ADDR_H_M, 1100 HCLGE_CFG_MAC_ADDR_H_S); 1101 1102 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1; 1103 1104 cfg->default_speed = hnae_get_field(__le32_to_cpu(req->param[3]), 1105 HCLGE_CFG_DEFAULT_SPEED_M, 1106 HCLGE_CFG_DEFAULT_SPEED_S); 1107 cfg->rss_size_max = hnae_get_field(__le32_to_cpu(req->param[3]), 1108 HCLGE_CFG_RSS_SIZE_M, 1109 HCLGE_CFG_RSS_SIZE_S); 1110 1111 for (i = 0; i < ETH_ALEN; i++) 1112 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff; 1113 1114 req = (struct hclge_cfg_param_cmd *)desc[1].data; 1115 cfg->numa_node_map = __le32_to_cpu(req->param[0]); 1116 1117 cfg->speed_ability = hnae_get_field(__le32_to_cpu(req->param[1]), 1118 HCLGE_CFG_SPEED_ABILITY_M, 1119 HCLGE_CFG_SPEED_ABILITY_S); 1120 } 1121 1122 /* hclge_get_cfg: query the static parameter from flash 1123 * @hdev: pointer to struct hclge_dev 1124 * @hcfg: the config structure to be getted 1125 */ 1126 static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg) 1127 { 1128 struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM]; 1129 struct hclge_cfg_param_cmd *req; 1130 int i, ret; 1131 1132 for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) { 1133 u32 offset = 0; 1134 1135 req = (struct hclge_cfg_param_cmd *)desc[i].data; 1136 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM, 1137 true); 1138 hnae_set_field(offset, HCLGE_CFG_OFFSET_M, 1139 HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES); 1140 /* Len should be united by 4 bytes when send to hardware */ 1141 hnae_set_field(offset, HCLGE_CFG_RD_LEN_M, HCLGE_CFG_RD_LEN_S, 1142 HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT); 1143 req->offset = cpu_to_le32(offset); 1144 } 1145 1146 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM); 1147 if (ret) { 1148 dev_err(&hdev->pdev->dev, 1149 "get config failed %d.\n", ret); 1150 return ret; 1151 } 1152 1153 hclge_parse_cfg(hcfg, desc); 1154 return 0; 1155 } 1156 1157 static int hclge_get_cap(struct hclge_dev *hdev) 1158 { 1159 int ret; 1160 1161 ret = hclge_query_function_status(hdev); 1162 if (ret) { 1163 dev_err(&hdev->pdev->dev, 1164 "query function status error %d.\n", ret); 1165 return ret; 1166 } 1167 1168 /* get pf resource */ 1169 ret = hclge_query_pf_resource(hdev); 1170 if (ret) { 1171 dev_err(&hdev->pdev->dev, 1172 "query pf resource error %d.\n", ret); 1173 return ret; 1174 } 1175 1176 return 0; 1177 } 1178 1179 static int hclge_configure(struct hclge_dev *hdev) 1180 { 1181 struct hclge_cfg cfg; 1182 int ret, i; 1183 1184 ret = hclge_get_cfg(hdev, &cfg); 1185 if (ret) { 1186 dev_err(&hdev->pdev->dev, "get mac mode error %d.\n", ret); 1187 return ret; 1188 } 1189 1190 hdev->num_vmdq_vport = cfg.vmdq_vport_num; 1191 hdev->base_tqp_pid = 0; 1192 hdev->rss_size_max = cfg.rss_size_max; 1193 hdev->rx_buf_len = cfg.rx_buf_len; 1194 ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr); 1195 hdev->hw.mac.media_type = cfg.media_type; 1196 hdev->hw.mac.phy_addr = cfg.phy_addr; 1197 hdev->num_desc = cfg.tqp_desc_num; 1198 hdev->tm_info.num_pg = 1; 1199 hdev->tc_max = cfg.tc_num; 1200 hdev->tm_info.hw_pfc_map = 0; 1201 1202 ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed); 1203 if (ret) { 1204 dev_err(&hdev->pdev->dev, "Get wrong speed ret=%d.\n", ret); 1205 return ret; 1206 } 1207 1208 hclge_parse_link_mode(hdev, cfg.speed_ability); 1209 1210 if ((hdev->tc_max > HNAE3_MAX_TC) || 1211 (hdev->tc_max < 1)) { 1212 dev_warn(&hdev->pdev->dev, "TC num = %d.\n", 1213 hdev->tc_max); 1214 hdev->tc_max = 1; 1215 } 1216 1217 /* Dev does not support DCB */ 1218 if (!hnae3_dev_dcb_supported(hdev)) { 1219 hdev->tc_max = 1; 1220 hdev->pfc_max = 0; 1221 } else { 1222 hdev->pfc_max = hdev->tc_max; 1223 } 1224 1225 hdev->tm_info.num_tc = hdev->tc_max; 1226 1227 /* Currently not support uncontiuous tc */ 1228 for (i = 0; i < hdev->tm_info.num_tc; i++) 1229 hnae_set_bit(hdev->hw_tc_map, i, 1); 1230 1231 hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE; 1232 1233 return ret; 1234 } 1235 1236 static int hclge_config_tso(struct hclge_dev *hdev, int tso_mss_min, 1237 int tso_mss_max) 1238 { 1239 struct hclge_cfg_tso_status_cmd *req; 1240 struct hclge_desc desc; 1241 u16 tso_mss; 1242 1243 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false); 1244 1245 req = (struct hclge_cfg_tso_status_cmd *)desc.data; 1246 1247 tso_mss = 0; 1248 hnae_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M, 1249 HCLGE_TSO_MSS_MIN_S, tso_mss_min); 1250 req->tso_mss_min = cpu_to_le16(tso_mss); 1251 1252 tso_mss = 0; 1253 hnae_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M, 1254 HCLGE_TSO_MSS_MIN_S, tso_mss_max); 1255 req->tso_mss_max = cpu_to_le16(tso_mss); 1256 1257 return hclge_cmd_send(&hdev->hw, &desc, 1); 1258 } 1259 1260 static int hclge_alloc_tqps(struct hclge_dev *hdev) 1261 { 1262 struct hclge_tqp *tqp; 1263 int i; 1264 1265 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 1266 sizeof(struct hclge_tqp), GFP_KERNEL); 1267 if (!hdev->htqp) 1268 return -ENOMEM; 1269 1270 tqp = hdev->htqp; 1271 1272 for (i = 0; i < hdev->num_tqps; i++) { 1273 tqp->dev = &hdev->pdev->dev; 1274 tqp->index = i; 1275 1276 tqp->q.ae_algo = &ae_algo; 1277 tqp->q.buf_size = hdev->rx_buf_len; 1278 tqp->q.desc_num = hdev->num_desc; 1279 tqp->q.io_base = hdev->hw.io_base + HCLGE_TQP_REG_OFFSET + 1280 i * HCLGE_TQP_REG_SIZE; 1281 1282 tqp++; 1283 } 1284 1285 return 0; 1286 } 1287 1288 static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id, 1289 u16 tqp_pid, u16 tqp_vid, bool is_pf) 1290 { 1291 struct hclge_tqp_map_cmd *req; 1292 struct hclge_desc desc; 1293 int ret; 1294 1295 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false); 1296 1297 req = (struct hclge_tqp_map_cmd *)desc.data; 1298 req->tqp_id = cpu_to_le16(tqp_pid); 1299 req->tqp_vf = func_id; 1300 req->tqp_flag = !is_pf << HCLGE_TQP_MAP_TYPE_B | 1301 1 << HCLGE_TQP_MAP_EN_B; 1302 req->tqp_vid = cpu_to_le16(tqp_vid); 1303 1304 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1305 if (ret) { 1306 dev_err(&hdev->pdev->dev, "TQP map failed %d.\n", 1307 ret); 1308 return ret; 1309 } 1310 1311 return 0; 1312 } 1313 1314 static int hclge_assign_tqp(struct hclge_vport *vport, 1315 struct hnae3_queue **tqp, u16 num_tqps) 1316 { 1317 struct hclge_dev *hdev = vport->back; 1318 int i, alloced; 1319 1320 for (i = 0, alloced = 0; i < hdev->num_tqps && 1321 alloced < num_tqps; i++) { 1322 if (!hdev->htqp[i].alloced) { 1323 hdev->htqp[i].q.handle = &vport->nic; 1324 hdev->htqp[i].q.tqp_index = alloced; 1325 tqp[alloced] = &hdev->htqp[i].q; 1326 hdev->htqp[i].alloced = true; 1327 alloced++; 1328 } 1329 } 1330 vport->alloc_tqps = num_tqps; 1331 1332 return 0; 1333 } 1334 1335 static int hclge_knic_setup(struct hclge_vport *vport, u16 num_tqps) 1336 { 1337 struct hnae3_handle *nic = &vport->nic; 1338 struct hnae3_knic_private_info *kinfo = &nic->kinfo; 1339 struct hclge_dev *hdev = vport->back; 1340 int i, ret; 1341 1342 kinfo->num_desc = hdev->num_desc; 1343 kinfo->rx_buf_len = hdev->rx_buf_len; 1344 kinfo->num_tc = min_t(u16, num_tqps, hdev->tm_info.num_tc); 1345 kinfo->rss_size 1346 = min_t(u16, hdev->rss_size_max, num_tqps / kinfo->num_tc); 1347 kinfo->num_tqps = kinfo->rss_size * kinfo->num_tc; 1348 1349 for (i = 0; i < HNAE3_MAX_TC; i++) { 1350 if (hdev->hw_tc_map & BIT(i)) { 1351 kinfo->tc_info[i].enable = true; 1352 kinfo->tc_info[i].tqp_offset = i * kinfo->rss_size; 1353 kinfo->tc_info[i].tqp_count = kinfo->rss_size; 1354 kinfo->tc_info[i].tc = i; 1355 } else { 1356 /* Set to default queue if TC is disable */ 1357 kinfo->tc_info[i].enable = false; 1358 kinfo->tc_info[i].tqp_offset = 0; 1359 kinfo->tc_info[i].tqp_count = 1; 1360 kinfo->tc_info[i].tc = 0; 1361 } 1362 } 1363 1364 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps, 1365 sizeof(struct hnae3_queue *), GFP_KERNEL); 1366 if (!kinfo->tqp) 1367 return -ENOMEM; 1368 1369 ret = hclge_assign_tqp(vport, kinfo->tqp, kinfo->num_tqps); 1370 if (ret) { 1371 dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret); 1372 return -EINVAL; 1373 } 1374 1375 return 0; 1376 } 1377 1378 static int hclge_map_tqp_to_vport(struct hclge_dev *hdev, 1379 struct hclge_vport *vport) 1380 { 1381 struct hnae3_handle *nic = &vport->nic; 1382 struct hnae3_knic_private_info *kinfo; 1383 u16 i; 1384 1385 kinfo = &nic->kinfo; 1386 for (i = 0; i < kinfo->num_tqps; i++) { 1387 struct hclge_tqp *q = 1388 container_of(kinfo->tqp[i], struct hclge_tqp, q); 1389 bool is_pf; 1390 int ret; 1391 1392 is_pf = !(vport->vport_id); 1393 ret = hclge_map_tqps_to_func(hdev, vport->vport_id, q->index, 1394 i, is_pf); 1395 if (ret) 1396 return ret; 1397 } 1398 1399 return 0; 1400 } 1401 1402 static int hclge_map_tqp(struct hclge_dev *hdev) 1403 { 1404 struct hclge_vport *vport = hdev->vport; 1405 u16 i, num_vport; 1406 1407 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1; 1408 for (i = 0; i < num_vport; i++) { 1409 int ret; 1410 1411 ret = hclge_map_tqp_to_vport(hdev, vport); 1412 if (ret) 1413 return ret; 1414 1415 vport++; 1416 } 1417 1418 return 0; 1419 } 1420 1421 static void hclge_unic_setup(struct hclge_vport *vport, u16 num_tqps) 1422 { 1423 /* this would be initialized later */ 1424 } 1425 1426 static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps) 1427 { 1428 struct hnae3_handle *nic = &vport->nic; 1429 struct hclge_dev *hdev = vport->back; 1430 int ret; 1431 1432 nic->pdev = hdev->pdev; 1433 nic->ae_algo = &ae_algo; 1434 nic->numa_node_mask = hdev->numa_node_mask; 1435 1436 if (hdev->ae_dev->dev_type == HNAE3_DEV_KNIC) { 1437 ret = hclge_knic_setup(vport, num_tqps); 1438 if (ret) { 1439 dev_err(&hdev->pdev->dev, "knic setup failed %d\n", 1440 ret); 1441 return ret; 1442 } 1443 } else { 1444 hclge_unic_setup(vport, num_tqps); 1445 } 1446 1447 return 0; 1448 } 1449 1450 static int hclge_alloc_vport(struct hclge_dev *hdev) 1451 { 1452 struct pci_dev *pdev = hdev->pdev; 1453 struct hclge_vport *vport; 1454 u32 tqp_main_vport; 1455 u32 tqp_per_vport; 1456 int num_vport, i; 1457 int ret; 1458 1459 /* We need to alloc a vport for main NIC of PF */ 1460 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1; 1461 1462 if (hdev->num_tqps < num_vport) 1463 num_vport = hdev->num_tqps; 1464 1465 /* Alloc the same number of TQPs for every vport */ 1466 tqp_per_vport = hdev->num_tqps / num_vport; 1467 tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport; 1468 1469 vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport), 1470 GFP_KERNEL); 1471 if (!vport) 1472 return -ENOMEM; 1473 1474 hdev->vport = vport; 1475 hdev->num_alloc_vport = num_vport; 1476 1477 #ifdef CONFIG_PCI_IOV 1478 /* Enable SRIOV */ 1479 if (hdev->num_req_vfs) { 1480 dev_info(&pdev->dev, "active VFs(%d) found, enabling SRIOV\n", 1481 hdev->num_req_vfs); 1482 ret = pci_enable_sriov(hdev->pdev, hdev->num_req_vfs); 1483 if (ret) { 1484 hdev->num_alloc_vfs = 0; 1485 dev_err(&pdev->dev, "SRIOV enable failed %d\n", 1486 ret); 1487 return ret; 1488 } 1489 } 1490 hdev->num_alloc_vfs = hdev->num_req_vfs; 1491 #endif 1492 1493 for (i = 0; i < num_vport; i++) { 1494 vport->back = hdev; 1495 vport->vport_id = i; 1496 1497 if (i == 0) 1498 ret = hclge_vport_setup(vport, tqp_main_vport); 1499 else 1500 ret = hclge_vport_setup(vport, tqp_per_vport); 1501 if (ret) { 1502 dev_err(&pdev->dev, 1503 "vport setup failed for vport %d, %d\n", 1504 i, ret); 1505 return ret; 1506 } 1507 1508 vport++; 1509 } 1510 1511 return 0; 1512 } 1513 1514 static int hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev, 1515 struct hclge_pkt_buf_alloc *buf_alloc) 1516 { 1517 /* TX buffer size is unit by 128 byte */ 1518 #define HCLGE_BUF_SIZE_UNIT_SHIFT 7 1519 #define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15) 1520 struct hclge_tx_buff_alloc_cmd *req; 1521 struct hclge_desc desc; 1522 int ret; 1523 u8 i; 1524 1525 req = (struct hclge_tx_buff_alloc_cmd *)desc.data; 1526 1527 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0); 1528 for (i = 0; i < HCLGE_TC_NUM; i++) { 1529 u32 buf_size = buf_alloc->priv_buf[i].tx_buf_size; 1530 1531 req->tx_pkt_buff[i] = 1532 cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) | 1533 HCLGE_BUF_SIZE_UPDATE_EN_MSK); 1534 } 1535 1536 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1537 if (ret) { 1538 dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n", 1539 ret); 1540 return ret; 1541 } 1542 1543 return 0; 1544 } 1545 1546 static int hclge_tx_buffer_alloc(struct hclge_dev *hdev, 1547 struct hclge_pkt_buf_alloc *buf_alloc) 1548 { 1549 int ret = hclge_cmd_alloc_tx_buff(hdev, buf_alloc); 1550 1551 if (ret) { 1552 dev_err(&hdev->pdev->dev, 1553 "tx buffer alloc failed %d\n", ret); 1554 return ret; 1555 } 1556 1557 return 0; 1558 } 1559 1560 static int hclge_get_tc_num(struct hclge_dev *hdev) 1561 { 1562 int i, cnt = 0; 1563 1564 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) 1565 if (hdev->hw_tc_map & BIT(i)) 1566 cnt++; 1567 return cnt; 1568 } 1569 1570 static int hclge_get_pfc_enalbe_num(struct hclge_dev *hdev) 1571 { 1572 int i, cnt = 0; 1573 1574 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) 1575 if (hdev->hw_tc_map & BIT(i) && 1576 hdev->tm_info.hw_pfc_map & BIT(i)) 1577 cnt++; 1578 return cnt; 1579 } 1580 1581 /* Get the number of pfc enabled TCs, which have private buffer */ 1582 static int hclge_get_pfc_priv_num(struct hclge_dev *hdev, 1583 struct hclge_pkt_buf_alloc *buf_alloc) 1584 { 1585 struct hclge_priv_buf *priv; 1586 int i, cnt = 0; 1587 1588 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1589 priv = &buf_alloc->priv_buf[i]; 1590 if ((hdev->tm_info.hw_pfc_map & BIT(i)) && 1591 priv->enable) 1592 cnt++; 1593 } 1594 1595 return cnt; 1596 } 1597 1598 /* Get the number of pfc disabled TCs, which have private buffer */ 1599 static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev, 1600 struct hclge_pkt_buf_alloc *buf_alloc) 1601 { 1602 struct hclge_priv_buf *priv; 1603 int i, cnt = 0; 1604 1605 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1606 priv = &buf_alloc->priv_buf[i]; 1607 if (hdev->hw_tc_map & BIT(i) && 1608 !(hdev->tm_info.hw_pfc_map & BIT(i)) && 1609 priv->enable) 1610 cnt++; 1611 } 1612 1613 return cnt; 1614 } 1615 1616 static u32 hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc) 1617 { 1618 struct hclge_priv_buf *priv; 1619 u32 rx_priv = 0; 1620 int i; 1621 1622 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1623 priv = &buf_alloc->priv_buf[i]; 1624 if (priv->enable) 1625 rx_priv += priv->buf_size; 1626 } 1627 return rx_priv; 1628 } 1629 1630 static u32 hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc) 1631 { 1632 u32 i, total_tx_size = 0; 1633 1634 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) 1635 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size; 1636 1637 return total_tx_size; 1638 } 1639 1640 static bool hclge_is_rx_buf_ok(struct hclge_dev *hdev, 1641 struct hclge_pkt_buf_alloc *buf_alloc, 1642 u32 rx_all) 1643 { 1644 u32 shared_buf_min, shared_buf_tc, shared_std; 1645 int tc_num, pfc_enable_num; 1646 u32 shared_buf; 1647 u32 rx_priv; 1648 int i; 1649 1650 tc_num = hclge_get_tc_num(hdev); 1651 pfc_enable_num = hclge_get_pfc_enalbe_num(hdev); 1652 1653 if (hnae3_dev_dcb_supported(hdev)) 1654 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_DV; 1655 else 1656 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_NON_DCB_DV; 1657 1658 shared_buf_tc = pfc_enable_num * hdev->mps + 1659 (tc_num - pfc_enable_num) * hdev->mps / 2 + 1660 hdev->mps; 1661 shared_std = max_t(u32, shared_buf_min, shared_buf_tc); 1662 1663 rx_priv = hclge_get_rx_priv_buff_alloced(buf_alloc); 1664 if (rx_all <= rx_priv + shared_std) 1665 return false; 1666 1667 shared_buf = rx_all - rx_priv; 1668 buf_alloc->s_buf.buf_size = shared_buf; 1669 buf_alloc->s_buf.self.high = shared_buf; 1670 buf_alloc->s_buf.self.low = 2 * hdev->mps; 1671 1672 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1673 if ((hdev->hw_tc_map & BIT(i)) && 1674 (hdev->tm_info.hw_pfc_map & BIT(i))) { 1675 buf_alloc->s_buf.tc_thrd[i].low = hdev->mps; 1676 buf_alloc->s_buf.tc_thrd[i].high = 2 * hdev->mps; 1677 } else { 1678 buf_alloc->s_buf.tc_thrd[i].low = 0; 1679 buf_alloc->s_buf.tc_thrd[i].high = hdev->mps; 1680 } 1681 } 1682 1683 return true; 1684 } 1685 1686 static int hclge_tx_buffer_calc(struct hclge_dev *hdev, 1687 struct hclge_pkt_buf_alloc *buf_alloc) 1688 { 1689 u32 i, total_size; 1690 1691 total_size = hdev->pkt_buf_size; 1692 1693 /* alloc tx buffer for all enabled tc */ 1694 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1695 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 1696 1697 if (total_size < HCLGE_DEFAULT_TX_BUF) 1698 return -ENOMEM; 1699 1700 if (hdev->hw_tc_map & BIT(i)) 1701 priv->tx_buf_size = HCLGE_DEFAULT_TX_BUF; 1702 else 1703 priv->tx_buf_size = 0; 1704 1705 total_size -= priv->tx_buf_size; 1706 } 1707 1708 return 0; 1709 } 1710 1711 /* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs 1712 * @hdev: pointer to struct hclge_dev 1713 * @buf_alloc: pointer to buffer calculation data 1714 * @return: 0: calculate sucessful, negative: fail 1715 */ 1716 static int hclge_rx_buffer_calc(struct hclge_dev *hdev, 1717 struct hclge_pkt_buf_alloc *buf_alloc) 1718 { 1719 u32 rx_all = hdev->pkt_buf_size; 1720 int no_pfc_priv_num, pfc_priv_num; 1721 struct hclge_priv_buf *priv; 1722 int i; 1723 1724 rx_all -= hclge_get_tx_buff_alloced(buf_alloc); 1725 1726 /* When DCB is not supported, rx private 1727 * buffer is not allocated. 1728 */ 1729 if (!hnae3_dev_dcb_supported(hdev)) { 1730 if (!hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all)) 1731 return -ENOMEM; 1732 1733 return 0; 1734 } 1735 1736 /* step 1, try to alloc private buffer for all enabled tc */ 1737 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1738 priv = &buf_alloc->priv_buf[i]; 1739 if (hdev->hw_tc_map & BIT(i)) { 1740 priv->enable = 1; 1741 if (hdev->tm_info.hw_pfc_map & BIT(i)) { 1742 priv->wl.low = hdev->mps; 1743 priv->wl.high = priv->wl.low + hdev->mps; 1744 priv->buf_size = priv->wl.high + 1745 HCLGE_DEFAULT_DV; 1746 } else { 1747 priv->wl.low = 0; 1748 priv->wl.high = 2 * hdev->mps; 1749 priv->buf_size = priv->wl.high; 1750 } 1751 } else { 1752 priv->enable = 0; 1753 priv->wl.low = 0; 1754 priv->wl.high = 0; 1755 priv->buf_size = 0; 1756 } 1757 } 1758 1759 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all)) 1760 return 0; 1761 1762 /* step 2, try to decrease the buffer size of 1763 * no pfc TC's private buffer 1764 */ 1765 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1766 priv = &buf_alloc->priv_buf[i]; 1767 1768 priv->enable = 0; 1769 priv->wl.low = 0; 1770 priv->wl.high = 0; 1771 priv->buf_size = 0; 1772 1773 if (!(hdev->hw_tc_map & BIT(i))) 1774 continue; 1775 1776 priv->enable = 1; 1777 1778 if (hdev->tm_info.hw_pfc_map & BIT(i)) { 1779 priv->wl.low = 128; 1780 priv->wl.high = priv->wl.low + hdev->mps; 1781 priv->buf_size = priv->wl.high + HCLGE_DEFAULT_DV; 1782 } else { 1783 priv->wl.low = 0; 1784 priv->wl.high = hdev->mps; 1785 priv->buf_size = priv->wl.high; 1786 } 1787 } 1788 1789 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all)) 1790 return 0; 1791 1792 /* step 3, try to reduce the number of pfc disabled TCs, 1793 * which have private buffer 1794 */ 1795 /* get the total no pfc enable TC number, which have private buffer */ 1796 no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev, buf_alloc); 1797 1798 /* let the last to be cleared first */ 1799 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) { 1800 priv = &buf_alloc->priv_buf[i]; 1801 1802 if (hdev->hw_tc_map & BIT(i) && 1803 !(hdev->tm_info.hw_pfc_map & BIT(i))) { 1804 /* Clear the no pfc TC private buffer */ 1805 priv->wl.low = 0; 1806 priv->wl.high = 0; 1807 priv->buf_size = 0; 1808 priv->enable = 0; 1809 no_pfc_priv_num--; 1810 } 1811 1812 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) || 1813 no_pfc_priv_num == 0) 1814 break; 1815 } 1816 1817 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all)) 1818 return 0; 1819 1820 /* step 4, try to reduce the number of pfc enabled TCs 1821 * which have private buffer. 1822 */ 1823 pfc_priv_num = hclge_get_pfc_priv_num(hdev, buf_alloc); 1824 1825 /* let the last to be cleared first */ 1826 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) { 1827 priv = &buf_alloc->priv_buf[i]; 1828 1829 if (hdev->hw_tc_map & BIT(i) && 1830 hdev->tm_info.hw_pfc_map & BIT(i)) { 1831 /* Reduce the number of pfc TC with private buffer */ 1832 priv->wl.low = 0; 1833 priv->enable = 0; 1834 priv->wl.high = 0; 1835 priv->buf_size = 0; 1836 pfc_priv_num--; 1837 } 1838 1839 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) || 1840 pfc_priv_num == 0) 1841 break; 1842 } 1843 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all)) 1844 return 0; 1845 1846 return -ENOMEM; 1847 } 1848 1849 static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev, 1850 struct hclge_pkt_buf_alloc *buf_alloc) 1851 { 1852 struct hclge_rx_priv_buff_cmd *req; 1853 struct hclge_desc desc; 1854 int ret; 1855 int i; 1856 1857 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false); 1858 req = (struct hclge_rx_priv_buff_cmd *)desc.data; 1859 1860 /* Alloc private buffer TCs */ 1861 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1862 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 1863 1864 req->buf_num[i] = 1865 cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S); 1866 req->buf_num[i] |= 1867 cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B); 1868 } 1869 1870 req->shared_buf = 1871 cpu_to_le16((buf_alloc->s_buf.buf_size >> HCLGE_BUF_UNIT_S) | 1872 (1 << HCLGE_TC0_PRI_BUF_EN_B)); 1873 1874 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1875 if (ret) { 1876 dev_err(&hdev->pdev->dev, 1877 "rx private buffer alloc cmd failed %d\n", ret); 1878 return ret; 1879 } 1880 1881 return 0; 1882 } 1883 1884 #define HCLGE_PRIV_ENABLE(a) ((a) > 0 ? 1 : 0) 1885 1886 static int hclge_rx_priv_wl_config(struct hclge_dev *hdev, 1887 struct hclge_pkt_buf_alloc *buf_alloc) 1888 { 1889 struct hclge_rx_priv_wl_buf *req; 1890 struct hclge_priv_buf *priv; 1891 struct hclge_desc desc[2]; 1892 int i, j; 1893 int ret; 1894 1895 for (i = 0; i < 2; i++) { 1896 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC, 1897 false); 1898 req = (struct hclge_rx_priv_wl_buf *)desc[i].data; 1899 1900 /* The first descriptor set the NEXT bit to 1 */ 1901 if (i == 0) 1902 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 1903 else 1904 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 1905 1906 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) { 1907 u32 idx = i * HCLGE_TC_NUM_ONE_DESC + j; 1908 1909 priv = &buf_alloc->priv_buf[idx]; 1910 req->tc_wl[j].high = 1911 cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S); 1912 req->tc_wl[j].high |= 1913 cpu_to_le16(HCLGE_PRIV_ENABLE(priv->wl.high) << 1914 HCLGE_RX_PRIV_EN_B); 1915 req->tc_wl[j].low = 1916 cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S); 1917 req->tc_wl[j].low |= 1918 cpu_to_le16(HCLGE_PRIV_ENABLE(priv->wl.low) << 1919 HCLGE_RX_PRIV_EN_B); 1920 } 1921 } 1922 1923 /* Send 2 descriptor at one time */ 1924 ret = hclge_cmd_send(&hdev->hw, desc, 2); 1925 if (ret) { 1926 dev_err(&hdev->pdev->dev, 1927 "rx private waterline config cmd failed %d\n", 1928 ret); 1929 return ret; 1930 } 1931 return 0; 1932 } 1933 1934 static int hclge_common_thrd_config(struct hclge_dev *hdev, 1935 struct hclge_pkt_buf_alloc *buf_alloc) 1936 { 1937 struct hclge_shared_buf *s_buf = &buf_alloc->s_buf; 1938 struct hclge_rx_com_thrd *req; 1939 struct hclge_desc desc[2]; 1940 struct hclge_tc_thrd *tc; 1941 int i, j; 1942 int ret; 1943 1944 for (i = 0; i < 2; i++) { 1945 hclge_cmd_setup_basic_desc(&desc[i], 1946 HCLGE_OPC_RX_COM_THRD_ALLOC, false); 1947 req = (struct hclge_rx_com_thrd *)&desc[i].data; 1948 1949 /* The first descriptor set the NEXT bit to 1 */ 1950 if (i == 0) 1951 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 1952 else 1953 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 1954 1955 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) { 1956 tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j]; 1957 1958 req->com_thrd[j].high = 1959 cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S); 1960 req->com_thrd[j].high |= 1961 cpu_to_le16(HCLGE_PRIV_ENABLE(tc->high) << 1962 HCLGE_RX_PRIV_EN_B); 1963 req->com_thrd[j].low = 1964 cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S); 1965 req->com_thrd[j].low |= 1966 cpu_to_le16(HCLGE_PRIV_ENABLE(tc->low) << 1967 HCLGE_RX_PRIV_EN_B); 1968 } 1969 } 1970 1971 /* Send 2 descriptors at one time */ 1972 ret = hclge_cmd_send(&hdev->hw, desc, 2); 1973 if (ret) { 1974 dev_err(&hdev->pdev->dev, 1975 "common threshold config cmd failed %d\n", ret); 1976 return ret; 1977 } 1978 return 0; 1979 } 1980 1981 static int hclge_common_wl_config(struct hclge_dev *hdev, 1982 struct hclge_pkt_buf_alloc *buf_alloc) 1983 { 1984 struct hclge_shared_buf *buf = &buf_alloc->s_buf; 1985 struct hclge_rx_com_wl *req; 1986 struct hclge_desc desc; 1987 int ret; 1988 1989 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false); 1990 1991 req = (struct hclge_rx_com_wl *)desc.data; 1992 req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S); 1993 req->com_wl.high |= 1994 cpu_to_le16(HCLGE_PRIV_ENABLE(buf->self.high) << 1995 HCLGE_RX_PRIV_EN_B); 1996 1997 req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S); 1998 req->com_wl.low |= 1999 cpu_to_le16(HCLGE_PRIV_ENABLE(buf->self.low) << 2000 HCLGE_RX_PRIV_EN_B); 2001 2002 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2003 if (ret) { 2004 dev_err(&hdev->pdev->dev, 2005 "common waterline config cmd failed %d\n", ret); 2006 return ret; 2007 } 2008 2009 return 0; 2010 } 2011 2012 int hclge_buffer_alloc(struct hclge_dev *hdev) 2013 { 2014 struct hclge_pkt_buf_alloc *pkt_buf; 2015 int ret; 2016 2017 pkt_buf = kzalloc(sizeof(*pkt_buf), GFP_KERNEL); 2018 if (!pkt_buf) 2019 return -ENOMEM; 2020 2021 ret = hclge_tx_buffer_calc(hdev, pkt_buf); 2022 if (ret) { 2023 dev_err(&hdev->pdev->dev, 2024 "could not calc tx buffer size for all TCs %d\n", ret); 2025 goto out; 2026 } 2027 2028 ret = hclge_tx_buffer_alloc(hdev, pkt_buf); 2029 if (ret) { 2030 dev_err(&hdev->pdev->dev, 2031 "could not alloc tx buffers %d\n", ret); 2032 goto out; 2033 } 2034 2035 ret = hclge_rx_buffer_calc(hdev, pkt_buf); 2036 if (ret) { 2037 dev_err(&hdev->pdev->dev, 2038 "could not calc rx priv buffer size for all TCs %d\n", 2039 ret); 2040 goto out; 2041 } 2042 2043 ret = hclge_rx_priv_buf_alloc(hdev, pkt_buf); 2044 if (ret) { 2045 dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n", 2046 ret); 2047 goto out; 2048 } 2049 2050 if (hnae3_dev_dcb_supported(hdev)) { 2051 ret = hclge_rx_priv_wl_config(hdev, pkt_buf); 2052 if (ret) { 2053 dev_err(&hdev->pdev->dev, 2054 "could not configure rx private waterline %d\n", 2055 ret); 2056 goto out; 2057 } 2058 2059 ret = hclge_common_thrd_config(hdev, pkt_buf); 2060 if (ret) { 2061 dev_err(&hdev->pdev->dev, 2062 "could not configure common threshold %d\n", 2063 ret); 2064 goto out; 2065 } 2066 } 2067 2068 ret = hclge_common_wl_config(hdev, pkt_buf); 2069 if (ret) 2070 dev_err(&hdev->pdev->dev, 2071 "could not configure common waterline %d\n", ret); 2072 2073 out: 2074 kfree(pkt_buf); 2075 return ret; 2076 } 2077 2078 static int hclge_init_roce_base_info(struct hclge_vport *vport) 2079 { 2080 struct hnae3_handle *roce = &vport->roce; 2081 struct hnae3_handle *nic = &vport->nic; 2082 2083 roce->rinfo.num_vectors = vport->back->num_roce_msi; 2084 2085 if (vport->back->num_msi_left < vport->roce.rinfo.num_vectors || 2086 vport->back->num_msi_left == 0) 2087 return -EINVAL; 2088 2089 roce->rinfo.base_vector = vport->back->roce_base_vector; 2090 2091 roce->rinfo.netdev = nic->kinfo.netdev; 2092 roce->rinfo.roce_io_base = vport->back->hw.io_base; 2093 2094 roce->pdev = nic->pdev; 2095 roce->ae_algo = nic->ae_algo; 2096 roce->numa_node_mask = nic->numa_node_mask; 2097 2098 return 0; 2099 } 2100 2101 static int hclge_init_msi(struct hclge_dev *hdev) 2102 { 2103 struct pci_dev *pdev = hdev->pdev; 2104 int vectors; 2105 int i; 2106 2107 vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi, 2108 PCI_IRQ_MSI | PCI_IRQ_MSIX); 2109 if (vectors < 0) { 2110 dev_err(&pdev->dev, 2111 "failed(%d) to allocate MSI/MSI-X vectors\n", 2112 vectors); 2113 return vectors; 2114 } 2115 if (vectors < hdev->num_msi) 2116 dev_warn(&hdev->pdev->dev, 2117 "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n", 2118 hdev->num_msi, vectors); 2119 2120 hdev->num_msi = vectors; 2121 hdev->num_msi_left = vectors; 2122 hdev->base_msi_vector = pdev->irq; 2123 hdev->roce_base_vector = hdev->base_msi_vector + 2124 HCLGE_ROCE_VECTOR_OFFSET; 2125 2126 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2127 sizeof(u16), GFP_KERNEL); 2128 if (!hdev->vector_status) { 2129 pci_free_irq_vectors(pdev); 2130 return -ENOMEM; 2131 } 2132 2133 for (i = 0; i < hdev->num_msi; i++) 2134 hdev->vector_status[i] = HCLGE_INVALID_VPORT; 2135 2136 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2137 sizeof(int), GFP_KERNEL); 2138 if (!hdev->vector_irq) { 2139 pci_free_irq_vectors(pdev); 2140 return -ENOMEM; 2141 } 2142 2143 return 0; 2144 } 2145 2146 static void hclge_check_speed_dup(struct hclge_dev *hdev, int duplex, int speed) 2147 { 2148 struct hclge_mac *mac = &hdev->hw.mac; 2149 2150 if ((speed == HCLGE_MAC_SPEED_10M) || (speed == HCLGE_MAC_SPEED_100M)) 2151 mac->duplex = (u8)duplex; 2152 else 2153 mac->duplex = HCLGE_MAC_FULL; 2154 2155 mac->speed = speed; 2156 } 2157 2158 int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex) 2159 { 2160 struct hclge_config_mac_speed_dup_cmd *req; 2161 struct hclge_desc desc; 2162 int ret; 2163 2164 req = (struct hclge_config_mac_speed_dup_cmd *)desc.data; 2165 2166 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false); 2167 2168 hnae_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, !!duplex); 2169 2170 switch (speed) { 2171 case HCLGE_MAC_SPEED_10M: 2172 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, 2173 HCLGE_CFG_SPEED_S, 6); 2174 break; 2175 case HCLGE_MAC_SPEED_100M: 2176 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, 2177 HCLGE_CFG_SPEED_S, 7); 2178 break; 2179 case HCLGE_MAC_SPEED_1G: 2180 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, 2181 HCLGE_CFG_SPEED_S, 0); 2182 break; 2183 case HCLGE_MAC_SPEED_10G: 2184 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, 2185 HCLGE_CFG_SPEED_S, 1); 2186 break; 2187 case HCLGE_MAC_SPEED_25G: 2188 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, 2189 HCLGE_CFG_SPEED_S, 2); 2190 break; 2191 case HCLGE_MAC_SPEED_40G: 2192 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, 2193 HCLGE_CFG_SPEED_S, 3); 2194 break; 2195 case HCLGE_MAC_SPEED_50G: 2196 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, 2197 HCLGE_CFG_SPEED_S, 4); 2198 break; 2199 case HCLGE_MAC_SPEED_100G: 2200 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, 2201 HCLGE_CFG_SPEED_S, 5); 2202 break; 2203 default: 2204 dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed); 2205 return -EINVAL; 2206 } 2207 2208 hnae_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B, 2209 1); 2210 2211 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2212 if (ret) { 2213 dev_err(&hdev->pdev->dev, 2214 "mac speed/duplex config cmd failed %d.\n", ret); 2215 return ret; 2216 } 2217 2218 hclge_check_speed_dup(hdev, duplex, speed); 2219 2220 return 0; 2221 } 2222 2223 static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed, 2224 u8 duplex) 2225 { 2226 struct hclge_vport *vport = hclge_get_vport(handle); 2227 struct hclge_dev *hdev = vport->back; 2228 2229 return hclge_cfg_mac_speed_dup(hdev, speed, duplex); 2230 } 2231 2232 static int hclge_query_mac_an_speed_dup(struct hclge_dev *hdev, int *speed, 2233 u8 *duplex) 2234 { 2235 struct hclge_query_an_speed_dup_cmd *req; 2236 struct hclge_desc desc; 2237 int speed_tmp; 2238 int ret; 2239 2240 req = (struct hclge_query_an_speed_dup_cmd *)desc.data; 2241 2242 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_AN_RESULT, true); 2243 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2244 if (ret) { 2245 dev_err(&hdev->pdev->dev, 2246 "mac speed/autoneg/duplex query cmd failed %d\n", 2247 ret); 2248 return ret; 2249 } 2250 2251 *duplex = hnae_get_bit(req->an_syn_dup_speed, HCLGE_QUERY_DUPLEX_B); 2252 speed_tmp = hnae_get_field(req->an_syn_dup_speed, HCLGE_QUERY_SPEED_M, 2253 HCLGE_QUERY_SPEED_S); 2254 2255 ret = hclge_parse_speed(speed_tmp, speed); 2256 if (ret) { 2257 dev_err(&hdev->pdev->dev, 2258 "could not parse speed(=%d), %d\n", speed_tmp, ret); 2259 return -EIO; 2260 } 2261 2262 return 0; 2263 } 2264 2265 static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable) 2266 { 2267 struct hclge_config_auto_neg_cmd *req; 2268 struct hclge_desc desc; 2269 u32 flag = 0; 2270 int ret; 2271 2272 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false); 2273 2274 req = (struct hclge_config_auto_neg_cmd *)desc.data; 2275 hnae_set_bit(flag, HCLGE_MAC_CFG_AN_EN_B, !!enable); 2276 req->cfg_an_cmd_flag = cpu_to_le32(flag); 2277 2278 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2279 if (ret) { 2280 dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n", 2281 ret); 2282 return ret; 2283 } 2284 2285 return 0; 2286 } 2287 2288 static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable) 2289 { 2290 struct hclge_vport *vport = hclge_get_vport(handle); 2291 struct hclge_dev *hdev = vport->back; 2292 2293 return hclge_set_autoneg_en(hdev, enable); 2294 } 2295 2296 static int hclge_get_autoneg(struct hnae3_handle *handle) 2297 { 2298 struct hclge_vport *vport = hclge_get_vport(handle); 2299 struct hclge_dev *hdev = vport->back; 2300 struct phy_device *phydev = hdev->hw.mac.phydev; 2301 2302 if (phydev) 2303 return phydev->autoneg; 2304 2305 return hdev->hw.mac.autoneg; 2306 } 2307 2308 static int hclge_set_default_mac_vlan_mask(struct hclge_dev *hdev, 2309 bool mask_vlan, 2310 u8 *mac_mask) 2311 { 2312 struct hclge_mac_vlan_mask_entry_cmd *req; 2313 struct hclge_desc desc; 2314 int status; 2315 2316 req = (struct hclge_mac_vlan_mask_entry_cmd *)desc.data; 2317 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_MASK_SET, false); 2318 2319 hnae_set_bit(req->vlan_mask, HCLGE_VLAN_MASK_EN_B, 2320 mask_vlan ? 1 : 0); 2321 ether_addr_copy(req->mac_mask, mac_mask); 2322 2323 status = hclge_cmd_send(&hdev->hw, &desc, 1); 2324 if (status) 2325 dev_err(&hdev->pdev->dev, 2326 "Config mac_vlan_mask failed for cmd_send, ret =%d\n", 2327 status); 2328 2329 return status; 2330 } 2331 2332 static int hclge_mac_init(struct hclge_dev *hdev) 2333 { 2334 struct hnae3_handle *handle = &hdev->vport[0].nic; 2335 struct net_device *netdev = handle->kinfo.netdev; 2336 struct hclge_mac *mac = &hdev->hw.mac; 2337 u8 mac_mask[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; 2338 int mtu; 2339 int ret; 2340 2341 ret = hclge_cfg_mac_speed_dup(hdev, hdev->hw.mac.speed, HCLGE_MAC_FULL); 2342 if (ret) { 2343 dev_err(&hdev->pdev->dev, 2344 "Config mac speed dup fail ret=%d\n", ret); 2345 return ret; 2346 } 2347 2348 mac->link = 0; 2349 2350 /* Initialize the MTA table work mode */ 2351 hdev->accept_mta_mc = true; 2352 hdev->enable_mta = true; 2353 hdev->mta_mac_sel_type = HCLGE_MAC_ADDR_47_36; 2354 2355 ret = hclge_set_mta_filter_mode(hdev, 2356 hdev->mta_mac_sel_type, 2357 hdev->enable_mta); 2358 if (ret) { 2359 dev_err(&hdev->pdev->dev, "set mta filter mode failed %d\n", 2360 ret); 2361 return ret; 2362 } 2363 2364 ret = hclge_cfg_func_mta_filter(hdev, 0, hdev->accept_mta_mc); 2365 if (ret) { 2366 dev_err(&hdev->pdev->dev, 2367 "set mta filter mode fail ret=%d\n", ret); 2368 return ret; 2369 } 2370 2371 ret = hclge_set_default_mac_vlan_mask(hdev, true, mac_mask); 2372 if (ret) { 2373 dev_err(&hdev->pdev->dev, 2374 "set default mac_vlan_mask fail ret=%d\n", ret); 2375 return ret; 2376 } 2377 2378 if (netdev) 2379 mtu = netdev->mtu; 2380 else 2381 mtu = ETH_DATA_LEN; 2382 2383 ret = hclge_set_mtu(handle, mtu); 2384 if (ret) { 2385 dev_err(&hdev->pdev->dev, 2386 "set mtu failed ret=%d\n", ret); 2387 return ret; 2388 } 2389 2390 return 0; 2391 } 2392 2393 static void hclge_mbx_task_schedule(struct hclge_dev *hdev) 2394 { 2395 if (!test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state)) 2396 schedule_work(&hdev->mbx_service_task); 2397 } 2398 2399 static void hclge_reset_task_schedule(struct hclge_dev *hdev) 2400 { 2401 if (!test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state)) 2402 schedule_work(&hdev->rst_service_task); 2403 } 2404 2405 static void hclge_task_schedule(struct hclge_dev *hdev) 2406 { 2407 if (!test_bit(HCLGE_STATE_DOWN, &hdev->state) && 2408 !test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 2409 !test_and_set_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state)) 2410 (void)schedule_work(&hdev->service_task); 2411 } 2412 2413 static int hclge_get_mac_link_status(struct hclge_dev *hdev) 2414 { 2415 struct hclge_link_status_cmd *req; 2416 struct hclge_desc desc; 2417 int link_status; 2418 int ret; 2419 2420 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true); 2421 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2422 if (ret) { 2423 dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n", 2424 ret); 2425 return ret; 2426 } 2427 2428 req = (struct hclge_link_status_cmd *)desc.data; 2429 link_status = req->status & HCLGE_LINK_STATUS; 2430 2431 return !!link_status; 2432 } 2433 2434 static int hclge_get_mac_phy_link(struct hclge_dev *hdev) 2435 { 2436 int mac_state; 2437 int link_stat; 2438 2439 mac_state = hclge_get_mac_link_status(hdev); 2440 2441 if (hdev->hw.mac.phydev) { 2442 if (!genphy_read_status(hdev->hw.mac.phydev)) 2443 link_stat = mac_state & 2444 hdev->hw.mac.phydev->link; 2445 else 2446 link_stat = 0; 2447 2448 } else { 2449 link_stat = mac_state; 2450 } 2451 2452 return !!link_stat; 2453 } 2454 2455 static void hclge_update_link_status(struct hclge_dev *hdev) 2456 { 2457 struct hnae3_client *client = hdev->nic_client; 2458 struct hnae3_handle *handle; 2459 int state; 2460 int i; 2461 2462 if (!client) 2463 return; 2464 state = hclge_get_mac_phy_link(hdev); 2465 if (state != hdev->hw.mac.link) { 2466 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) { 2467 handle = &hdev->vport[i].nic; 2468 client->ops->link_status_change(handle, state); 2469 } 2470 hdev->hw.mac.link = state; 2471 } 2472 } 2473 2474 static int hclge_update_speed_duplex(struct hclge_dev *hdev) 2475 { 2476 struct hclge_mac mac = hdev->hw.mac; 2477 u8 duplex; 2478 int speed; 2479 int ret; 2480 2481 /* get the speed and duplex as autoneg'result from mac cmd when phy 2482 * doesn't exit. 2483 */ 2484 if (mac.phydev || !mac.autoneg) 2485 return 0; 2486 2487 ret = hclge_query_mac_an_speed_dup(hdev, &speed, &duplex); 2488 if (ret) { 2489 dev_err(&hdev->pdev->dev, 2490 "mac autoneg/speed/duplex query failed %d\n", ret); 2491 return ret; 2492 } 2493 2494 if ((mac.speed != speed) || (mac.duplex != duplex)) { 2495 ret = hclge_cfg_mac_speed_dup(hdev, speed, duplex); 2496 if (ret) { 2497 dev_err(&hdev->pdev->dev, 2498 "mac speed/duplex config failed %d\n", ret); 2499 return ret; 2500 } 2501 } 2502 2503 return 0; 2504 } 2505 2506 static int hclge_update_speed_duplex_h(struct hnae3_handle *handle) 2507 { 2508 struct hclge_vport *vport = hclge_get_vport(handle); 2509 struct hclge_dev *hdev = vport->back; 2510 2511 return hclge_update_speed_duplex(hdev); 2512 } 2513 2514 static int hclge_get_status(struct hnae3_handle *handle) 2515 { 2516 struct hclge_vport *vport = hclge_get_vport(handle); 2517 struct hclge_dev *hdev = vport->back; 2518 2519 hclge_update_link_status(hdev); 2520 2521 return hdev->hw.mac.link; 2522 } 2523 2524 static void hclge_service_timer(struct timer_list *t) 2525 { 2526 struct hclge_dev *hdev = from_timer(hdev, t, service_timer); 2527 2528 mod_timer(&hdev->service_timer, jiffies + HZ); 2529 hdev->hw_stats.stats_timer++; 2530 hclge_task_schedule(hdev); 2531 } 2532 2533 static void hclge_service_complete(struct hclge_dev *hdev) 2534 { 2535 WARN_ON(!test_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state)); 2536 2537 /* Flush memory before next watchdog */ 2538 smp_mb__before_atomic(); 2539 clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state); 2540 } 2541 2542 static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval) 2543 { 2544 u32 rst_src_reg; 2545 u32 cmdq_src_reg; 2546 2547 /* fetch the events from their corresponding regs */ 2548 rst_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG); 2549 cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG); 2550 2551 /* Assumption: If by any chance reset and mailbox events are reported 2552 * together then we will only process reset event in this go and will 2553 * defer the processing of the mailbox events. Since, we would have not 2554 * cleared RX CMDQ event this time we would receive again another 2555 * interrupt from H/W just for the mailbox. 2556 */ 2557 2558 /* check for vector0 reset event sources */ 2559 if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & rst_src_reg) { 2560 set_bit(HNAE3_GLOBAL_RESET, &hdev->reset_pending); 2561 *clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B); 2562 return HCLGE_VECTOR0_EVENT_RST; 2563 } 2564 2565 if (BIT(HCLGE_VECTOR0_CORERESET_INT_B) & rst_src_reg) { 2566 set_bit(HNAE3_CORE_RESET, &hdev->reset_pending); 2567 *clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B); 2568 return HCLGE_VECTOR0_EVENT_RST; 2569 } 2570 2571 if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & rst_src_reg) { 2572 set_bit(HNAE3_IMP_RESET, &hdev->reset_pending); 2573 *clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B); 2574 return HCLGE_VECTOR0_EVENT_RST; 2575 } 2576 2577 /* check for vector0 mailbox(=CMDQ RX) event source */ 2578 if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) { 2579 cmdq_src_reg &= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B); 2580 *clearval = cmdq_src_reg; 2581 return HCLGE_VECTOR0_EVENT_MBX; 2582 } 2583 2584 return HCLGE_VECTOR0_EVENT_OTHER; 2585 } 2586 2587 static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type, 2588 u32 regclr) 2589 { 2590 switch (event_type) { 2591 case HCLGE_VECTOR0_EVENT_RST: 2592 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr); 2593 break; 2594 case HCLGE_VECTOR0_EVENT_MBX: 2595 hclge_write_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG, regclr); 2596 break; 2597 } 2598 } 2599 2600 static void hclge_enable_vector(struct hclge_misc_vector *vector, bool enable) 2601 { 2602 writel(enable ? 1 : 0, vector->addr); 2603 } 2604 2605 static irqreturn_t hclge_misc_irq_handle(int irq, void *data) 2606 { 2607 struct hclge_dev *hdev = data; 2608 u32 event_cause; 2609 u32 clearval; 2610 2611 hclge_enable_vector(&hdev->misc_vector, false); 2612 event_cause = hclge_check_event_cause(hdev, &clearval); 2613 2614 /* vector 0 interrupt is shared with reset and mailbox source events.*/ 2615 switch (event_cause) { 2616 case HCLGE_VECTOR0_EVENT_RST: 2617 hclge_reset_task_schedule(hdev); 2618 break; 2619 case HCLGE_VECTOR0_EVENT_MBX: 2620 /* If we are here then, 2621 * 1. Either we are not handling any mbx task and we are not 2622 * scheduled as well 2623 * OR 2624 * 2. We could be handling a mbx task but nothing more is 2625 * scheduled. 2626 * In both cases, we should schedule mbx task as there are more 2627 * mbx messages reported by this interrupt. 2628 */ 2629 hclge_mbx_task_schedule(hdev); 2630 2631 default: 2632 dev_dbg(&hdev->pdev->dev, 2633 "received unknown or unhandled event of vector0\n"); 2634 break; 2635 } 2636 2637 /* we should clear the source of interrupt */ 2638 hclge_clear_event_cause(hdev, event_cause, clearval); 2639 hclge_enable_vector(&hdev->misc_vector, true); 2640 2641 return IRQ_HANDLED; 2642 } 2643 2644 static void hclge_free_vector(struct hclge_dev *hdev, int vector_id) 2645 { 2646 hdev->vector_status[vector_id] = HCLGE_INVALID_VPORT; 2647 hdev->num_msi_left += 1; 2648 hdev->num_msi_used -= 1; 2649 } 2650 2651 static void hclge_get_misc_vector(struct hclge_dev *hdev) 2652 { 2653 struct hclge_misc_vector *vector = &hdev->misc_vector; 2654 2655 vector->vector_irq = pci_irq_vector(hdev->pdev, 0); 2656 2657 vector->addr = hdev->hw.io_base + HCLGE_MISC_VECTOR_REG_BASE; 2658 hdev->vector_status[0] = 0; 2659 2660 hdev->num_msi_left -= 1; 2661 hdev->num_msi_used += 1; 2662 } 2663 2664 static int hclge_misc_irq_init(struct hclge_dev *hdev) 2665 { 2666 int ret; 2667 2668 hclge_get_misc_vector(hdev); 2669 2670 /* this would be explicitly freed in the end */ 2671 ret = request_irq(hdev->misc_vector.vector_irq, hclge_misc_irq_handle, 2672 0, "hclge_misc", hdev); 2673 if (ret) { 2674 hclge_free_vector(hdev, 0); 2675 dev_err(&hdev->pdev->dev, "request misc irq(%d) fail\n", 2676 hdev->misc_vector.vector_irq); 2677 } 2678 2679 return ret; 2680 } 2681 2682 static void hclge_misc_irq_uninit(struct hclge_dev *hdev) 2683 { 2684 free_irq(hdev->misc_vector.vector_irq, hdev); 2685 hclge_free_vector(hdev, 0); 2686 } 2687 2688 static int hclge_notify_client(struct hclge_dev *hdev, 2689 enum hnae3_reset_notify_type type) 2690 { 2691 struct hnae3_client *client = hdev->nic_client; 2692 u16 i; 2693 2694 if (!client->ops->reset_notify) 2695 return -EOPNOTSUPP; 2696 2697 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) { 2698 struct hnae3_handle *handle = &hdev->vport[i].nic; 2699 int ret; 2700 2701 ret = client->ops->reset_notify(handle, type); 2702 if (ret) 2703 return ret; 2704 } 2705 2706 return 0; 2707 } 2708 2709 static int hclge_reset_wait(struct hclge_dev *hdev) 2710 { 2711 #define HCLGE_RESET_WATI_MS 100 2712 #define HCLGE_RESET_WAIT_CNT 5 2713 u32 val, reg, reg_bit; 2714 u32 cnt = 0; 2715 2716 switch (hdev->reset_type) { 2717 case HNAE3_GLOBAL_RESET: 2718 reg = HCLGE_GLOBAL_RESET_REG; 2719 reg_bit = HCLGE_GLOBAL_RESET_BIT; 2720 break; 2721 case HNAE3_CORE_RESET: 2722 reg = HCLGE_GLOBAL_RESET_REG; 2723 reg_bit = HCLGE_CORE_RESET_BIT; 2724 break; 2725 case HNAE3_FUNC_RESET: 2726 reg = HCLGE_FUN_RST_ING; 2727 reg_bit = HCLGE_FUN_RST_ING_B; 2728 break; 2729 default: 2730 dev_err(&hdev->pdev->dev, 2731 "Wait for unsupported reset type: %d\n", 2732 hdev->reset_type); 2733 return -EINVAL; 2734 } 2735 2736 val = hclge_read_dev(&hdev->hw, reg); 2737 while (hnae_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) { 2738 msleep(HCLGE_RESET_WATI_MS); 2739 val = hclge_read_dev(&hdev->hw, reg); 2740 cnt++; 2741 } 2742 2743 if (cnt >= HCLGE_RESET_WAIT_CNT) { 2744 dev_warn(&hdev->pdev->dev, 2745 "Wait for reset timeout: %d\n", hdev->reset_type); 2746 return -EBUSY; 2747 } 2748 2749 return 0; 2750 } 2751 2752 int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id) 2753 { 2754 struct hclge_desc desc; 2755 struct hclge_reset_cmd *req = (struct hclge_reset_cmd *)desc.data; 2756 int ret; 2757 2758 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false); 2759 hnae_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_MAC_B, 0); 2760 hnae_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_FUNC_B, 1); 2761 req->fun_reset_vfid = func_id; 2762 2763 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2764 if (ret) 2765 dev_err(&hdev->pdev->dev, 2766 "send function reset cmd fail, status =%d\n", ret); 2767 2768 return ret; 2769 } 2770 2771 static void hclge_do_reset(struct hclge_dev *hdev) 2772 { 2773 struct pci_dev *pdev = hdev->pdev; 2774 u32 val; 2775 2776 switch (hdev->reset_type) { 2777 case HNAE3_GLOBAL_RESET: 2778 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG); 2779 hnae_set_bit(val, HCLGE_GLOBAL_RESET_BIT, 1); 2780 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val); 2781 dev_info(&pdev->dev, "Global Reset requested\n"); 2782 break; 2783 case HNAE3_CORE_RESET: 2784 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG); 2785 hnae_set_bit(val, HCLGE_CORE_RESET_BIT, 1); 2786 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val); 2787 dev_info(&pdev->dev, "Core Reset requested\n"); 2788 break; 2789 case HNAE3_FUNC_RESET: 2790 dev_info(&pdev->dev, "PF Reset requested\n"); 2791 hclge_func_reset_cmd(hdev, 0); 2792 /* schedule again to check later */ 2793 set_bit(HNAE3_FUNC_RESET, &hdev->reset_pending); 2794 hclge_reset_task_schedule(hdev); 2795 break; 2796 default: 2797 dev_warn(&pdev->dev, 2798 "Unsupported reset type: %d\n", hdev->reset_type); 2799 break; 2800 } 2801 } 2802 2803 static enum hnae3_reset_type hclge_get_reset_level(struct hclge_dev *hdev, 2804 unsigned long *addr) 2805 { 2806 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 2807 2808 /* return the highest priority reset level amongst all */ 2809 if (test_bit(HNAE3_GLOBAL_RESET, addr)) 2810 rst_level = HNAE3_GLOBAL_RESET; 2811 else if (test_bit(HNAE3_CORE_RESET, addr)) 2812 rst_level = HNAE3_CORE_RESET; 2813 else if (test_bit(HNAE3_IMP_RESET, addr)) 2814 rst_level = HNAE3_IMP_RESET; 2815 else if (test_bit(HNAE3_FUNC_RESET, addr)) 2816 rst_level = HNAE3_FUNC_RESET; 2817 2818 /* now, clear all other resets */ 2819 clear_bit(HNAE3_GLOBAL_RESET, addr); 2820 clear_bit(HNAE3_CORE_RESET, addr); 2821 clear_bit(HNAE3_IMP_RESET, addr); 2822 clear_bit(HNAE3_FUNC_RESET, addr); 2823 2824 return rst_level; 2825 } 2826 2827 static void hclge_reset(struct hclge_dev *hdev) 2828 { 2829 /* perform reset of the stack & ae device for a client */ 2830 2831 hclge_notify_client(hdev, HNAE3_DOWN_CLIENT); 2832 2833 if (!hclge_reset_wait(hdev)) { 2834 rtnl_lock(); 2835 hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT); 2836 hclge_reset_ae_dev(hdev->ae_dev); 2837 hclge_notify_client(hdev, HNAE3_INIT_CLIENT); 2838 rtnl_unlock(); 2839 } else { 2840 /* schedule again to check pending resets later */ 2841 set_bit(hdev->reset_type, &hdev->reset_pending); 2842 hclge_reset_task_schedule(hdev); 2843 } 2844 2845 hclge_notify_client(hdev, HNAE3_UP_CLIENT); 2846 } 2847 2848 static void hclge_reset_event(struct hnae3_handle *handle) 2849 { 2850 struct hclge_vport *vport = hclge_get_vport(handle); 2851 struct hclge_dev *hdev = vport->back; 2852 2853 /* check if this is a new reset request and we are not here just because 2854 * last reset attempt did not succeed and watchdog hit us again. We will 2855 * know this if last reset request did not occur very recently (watchdog 2856 * timer = 5*HZ, let us check after sufficiently large time, say 4*5*Hz) 2857 * In case of new request we reset the "reset level" to PF reset. 2858 */ 2859 if (time_after(jiffies, (handle->last_reset_time + 4 * 5 * HZ))) 2860 handle->reset_level = HNAE3_FUNC_RESET; 2861 2862 dev_info(&hdev->pdev->dev, "received reset event , reset type is %d", 2863 handle->reset_level); 2864 2865 /* request reset & schedule reset task */ 2866 set_bit(handle->reset_level, &hdev->reset_request); 2867 hclge_reset_task_schedule(hdev); 2868 2869 if (handle->reset_level < HNAE3_GLOBAL_RESET) 2870 handle->reset_level++; 2871 2872 handle->last_reset_time = jiffies; 2873 } 2874 2875 static void hclge_reset_subtask(struct hclge_dev *hdev) 2876 { 2877 /* check if there is any ongoing reset in the hardware. This status can 2878 * be checked from reset_pending. If there is then, we need to wait for 2879 * hardware to complete reset. 2880 * a. If we are able to figure out in reasonable time that hardware 2881 * has fully resetted then, we can proceed with driver, client 2882 * reset. 2883 * b. else, we can come back later to check this status so re-sched 2884 * now. 2885 */ 2886 hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_pending); 2887 if (hdev->reset_type != HNAE3_NONE_RESET) 2888 hclge_reset(hdev); 2889 2890 /* check if we got any *new* reset requests to be honored */ 2891 hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_request); 2892 if (hdev->reset_type != HNAE3_NONE_RESET) 2893 hclge_do_reset(hdev); 2894 2895 hdev->reset_type = HNAE3_NONE_RESET; 2896 } 2897 2898 static void hclge_reset_service_task(struct work_struct *work) 2899 { 2900 struct hclge_dev *hdev = 2901 container_of(work, struct hclge_dev, rst_service_task); 2902 2903 if (test_and_set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 2904 return; 2905 2906 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state); 2907 2908 hclge_reset_subtask(hdev); 2909 2910 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 2911 } 2912 2913 static void hclge_mailbox_service_task(struct work_struct *work) 2914 { 2915 struct hclge_dev *hdev = 2916 container_of(work, struct hclge_dev, mbx_service_task); 2917 2918 if (test_and_set_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state)) 2919 return; 2920 2921 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state); 2922 2923 hclge_mbx_handler(hdev); 2924 2925 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state); 2926 } 2927 2928 static void hclge_service_task(struct work_struct *work) 2929 { 2930 struct hclge_dev *hdev = 2931 container_of(work, struct hclge_dev, service_task); 2932 2933 /* The total rx/tx packets statstics are wanted to be updated 2934 * per second. Both hclge_update_stats_for_all() and 2935 * hclge_mac_get_traffic_stats() can do it. 2936 */ 2937 if (hdev->hw_stats.stats_timer >= HCLGE_STATS_TIMER_INTERVAL) { 2938 hclge_update_stats_for_all(hdev); 2939 hdev->hw_stats.stats_timer = 0; 2940 } else { 2941 hclge_mac_get_traffic_stats(hdev); 2942 } 2943 2944 hclge_update_speed_duplex(hdev); 2945 hclge_update_link_status(hdev); 2946 hclge_update_led_status(hdev); 2947 hclge_service_complete(hdev); 2948 } 2949 2950 static void hclge_disable_sriov(struct hclge_dev *hdev) 2951 { 2952 /* If our VFs are assigned we cannot shut down SR-IOV 2953 * without causing issues, so just leave the hardware 2954 * available but disabled 2955 */ 2956 if (pci_vfs_assigned(hdev->pdev)) { 2957 dev_warn(&hdev->pdev->dev, 2958 "disabling driver while VFs are assigned\n"); 2959 return; 2960 } 2961 2962 pci_disable_sriov(hdev->pdev); 2963 } 2964 2965 struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle) 2966 { 2967 /* VF handle has no client */ 2968 if (!handle->client) 2969 return container_of(handle, struct hclge_vport, nic); 2970 else if (handle->client->type == HNAE3_CLIENT_ROCE) 2971 return container_of(handle, struct hclge_vport, roce); 2972 else 2973 return container_of(handle, struct hclge_vport, nic); 2974 } 2975 2976 static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num, 2977 struct hnae3_vector_info *vector_info) 2978 { 2979 struct hclge_vport *vport = hclge_get_vport(handle); 2980 struct hnae3_vector_info *vector = vector_info; 2981 struct hclge_dev *hdev = vport->back; 2982 int alloc = 0; 2983 int i, j; 2984 2985 vector_num = min(hdev->num_msi_left, vector_num); 2986 2987 for (j = 0; j < vector_num; j++) { 2988 for (i = 1; i < hdev->num_msi; i++) { 2989 if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) { 2990 vector->vector = pci_irq_vector(hdev->pdev, i); 2991 vector->io_addr = hdev->hw.io_base + 2992 HCLGE_VECTOR_REG_BASE + 2993 (i - 1) * HCLGE_VECTOR_REG_OFFSET + 2994 vport->vport_id * 2995 HCLGE_VECTOR_VF_OFFSET; 2996 hdev->vector_status[i] = vport->vport_id; 2997 hdev->vector_irq[i] = vector->vector; 2998 2999 vector++; 3000 alloc++; 3001 3002 break; 3003 } 3004 } 3005 } 3006 hdev->num_msi_left -= alloc; 3007 hdev->num_msi_used += alloc; 3008 3009 return alloc; 3010 } 3011 3012 static int hclge_get_vector_index(struct hclge_dev *hdev, int vector) 3013 { 3014 int i; 3015 3016 for (i = 0; i < hdev->num_msi; i++) 3017 if (vector == hdev->vector_irq[i]) 3018 return i; 3019 3020 return -EINVAL; 3021 } 3022 3023 static int hclge_put_vector(struct hnae3_handle *handle, int vector) 3024 { 3025 struct hclge_vport *vport = hclge_get_vport(handle); 3026 struct hclge_dev *hdev = vport->back; 3027 int vector_id; 3028 3029 vector_id = hclge_get_vector_index(hdev, vector); 3030 if (vector_id < 0) { 3031 dev_err(&hdev->pdev->dev, 3032 "Get vector index fail. vector_id =%d\n", vector_id); 3033 return vector_id; 3034 } 3035 3036 hclge_free_vector(hdev, vector_id); 3037 3038 return 0; 3039 } 3040 3041 static u32 hclge_get_rss_key_size(struct hnae3_handle *handle) 3042 { 3043 return HCLGE_RSS_KEY_SIZE; 3044 } 3045 3046 static u32 hclge_get_rss_indir_size(struct hnae3_handle *handle) 3047 { 3048 return HCLGE_RSS_IND_TBL_SIZE; 3049 } 3050 3051 static int hclge_set_rss_algo_key(struct hclge_dev *hdev, 3052 const u8 hfunc, const u8 *key) 3053 { 3054 struct hclge_rss_config_cmd *req; 3055 struct hclge_desc desc; 3056 int key_offset; 3057 int key_size; 3058 int ret; 3059 3060 req = (struct hclge_rss_config_cmd *)desc.data; 3061 3062 for (key_offset = 0; key_offset < 3; key_offset++) { 3063 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_GENERIC_CONFIG, 3064 false); 3065 3066 req->hash_config |= (hfunc & HCLGE_RSS_HASH_ALGO_MASK); 3067 req->hash_config |= (key_offset << HCLGE_RSS_HASH_KEY_OFFSET_B); 3068 3069 if (key_offset == 2) 3070 key_size = 3071 HCLGE_RSS_KEY_SIZE - HCLGE_RSS_HASH_KEY_NUM * 2; 3072 else 3073 key_size = HCLGE_RSS_HASH_KEY_NUM; 3074 3075 memcpy(req->hash_key, 3076 key + key_offset * HCLGE_RSS_HASH_KEY_NUM, key_size); 3077 3078 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3079 if (ret) { 3080 dev_err(&hdev->pdev->dev, 3081 "Configure RSS config fail, status = %d\n", 3082 ret); 3083 return ret; 3084 } 3085 } 3086 return 0; 3087 } 3088 3089 static int hclge_set_rss_indir_table(struct hclge_dev *hdev, const u8 *indir) 3090 { 3091 struct hclge_rss_indirection_table_cmd *req; 3092 struct hclge_desc desc; 3093 int i, j; 3094 int ret; 3095 3096 req = (struct hclge_rss_indirection_table_cmd *)desc.data; 3097 3098 for (i = 0; i < HCLGE_RSS_CFG_TBL_NUM; i++) { 3099 hclge_cmd_setup_basic_desc 3100 (&desc, HCLGE_OPC_RSS_INDIR_TABLE, false); 3101 3102 req->start_table_index = 3103 cpu_to_le16(i * HCLGE_RSS_CFG_TBL_SIZE); 3104 req->rss_set_bitmap = cpu_to_le16(HCLGE_RSS_SET_BITMAP_MSK); 3105 3106 for (j = 0; j < HCLGE_RSS_CFG_TBL_SIZE; j++) 3107 req->rss_result[j] = 3108 indir[i * HCLGE_RSS_CFG_TBL_SIZE + j]; 3109 3110 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3111 if (ret) { 3112 dev_err(&hdev->pdev->dev, 3113 "Configure rss indir table fail,status = %d\n", 3114 ret); 3115 return ret; 3116 } 3117 } 3118 return 0; 3119 } 3120 3121 static int hclge_set_rss_tc_mode(struct hclge_dev *hdev, u16 *tc_valid, 3122 u16 *tc_size, u16 *tc_offset) 3123 { 3124 struct hclge_rss_tc_mode_cmd *req; 3125 struct hclge_desc desc; 3126 int ret; 3127 int i; 3128 3129 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_TC_MODE, false); 3130 req = (struct hclge_rss_tc_mode_cmd *)desc.data; 3131 3132 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 3133 u16 mode = 0; 3134 3135 hnae_set_bit(mode, HCLGE_RSS_TC_VALID_B, (tc_valid[i] & 0x1)); 3136 hnae_set_field(mode, HCLGE_RSS_TC_SIZE_M, 3137 HCLGE_RSS_TC_SIZE_S, tc_size[i]); 3138 hnae_set_field(mode, HCLGE_RSS_TC_OFFSET_M, 3139 HCLGE_RSS_TC_OFFSET_S, tc_offset[i]); 3140 3141 req->rss_tc_mode[i] = cpu_to_le16(mode); 3142 } 3143 3144 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3145 if (ret) { 3146 dev_err(&hdev->pdev->dev, 3147 "Configure rss tc mode fail, status = %d\n", ret); 3148 return ret; 3149 } 3150 3151 return 0; 3152 } 3153 3154 static int hclge_set_rss_input_tuple(struct hclge_dev *hdev) 3155 { 3156 struct hclge_rss_input_tuple_cmd *req; 3157 struct hclge_desc desc; 3158 int ret; 3159 3160 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false); 3161 3162 req = (struct hclge_rss_input_tuple_cmd *)desc.data; 3163 3164 /* Get the tuple cfg from pf */ 3165 req->ipv4_tcp_en = hdev->vport[0].rss_tuple_sets.ipv4_tcp_en; 3166 req->ipv4_udp_en = hdev->vport[0].rss_tuple_sets.ipv4_udp_en; 3167 req->ipv4_sctp_en = hdev->vport[0].rss_tuple_sets.ipv4_sctp_en; 3168 req->ipv4_fragment_en = hdev->vport[0].rss_tuple_sets.ipv4_fragment_en; 3169 req->ipv6_tcp_en = hdev->vport[0].rss_tuple_sets.ipv6_tcp_en; 3170 req->ipv6_udp_en = hdev->vport[0].rss_tuple_sets.ipv6_udp_en; 3171 req->ipv6_sctp_en = hdev->vport[0].rss_tuple_sets.ipv6_sctp_en; 3172 req->ipv6_fragment_en = hdev->vport[0].rss_tuple_sets.ipv6_fragment_en; 3173 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3174 if (ret) { 3175 dev_err(&hdev->pdev->dev, 3176 "Configure rss input fail, status = %d\n", ret); 3177 return ret; 3178 } 3179 3180 return 0; 3181 } 3182 3183 static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir, 3184 u8 *key, u8 *hfunc) 3185 { 3186 struct hclge_vport *vport = hclge_get_vport(handle); 3187 int i; 3188 3189 /* Get hash algorithm */ 3190 if (hfunc) 3191 *hfunc = vport->rss_algo; 3192 3193 /* Get the RSS Key required by the user */ 3194 if (key) 3195 memcpy(key, vport->rss_hash_key, HCLGE_RSS_KEY_SIZE); 3196 3197 /* Get indirect table */ 3198 if (indir) 3199 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++) 3200 indir[i] = vport->rss_indirection_tbl[i]; 3201 3202 return 0; 3203 } 3204 3205 static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir, 3206 const u8 *key, const u8 hfunc) 3207 { 3208 struct hclge_vport *vport = hclge_get_vport(handle); 3209 struct hclge_dev *hdev = vport->back; 3210 u8 hash_algo; 3211 int ret, i; 3212 3213 /* Set the RSS Hash Key if specififed by the user */ 3214 if (key) { 3215 3216 if (hfunc == ETH_RSS_HASH_TOP || 3217 hfunc == ETH_RSS_HASH_NO_CHANGE) 3218 hash_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ; 3219 else 3220 return -EINVAL; 3221 ret = hclge_set_rss_algo_key(hdev, hash_algo, key); 3222 if (ret) 3223 return ret; 3224 3225 /* Update the shadow RSS key with user specified qids */ 3226 memcpy(vport->rss_hash_key, key, HCLGE_RSS_KEY_SIZE); 3227 vport->rss_algo = hash_algo; 3228 } 3229 3230 /* Update the shadow RSS table with user specified qids */ 3231 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++) 3232 vport->rss_indirection_tbl[i] = indir[i]; 3233 3234 /* Update the hardware */ 3235 return hclge_set_rss_indir_table(hdev, vport->rss_indirection_tbl); 3236 } 3237 3238 static u8 hclge_get_rss_hash_bits(struct ethtool_rxnfc *nfc) 3239 { 3240 u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGE_S_PORT_BIT : 0; 3241 3242 if (nfc->data & RXH_L4_B_2_3) 3243 hash_sets |= HCLGE_D_PORT_BIT; 3244 else 3245 hash_sets &= ~HCLGE_D_PORT_BIT; 3246 3247 if (nfc->data & RXH_IP_SRC) 3248 hash_sets |= HCLGE_S_IP_BIT; 3249 else 3250 hash_sets &= ~HCLGE_S_IP_BIT; 3251 3252 if (nfc->data & RXH_IP_DST) 3253 hash_sets |= HCLGE_D_IP_BIT; 3254 else 3255 hash_sets &= ~HCLGE_D_IP_BIT; 3256 3257 if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW) 3258 hash_sets |= HCLGE_V_TAG_BIT; 3259 3260 return hash_sets; 3261 } 3262 3263 static int hclge_set_rss_tuple(struct hnae3_handle *handle, 3264 struct ethtool_rxnfc *nfc) 3265 { 3266 struct hclge_vport *vport = hclge_get_vport(handle); 3267 struct hclge_dev *hdev = vport->back; 3268 struct hclge_rss_input_tuple_cmd *req; 3269 struct hclge_desc desc; 3270 u8 tuple_sets; 3271 int ret; 3272 3273 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST | 3274 RXH_L4_B_0_1 | RXH_L4_B_2_3)) 3275 return -EINVAL; 3276 3277 req = (struct hclge_rss_input_tuple_cmd *)desc.data; 3278 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false); 3279 3280 req->ipv4_tcp_en = vport->rss_tuple_sets.ipv4_tcp_en; 3281 req->ipv4_udp_en = vport->rss_tuple_sets.ipv4_udp_en; 3282 req->ipv4_sctp_en = vport->rss_tuple_sets.ipv4_sctp_en; 3283 req->ipv4_fragment_en = vport->rss_tuple_sets.ipv4_fragment_en; 3284 req->ipv6_tcp_en = vport->rss_tuple_sets.ipv6_tcp_en; 3285 req->ipv6_udp_en = vport->rss_tuple_sets.ipv6_udp_en; 3286 req->ipv6_sctp_en = vport->rss_tuple_sets.ipv6_sctp_en; 3287 req->ipv6_fragment_en = vport->rss_tuple_sets.ipv6_fragment_en; 3288 3289 tuple_sets = hclge_get_rss_hash_bits(nfc); 3290 switch (nfc->flow_type) { 3291 case TCP_V4_FLOW: 3292 req->ipv4_tcp_en = tuple_sets; 3293 break; 3294 case TCP_V6_FLOW: 3295 req->ipv6_tcp_en = tuple_sets; 3296 break; 3297 case UDP_V4_FLOW: 3298 req->ipv4_udp_en = tuple_sets; 3299 break; 3300 case UDP_V6_FLOW: 3301 req->ipv6_udp_en = tuple_sets; 3302 break; 3303 case SCTP_V4_FLOW: 3304 req->ipv4_sctp_en = tuple_sets; 3305 break; 3306 case SCTP_V6_FLOW: 3307 if ((nfc->data & RXH_L4_B_0_1) || 3308 (nfc->data & RXH_L4_B_2_3)) 3309 return -EINVAL; 3310 3311 req->ipv6_sctp_en = tuple_sets; 3312 break; 3313 case IPV4_FLOW: 3314 req->ipv4_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER; 3315 break; 3316 case IPV6_FLOW: 3317 req->ipv6_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER; 3318 break; 3319 default: 3320 return -EINVAL; 3321 } 3322 3323 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3324 if (ret) { 3325 dev_err(&hdev->pdev->dev, 3326 "Set rss tuple fail, status = %d\n", ret); 3327 return ret; 3328 } 3329 3330 vport->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en; 3331 vport->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en; 3332 vport->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en; 3333 vport->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en; 3334 vport->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en; 3335 vport->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en; 3336 vport->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en; 3337 vport->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en; 3338 return 0; 3339 } 3340 3341 static int hclge_get_rss_tuple(struct hnae3_handle *handle, 3342 struct ethtool_rxnfc *nfc) 3343 { 3344 struct hclge_vport *vport = hclge_get_vport(handle); 3345 u8 tuple_sets; 3346 3347 nfc->data = 0; 3348 3349 switch (nfc->flow_type) { 3350 case TCP_V4_FLOW: 3351 tuple_sets = vport->rss_tuple_sets.ipv4_tcp_en; 3352 break; 3353 case UDP_V4_FLOW: 3354 tuple_sets = vport->rss_tuple_sets.ipv4_udp_en; 3355 break; 3356 case TCP_V6_FLOW: 3357 tuple_sets = vport->rss_tuple_sets.ipv6_tcp_en; 3358 break; 3359 case UDP_V6_FLOW: 3360 tuple_sets = vport->rss_tuple_sets.ipv6_udp_en; 3361 break; 3362 case SCTP_V4_FLOW: 3363 tuple_sets = vport->rss_tuple_sets.ipv4_sctp_en; 3364 break; 3365 case SCTP_V6_FLOW: 3366 tuple_sets = vport->rss_tuple_sets.ipv6_sctp_en; 3367 break; 3368 case IPV4_FLOW: 3369 case IPV6_FLOW: 3370 tuple_sets = HCLGE_S_IP_BIT | HCLGE_D_IP_BIT; 3371 break; 3372 default: 3373 return -EINVAL; 3374 } 3375 3376 if (!tuple_sets) 3377 return 0; 3378 3379 if (tuple_sets & HCLGE_D_PORT_BIT) 3380 nfc->data |= RXH_L4_B_2_3; 3381 if (tuple_sets & HCLGE_S_PORT_BIT) 3382 nfc->data |= RXH_L4_B_0_1; 3383 if (tuple_sets & HCLGE_D_IP_BIT) 3384 nfc->data |= RXH_IP_DST; 3385 if (tuple_sets & HCLGE_S_IP_BIT) 3386 nfc->data |= RXH_IP_SRC; 3387 3388 return 0; 3389 } 3390 3391 static int hclge_get_tc_size(struct hnae3_handle *handle) 3392 { 3393 struct hclge_vport *vport = hclge_get_vport(handle); 3394 struct hclge_dev *hdev = vport->back; 3395 3396 return hdev->rss_size_max; 3397 } 3398 3399 int hclge_rss_init_hw(struct hclge_dev *hdev) 3400 { 3401 struct hclge_vport *vport = hdev->vport; 3402 u8 *rss_indir = vport[0].rss_indirection_tbl; 3403 u16 rss_size = vport[0].alloc_rss_size; 3404 u8 *key = vport[0].rss_hash_key; 3405 u8 hfunc = vport[0].rss_algo; 3406 u16 tc_offset[HCLGE_MAX_TC_NUM]; 3407 u16 tc_valid[HCLGE_MAX_TC_NUM]; 3408 u16 tc_size[HCLGE_MAX_TC_NUM]; 3409 u16 roundup_size; 3410 int i, ret; 3411 3412 ret = hclge_set_rss_indir_table(hdev, rss_indir); 3413 if (ret) 3414 return ret; 3415 3416 ret = hclge_set_rss_algo_key(hdev, hfunc, key); 3417 if (ret) 3418 return ret; 3419 3420 ret = hclge_set_rss_input_tuple(hdev); 3421 if (ret) 3422 return ret; 3423 3424 /* Each TC have the same queue size, and tc_size set to hardware is 3425 * the log2 of roundup power of two of rss_size, the acutal queue 3426 * size is limited by indirection table. 3427 */ 3428 if (rss_size > HCLGE_RSS_TC_SIZE_7 || rss_size == 0) { 3429 dev_err(&hdev->pdev->dev, 3430 "Configure rss tc size failed, invalid TC_SIZE = %d\n", 3431 rss_size); 3432 return -EINVAL; 3433 } 3434 3435 roundup_size = roundup_pow_of_two(rss_size); 3436 roundup_size = ilog2(roundup_size); 3437 3438 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 3439 tc_valid[i] = 0; 3440 3441 if (!(hdev->hw_tc_map & BIT(i))) 3442 continue; 3443 3444 tc_valid[i] = 1; 3445 tc_size[i] = roundup_size; 3446 tc_offset[i] = rss_size * i; 3447 } 3448 3449 return hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset); 3450 } 3451 3452 void hclge_rss_indir_init_cfg(struct hclge_dev *hdev) 3453 { 3454 struct hclge_vport *vport = hdev->vport; 3455 int i, j; 3456 3457 for (j = 0; j < hdev->num_vmdq_vport + 1; j++) { 3458 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++) 3459 vport[j].rss_indirection_tbl[i] = 3460 i % vport[j].alloc_rss_size; 3461 } 3462 } 3463 3464 static void hclge_rss_init_cfg(struct hclge_dev *hdev) 3465 { 3466 struct hclge_vport *vport = hdev->vport; 3467 int i; 3468 3469 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) { 3470 vport[i].rss_tuple_sets.ipv4_tcp_en = 3471 HCLGE_RSS_INPUT_TUPLE_OTHER; 3472 vport[i].rss_tuple_sets.ipv4_udp_en = 3473 HCLGE_RSS_INPUT_TUPLE_OTHER; 3474 vport[i].rss_tuple_sets.ipv4_sctp_en = 3475 HCLGE_RSS_INPUT_TUPLE_SCTP; 3476 vport[i].rss_tuple_sets.ipv4_fragment_en = 3477 HCLGE_RSS_INPUT_TUPLE_OTHER; 3478 vport[i].rss_tuple_sets.ipv6_tcp_en = 3479 HCLGE_RSS_INPUT_TUPLE_OTHER; 3480 vport[i].rss_tuple_sets.ipv6_udp_en = 3481 HCLGE_RSS_INPUT_TUPLE_OTHER; 3482 vport[i].rss_tuple_sets.ipv6_sctp_en = 3483 HCLGE_RSS_INPUT_TUPLE_SCTP; 3484 vport[i].rss_tuple_sets.ipv6_fragment_en = 3485 HCLGE_RSS_INPUT_TUPLE_OTHER; 3486 3487 vport[i].rss_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ; 3488 3489 netdev_rss_key_fill(vport[i].rss_hash_key, HCLGE_RSS_KEY_SIZE); 3490 } 3491 3492 hclge_rss_indir_init_cfg(hdev); 3493 } 3494 3495 int hclge_bind_ring_with_vector(struct hclge_vport *vport, 3496 int vector_id, bool en, 3497 struct hnae3_ring_chain_node *ring_chain) 3498 { 3499 struct hclge_dev *hdev = vport->back; 3500 struct hnae3_ring_chain_node *node; 3501 struct hclge_desc desc; 3502 struct hclge_ctrl_vector_chain_cmd *req 3503 = (struct hclge_ctrl_vector_chain_cmd *)desc.data; 3504 enum hclge_cmd_status status; 3505 enum hclge_opcode_type op; 3506 u16 tqp_type_and_id; 3507 int i; 3508 3509 op = en ? HCLGE_OPC_ADD_RING_TO_VECTOR : HCLGE_OPC_DEL_RING_TO_VECTOR; 3510 hclge_cmd_setup_basic_desc(&desc, op, false); 3511 req->int_vector_id = vector_id; 3512 3513 i = 0; 3514 for (node = ring_chain; node; node = node->next) { 3515 tqp_type_and_id = le16_to_cpu(req->tqp_type_and_id[i]); 3516 hnae_set_field(tqp_type_and_id, HCLGE_INT_TYPE_M, 3517 HCLGE_INT_TYPE_S, 3518 hnae_get_bit(node->flag, HNAE3_RING_TYPE_B)); 3519 hnae_set_field(tqp_type_and_id, HCLGE_TQP_ID_M, 3520 HCLGE_TQP_ID_S, node->tqp_index); 3521 hnae_set_field(tqp_type_and_id, HCLGE_INT_GL_IDX_M, 3522 HCLGE_INT_GL_IDX_S, 3523 hnae_get_field(node->int_gl_idx, 3524 HNAE3_RING_GL_IDX_M, 3525 HNAE3_RING_GL_IDX_S)); 3526 req->tqp_type_and_id[i] = cpu_to_le16(tqp_type_and_id); 3527 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) { 3528 req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD; 3529 req->vfid = vport->vport_id; 3530 3531 status = hclge_cmd_send(&hdev->hw, &desc, 1); 3532 if (status) { 3533 dev_err(&hdev->pdev->dev, 3534 "Map TQP fail, status is %d.\n", 3535 status); 3536 return -EIO; 3537 } 3538 i = 0; 3539 3540 hclge_cmd_setup_basic_desc(&desc, 3541 op, 3542 false); 3543 req->int_vector_id = vector_id; 3544 } 3545 } 3546 3547 if (i > 0) { 3548 req->int_cause_num = i; 3549 req->vfid = vport->vport_id; 3550 status = hclge_cmd_send(&hdev->hw, &desc, 1); 3551 if (status) { 3552 dev_err(&hdev->pdev->dev, 3553 "Map TQP fail, status is %d.\n", status); 3554 return -EIO; 3555 } 3556 } 3557 3558 return 0; 3559 } 3560 3561 static int hclge_map_ring_to_vector(struct hnae3_handle *handle, 3562 int vector, 3563 struct hnae3_ring_chain_node *ring_chain) 3564 { 3565 struct hclge_vport *vport = hclge_get_vport(handle); 3566 struct hclge_dev *hdev = vport->back; 3567 int vector_id; 3568 3569 vector_id = hclge_get_vector_index(hdev, vector); 3570 if (vector_id < 0) { 3571 dev_err(&hdev->pdev->dev, 3572 "Get vector index fail. vector_id =%d\n", vector_id); 3573 return vector_id; 3574 } 3575 3576 return hclge_bind_ring_with_vector(vport, vector_id, true, ring_chain); 3577 } 3578 3579 static int hclge_unmap_ring_frm_vector(struct hnae3_handle *handle, 3580 int vector, 3581 struct hnae3_ring_chain_node *ring_chain) 3582 { 3583 struct hclge_vport *vport = hclge_get_vport(handle); 3584 struct hclge_dev *hdev = vport->back; 3585 int vector_id, ret; 3586 3587 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 3588 return 0; 3589 3590 vector_id = hclge_get_vector_index(hdev, vector); 3591 if (vector_id < 0) { 3592 dev_err(&handle->pdev->dev, 3593 "Get vector index fail. ret =%d\n", vector_id); 3594 return vector_id; 3595 } 3596 3597 ret = hclge_bind_ring_with_vector(vport, vector_id, false, ring_chain); 3598 if (ret) 3599 dev_err(&handle->pdev->dev, 3600 "Unmap ring from vector fail. vectorid=%d, ret =%d\n", 3601 vector_id, 3602 ret); 3603 3604 return ret; 3605 } 3606 3607 int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev, 3608 struct hclge_promisc_param *param) 3609 { 3610 struct hclge_promisc_cfg_cmd *req; 3611 struct hclge_desc desc; 3612 int ret; 3613 3614 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PROMISC_MODE, false); 3615 3616 req = (struct hclge_promisc_cfg_cmd *)desc.data; 3617 req->vf_id = param->vf_id; 3618 req->flag = (param->enable << HCLGE_PROMISC_EN_B); 3619 3620 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3621 if (ret) { 3622 dev_err(&hdev->pdev->dev, 3623 "Set promisc mode fail, status is %d.\n", ret); 3624 return ret; 3625 } 3626 return 0; 3627 } 3628 3629 void hclge_promisc_param_init(struct hclge_promisc_param *param, bool en_uc, 3630 bool en_mc, bool en_bc, int vport_id) 3631 { 3632 if (!param) 3633 return; 3634 3635 memset(param, 0, sizeof(struct hclge_promisc_param)); 3636 if (en_uc) 3637 param->enable = HCLGE_PROMISC_EN_UC; 3638 if (en_mc) 3639 param->enable |= HCLGE_PROMISC_EN_MC; 3640 if (en_bc) 3641 param->enable |= HCLGE_PROMISC_EN_BC; 3642 param->vf_id = vport_id; 3643 } 3644 3645 static void hclge_set_promisc_mode(struct hnae3_handle *handle, u32 en) 3646 { 3647 struct hclge_vport *vport = hclge_get_vport(handle); 3648 struct hclge_dev *hdev = vport->back; 3649 struct hclge_promisc_param param; 3650 3651 hclge_promisc_param_init(¶m, en, en, true, vport->vport_id); 3652 hclge_cmd_set_promisc_mode(hdev, ¶m); 3653 } 3654 3655 static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable) 3656 { 3657 struct hclge_desc desc; 3658 struct hclge_config_mac_mode_cmd *req = 3659 (struct hclge_config_mac_mode_cmd *)desc.data; 3660 u32 loop_en = 0; 3661 int ret; 3662 3663 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false); 3664 hnae_set_bit(loop_en, HCLGE_MAC_TX_EN_B, enable); 3665 hnae_set_bit(loop_en, HCLGE_MAC_RX_EN_B, enable); 3666 hnae_set_bit(loop_en, HCLGE_MAC_PAD_TX_B, enable); 3667 hnae_set_bit(loop_en, HCLGE_MAC_PAD_RX_B, enable); 3668 hnae_set_bit(loop_en, HCLGE_MAC_1588_TX_B, 0); 3669 hnae_set_bit(loop_en, HCLGE_MAC_1588_RX_B, 0); 3670 hnae_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 0); 3671 hnae_set_bit(loop_en, HCLGE_MAC_LINE_LP_B, 0); 3672 hnae_set_bit(loop_en, HCLGE_MAC_FCS_TX_B, enable); 3673 hnae_set_bit(loop_en, HCLGE_MAC_RX_FCS_B, enable); 3674 hnae_set_bit(loop_en, HCLGE_MAC_RX_FCS_STRIP_B, enable); 3675 hnae_set_bit(loop_en, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, enable); 3676 hnae_set_bit(loop_en, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, enable); 3677 hnae_set_bit(loop_en, HCLGE_MAC_TX_UNDER_MIN_ERR_B, enable); 3678 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en); 3679 3680 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3681 if (ret) 3682 dev_err(&hdev->pdev->dev, 3683 "mac enable fail, ret =%d.\n", ret); 3684 } 3685 3686 static int hclge_set_loopback(struct hnae3_handle *handle, 3687 enum hnae3_loop loop_mode, bool en) 3688 { 3689 struct hclge_vport *vport = hclge_get_vport(handle); 3690 struct hclge_config_mac_mode_cmd *req; 3691 struct hclge_dev *hdev = vport->back; 3692 struct hclge_desc desc; 3693 u32 loop_en; 3694 int ret; 3695 3696 switch (loop_mode) { 3697 case HNAE3_MAC_INTER_LOOP_MAC: 3698 req = (struct hclge_config_mac_mode_cmd *)&desc.data[0]; 3699 /* 1 Read out the MAC mode config at first */ 3700 hclge_cmd_setup_basic_desc(&desc, 3701 HCLGE_OPC_CONFIG_MAC_MODE, 3702 true); 3703 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3704 if (ret) { 3705 dev_err(&hdev->pdev->dev, 3706 "mac loopback get fail, ret =%d.\n", 3707 ret); 3708 return ret; 3709 } 3710 3711 /* 2 Then setup the loopback flag */ 3712 loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en); 3713 if (en) 3714 hnae_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 1); 3715 else 3716 hnae_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 0); 3717 3718 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en); 3719 3720 /* 3 Config mac work mode with loopback flag 3721 * and its original configure parameters 3722 */ 3723 hclge_cmd_reuse_desc(&desc, false); 3724 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3725 if (ret) 3726 dev_err(&hdev->pdev->dev, 3727 "mac loopback set fail, ret =%d.\n", ret); 3728 break; 3729 default: 3730 ret = -ENOTSUPP; 3731 dev_err(&hdev->pdev->dev, 3732 "loop_mode %d is not supported\n", loop_mode); 3733 break; 3734 } 3735 3736 return ret; 3737 } 3738 3739 static int hclge_tqp_enable(struct hclge_dev *hdev, int tqp_id, 3740 int stream_id, bool enable) 3741 { 3742 struct hclge_desc desc; 3743 struct hclge_cfg_com_tqp_queue_cmd *req = 3744 (struct hclge_cfg_com_tqp_queue_cmd *)desc.data; 3745 int ret; 3746 3747 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false); 3748 req->tqp_id = cpu_to_le16(tqp_id & HCLGE_RING_ID_MASK); 3749 req->stream_id = cpu_to_le16(stream_id); 3750 req->enable |= enable << HCLGE_TQP_ENABLE_B; 3751 3752 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3753 if (ret) 3754 dev_err(&hdev->pdev->dev, 3755 "Tqp enable fail, status =%d.\n", ret); 3756 return ret; 3757 } 3758 3759 static void hclge_reset_tqp_stats(struct hnae3_handle *handle) 3760 { 3761 struct hclge_vport *vport = hclge_get_vport(handle); 3762 struct hnae3_queue *queue; 3763 struct hclge_tqp *tqp; 3764 int i; 3765 3766 for (i = 0; i < vport->alloc_tqps; i++) { 3767 queue = handle->kinfo.tqp[i]; 3768 tqp = container_of(queue, struct hclge_tqp, q); 3769 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats)); 3770 } 3771 } 3772 3773 static int hclge_ae_start(struct hnae3_handle *handle) 3774 { 3775 struct hclge_vport *vport = hclge_get_vport(handle); 3776 struct hclge_dev *hdev = vport->back; 3777 int i, ret; 3778 3779 for (i = 0; i < vport->alloc_tqps; i++) 3780 hclge_tqp_enable(hdev, i, 0, true); 3781 3782 /* mac enable */ 3783 hclge_cfg_mac_mode(hdev, true); 3784 clear_bit(HCLGE_STATE_DOWN, &hdev->state); 3785 mod_timer(&hdev->service_timer, jiffies + HZ); 3786 3787 /* reset tqp stats */ 3788 hclge_reset_tqp_stats(handle); 3789 3790 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 3791 return 0; 3792 3793 ret = hclge_mac_start_phy(hdev); 3794 if (ret) 3795 return ret; 3796 3797 return 0; 3798 } 3799 3800 static void hclge_ae_stop(struct hnae3_handle *handle) 3801 { 3802 struct hclge_vport *vport = hclge_get_vport(handle); 3803 struct hclge_dev *hdev = vport->back; 3804 int i; 3805 3806 del_timer_sync(&hdev->service_timer); 3807 cancel_work_sync(&hdev->service_task); 3808 3809 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 3810 return; 3811 3812 for (i = 0; i < vport->alloc_tqps; i++) 3813 hclge_tqp_enable(hdev, i, 0, false); 3814 3815 /* Mac disable */ 3816 hclge_cfg_mac_mode(hdev, false); 3817 3818 hclge_mac_stop_phy(hdev); 3819 3820 /* reset tqp stats */ 3821 hclge_reset_tqp_stats(handle); 3822 hclge_update_link_status(hdev); 3823 } 3824 3825 static int hclge_get_mac_vlan_cmd_status(struct hclge_vport *vport, 3826 u16 cmdq_resp, u8 resp_code, 3827 enum hclge_mac_vlan_tbl_opcode op) 3828 { 3829 struct hclge_dev *hdev = vport->back; 3830 int return_status = -EIO; 3831 3832 if (cmdq_resp) { 3833 dev_err(&hdev->pdev->dev, 3834 "cmdq execute failed for get_mac_vlan_cmd_status,status=%d.\n", 3835 cmdq_resp); 3836 return -EIO; 3837 } 3838 3839 if (op == HCLGE_MAC_VLAN_ADD) { 3840 if ((!resp_code) || (resp_code == 1)) { 3841 return_status = 0; 3842 } else if (resp_code == 2) { 3843 return_status = -ENOSPC; 3844 dev_err(&hdev->pdev->dev, 3845 "add mac addr failed for uc_overflow.\n"); 3846 } else if (resp_code == 3) { 3847 return_status = -ENOSPC; 3848 dev_err(&hdev->pdev->dev, 3849 "add mac addr failed for mc_overflow.\n"); 3850 } else { 3851 dev_err(&hdev->pdev->dev, 3852 "add mac addr failed for undefined, code=%d.\n", 3853 resp_code); 3854 } 3855 } else if (op == HCLGE_MAC_VLAN_REMOVE) { 3856 if (!resp_code) { 3857 return_status = 0; 3858 } else if (resp_code == 1) { 3859 return_status = -ENOENT; 3860 dev_dbg(&hdev->pdev->dev, 3861 "remove mac addr failed for miss.\n"); 3862 } else { 3863 dev_err(&hdev->pdev->dev, 3864 "remove mac addr failed for undefined, code=%d.\n", 3865 resp_code); 3866 } 3867 } else if (op == HCLGE_MAC_VLAN_LKUP) { 3868 if (!resp_code) { 3869 return_status = 0; 3870 } else if (resp_code == 1) { 3871 return_status = -ENOENT; 3872 dev_dbg(&hdev->pdev->dev, 3873 "lookup mac addr failed for miss.\n"); 3874 } else { 3875 dev_err(&hdev->pdev->dev, 3876 "lookup mac addr failed for undefined, code=%d.\n", 3877 resp_code); 3878 } 3879 } else { 3880 return_status = -EINVAL; 3881 dev_err(&hdev->pdev->dev, 3882 "unknown opcode for get_mac_vlan_cmd_status,opcode=%d.\n", 3883 op); 3884 } 3885 3886 return return_status; 3887 } 3888 3889 static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr) 3890 { 3891 int word_num; 3892 int bit_num; 3893 3894 if (vfid > 255 || vfid < 0) 3895 return -EIO; 3896 3897 if (vfid >= 0 && vfid <= 191) { 3898 word_num = vfid / 32; 3899 bit_num = vfid % 32; 3900 if (clr) 3901 desc[1].data[word_num] &= cpu_to_le32(~(1 << bit_num)); 3902 else 3903 desc[1].data[word_num] |= cpu_to_le32(1 << bit_num); 3904 } else { 3905 word_num = (vfid - 192) / 32; 3906 bit_num = vfid % 32; 3907 if (clr) 3908 desc[2].data[word_num] &= cpu_to_le32(~(1 << bit_num)); 3909 else 3910 desc[2].data[word_num] |= cpu_to_le32(1 << bit_num); 3911 } 3912 3913 return 0; 3914 } 3915 3916 static bool hclge_is_all_function_id_zero(struct hclge_desc *desc) 3917 { 3918 #define HCLGE_DESC_NUMBER 3 3919 #define HCLGE_FUNC_NUMBER_PER_DESC 6 3920 int i, j; 3921 3922 for (i = 0; i < HCLGE_DESC_NUMBER; i++) 3923 for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++) 3924 if (desc[i].data[j]) 3925 return false; 3926 3927 return true; 3928 } 3929 3930 static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd *new_req, 3931 const u8 *addr) 3932 { 3933 const unsigned char *mac_addr = addr; 3934 u32 high_val = mac_addr[2] << 16 | (mac_addr[3] << 24) | 3935 (mac_addr[0]) | (mac_addr[1] << 8); 3936 u32 low_val = mac_addr[4] | (mac_addr[5] << 8); 3937 3938 new_req->mac_addr_hi32 = cpu_to_le32(high_val); 3939 new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff); 3940 } 3941 3942 static u16 hclge_get_mac_addr_to_mta_index(struct hclge_vport *vport, 3943 const u8 *addr) 3944 { 3945 u16 high_val = addr[1] | (addr[0] << 8); 3946 struct hclge_dev *hdev = vport->back; 3947 u32 rsh = 4 - hdev->mta_mac_sel_type; 3948 u16 ret_val = (high_val >> rsh) & 0xfff; 3949 3950 return ret_val; 3951 } 3952 3953 static int hclge_set_mta_filter_mode(struct hclge_dev *hdev, 3954 enum hclge_mta_dmac_sel_type mta_mac_sel, 3955 bool enable) 3956 { 3957 struct hclge_mta_filter_mode_cmd *req; 3958 struct hclge_desc desc; 3959 int ret; 3960 3961 req = (struct hclge_mta_filter_mode_cmd *)desc.data; 3962 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_MODE_CFG, false); 3963 3964 hnae_set_bit(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_EN_B, 3965 enable); 3966 hnae_set_field(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_SEL_M, 3967 HCLGE_CFG_MTA_MAC_SEL_S, mta_mac_sel); 3968 3969 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3970 if (ret) { 3971 dev_err(&hdev->pdev->dev, 3972 "Config mat filter mode failed for cmd_send, ret =%d.\n", 3973 ret); 3974 return ret; 3975 } 3976 3977 return 0; 3978 } 3979 3980 int hclge_cfg_func_mta_filter(struct hclge_dev *hdev, 3981 u8 func_id, 3982 bool enable) 3983 { 3984 struct hclge_cfg_func_mta_filter_cmd *req; 3985 struct hclge_desc desc; 3986 int ret; 3987 3988 req = (struct hclge_cfg_func_mta_filter_cmd *)desc.data; 3989 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_FUNC_CFG, false); 3990 3991 hnae_set_bit(req->accept, HCLGE_CFG_FUNC_MTA_ACCEPT_B, 3992 enable); 3993 req->function_id = func_id; 3994 3995 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3996 if (ret) { 3997 dev_err(&hdev->pdev->dev, 3998 "Config func_id enable failed for cmd_send, ret =%d.\n", 3999 ret); 4000 return ret; 4001 } 4002 4003 return 0; 4004 } 4005 4006 static int hclge_set_mta_table_item(struct hclge_vport *vport, 4007 u16 idx, 4008 bool enable) 4009 { 4010 struct hclge_dev *hdev = vport->back; 4011 struct hclge_cfg_func_mta_item_cmd *req; 4012 struct hclge_desc desc; 4013 u16 item_idx = 0; 4014 int ret; 4015 4016 req = (struct hclge_cfg_func_mta_item_cmd *)desc.data; 4017 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_TBL_ITEM_CFG, false); 4018 hnae_set_bit(req->accept, HCLGE_CFG_MTA_ITEM_ACCEPT_B, enable); 4019 4020 hnae_set_field(item_idx, HCLGE_CFG_MTA_ITEM_IDX_M, 4021 HCLGE_CFG_MTA_ITEM_IDX_S, idx); 4022 req->item_idx = cpu_to_le16(item_idx); 4023 4024 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 4025 if (ret) { 4026 dev_err(&hdev->pdev->dev, 4027 "Config mta table item failed for cmd_send, ret =%d.\n", 4028 ret); 4029 return ret; 4030 } 4031 4032 return 0; 4033 } 4034 4035 static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport, 4036 struct hclge_mac_vlan_tbl_entry_cmd *req) 4037 { 4038 struct hclge_dev *hdev = vport->back; 4039 struct hclge_desc desc; 4040 u8 resp_code; 4041 u16 retval; 4042 int ret; 4043 4044 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_REMOVE, false); 4045 4046 memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 4047 4048 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 4049 if (ret) { 4050 dev_err(&hdev->pdev->dev, 4051 "del mac addr failed for cmd_send, ret =%d.\n", 4052 ret); 4053 return ret; 4054 } 4055 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; 4056 retval = le16_to_cpu(desc.retval); 4057 4058 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code, 4059 HCLGE_MAC_VLAN_REMOVE); 4060 } 4061 4062 static int hclge_lookup_mac_vlan_tbl(struct hclge_vport *vport, 4063 struct hclge_mac_vlan_tbl_entry_cmd *req, 4064 struct hclge_desc *desc, 4065 bool is_mc) 4066 { 4067 struct hclge_dev *hdev = vport->back; 4068 u8 resp_code; 4069 u16 retval; 4070 int ret; 4071 4072 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_MAC_VLAN_ADD, true); 4073 if (is_mc) { 4074 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 4075 memcpy(desc[0].data, 4076 req, 4077 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 4078 hclge_cmd_setup_basic_desc(&desc[1], 4079 HCLGE_OPC_MAC_VLAN_ADD, 4080 true); 4081 desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 4082 hclge_cmd_setup_basic_desc(&desc[2], 4083 HCLGE_OPC_MAC_VLAN_ADD, 4084 true); 4085 ret = hclge_cmd_send(&hdev->hw, desc, 3); 4086 } else { 4087 memcpy(desc[0].data, 4088 req, 4089 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 4090 ret = hclge_cmd_send(&hdev->hw, desc, 1); 4091 } 4092 if (ret) { 4093 dev_err(&hdev->pdev->dev, 4094 "lookup mac addr failed for cmd_send, ret =%d.\n", 4095 ret); 4096 return ret; 4097 } 4098 resp_code = (le32_to_cpu(desc[0].data[0]) >> 8) & 0xff; 4099 retval = le16_to_cpu(desc[0].retval); 4100 4101 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code, 4102 HCLGE_MAC_VLAN_LKUP); 4103 } 4104 4105 static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport, 4106 struct hclge_mac_vlan_tbl_entry_cmd *req, 4107 struct hclge_desc *mc_desc) 4108 { 4109 struct hclge_dev *hdev = vport->back; 4110 int cfg_status; 4111 u8 resp_code; 4112 u16 retval; 4113 int ret; 4114 4115 if (!mc_desc) { 4116 struct hclge_desc desc; 4117 4118 hclge_cmd_setup_basic_desc(&desc, 4119 HCLGE_OPC_MAC_VLAN_ADD, 4120 false); 4121 memcpy(desc.data, req, 4122 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 4123 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 4124 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; 4125 retval = le16_to_cpu(desc.retval); 4126 4127 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval, 4128 resp_code, 4129 HCLGE_MAC_VLAN_ADD); 4130 } else { 4131 hclge_cmd_reuse_desc(&mc_desc[0], false); 4132 mc_desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 4133 hclge_cmd_reuse_desc(&mc_desc[1], false); 4134 mc_desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 4135 hclge_cmd_reuse_desc(&mc_desc[2], false); 4136 mc_desc[2].flag &= cpu_to_le16(~HCLGE_CMD_FLAG_NEXT); 4137 memcpy(mc_desc[0].data, req, 4138 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 4139 ret = hclge_cmd_send(&hdev->hw, mc_desc, 3); 4140 resp_code = (le32_to_cpu(mc_desc[0].data[0]) >> 8) & 0xff; 4141 retval = le16_to_cpu(mc_desc[0].retval); 4142 4143 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval, 4144 resp_code, 4145 HCLGE_MAC_VLAN_ADD); 4146 } 4147 4148 if (ret) { 4149 dev_err(&hdev->pdev->dev, 4150 "add mac addr failed for cmd_send, ret =%d.\n", 4151 ret); 4152 return ret; 4153 } 4154 4155 return cfg_status; 4156 } 4157 4158 static int hclge_add_uc_addr(struct hnae3_handle *handle, 4159 const unsigned char *addr) 4160 { 4161 struct hclge_vport *vport = hclge_get_vport(handle); 4162 4163 return hclge_add_uc_addr_common(vport, addr); 4164 } 4165 4166 int hclge_add_uc_addr_common(struct hclge_vport *vport, 4167 const unsigned char *addr) 4168 { 4169 struct hclge_dev *hdev = vport->back; 4170 struct hclge_mac_vlan_tbl_entry_cmd req; 4171 struct hclge_desc desc; 4172 u16 egress_port = 0; 4173 int ret; 4174 4175 /* mac addr check */ 4176 if (is_zero_ether_addr(addr) || 4177 is_broadcast_ether_addr(addr) || 4178 is_multicast_ether_addr(addr)) { 4179 dev_err(&hdev->pdev->dev, 4180 "Set_uc mac err! invalid mac:%pM. is_zero:%d,is_br=%d,is_mul=%d\n", 4181 addr, 4182 is_zero_ether_addr(addr), 4183 is_broadcast_ether_addr(addr), 4184 is_multicast_ether_addr(addr)); 4185 return -EINVAL; 4186 } 4187 4188 memset(&req, 0, sizeof(req)); 4189 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1); 4190 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0); 4191 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 0); 4192 hnae_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0); 4193 4194 hnae_set_bit(egress_port, HCLGE_MAC_EPORT_SW_EN_B, 0); 4195 hnae_set_bit(egress_port, HCLGE_MAC_EPORT_TYPE_B, 0); 4196 hnae_set_field(egress_port, HCLGE_MAC_EPORT_VFID_M, 4197 HCLGE_MAC_EPORT_VFID_S, vport->vport_id); 4198 hnae_set_field(egress_port, HCLGE_MAC_EPORT_PFID_M, 4199 HCLGE_MAC_EPORT_PFID_S, 0); 4200 4201 req.egress_port = cpu_to_le16(egress_port); 4202 4203 hclge_prepare_mac_addr(&req, addr); 4204 4205 /* Lookup the mac address in the mac_vlan table, and add 4206 * it if the entry is inexistent. Repeated unicast entry 4207 * is not allowed in the mac vlan table. 4208 */ 4209 ret = hclge_lookup_mac_vlan_tbl(vport, &req, &desc, false); 4210 if (ret == -ENOENT) 4211 return hclge_add_mac_vlan_tbl(vport, &req, NULL); 4212 4213 /* check if we just hit the duplicate */ 4214 if (!ret) 4215 ret = -EINVAL; 4216 4217 dev_err(&hdev->pdev->dev, 4218 "PF failed to add unicast entry(%pM) in the MAC table\n", 4219 addr); 4220 4221 return ret; 4222 } 4223 4224 static int hclge_rm_uc_addr(struct hnae3_handle *handle, 4225 const unsigned char *addr) 4226 { 4227 struct hclge_vport *vport = hclge_get_vport(handle); 4228 4229 return hclge_rm_uc_addr_common(vport, addr); 4230 } 4231 4232 int hclge_rm_uc_addr_common(struct hclge_vport *vport, 4233 const unsigned char *addr) 4234 { 4235 struct hclge_dev *hdev = vport->back; 4236 struct hclge_mac_vlan_tbl_entry_cmd req; 4237 int ret; 4238 4239 /* mac addr check */ 4240 if (is_zero_ether_addr(addr) || 4241 is_broadcast_ether_addr(addr) || 4242 is_multicast_ether_addr(addr)) { 4243 dev_dbg(&hdev->pdev->dev, 4244 "Remove mac err! invalid mac:%pM.\n", 4245 addr); 4246 return -EINVAL; 4247 } 4248 4249 memset(&req, 0, sizeof(req)); 4250 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1); 4251 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0); 4252 hclge_prepare_mac_addr(&req, addr); 4253 ret = hclge_remove_mac_vlan_tbl(vport, &req); 4254 4255 return ret; 4256 } 4257 4258 static int hclge_add_mc_addr(struct hnae3_handle *handle, 4259 const unsigned char *addr) 4260 { 4261 struct hclge_vport *vport = hclge_get_vport(handle); 4262 4263 return hclge_add_mc_addr_common(vport, addr); 4264 } 4265 4266 int hclge_add_mc_addr_common(struct hclge_vport *vport, 4267 const unsigned char *addr) 4268 { 4269 struct hclge_dev *hdev = vport->back; 4270 struct hclge_mac_vlan_tbl_entry_cmd req; 4271 struct hclge_desc desc[3]; 4272 u16 tbl_idx; 4273 int status; 4274 4275 /* mac addr check */ 4276 if (!is_multicast_ether_addr(addr)) { 4277 dev_err(&hdev->pdev->dev, 4278 "Add mc mac err! invalid mac:%pM.\n", 4279 addr); 4280 return -EINVAL; 4281 } 4282 memset(&req, 0, sizeof(req)); 4283 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1); 4284 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0); 4285 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1); 4286 hnae_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0); 4287 hclge_prepare_mac_addr(&req, addr); 4288 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true); 4289 if (!status) { 4290 /* This mac addr exist, update VFID for it */ 4291 hclge_update_desc_vfid(desc, vport->vport_id, false); 4292 status = hclge_add_mac_vlan_tbl(vport, &req, desc); 4293 } else { 4294 /* This mac addr do not exist, add new entry for it */ 4295 memset(desc[0].data, 0, sizeof(desc[0].data)); 4296 memset(desc[1].data, 0, sizeof(desc[0].data)); 4297 memset(desc[2].data, 0, sizeof(desc[0].data)); 4298 hclge_update_desc_vfid(desc, vport->vport_id, false); 4299 status = hclge_add_mac_vlan_tbl(vport, &req, desc); 4300 } 4301 4302 /* Set MTA table for this MAC address */ 4303 tbl_idx = hclge_get_mac_addr_to_mta_index(vport, addr); 4304 status = hclge_set_mta_table_item(vport, tbl_idx, true); 4305 4306 return status; 4307 } 4308 4309 static int hclge_rm_mc_addr(struct hnae3_handle *handle, 4310 const unsigned char *addr) 4311 { 4312 struct hclge_vport *vport = hclge_get_vport(handle); 4313 4314 return hclge_rm_mc_addr_common(vport, addr); 4315 } 4316 4317 int hclge_rm_mc_addr_common(struct hclge_vport *vport, 4318 const unsigned char *addr) 4319 { 4320 struct hclge_dev *hdev = vport->back; 4321 struct hclge_mac_vlan_tbl_entry_cmd req; 4322 enum hclge_cmd_status status; 4323 struct hclge_desc desc[3]; 4324 u16 tbl_idx; 4325 4326 /* mac addr check */ 4327 if (!is_multicast_ether_addr(addr)) { 4328 dev_dbg(&hdev->pdev->dev, 4329 "Remove mc mac err! invalid mac:%pM.\n", 4330 addr); 4331 return -EINVAL; 4332 } 4333 4334 memset(&req, 0, sizeof(req)); 4335 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1); 4336 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0); 4337 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1); 4338 hnae_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0); 4339 hclge_prepare_mac_addr(&req, addr); 4340 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true); 4341 if (!status) { 4342 /* This mac addr exist, remove this handle's VFID for it */ 4343 hclge_update_desc_vfid(desc, vport->vport_id, true); 4344 4345 if (hclge_is_all_function_id_zero(desc)) 4346 /* All the vfid is zero, so need to delete this entry */ 4347 status = hclge_remove_mac_vlan_tbl(vport, &req); 4348 else 4349 /* Not all the vfid is zero, update the vfid */ 4350 status = hclge_add_mac_vlan_tbl(vport, &req, desc); 4351 4352 } else { 4353 /* This mac addr do not exist, can't delete it */ 4354 dev_err(&hdev->pdev->dev, 4355 "Rm multicast mac addr failed, ret = %d.\n", 4356 status); 4357 return -EIO; 4358 } 4359 4360 /* Set MTB table for this MAC address */ 4361 tbl_idx = hclge_get_mac_addr_to_mta_index(vport, addr); 4362 status = hclge_set_mta_table_item(vport, tbl_idx, false); 4363 4364 return status; 4365 } 4366 4367 static int hclge_get_mac_ethertype_cmd_status(struct hclge_dev *hdev, 4368 u16 cmdq_resp, u8 resp_code) 4369 { 4370 #define HCLGE_ETHERTYPE_SUCCESS_ADD 0 4371 #define HCLGE_ETHERTYPE_ALREADY_ADD 1 4372 #define HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW 2 4373 #define HCLGE_ETHERTYPE_KEY_CONFLICT 3 4374 4375 int return_status; 4376 4377 if (cmdq_resp) { 4378 dev_err(&hdev->pdev->dev, 4379 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n", 4380 cmdq_resp); 4381 return -EIO; 4382 } 4383 4384 switch (resp_code) { 4385 case HCLGE_ETHERTYPE_SUCCESS_ADD: 4386 case HCLGE_ETHERTYPE_ALREADY_ADD: 4387 return_status = 0; 4388 break; 4389 case HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW: 4390 dev_err(&hdev->pdev->dev, 4391 "add mac ethertype failed for manager table overflow.\n"); 4392 return_status = -EIO; 4393 break; 4394 case HCLGE_ETHERTYPE_KEY_CONFLICT: 4395 dev_err(&hdev->pdev->dev, 4396 "add mac ethertype failed for key conflict.\n"); 4397 return_status = -EIO; 4398 break; 4399 default: 4400 dev_err(&hdev->pdev->dev, 4401 "add mac ethertype failed for undefined, code=%d.\n", 4402 resp_code); 4403 return_status = -EIO; 4404 } 4405 4406 return return_status; 4407 } 4408 4409 static int hclge_add_mgr_tbl(struct hclge_dev *hdev, 4410 const struct hclge_mac_mgr_tbl_entry_cmd *req) 4411 { 4412 struct hclge_desc desc; 4413 u8 resp_code; 4414 u16 retval; 4415 int ret; 4416 4417 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_ETHTYPE_ADD, false); 4418 memcpy(desc.data, req, sizeof(struct hclge_mac_mgr_tbl_entry_cmd)); 4419 4420 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 4421 if (ret) { 4422 dev_err(&hdev->pdev->dev, 4423 "add mac ethertype failed for cmd_send, ret =%d.\n", 4424 ret); 4425 return ret; 4426 } 4427 4428 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; 4429 retval = le16_to_cpu(desc.retval); 4430 4431 return hclge_get_mac_ethertype_cmd_status(hdev, retval, resp_code); 4432 } 4433 4434 static int init_mgr_tbl(struct hclge_dev *hdev) 4435 { 4436 int ret; 4437 int i; 4438 4439 for (i = 0; i < ARRAY_SIZE(hclge_mgr_table); i++) { 4440 ret = hclge_add_mgr_tbl(hdev, &hclge_mgr_table[i]); 4441 if (ret) { 4442 dev_err(&hdev->pdev->dev, 4443 "add mac ethertype failed, ret =%d.\n", 4444 ret); 4445 return ret; 4446 } 4447 } 4448 4449 return 0; 4450 } 4451 4452 static void hclge_get_mac_addr(struct hnae3_handle *handle, u8 *p) 4453 { 4454 struct hclge_vport *vport = hclge_get_vport(handle); 4455 struct hclge_dev *hdev = vport->back; 4456 4457 ether_addr_copy(p, hdev->hw.mac.mac_addr); 4458 } 4459 4460 static int hclge_set_mac_addr(struct hnae3_handle *handle, void *p, 4461 bool is_first) 4462 { 4463 const unsigned char *new_addr = (const unsigned char *)p; 4464 struct hclge_vport *vport = hclge_get_vport(handle); 4465 struct hclge_dev *hdev = vport->back; 4466 int ret; 4467 4468 /* mac addr check */ 4469 if (is_zero_ether_addr(new_addr) || 4470 is_broadcast_ether_addr(new_addr) || 4471 is_multicast_ether_addr(new_addr)) { 4472 dev_err(&hdev->pdev->dev, 4473 "Change uc mac err! invalid mac:%p.\n", 4474 new_addr); 4475 return -EINVAL; 4476 } 4477 4478 if (!is_first && hclge_rm_uc_addr(handle, hdev->hw.mac.mac_addr)) 4479 dev_warn(&hdev->pdev->dev, 4480 "remove old uc mac address fail.\n"); 4481 4482 ret = hclge_add_uc_addr(handle, new_addr); 4483 if (ret) { 4484 dev_err(&hdev->pdev->dev, 4485 "add uc mac address fail, ret =%d.\n", 4486 ret); 4487 4488 if (!is_first && 4489 hclge_add_uc_addr(handle, hdev->hw.mac.mac_addr)) 4490 dev_err(&hdev->pdev->dev, 4491 "restore uc mac address fail.\n"); 4492 4493 return -EIO; 4494 } 4495 4496 ret = hclge_pause_addr_cfg(hdev, new_addr); 4497 if (ret) { 4498 dev_err(&hdev->pdev->dev, 4499 "configure mac pause address fail, ret =%d.\n", 4500 ret); 4501 return -EIO; 4502 } 4503 4504 ether_addr_copy(hdev->hw.mac.mac_addr, new_addr); 4505 4506 return 0; 4507 } 4508 4509 static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type, 4510 bool filter_en) 4511 { 4512 struct hclge_vlan_filter_ctrl_cmd *req; 4513 struct hclge_desc desc; 4514 int ret; 4515 4516 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, false); 4517 4518 req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data; 4519 req->vlan_type = vlan_type; 4520 req->vlan_fe = filter_en; 4521 4522 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 4523 if (ret) { 4524 dev_err(&hdev->pdev->dev, "set vlan filter fail, ret =%d.\n", 4525 ret); 4526 return ret; 4527 } 4528 4529 return 0; 4530 } 4531 4532 #define HCLGE_FILTER_TYPE_VF 0 4533 #define HCLGE_FILTER_TYPE_PORT 1 4534 4535 static void hclge_enable_vlan_filter(struct hnae3_handle *handle, bool enable) 4536 { 4537 struct hclge_vport *vport = hclge_get_vport(handle); 4538 struct hclge_dev *hdev = vport->back; 4539 4540 hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, enable); 4541 } 4542 4543 int hclge_set_vf_vlan_common(struct hclge_dev *hdev, int vfid, 4544 bool is_kill, u16 vlan, u8 qos, __be16 proto) 4545 { 4546 #define HCLGE_MAX_VF_BYTES 16 4547 struct hclge_vlan_filter_vf_cfg_cmd *req0; 4548 struct hclge_vlan_filter_vf_cfg_cmd *req1; 4549 struct hclge_desc desc[2]; 4550 u8 vf_byte_val; 4551 u8 vf_byte_off; 4552 int ret; 4553 4554 hclge_cmd_setup_basic_desc(&desc[0], 4555 HCLGE_OPC_VLAN_FILTER_VF_CFG, false); 4556 hclge_cmd_setup_basic_desc(&desc[1], 4557 HCLGE_OPC_VLAN_FILTER_VF_CFG, false); 4558 4559 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 4560 4561 vf_byte_off = vfid / 8; 4562 vf_byte_val = 1 << (vfid % 8); 4563 4564 req0 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data; 4565 req1 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[1].data; 4566 4567 req0->vlan_id = cpu_to_le16(vlan); 4568 req0->vlan_cfg = is_kill; 4569 4570 if (vf_byte_off < HCLGE_MAX_VF_BYTES) 4571 req0->vf_bitmap[vf_byte_off] = vf_byte_val; 4572 else 4573 req1->vf_bitmap[vf_byte_off - HCLGE_MAX_VF_BYTES] = vf_byte_val; 4574 4575 ret = hclge_cmd_send(&hdev->hw, desc, 2); 4576 if (ret) { 4577 dev_err(&hdev->pdev->dev, 4578 "Send vf vlan command fail, ret =%d.\n", 4579 ret); 4580 return ret; 4581 } 4582 4583 if (!is_kill) { 4584 if (!req0->resp_code || req0->resp_code == 1) 4585 return 0; 4586 4587 dev_err(&hdev->pdev->dev, 4588 "Add vf vlan filter fail, ret =%d.\n", 4589 req0->resp_code); 4590 } else { 4591 if (!req0->resp_code) 4592 return 0; 4593 4594 dev_err(&hdev->pdev->dev, 4595 "Kill vf vlan filter fail, ret =%d.\n", 4596 req0->resp_code); 4597 } 4598 4599 return -EIO; 4600 } 4601 4602 static int hclge_set_port_vlan_filter(struct hnae3_handle *handle, 4603 __be16 proto, u16 vlan_id, 4604 bool is_kill) 4605 { 4606 struct hclge_vport *vport = hclge_get_vport(handle); 4607 struct hclge_dev *hdev = vport->back; 4608 struct hclge_vlan_filter_pf_cfg_cmd *req; 4609 struct hclge_desc desc; 4610 u8 vlan_offset_byte_val; 4611 u8 vlan_offset_byte; 4612 u8 vlan_offset_160; 4613 int ret; 4614 4615 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_PF_CFG, false); 4616 4617 vlan_offset_160 = vlan_id / 160; 4618 vlan_offset_byte = (vlan_id % 160) / 8; 4619 vlan_offset_byte_val = 1 << (vlan_id % 8); 4620 4621 req = (struct hclge_vlan_filter_pf_cfg_cmd *)desc.data; 4622 req->vlan_offset = vlan_offset_160; 4623 req->vlan_cfg = is_kill; 4624 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val; 4625 4626 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 4627 if (ret) { 4628 dev_err(&hdev->pdev->dev, 4629 "port vlan command, send fail, ret =%d.\n", 4630 ret); 4631 return ret; 4632 } 4633 4634 ret = hclge_set_vf_vlan_common(hdev, 0, is_kill, vlan_id, 0, proto); 4635 if (ret) { 4636 dev_err(&hdev->pdev->dev, 4637 "Set pf vlan filter config fail, ret =%d.\n", 4638 ret); 4639 return -EIO; 4640 } 4641 4642 return 0; 4643 } 4644 4645 static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid, 4646 u16 vlan, u8 qos, __be16 proto) 4647 { 4648 struct hclge_vport *vport = hclge_get_vport(handle); 4649 struct hclge_dev *hdev = vport->back; 4650 4651 if ((vfid >= hdev->num_alloc_vfs) || (vlan > 4095) || (qos > 7)) 4652 return -EINVAL; 4653 if (proto != htons(ETH_P_8021Q)) 4654 return -EPROTONOSUPPORT; 4655 4656 return hclge_set_vf_vlan_common(hdev, vfid, false, vlan, qos, proto); 4657 } 4658 4659 static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport *vport) 4660 { 4661 struct hclge_tx_vtag_cfg *vcfg = &vport->txvlan_cfg; 4662 struct hclge_vport_vtag_tx_cfg_cmd *req; 4663 struct hclge_dev *hdev = vport->back; 4664 struct hclge_desc desc; 4665 int status; 4666 4667 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_TX_CFG, false); 4668 4669 req = (struct hclge_vport_vtag_tx_cfg_cmd *)desc.data; 4670 req->def_vlan_tag1 = cpu_to_le16(vcfg->default_tag1); 4671 req->def_vlan_tag2 = cpu_to_le16(vcfg->default_tag2); 4672 hnae_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG_B, 4673 vcfg->accept_tag ? 1 : 0); 4674 hnae_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG_B, 4675 vcfg->accept_untag ? 1 : 0); 4676 hnae_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG1_EN_B, 4677 vcfg->insert_tag1_en ? 1 : 0); 4678 hnae_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG2_EN_B, 4679 vcfg->insert_tag2_en ? 1 : 0); 4680 hnae_set_bit(req->vport_vlan_cfg, HCLGE_CFG_NIC_ROCE_SEL_B, 0); 4681 4682 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD; 4683 req->vf_bitmap[req->vf_offset] = 4684 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE); 4685 4686 status = hclge_cmd_send(&hdev->hw, &desc, 1); 4687 if (status) 4688 dev_err(&hdev->pdev->dev, 4689 "Send port txvlan cfg command fail, ret =%d\n", 4690 status); 4691 4692 return status; 4693 } 4694 4695 static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport *vport) 4696 { 4697 struct hclge_rx_vtag_cfg *vcfg = &vport->rxvlan_cfg; 4698 struct hclge_vport_vtag_rx_cfg_cmd *req; 4699 struct hclge_dev *hdev = vport->back; 4700 struct hclge_desc desc; 4701 int status; 4702 4703 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_RX_CFG, false); 4704 4705 req = (struct hclge_vport_vtag_rx_cfg_cmd *)desc.data; 4706 hnae_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG1_EN_B, 4707 vcfg->strip_tag1_en ? 1 : 0); 4708 hnae_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG2_EN_B, 4709 vcfg->strip_tag2_en ? 1 : 0); 4710 hnae_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG1_EN_B, 4711 vcfg->vlan1_vlan_prionly ? 1 : 0); 4712 hnae_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG2_EN_B, 4713 vcfg->vlan2_vlan_prionly ? 1 : 0); 4714 4715 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD; 4716 req->vf_bitmap[req->vf_offset] = 4717 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE); 4718 4719 status = hclge_cmd_send(&hdev->hw, &desc, 1); 4720 if (status) 4721 dev_err(&hdev->pdev->dev, 4722 "Send port rxvlan cfg command fail, ret =%d\n", 4723 status); 4724 4725 return status; 4726 } 4727 4728 static int hclge_set_vlan_protocol_type(struct hclge_dev *hdev) 4729 { 4730 struct hclge_rx_vlan_type_cfg_cmd *rx_req; 4731 struct hclge_tx_vlan_type_cfg_cmd *tx_req; 4732 struct hclge_desc desc; 4733 int status; 4734 4735 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_TYPE_ID, false); 4736 rx_req = (struct hclge_rx_vlan_type_cfg_cmd *)desc.data; 4737 rx_req->ot_fst_vlan_type = 4738 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_fst_vlan_type); 4739 rx_req->ot_sec_vlan_type = 4740 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_sec_vlan_type); 4741 rx_req->in_fst_vlan_type = 4742 cpu_to_le16(hdev->vlan_type_cfg.rx_in_fst_vlan_type); 4743 rx_req->in_sec_vlan_type = 4744 cpu_to_le16(hdev->vlan_type_cfg.rx_in_sec_vlan_type); 4745 4746 status = hclge_cmd_send(&hdev->hw, &desc, 1); 4747 if (status) { 4748 dev_err(&hdev->pdev->dev, 4749 "Send rxvlan protocol type command fail, ret =%d\n", 4750 status); 4751 return status; 4752 } 4753 4754 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_INSERT, false); 4755 4756 tx_req = (struct hclge_tx_vlan_type_cfg_cmd *)&desc.data; 4757 tx_req->ot_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_ot_vlan_type); 4758 tx_req->in_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_in_vlan_type); 4759 4760 status = hclge_cmd_send(&hdev->hw, &desc, 1); 4761 if (status) 4762 dev_err(&hdev->pdev->dev, 4763 "Send txvlan protocol type command fail, ret =%d\n", 4764 status); 4765 4766 return status; 4767 } 4768 4769 static int hclge_init_vlan_config(struct hclge_dev *hdev) 4770 { 4771 #define HCLGE_DEF_VLAN_TYPE 0x8100 4772 4773 struct hnae3_handle *handle; 4774 struct hclge_vport *vport; 4775 int ret; 4776 int i; 4777 4778 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, true); 4779 if (ret) 4780 return ret; 4781 4782 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT, true); 4783 if (ret) 4784 return ret; 4785 4786 hdev->vlan_type_cfg.rx_in_fst_vlan_type = HCLGE_DEF_VLAN_TYPE; 4787 hdev->vlan_type_cfg.rx_in_sec_vlan_type = HCLGE_DEF_VLAN_TYPE; 4788 hdev->vlan_type_cfg.rx_ot_fst_vlan_type = HCLGE_DEF_VLAN_TYPE; 4789 hdev->vlan_type_cfg.rx_ot_sec_vlan_type = HCLGE_DEF_VLAN_TYPE; 4790 hdev->vlan_type_cfg.tx_ot_vlan_type = HCLGE_DEF_VLAN_TYPE; 4791 hdev->vlan_type_cfg.tx_in_vlan_type = HCLGE_DEF_VLAN_TYPE; 4792 4793 ret = hclge_set_vlan_protocol_type(hdev); 4794 if (ret) 4795 return ret; 4796 4797 for (i = 0; i < hdev->num_alloc_vport; i++) { 4798 vport = &hdev->vport[i]; 4799 vport->txvlan_cfg.accept_tag = true; 4800 vport->txvlan_cfg.accept_untag = true; 4801 vport->txvlan_cfg.insert_tag1_en = false; 4802 vport->txvlan_cfg.insert_tag2_en = false; 4803 vport->txvlan_cfg.default_tag1 = 0; 4804 vport->txvlan_cfg.default_tag2 = 0; 4805 4806 ret = hclge_set_vlan_tx_offload_cfg(vport); 4807 if (ret) 4808 return ret; 4809 4810 vport->rxvlan_cfg.strip_tag1_en = false; 4811 vport->rxvlan_cfg.strip_tag2_en = true; 4812 vport->rxvlan_cfg.vlan1_vlan_prionly = false; 4813 vport->rxvlan_cfg.vlan2_vlan_prionly = false; 4814 4815 ret = hclge_set_vlan_rx_offload_cfg(vport); 4816 if (ret) 4817 return ret; 4818 } 4819 4820 handle = &hdev->vport[0].nic; 4821 return hclge_set_port_vlan_filter(handle, htons(ETH_P_8021Q), 0, false); 4822 } 4823 4824 static int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 4825 { 4826 struct hclge_vport *vport = hclge_get_vport(handle); 4827 4828 vport->rxvlan_cfg.strip_tag1_en = false; 4829 vport->rxvlan_cfg.strip_tag2_en = enable; 4830 vport->rxvlan_cfg.vlan1_vlan_prionly = false; 4831 vport->rxvlan_cfg.vlan2_vlan_prionly = false; 4832 4833 return hclge_set_vlan_rx_offload_cfg(vport); 4834 } 4835 4836 static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mtu) 4837 { 4838 struct hclge_config_max_frm_size_cmd *req; 4839 struct hclge_desc desc; 4840 int max_frm_size; 4841 int ret; 4842 4843 max_frm_size = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 4844 4845 if (max_frm_size < HCLGE_MAC_MIN_FRAME || 4846 max_frm_size > HCLGE_MAC_MAX_FRAME) 4847 return -EINVAL; 4848 4849 max_frm_size = max(max_frm_size, HCLGE_MAC_DEFAULT_FRAME); 4850 4851 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, false); 4852 4853 req = (struct hclge_config_max_frm_size_cmd *)desc.data; 4854 req->max_frm_size = cpu_to_le16(max_frm_size); 4855 4856 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 4857 if (ret) { 4858 dev_err(&hdev->pdev->dev, "set mtu fail, ret =%d.\n", ret); 4859 return ret; 4860 } 4861 4862 hdev->mps = max_frm_size; 4863 4864 return 0; 4865 } 4866 4867 static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu) 4868 { 4869 struct hclge_vport *vport = hclge_get_vport(handle); 4870 struct hclge_dev *hdev = vport->back; 4871 int ret; 4872 4873 ret = hclge_set_mac_mtu(hdev, new_mtu); 4874 if (ret) { 4875 dev_err(&hdev->pdev->dev, 4876 "Change mtu fail, ret =%d\n", ret); 4877 return ret; 4878 } 4879 4880 ret = hclge_buffer_alloc(hdev); 4881 if (ret) 4882 dev_err(&hdev->pdev->dev, 4883 "Allocate buffer fail, ret =%d\n", ret); 4884 4885 return ret; 4886 } 4887 4888 static int hclge_send_reset_tqp_cmd(struct hclge_dev *hdev, u16 queue_id, 4889 bool enable) 4890 { 4891 struct hclge_reset_tqp_queue_cmd *req; 4892 struct hclge_desc desc; 4893 int ret; 4894 4895 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, false); 4896 4897 req = (struct hclge_reset_tqp_queue_cmd *)desc.data; 4898 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK); 4899 hnae_set_bit(req->reset_req, HCLGE_TQP_RESET_B, enable); 4900 4901 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 4902 if (ret) { 4903 dev_err(&hdev->pdev->dev, 4904 "Send tqp reset cmd error, status =%d\n", ret); 4905 return ret; 4906 } 4907 4908 return 0; 4909 } 4910 4911 static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id) 4912 { 4913 struct hclge_reset_tqp_queue_cmd *req; 4914 struct hclge_desc desc; 4915 int ret; 4916 4917 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, true); 4918 4919 req = (struct hclge_reset_tqp_queue_cmd *)desc.data; 4920 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK); 4921 4922 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 4923 if (ret) { 4924 dev_err(&hdev->pdev->dev, 4925 "Get reset status error, status =%d\n", ret); 4926 return ret; 4927 } 4928 4929 return hnae_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B); 4930 } 4931 4932 static u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle, 4933 u16 queue_id) 4934 { 4935 struct hnae3_queue *queue; 4936 struct hclge_tqp *tqp; 4937 4938 queue = handle->kinfo.tqp[queue_id]; 4939 tqp = container_of(queue, struct hclge_tqp, q); 4940 4941 return tqp->index; 4942 } 4943 4944 void hclge_reset_tqp(struct hnae3_handle *handle, u16 queue_id) 4945 { 4946 struct hclge_vport *vport = hclge_get_vport(handle); 4947 struct hclge_dev *hdev = vport->back; 4948 int reset_try_times = 0; 4949 int reset_status; 4950 u16 queue_gid; 4951 int ret; 4952 4953 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 4954 return; 4955 4956 queue_gid = hclge_covert_handle_qid_global(handle, queue_id); 4957 4958 ret = hclge_tqp_enable(hdev, queue_id, 0, false); 4959 if (ret) { 4960 dev_warn(&hdev->pdev->dev, "Disable tqp fail, ret = %d\n", ret); 4961 return; 4962 } 4963 4964 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, true); 4965 if (ret) { 4966 dev_warn(&hdev->pdev->dev, 4967 "Send reset tqp cmd fail, ret = %d\n", ret); 4968 return; 4969 } 4970 4971 reset_try_times = 0; 4972 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) { 4973 /* Wait for tqp hw reset */ 4974 msleep(20); 4975 reset_status = hclge_get_reset_status(hdev, queue_gid); 4976 if (reset_status) 4977 break; 4978 } 4979 4980 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) { 4981 dev_warn(&hdev->pdev->dev, "Reset TQP fail\n"); 4982 return; 4983 } 4984 4985 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, false); 4986 if (ret) { 4987 dev_warn(&hdev->pdev->dev, 4988 "Deassert the soft reset fail, ret = %d\n", ret); 4989 return; 4990 } 4991 } 4992 4993 void hclge_reset_vf_queue(struct hclge_vport *vport, u16 queue_id) 4994 { 4995 struct hclge_dev *hdev = vport->back; 4996 int reset_try_times = 0; 4997 int reset_status; 4998 u16 queue_gid; 4999 int ret; 5000 5001 queue_gid = hclge_covert_handle_qid_global(&vport->nic, queue_id); 5002 5003 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, true); 5004 if (ret) { 5005 dev_warn(&hdev->pdev->dev, 5006 "Send reset tqp cmd fail, ret = %d\n", ret); 5007 return; 5008 } 5009 5010 reset_try_times = 0; 5011 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) { 5012 /* Wait for tqp hw reset */ 5013 msleep(20); 5014 reset_status = hclge_get_reset_status(hdev, queue_gid); 5015 if (reset_status) 5016 break; 5017 } 5018 5019 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) { 5020 dev_warn(&hdev->pdev->dev, "Reset TQP fail\n"); 5021 return; 5022 } 5023 5024 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, false); 5025 if (ret) 5026 dev_warn(&hdev->pdev->dev, 5027 "Deassert the soft reset fail, ret = %d\n", ret); 5028 } 5029 5030 static u32 hclge_get_fw_version(struct hnae3_handle *handle) 5031 { 5032 struct hclge_vport *vport = hclge_get_vport(handle); 5033 struct hclge_dev *hdev = vport->back; 5034 5035 return hdev->fw_version; 5036 } 5037 5038 static void hclge_get_flowctrl_adv(struct hnae3_handle *handle, 5039 u32 *flowctrl_adv) 5040 { 5041 struct hclge_vport *vport = hclge_get_vport(handle); 5042 struct hclge_dev *hdev = vport->back; 5043 struct phy_device *phydev = hdev->hw.mac.phydev; 5044 5045 if (!phydev) 5046 return; 5047 5048 *flowctrl_adv |= (phydev->advertising & ADVERTISED_Pause) | 5049 (phydev->advertising & ADVERTISED_Asym_Pause); 5050 } 5051 5052 static void hclge_set_flowctrl_adv(struct hclge_dev *hdev, u32 rx_en, u32 tx_en) 5053 { 5054 struct phy_device *phydev = hdev->hw.mac.phydev; 5055 5056 if (!phydev) 5057 return; 5058 5059 phydev->advertising &= ~(ADVERTISED_Pause | ADVERTISED_Asym_Pause); 5060 5061 if (rx_en) 5062 phydev->advertising |= ADVERTISED_Pause | ADVERTISED_Asym_Pause; 5063 5064 if (tx_en) 5065 phydev->advertising ^= ADVERTISED_Asym_Pause; 5066 } 5067 5068 static int hclge_cfg_pauseparam(struct hclge_dev *hdev, u32 rx_en, u32 tx_en) 5069 { 5070 int ret; 5071 5072 if (rx_en && tx_en) 5073 hdev->fc_mode_last_time = HCLGE_FC_FULL; 5074 else if (rx_en && !tx_en) 5075 hdev->fc_mode_last_time = HCLGE_FC_RX_PAUSE; 5076 else if (!rx_en && tx_en) 5077 hdev->fc_mode_last_time = HCLGE_FC_TX_PAUSE; 5078 else 5079 hdev->fc_mode_last_time = HCLGE_FC_NONE; 5080 5081 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) 5082 return 0; 5083 5084 ret = hclge_mac_pause_en_cfg(hdev, tx_en, rx_en); 5085 if (ret) { 5086 dev_err(&hdev->pdev->dev, "configure pauseparam error, ret = %d.\n", 5087 ret); 5088 return ret; 5089 } 5090 5091 hdev->tm_info.fc_mode = hdev->fc_mode_last_time; 5092 5093 return 0; 5094 } 5095 5096 int hclge_cfg_flowctrl(struct hclge_dev *hdev) 5097 { 5098 struct phy_device *phydev = hdev->hw.mac.phydev; 5099 u16 remote_advertising = 0; 5100 u16 local_advertising = 0; 5101 u32 rx_pause, tx_pause; 5102 u8 flowctl; 5103 5104 if (!phydev->link || !phydev->autoneg) 5105 return 0; 5106 5107 if (phydev->advertising & ADVERTISED_Pause) 5108 local_advertising = ADVERTISE_PAUSE_CAP; 5109 5110 if (phydev->advertising & ADVERTISED_Asym_Pause) 5111 local_advertising |= ADVERTISE_PAUSE_ASYM; 5112 5113 if (phydev->pause) 5114 remote_advertising = LPA_PAUSE_CAP; 5115 5116 if (phydev->asym_pause) 5117 remote_advertising |= LPA_PAUSE_ASYM; 5118 5119 flowctl = mii_resolve_flowctrl_fdx(local_advertising, 5120 remote_advertising); 5121 tx_pause = flowctl & FLOW_CTRL_TX; 5122 rx_pause = flowctl & FLOW_CTRL_RX; 5123 5124 if (phydev->duplex == HCLGE_MAC_HALF) { 5125 tx_pause = 0; 5126 rx_pause = 0; 5127 } 5128 5129 return hclge_cfg_pauseparam(hdev, rx_pause, tx_pause); 5130 } 5131 5132 static void hclge_get_pauseparam(struct hnae3_handle *handle, u32 *auto_neg, 5133 u32 *rx_en, u32 *tx_en) 5134 { 5135 struct hclge_vport *vport = hclge_get_vport(handle); 5136 struct hclge_dev *hdev = vport->back; 5137 5138 *auto_neg = hclge_get_autoneg(handle); 5139 5140 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) { 5141 *rx_en = 0; 5142 *tx_en = 0; 5143 return; 5144 } 5145 5146 if (hdev->tm_info.fc_mode == HCLGE_FC_RX_PAUSE) { 5147 *rx_en = 1; 5148 *tx_en = 0; 5149 } else if (hdev->tm_info.fc_mode == HCLGE_FC_TX_PAUSE) { 5150 *tx_en = 1; 5151 *rx_en = 0; 5152 } else if (hdev->tm_info.fc_mode == HCLGE_FC_FULL) { 5153 *rx_en = 1; 5154 *tx_en = 1; 5155 } else { 5156 *rx_en = 0; 5157 *tx_en = 0; 5158 } 5159 } 5160 5161 static int hclge_set_pauseparam(struct hnae3_handle *handle, u32 auto_neg, 5162 u32 rx_en, u32 tx_en) 5163 { 5164 struct hclge_vport *vport = hclge_get_vport(handle); 5165 struct hclge_dev *hdev = vport->back; 5166 struct phy_device *phydev = hdev->hw.mac.phydev; 5167 u32 fc_autoneg; 5168 5169 /* Only support flow control negotiation for netdev with 5170 * phy attached for now. 5171 */ 5172 if (!phydev) 5173 return -EOPNOTSUPP; 5174 5175 fc_autoneg = hclge_get_autoneg(handle); 5176 if (auto_neg != fc_autoneg) { 5177 dev_info(&hdev->pdev->dev, 5178 "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n"); 5179 return -EOPNOTSUPP; 5180 } 5181 5182 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) { 5183 dev_info(&hdev->pdev->dev, 5184 "Priority flow control enabled. Cannot set link flow control.\n"); 5185 return -EOPNOTSUPP; 5186 } 5187 5188 hclge_set_flowctrl_adv(hdev, rx_en, tx_en); 5189 5190 if (!fc_autoneg) 5191 return hclge_cfg_pauseparam(hdev, rx_en, tx_en); 5192 5193 return phy_start_aneg(phydev); 5194 } 5195 5196 static void hclge_get_ksettings_an_result(struct hnae3_handle *handle, 5197 u8 *auto_neg, u32 *speed, u8 *duplex) 5198 { 5199 struct hclge_vport *vport = hclge_get_vport(handle); 5200 struct hclge_dev *hdev = vport->back; 5201 5202 if (speed) 5203 *speed = hdev->hw.mac.speed; 5204 if (duplex) 5205 *duplex = hdev->hw.mac.duplex; 5206 if (auto_neg) 5207 *auto_neg = hdev->hw.mac.autoneg; 5208 } 5209 5210 static void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type) 5211 { 5212 struct hclge_vport *vport = hclge_get_vport(handle); 5213 struct hclge_dev *hdev = vport->back; 5214 5215 if (media_type) 5216 *media_type = hdev->hw.mac.media_type; 5217 } 5218 5219 static void hclge_get_mdix_mode(struct hnae3_handle *handle, 5220 u8 *tp_mdix_ctrl, u8 *tp_mdix) 5221 { 5222 struct hclge_vport *vport = hclge_get_vport(handle); 5223 struct hclge_dev *hdev = vport->back; 5224 struct phy_device *phydev = hdev->hw.mac.phydev; 5225 int mdix_ctrl, mdix, retval, is_resolved; 5226 5227 if (!phydev) { 5228 *tp_mdix_ctrl = ETH_TP_MDI_INVALID; 5229 *tp_mdix = ETH_TP_MDI_INVALID; 5230 return; 5231 } 5232 5233 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX); 5234 5235 retval = phy_read(phydev, HCLGE_PHY_CSC_REG); 5236 mdix_ctrl = hnae_get_field(retval, HCLGE_PHY_MDIX_CTRL_M, 5237 HCLGE_PHY_MDIX_CTRL_S); 5238 5239 retval = phy_read(phydev, HCLGE_PHY_CSS_REG); 5240 mdix = hnae_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B); 5241 is_resolved = hnae_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B); 5242 5243 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER); 5244 5245 switch (mdix_ctrl) { 5246 case 0x0: 5247 *tp_mdix_ctrl = ETH_TP_MDI; 5248 break; 5249 case 0x1: 5250 *tp_mdix_ctrl = ETH_TP_MDI_X; 5251 break; 5252 case 0x3: 5253 *tp_mdix_ctrl = ETH_TP_MDI_AUTO; 5254 break; 5255 default: 5256 *tp_mdix_ctrl = ETH_TP_MDI_INVALID; 5257 break; 5258 } 5259 5260 if (!is_resolved) 5261 *tp_mdix = ETH_TP_MDI_INVALID; 5262 else if (mdix) 5263 *tp_mdix = ETH_TP_MDI_X; 5264 else 5265 *tp_mdix = ETH_TP_MDI; 5266 } 5267 5268 static int hclge_init_client_instance(struct hnae3_client *client, 5269 struct hnae3_ae_dev *ae_dev) 5270 { 5271 struct hclge_dev *hdev = ae_dev->priv; 5272 struct hclge_vport *vport; 5273 int i, ret; 5274 5275 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) { 5276 vport = &hdev->vport[i]; 5277 5278 switch (client->type) { 5279 case HNAE3_CLIENT_KNIC: 5280 5281 hdev->nic_client = client; 5282 vport->nic.client = client; 5283 ret = client->ops->init_instance(&vport->nic); 5284 if (ret) 5285 goto err; 5286 5287 if (hdev->roce_client && 5288 hnae3_dev_roce_supported(hdev)) { 5289 struct hnae3_client *rc = hdev->roce_client; 5290 5291 ret = hclge_init_roce_base_info(vport); 5292 if (ret) 5293 goto err; 5294 5295 ret = rc->ops->init_instance(&vport->roce); 5296 if (ret) 5297 goto err; 5298 } 5299 5300 break; 5301 case HNAE3_CLIENT_UNIC: 5302 hdev->nic_client = client; 5303 vport->nic.client = client; 5304 5305 ret = client->ops->init_instance(&vport->nic); 5306 if (ret) 5307 goto err; 5308 5309 break; 5310 case HNAE3_CLIENT_ROCE: 5311 if (hnae3_dev_roce_supported(hdev)) { 5312 hdev->roce_client = client; 5313 vport->roce.client = client; 5314 } 5315 5316 if (hdev->roce_client && hdev->nic_client) { 5317 ret = hclge_init_roce_base_info(vport); 5318 if (ret) 5319 goto err; 5320 5321 ret = client->ops->init_instance(&vport->roce); 5322 if (ret) 5323 goto err; 5324 } 5325 } 5326 } 5327 5328 return 0; 5329 err: 5330 return ret; 5331 } 5332 5333 static void hclge_uninit_client_instance(struct hnae3_client *client, 5334 struct hnae3_ae_dev *ae_dev) 5335 { 5336 struct hclge_dev *hdev = ae_dev->priv; 5337 struct hclge_vport *vport; 5338 int i; 5339 5340 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) { 5341 vport = &hdev->vport[i]; 5342 if (hdev->roce_client) { 5343 hdev->roce_client->ops->uninit_instance(&vport->roce, 5344 0); 5345 hdev->roce_client = NULL; 5346 vport->roce.client = NULL; 5347 } 5348 if (client->type == HNAE3_CLIENT_ROCE) 5349 return; 5350 if (client->ops->uninit_instance) { 5351 client->ops->uninit_instance(&vport->nic, 0); 5352 hdev->nic_client = NULL; 5353 vport->nic.client = NULL; 5354 } 5355 } 5356 } 5357 5358 static int hclge_pci_init(struct hclge_dev *hdev) 5359 { 5360 struct pci_dev *pdev = hdev->pdev; 5361 struct hclge_hw *hw; 5362 int ret; 5363 5364 ret = pci_enable_device(pdev); 5365 if (ret) { 5366 dev_err(&pdev->dev, "failed to enable PCI device\n"); 5367 goto err_no_drvdata; 5368 } 5369 5370 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 5371 if (ret) { 5372 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 5373 if (ret) { 5374 dev_err(&pdev->dev, 5375 "can't set consistent PCI DMA"); 5376 goto err_disable_device; 5377 } 5378 dev_warn(&pdev->dev, "set DMA mask to 32 bits\n"); 5379 } 5380 5381 ret = pci_request_regions(pdev, HCLGE_DRIVER_NAME); 5382 if (ret) { 5383 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 5384 goto err_disable_device; 5385 } 5386 5387 pci_set_master(pdev); 5388 hw = &hdev->hw; 5389 hw->back = hdev; 5390 hw->io_base = pcim_iomap(pdev, 2, 0); 5391 if (!hw->io_base) { 5392 dev_err(&pdev->dev, "Can't map configuration register space\n"); 5393 ret = -ENOMEM; 5394 goto err_clr_master; 5395 } 5396 5397 hdev->num_req_vfs = pci_sriov_get_totalvfs(pdev); 5398 5399 return 0; 5400 err_clr_master: 5401 pci_clear_master(pdev); 5402 pci_release_regions(pdev); 5403 err_disable_device: 5404 pci_disable_device(pdev); 5405 err_no_drvdata: 5406 pci_set_drvdata(pdev, NULL); 5407 5408 return ret; 5409 } 5410 5411 static void hclge_pci_uninit(struct hclge_dev *hdev) 5412 { 5413 struct pci_dev *pdev = hdev->pdev; 5414 5415 pci_free_irq_vectors(pdev); 5416 pci_clear_master(pdev); 5417 pci_release_mem_regions(pdev); 5418 pci_disable_device(pdev); 5419 } 5420 5421 static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev) 5422 { 5423 struct pci_dev *pdev = ae_dev->pdev; 5424 struct hclge_dev *hdev; 5425 int ret; 5426 5427 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 5428 if (!hdev) { 5429 ret = -ENOMEM; 5430 goto err_hclge_dev; 5431 } 5432 5433 hdev->pdev = pdev; 5434 hdev->ae_dev = ae_dev; 5435 hdev->reset_type = HNAE3_NONE_RESET; 5436 hdev->reset_request = 0; 5437 hdev->reset_pending = 0; 5438 ae_dev->priv = hdev; 5439 5440 ret = hclge_pci_init(hdev); 5441 if (ret) { 5442 dev_err(&pdev->dev, "PCI init failed\n"); 5443 goto err_pci_init; 5444 } 5445 5446 /* Firmware command queue initialize */ 5447 ret = hclge_cmd_queue_init(hdev); 5448 if (ret) { 5449 dev_err(&pdev->dev, "Cmd queue init failed, ret = %d.\n", ret); 5450 return ret; 5451 } 5452 5453 /* Firmware command initialize */ 5454 ret = hclge_cmd_init(hdev); 5455 if (ret) 5456 goto err_cmd_init; 5457 5458 ret = hclge_get_cap(hdev); 5459 if (ret) { 5460 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n", 5461 ret); 5462 return ret; 5463 } 5464 5465 ret = hclge_configure(hdev); 5466 if (ret) { 5467 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret); 5468 return ret; 5469 } 5470 5471 ret = hclge_init_msi(hdev); 5472 if (ret) { 5473 dev_err(&pdev->dev, "Init MSI/MSI-X error, ret = %d.\n", ret); 5474 return ret; 5475 } 5476 5477 ret = hclge_misc_irq_init(hdev); 5478 if (ret) { 5479 dev_err(&pdev->dev, 5480 "Misc IRQ(vector0) init error, ret = %d.\n", 5481 ret); 5482 return ret; 5483 } 5484 5485 ret = hclge_alloc_tqps(hdev); 5486 if (ret) { 5487 dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret); 5488 return ret; 5489 } 5490 5491 ret = hclge_alloc_vport(hdev); 5492 if (ret) { 5493 dev_err(&pdev->dev, "Allocate vport error, ret = %d.\n", ret); 5494 return ret; 5495 } 5496 5497 ret = hclge_map_tqp(hdev); 5498 if (ret) { 5499 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret); 5500 return ret; 5501 } 5502 5503 ret = hclge_mac_mdio_config(hdev); 5504 if (ret) { 5505 dev_warn(&hdev->pdev->dev, 5506 "mdio config fail ret=%d\n", ret); 5507 return ret; 5508 } 5509 5510 ret = hclge_mac_init(hdev); 5511 if (ret) { 5512 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret); 5513 return ret; 5514 } 5515 5516 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX); 5517 if (ret) { 5518 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret); 5519 return ret; 5520 } 5521 5522 ret = hclge_init_vlan_config(hdev); 5523 if (ret) { 5524 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret); 5525 return ret; 5526 } 5527 5528 ret = hclge_tm_schd_init(hdev); 5529 if (ret) { 5530 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret); 5531 return ret; 5532 } 5533 5534 hclge_rss_init_cfg(hdev); 5535 ret = hclge_rss_init_hw(hdev); 5536 if (ret) { 5537 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret); 5538 return ret; 5539 } 5540 5541 ret = init_mgr_tbl(hdev); 5542 if (ret) { 5543 dev_err(&pdev->dev, "manager table init fail, ret =%d\n", ret); 5544 return ret; 5545 } 5546 5547 hclge_dcb_ops_set(hdev); 5548 5549 timer_setup(&hdev->service_timer, hclge_service_timer, 0); 5550 INIT_WORK(&hdev->service_task, hclge_service_task); 5551 INIT_WORK(&hdev->rst_service_task, hclge_reset_service_task); 5552 INIT_WORK(&hdev->mbx_service_task, hclge_mailbox_service_task); 5553 5554 /* Enable MISC vector(vector0) */ 5555 hclge_enable_vector(&hdev->misc_vector, true); 5556 5557 set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state); 5558 set_bit(HCLGE_STATE_DOWN, &hdev->state); 5559 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state); 5560 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 5561 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state); 5562 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state); 5563 5564 pr_info("%s driver initialization finished.\n", HCLGE_DRIVER_NAME); 5565 return 0; 5566 5567 err_cmd_init: 5568 pci_release_regions(pdev); 5569 err_pci_init: 5570 pci_set_drvdata(pdev, NULL); 5571 err_hclge_dev: 5572 return ret; 5573 } 5574 5575 static void hclge_stats_clear(struct hclge_dev *hdev) 5576 { 5577 memset(&hdev->hw_stats, 0, sizeof(hdev->hw_stats)); 5578 } 5579 5580 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev) 5581 { 5582 struct hclge_dev *hdev = ae_dev->priv; 5583 struct pci_dev *pdev = ae_dev->pdev; 5584 int ret; 5585 5586 set_bit(HCLGE_STATE_DOWN, &hdev->state); 5587 5588 hclge_stats_clear(hdev); 5589 5590 ret = hclge_cmd_init(hdev); 5591 if (ret) { 5592 dev_err(&pdev->dev, "Cmd queue init failed\n"); 5593 return ret; 5594 } 5595 5596 ret = hclge_get_cap(hdev); 5597 if (ret) { 5598 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n", 5599 ret); 5600 return ret; 5601 } 5602 5603 ret = hclge_configure(hdev); 5604 if (ret) { 5605 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret); 5606 return ret; 5607 } 5608 5609 ret = hclge_map_tqp(hdev); 5610 if (ret) { 5611 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret); 5612 return ret; 5613 } 5614 5615 ret = hclge_mac_init(hdev); 5616 if (ret) { 5617 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret); 5618 return ret; 5619 } 5620 5621 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX); 5622 if (ret) { 5623 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret); 5624 return ret; 5625 } 5626 5627 ret = hclge_init_vlan_config(hdev); 5628 if (ret) { 5629 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret); 5630 return ret; 5631 } 5632 5633 ret = hclge_tm_init_hw(hdev); 5634 if (ret) { 5635 dev_err(&pdev->dev, "tm init hw fail, ret =%d\n", ret); 5636 return ret; 5637 } 5638 5639 ret = hclge_rss_init_hw(hdev); 5640 if (ret) { 5641 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret); 5642 return ret; 5643 } 5644 5645 /* Enable MISC vector(vector0) */ 5646 hclge_enable_vector(&hdev->misc_vector, true); 5647 5648 dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n", 5649 HCLGE_DRIVER_NAME); 5650 5651 return 0; 5652 } 5653 5654 static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 5655 { 5656 struct hclge_dev *hdev = ae_dev->priv; 5657 struct hclge_mac *mac = &hdev->hw.mac; 5658 5659 set_bit(HCLGE_STATE_DOWN, &hdev->state); 5660 5661 if (IS_ENABLED(CONFIG_PCI_IOV)) 5662 hclge_disable_sriov(hdev); 5663 5664 if (hdev->service_timer.function) 5665 del_timer_sync(&hdev->service_timer); 5666 if (hdev->service_task.func) 5667 cancel_work_sync(&hdev->service_task); 5668 if (hdev->rst_service_task.func) 5669 cancel_work_sync(&hdev->rst_service_task); 5670 if (hdev->mbx_service_task.func) 5671 cancel_work_sync(&hdev->mbx_service_task); 5672 5673 if (mac->phydev) 5674 mdiobus_unregister(mac->mdio_bus); 5675 5676 /* Disable MISC vector(vector0) */ 5677 hclge_enable_vector(&hdev->misc_vector, false); 5678 hclge_destroy_cmd_queue(&hdev->hw); 5679 hclge_misc_irq_uninit(hdev); 5680 hclge_pci_uninit(hdev); 5681 ae_dev->priv = NULL; 5682 } 5683 5684 static u32 hclge_get_max_channels(struct hnae3_handle *handle) 5685 { 5686 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 5687 struct hclge_vport *vport = hclge_get_vport(handle); 5688 struct hclge_dev *hdev = vport->back; 5689 5690 return min_t(u32, hdev->rss_size_max * kinfo->num_tc, hdev->num_tqps); 5691 } 5692 5693 static void hclge_get_channels(struct hnae3_handle *handle, 5694 struct ethtool_channels *ch) 5695 { 5696 struct hclge_vport *vport = hclge_get_vport(handle); 5697 5698 ch->max_combined = hclge_get_max_channels(handle); 5699 ch->other_count = 1; 5700 ch->max_other = 1; 5701 ch->combined_count = vport->alloc_tqps; 5702 } 5703 5704 static void hclge_get_tqps_and_rss_info(struct hnae3_handle *handle, 5705 u16 *free_tqps, u16 *max_rss_size) 5706 { 5707 struct hclge_vport *vport = hclge_get_vport(handle); 5708 struct hclge_dev *hdev = vport->back; 5709 u16 temp_tqps = 0; 5710 int i; 5711 5712 for (i = 0; i < hdev->num_tqps; i++) { 5713 if (!hdev->htqp[i].alloced) 5714 temp_tqps++; 5715 } 5716 *free_tqps = temp_tqps; 5717 *max_rss_size = hdev->rss_size_max; 5718 } 5719 5720 static void hclge_release_tqp(struct hclge_vport *vport) 5721 { 5722 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 5723 struct hclge_dev *hdev = vport->back; 5724 int i; 5725 5726 for (i = 0; i < kinfo->num_tqps; i++) { 5727 struct hclge_tqp *tqp = 5728 container_of(kinfo->tqp[i], struct hclge_tqp, q); 5729 5730 tqp->q.handle = NULL; 5731 tqp->q.tqp_index = 0; 5732 tqp->alloced = false; 5733 } 5734 5735 devm_kfree(&hdev->pdev->dev, kinfo->tqp); 5736 kinfo->tqp = NULL; 5737 } 5738 5739 static int hclge_set_channels(struct hnae3_handle *handle, u32 new_tqps_num) 5740 { 5741 struct hclge_vport *vport = hclge_get_vport(handle); 5742 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 5743 struct hclge_dev *hdev = vport->back; 5744 int cur_rss_size = kinfo->rss_size; 5745 int cur_tqps = kinfo->num_tqps; 5746 u16 tc_offset[HCLGE_MAX_TC_NUM]; 5747 u16 tc_valid[HCLGE_MAX_TC_NUM]; 5748 u16 tc_size[HCLGE_MAX_TC_NUM]; 5749 u16 roundup_size; 5750 u32 *rss_indir; 5751 int ret, i; 5752 5753 hclge_release_tqp(vport); 5754 5755 ret = hclge_knic_setup(vport, new_tqps_num); 5756 if (ret) { 5757 dev_err(&hdev->pdev->dev, "setup nic fail, ret =%d\n", ret); 5758 return ret; 5759 } 5760 5761 ret = hclge_map_tqp_to_vport(hdev, vport); 5762 if (ret) { 5763 dev_err(&hdev->pdev->dev, "map vport tqp fail, ret =%d\n", ret); 5764 return ret; 5765 } 5766 5767 ret = hclge_tm_schd_init(hdev); 5768 if (ret) { 5769 dev_err(&hdev->pdev->dev, "tm schd init fail, ret =%d\n", ret); 5770 return ret; 5771 } 5772 5773 roundup_size = roundup_pow_of_two(kinfo->rss_size); 5774 roundup_size = ilog2(roundup_size); 5775 /* Set the RSS TC mode according to the new RSS size */ 5776 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 5777 tc_valid[i] = 0; 5778 5779 if (!(hdev->hw_tc_map & BIT(i))) 5780 continue; 5781 5782 tc_valid[i] = 1; 5783 tc_size[i] = roundup_size; 5784 tc_offset[i] = kinfo->rss_size * i; 5785 } 5786 ret = hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset); 5787 if (ret) 5788 return ret; 5789 5790 /* Reinitializes the rss indirect table according to the new RSS size */ 5791 rss_indir = kcalloc(HCLGE_RSS_IND_TBL_SIZE, sizeof(u32), GFP_KERNEL); 5792 if (!rss_indir) 5793 return -ENOMEM; 5794 5795 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++) 5796 rss_indir[i] = i % kinfo->rss_size; 5797 5798 ret = hclge_set_rss(handle, rss_indir, NULL, 0); 5799 if (ret) 5800 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n", 5801 ret); 5802 5803 kfree(rss_indir); 5804 5805 if (!ret) 5806 dev_info(&hdev->pdev->dev, 5807 "Channels changed, rss_size from %d to %d, tqps from %d to %d", 5808 cur_rss_size, kinfo->rss_size, 5809 cur_tqps, kinfo->rss_size * kinfo->num_tc); 5810 5811 return ret; 5812 } 5813 5814 static int hclge_get_regs_num(struct hclge_dev *hdev, u32 *regs_num_32_bit, 5815 u32 *regs_num_64_bit) 5816 { 5817 struct hclge_desc desc; 5818 u32 total_num; 5819 int ret; 5820 5821 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_REG_NUM, true); 5822 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5823 if (ret) { 5824 dev_err(&hdev->pdev->dev, 5825 "Query register number cmd failed, ret = %d.\n", ret); 5826 return ret; 5827 } 5828 5829 *regs_num_32_bit = le32_to_cpu(desc.data[0]); 5830 *regs_num_64_bit = le32_to_cpu(desc.data[1]); 5831 5832 total_num = *regs_num_32_bit + *regs_num_64_bit; 5833 if (!total_num) 5834 return -EINVAL; 5835 5836 return 0; 5837 } 5838 5839 static int hclge_get_32_bit_regs(struct hclge_dev *hdev, u32 regs_num, 5840 void *data) 5841 { 5842 #define HCLGE_32_BIT_REG_RTN_DATANUM 8 5843 5844 struct hclge_desc *desc; 5845 u32 *reg_val = data; 5846 __le32 *desc_data; 5847 int cmd_num; 5848 int i, k, n; 5849 int ret; 5850 5851 if (regs_num == 0) 5852 return 0; 5853 5854 cmd_num = DIV_ROUND_UP(regs_num + 2, HCLGE_32_BIT_REG_RTN_DATANUM); 5855 desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL); 5856 if (!desc) 5857 return -ENOMEM; 5858 5859 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_32_BIT_REG, true); 5860 ret = hclge_cmd_send(&hdev->hw, desc, cmd_num); 5861 if (ret) { 5862 dev_err(&hdev->pdev->dev, 5863 "Query 32 bit register cmd failed, ret = %d.\n", ret); 5864 kfree(desc); 5865 return ret; 5866 } 5867 5868 for (i = 0; i < cmd_num; i++) { 5869 if (i == 0) { 5870 desc_data = (__le32 *)(&desc[i].data[0]); 5871 n = HCLGE_32_BIT_REG_RTN_DATANUM - 2; 5872 } else { 5873 desc_data = (__le32 *)(&desc[i]); 5874 n = HCLGE_32_BIT_REG_RTN_DATANUM; 5875 } 5876 for (k = 0; k < n; k++) { 5877 *reg_val++ = le32_to_cpu(*desc_data++); 5878 5879 regs_num--; 5880 if (!regs_num) 5881 break; 5882 } 5883 } 5884 5885 kfree(desc); 5886 return 0; 5887 } 5888 5889 static int hclge_get_64_bit_regs(struct hclge_dev *hdev, u32 regs_num, 5890 void *data) 5891 { 5892 #define HCLGE_64_BIT_REG_RTN_DATANUM 4 5893 5894 struct hclge_desc *desc; 5895 u64 *reg_val = data; 5896 __le64 *desc_data; 5897 int cmd_num; 5898 int i, k, n; 5899 int ret; 5900 5901 if (regs_num == 0) 5902 return 0; 5903 5904 cmd_num = DIV_ROUND_UP(regs_num + 1, HCLGE_64_BIT_REG_RTN_DATANUM); 5905 desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL); 5906 if (!desc) 5907 return -ENOMEM; 5908 5909 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_64_BIT_REG, true); 5910 ret = hclge_cmd_send(&hdev->hw, desc, cmd_num); 5911 if (ret) { 5912 dev_err(&hdev->pdev->dev, 5913 "Query 64 bit register cmd failed, ret = %d.\n", ret); 5914 kfree(desc); 5915 return ret; 5916 } 5917 5918 for (i = 0; i < cmd_num; i++) { 5919 if (i == 0) { 5920 desc_data = (__le64 *)(&desc[i].data[0]); 5921 n = HCLGE_64_BIT_REG_RTN_DATANUM - 1; 5922 } else { 5923 desc_data = (__le64 *)(&desc[i]); 5924 n = HCLGE_64_BIT_REG_RTN_DATANUM; 5925 } 5926 for (k = 0; k < n; k++) { 5927 *reg_val++ = le64_to_cpu(*desc_data++); 5928 5929 regs_num--; 5930 if (!regs_num) 5931 break; 5932 } 5933 } 5934 5935 kfree(desc); 5936 return 0; 5937 } 5938 5939 static int hclge_get_regs_len(struct hnae3_handle *handle) 5940 { 5941 struct hclge_vport *vport = hclge_get_vport(handle); 5942 struct hclge_dev *hdev = vport->back; 5943 u32 regs_num_32_bit, regs_num_64_bit; 5944 int ret; 5945 5946 ret = hclge_get_regs_num(hdev, ®s_num_32_bit, ®s_num_64_bit); 5947 if (ret) { 5948 dev_err(&hdev->pdev->dev, 5949 "Get register number failed, ret = %d.\n", ret); 5950 return -EOPNOTSUPP; 5951 } 5952 5953 return regs_num_32_bit * sizeof(u32) + regs_num_64_bit * sizeof(u64); 5954 } 5955 5956 static void hclge_get_regs(struct hnae3_handle *handle, u32 *version, 5957 void *data) 5958 { 5959 struct hclge_vport *vport = hclge_get_vport(handle); 5960 struct hclge_dev *hdev = vport->back; 5961 u32 regs_num_32_bit, regs_num_64_bit; 5962 int ret; 5963 5964 *version = hdev->fw_version; 5965 5966 ret = hclge_get_regs_num(hdev, ®s_num_32_bit, ®s_num_64_bit); 5967 if (ret) { 5968 dev_err(&hdev->pdev->dev, 5969 "Get register number failed, ret = %d.\n", ret); 5970 return; 5971 } 5972 5973 ret = hclge_get_32_bit_regs(hdev, regs_num_32_bit, data); 5974 if (ret) { 5975 dev_err(&hdev->pdev->dev, 5976 "Get 32 bit register failed, ret = %d.\n", ret); 5977 return; 5978 } 5979 5980 data = (u32 *)data + regs_num_32_bit; 5981 ret = hclge_get_64_bit_regs(hdev, regs_num_64_bit, 5982 data); 5983 if (ret) 5984 dev_err(&hdev->pdev->dev, 5985 "Get 64 bit register failed, ret = %d.\n", ret); 5986 } 5987 5988 static int hclge_set_led_status_sfp(struct hclge_dev *hdev, u8 speed_led_status, 5989 u8 act_led_status, u8 link_led_status, 5990 u8 locate_led_status) 5991 { 5992 struct hclge_set_led_state_cmd *req; 5993 struct hclge_desc desc; 5994 int ret; 5995 5996 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_LED_STATUS_CFG, false); 5997 5998 req = (struct hclge_set_led_state_cmd *)desc.data; 5999 hnae_set_field(req->port_speed_led_config, HCLGE_LED_PORT_SPEED_STATE_M, 6000 HCLGE_LED_PORT_SPEED_STATE_S, speed_led_status); 6001 hnae_set_field(req->link_led_config, HCLGE_LED_ACTIVITY_STATE_M, 6002 HCLGE_LED_ACTIVITY_STATE_S, act_led_status); 6003 hnae_set_field(req->activity_led_config, HCLGE_LED_LINK_STATE_M, 6004 HCLGE_LED_LINK_STATE_S, link_led_status); 6005 hnae_set_field(req->locate_led_config, HCLGE_LED_LOCATE_STATE_M, 6006 HCLGE_LED_LOCATE_STATE_S, locate_led_status); 6007 6008 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 6009 if (ret) 6010 dev_err(&hdev->pdev->dev, 6011 "Send set led state cmd error, ret =%d\n", ret); 6012 6013 return ret; 6014 } 6015 6016 enum hclge_led_status { 6017 HCLGE_LED_OFF, 6018 HCLGE_LED_ON, 6019 HCLGE_LED_NO_CHANGE = 0xFF, 6020 }; 6021 6022 static int hclge_set_led_id(struct hnae3_handle *handle, 6023 enum ethtool_phys_id_state status) 6024 { 6025 #define BLINK_FREQUENCY 2 6026 struct hclge_vport *vport = hclge_get_vport(handle); 6027 struct hclge_dev *hdev = vport->back; 6028 struct phy_device *phydev = hdev->hw.mac.phydev; 6029 int ret = 0; 6030 6031 if (phydev || hdev->hw.mac.media_type != HNAE3_MEDIA_TYPE_FIBER) 6032 return -EOPNOTSUPP; 6033 6034 switch (status) { 6035 case ETHTOOL_ID_ACTIVE: 6036 ret = hclge_set_led_status_sfp(hdev, 6037 HCLGE_LED_NO_CHANGE, 6038 HCLGE_LED_NO_CHANGE, 6039 HCLGE_LED_NO_CHANGE, 6040 HCLGE_LED_ON); 6041 break; 6042 case ETHTOOL_ID_INACTIVE: 6043 ret = hclge_set_led_status_sfp(hdev, 6044 HCLGE_LED_NO_CHANGE, 6045 HCLGE_LED_NO_CHANGE, 6046 HCLGE_LED_NO_CHANGE, 6047 HCLGE_LED_OFF); 6048 break; 6049 default: 6050 ret = -EINVAL; 6051 break; 6052 } 6053 6054 return ret; 6055 } 6056 6057 enum hclge_led_port_speed { 6058 HCLGE_SPEED_LED_FOR_1G, 6059 HCLGE_SPEED_LED_FOR_10G, 6060 HCLGE_SPEED_LED_FOR_25G, 6061 HCLGE_SPEED_LED_FOR_40G, 6062 HCLGE_SPEED_LED_FOR_50G, 6063 HCLGE_SPEED_LED_FOR_100G, 6064 }; 6065 6066 static u8 hclge_led_get_speed_status(u32 speed) 6067 { 6068 u8 speed_led; 6069 6070 switch (speed) { 6071 case HCLGE_MAC_SPEED_1G: 6072 speed_led = HCLGE_SPEED_LED_FOR_1G; 6073 break; 6074 case HCLGE_MAC_SPEED_10G: 6075 speed_led = HCLGE_SPEED_LED_FOR_10G; 6076 break; 6077 case HCLGE_MAC_SPEED_25G: 6078 speed_led = HCLGE_SPEED_LED_FOR_25G; 6079 break; 6080 case HCLGE_MAC_SPEED_40G: 6081 speed_led = HCLGE_SPEED_LED_FOR_40G; 6082 break; 6083 case HCLGE_MAC_SPEED_50G: 6084 speed_led = HCLGE_SPEED_LED_FOR_50G; 6085 break; 6086 case HCLGE_MAC_SPEED_100G: 6087 speed_led = HCLGE_SPEED_LED_FOR_100G; 6088 break; 6089 default: 6090 speed_led = HCLGE_LED_NO_CHANGE; 6091 } 6092 6093 return speed_led; 6094 } 6095 6096 static int hclge_update_led_status(struct hclge_dev *hdev) 6097 { 6098 u8 port_speed_status, link_status, activity_status; 6099 u64 rx_pkts, tx_pkts; 6100 6101 if (hdev->hw.mac.media_type != HNAE3_MEDIA_TYPE_FIBER) 6102 return 0; 6103 6104 port_speed_status = hclge_led_get_speed_status(hdev->hw.mac.speed); 6105 6106 rx_pkts = hdev->hw_stats.mac_stats.mac_rx_total_pkt_num; 6107 tx_pkts = hdev->hw_stats.mac_stats.mac_tx_total_pkt_num; 6108 if (rx_pkts != hdev->rx_pkts_for_led || 6109 tx_pkts != hdev->tx_pkts_for_led) 6110 activity_status = HCLGE_LED_ON; 6111 else 6112 activity_status = HCLGE_LED_OFF; 6113 hdev->rx_pkts_for_led = rx_pkts; 6114 hdev->tx_pkts_for_led = tx_pkts; 6115 6116 if (hdev->hw.mac.link) 6117 link_status = HCLGE_LED_ON; 6118 else 6119 link_status = HCLGE_LED_OFF; 6120 6121 return hclge_set_led_status_sfp(hdev, port_speed_status, 6122 activity_status, link_status, 6123 HCLGE_LED_NO_CHANGE); 6124 } 6125 6126 static void hclge_get_link_mode(struct hnae3_handle *handle, 6127 unsigned long *supported, 6128 unsigned long *advertising) 6129 { 6130 unsigned int size = BITS_TO_LONGS(__ETHTOOL_LINK_MODE_MASK_NBITS); 6131 struct hclge_vport *vport = hclge_get_vport(handle); 6132 struct hclge_dev *hdev = vport->back; 6133 unsigned int idx = 0; 6134 6135 for (; idx < size; idx++) { 6136 supported[idx] = hdev->hw.mac.supported[idx]; 6137 advertising[idx] = hdev->hw.mac.advertising[idx]; 6138 } 6139 } 6140 6141 static void hclge_get_port_type(struct hnae3_handle *handle, 6142 u8 *port_type) 6143 { 6144 struct hclge_vport *vport = hclge_get_vport(handle); 6145 struct hclge_dev *hdev = vport->back; 6146 u8 media_type = hdev->hw.mac.media_type; 6147 6148 switch (media_type) { 6149 case HNAE3_MEDIA_TYPE_FIBER: 6150 *port_type = PORT_FIBRE; 6151 break; 6152 case HNAE3_MEDIA_TYPE_COPPER: 6153 *port_type = PORT_TP; 6154 break; 6155 case HNAE3_MEDIA_TYPE_UNKNOWN: 6156 default: 6157 *port_type = PORT_OTHER; 6158 break; 6159 } 6160 } 6161 6162 static const struct hnae3_ae_ops hclge_ops = { 6163 .init_ae_dev = hclge_init_ae_dev, 6164 .uninit_ae_dev = hclge_uninit_ae_dev, 6165 .init_client_instance = hclge_init_client_instance, 6166 .uninit_client_instance = hclge_uninit_client_instance, 6167 .map_ring_to_vector = hclge_map_ring_to_vector, 6168 .unmap_ring_from_vector = hclge_unmap_ring_frm_vector, 6169 .get_vector = hclge_get_vector, 6170 .put_vector = hclge_put_vector, 6171 .set_promisc_mode = hclge_set_promisc_mode, 6172 .set_loopback = hclge_set_loopback, 6173 .start = hclge_ae_start, 6174 .stop = hclge_ae_stop, 6175 .get_status = hclge_get_status, 6176 .get_ksettings_an_result = hclge_get_ksettings_an_result, 6177 .update_speed_duplex_h = hclge_update_speed_duplex_h, 6178 .cfg_mac_speed_dup_h = hclge_cfg_mac_speed_dup_h, 6179 .get_media_type = hclge_get_media_type, 6180 .get_rss_key_size = hclge_get_rss_key_size, 6181 .get_rss_indir_size = hclge_get_rss_indir_size, 6182 .get_rss = hclge_get_rss, 6183 .set_rss = hclge_set_rss, 6184 .set_rss_tuple = hclge_set_rss_tuple, 6185 .get_rss_tuple = hclge_get_rss_tuple, 6186 .get_tc_size = hclge_get_tc_size, 6187 .get_mac_addr = hclge_get_mac_addr, 6188 .set_mac_addr = hclge_set_mac_addr, 6189 .add_uc_addr = hclge_add_uc_addr, 6190 .rm_uc_addr = hclge_rm_uc_addr, 6191 .add_mc_addr = hclge_add_mc_addr, 6192 .rm_mc_addr = hclge_rm_mc_addr, 6193 .set_autoneg = hclge_set_autoneg, 6194 .get_autoneg = hclge_get_autoneg, 6195 .get_pauseparam = hclge_get_pauseparam, 6196 .set_pauseparam = hclge_set_pauseparam, 6197 .set_mtu = hclge_set_mtu, 6198 .reset_queue = hclge_reset_tqp, 6199 .get_stats = hclge_get_stats, 6200 .update_stats = hclge_update_stats, 6201 .get_strings = hclge_get_strings, 6202 .get_sset_count = hclge_get_sset_count, 6203 .get_fw_version = hclge_get_fw_version, 6204 .get_mdix_mode = hclge_get_mdix_mode, 6205 .enable_vlan_filter = hclge_enable_vlan_filter, 6206 .set_vlan_filter = hclge_set_port_vlan_filter, 6207 .set_vf_vlan_filter = hclge_set_vf_vlan_filter, 6208 .enable_hw_strip_rxvtag = hclge_en_hw_strip_rxvtag, 6209 .reset_event = hclge_reset_event, 6210 .get_tqps_and_rss_info = hclge_get_tqps_and_rss_info, 6211 .set_channels = hclge_set_channels, 6212 .get_channels = hclge_get_channels, 6213 .get_flowctrl_adv = hclge_get_flowctrl_adv, 6214 .get_regs_len = hclge_get_regs_len, 6215 .get_regs = hclge_get_regs, 6216 .set_led_id = hclge_set_led_id, 6217 .get_link_mode = hclge_get_link_mode, 6218 .get_port_type = hclge_get_port_type, 6219 }; 6220 6221 static struct hnae3_ae_algo ae_algo = { 6222 .ops = &hclge_ops, 6223 .name = HCLGE_NAME, 6224 .pdev_id_table = ae_algo_pci_tbl, 6225 }; 6226 6227 static int hclge_init(void) 6228 { 6229 pr_info("%s is initializing\n", HCLGE_NAME); 6230 6231 return hnae3_register_ae_algo(&ae_algo); 6232 } 6233 6234 static void hclge_exit(void) 6235 { 6236 hnae3_unregister_ae_algo(&ae_algo); 6237 } 6238 module_init(hclge_init); 6239 module_exit(hclge_exit); 6240 6241 MODULE_LICENSE("GPL"); 6242 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 6243 MODULE_DESCRIPTION("HCLGE Driver"); 6244 MODULE_VERSION(HCLGE_MOD_VERSION); 6245