1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/module.h> 34 #include <rdma/ib_umem.h> 35 #include <rdma/ib_cache.h> 36 #include <rdma/ib_user_verbs.h> 37 #include <linux/mlx5/fs.h> 38 #include "mlx5_ib.h" 39 #include "ib_rep.h" 40 41 /* not supported currently */ 42 static int wq_signature; 43 44 enum { 45 MLX5_IB_ACK_REQ_FREQ = 8, 46 }; 47 48 enum { 49 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83, 50 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f, 51 MLX5_IB_LINK_TYPE_IB = 0, 52 MLX5_IB_LINK_TYPE_ETH = 1 53 }; 54 55 enum { 56 MLX5_IB_SQ_STRIDE = 6, 57 }; 58 59 static const u32 mlx5_ib_opcode[] = { 60 [IB_WR_SEND] = MLX5_OPCODE_SEND, 61 [IB_WR_LSO] = MLX5_OPCODE_LSO, 62 [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM, 63 [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE, 64 [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM, 65 [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ, 66 [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS, 67 [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA, 68 [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL, 69 [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR, 70 [IB_WR_REG_MR] = MLX5_OPCODE_UMR, 71 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS, 72 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA, 73 [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR, 74 }; 75 76 struct mlx5_wqe_eth_pad { 77 u8 rsvd0[16]; 78 }; 79 80 enum raw_qp_set_mask_map { 81 MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID = 1UL << 0, 82 MLX5_RAW_QP_RATE_LIMIT = 1UL << 1, 83 }; 84 85 struct mlx5_modify_raw_qp_param { 86 u16 operation; 87 88 u32 set_mask; /* raw_qp_set_mask_map */ 89 u32 rate_limit; 90 u8 rq_q_ctr_id; 91 }; 92 93 static void get_cqs(enum ib_qp_type qp_type, 94 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, 95 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq); 96 97 static int is_qp0(enum ib_qp_type qp_type) 98 { 99 return qp_type == IB_QPT_SMI; 100 } 101 102 static int is_sqp(enum ib_qp_type qp_type) 103 { 104 return is_qp0(qp_type) || is_qp1(qp_type); 105 } 106 107 static void *get_wqe(struct mlx5_ib_qp *qp, int offset) 108 { 109 return mlx5_buf_offset(&qp->buf, offset); 110 } 111 112 static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n) 113 { 114 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift)); 115 } 116 117 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n) 118 { 119 return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE)); 120 } 121 122 /** 123 * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space. 124 * 125 * @qp: QP to copy from. 126 * @send: copy from the send queue when non-zero, use the receive queue 127 * otherwise. 128 * @wqe_index: index to start copying from. For send work queues, the 129 * wqe_index is in units of MLX5_SEND_WQE_BB. 130 * For receive work queue, it is the number of work queue 131 * element in the queue. 132 * @buffer: destination buffer. 133 * @length: maximum number of bytes to copy. 134 * 135 * Copies at least a single WQE, but may copy more data. 136 * 137 * Return: the number of bytes copied, or an error code. 138 */ 139 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index, 140 void *buffer, u32 length, 141 struct mlx5_ib_qp_base *base) 142 { 143 struct ib_device *ibdev = qp->ibqp.device; 144 struct mlx5_ib_dev *dev = to_mdev(ibdev); 145 struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq; 146 size_t offset; 147 size_t wq_end; 148 struct ib_umem *umem = base->ubuffer.umem; 149 u32 first_copy_length; 150 int wqe_length; 151 int ret; 152 153 if (wq->wqe_cnt == 0) { 154 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n", 155 qp->ibqp.qp_type); 156 return -EINVAL; 157 } 158 159 offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift); 160 wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift); 161 162 if (send && length < sizeof(struct mlx5_wqe_ctrl_seg)) 163 return -EINVAL; 164 165 if (offset > umem->length || 166 (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length)) 167 return -EINVAL; 168 169 first_copy_length = min_t(u32, offset + length, wq_end) - offset; 170 ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length); 171 if (ret) 172 return ret; 173 174 if (send) { 175 struct mlx5_wqe_ctrl_seg *ctrl = buffer; 176 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK; 177 178 wqe_length = ds * MLX5_WQE_DS_UNITS; 179 } else { 180 wqe_length = 1 << wq->wqe_shift; 181 } 182 183 if (wqe_length <= first_copy_length) 184 return first_copy_length; 185 186 ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset, 187 wqe_length - first_copy_length); 188 if (ret) 189 return ret; 190 191 return wqe_length; 192 } 193 194 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type) 195 { 196 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp; 197 struct ib_event event; 198 199 if (type == MLX5_EVENT_TYPE_PATH_MIG) { 200 /* This event is only valid for trans_qps */ 201 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port; 202 } 203 204 if (ibqp->event_handler) { 205 event.device = ibqp->device; 206 event.element.qp = ibqp; 207 switch (type) { 208 case MLX5_EVENT_TYPE_PATH_MIG: 209 event.event = IB_EVENT_PATH_MIG; 210 break; 211 case MLX5_EVENT_TYPE_COMM_EST: 212 event.event = IB_EVENT_COMM_EST; 213 break; 214 case MLX5_EVENT_TYPE_SQ_DRAINED: 215 event.event = IB_EVENT_SQ_DRAINED; 216 break; 217 case MLX5_EVENT_TYPE_SRQ_LAST_WQE: 218 event.event = IB_EVENT_QP_LAST_WQE_REACHED; 219 break; 220 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 221 event.event = IB_EVENT_QP_FATAL; 222 break; 223 case MLX5_EVENT_TYPE_PATH_MIG_FAILED: 224 event.event = IB_EVENT_PATH_MIG_ERR; 225 break; 226 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 227 event.event = IB_EVENT_QP_REQ_ERR; 228 break; 229 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: 230 event.event = IB_EVENT_QP_ACCESS_ERR; 231 break; 232 default: 233 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn); 234 return; 235 } 236 237 ibqp->event_handler(&event, ibqp->qp_context); 238 } 239 } 240 241 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap, 242 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd) 243 { 244 int wqe_size; 245 int wq_size; 246 247 /* Sanity check RQ size before proceeding */ 248 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) 249 return -EINVAL; 250 251 if (!has_rq) { 252 qp->rq.max_gs = 0; 253 qp->rq.wqe_cnt = 0; 254 qp->rq.wqe_shift = 0; 255 cap->max_recv_wr = 0; 256 cap->max_recv_sge = 0; 257 } else { 258 if (ucmd) { 259 qp->rq.wqe_cnt = ucmd->rq_wqe_count; 260 qp->rq.wqe_shift = ucmd->rq_wqe_shift; 261 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig; 262 qp->rq.max_post = qp->rq.wqe_cnt; 263 } else { 264 wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0; 265 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg); 266 wqe_size = roundup_pow_of_two(wqe_size); 267 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size; 268 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB); 269 qp->rq.wqe_cnt = wq_size / wqe_size; 270 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) { 271 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n", 272 wqe_size, 273 MLX5_CAP_GEN(dev->mdev, 274 max_wqe_sz_rq)); 275 return -EINVAL; 276 } 277 qp->rq.wqe_shift = ilog2(wqe_size); 278 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig; 279 qp->rq.max_post = qp->rq.wqe_cnt; 280 } 281 } 282 283 return 0; 284 } 285 286 static int sq_overhead(struct ib_qp_init_attr *attr) 287 { 288 int size = 0; 289 290 switch (attr->qp_type) { 291 case IB_QPT_XRC_INI: 292 size += sizeof(struct mlx5_wqe_xrc_seg); 293 /* fall through */ 294 case IB_QPT_RC: 295 size += sizeof(struct mlx5_wqe_ctrl_seg) + 296 max(sizeof(struct mlx5_wqe_atomic_seg) + 297 sizeof(struct mlx5_wqe_raddr_seg), 298 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 299 sizeof(struct mlx5_mkey_seg)); 300 break; 301 302 case IB_QPT_XRC_TGT: 303 return 0; 304 305 case IB_QPT_UC: 306 size += sizeof(struct mlx5_wqe_ctrl_seg) + 307 max(sizeof(struct mlx5_wqe_raddr_seg), 308 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 309 sizeof(struct mlx5_mkey_seg)); 310 break; 311 312 case IB_QPT_UD: 313 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO) 314 size += sizeof(struct mlx5_wqe_eth_pad) + 315 sizeof(struct mlx5_wqe_eth_seg); 316 /* fall through */ 317 case IB_QPT_SMI: 318 case MLX5_IB_QPT_HW_GSI: 319 size += sizeof(struct mlx5_wqe_ctrl_seg) + 320 sizeof(struct mlx5_wqe_datagram_seg); 321 break; 322 323 case MLX5_IB_QPT_REG_UMR: 324 size += sizeof(struct mlx5_wqe_ctrl_seg) + 325 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 326 sizeof(struct mlx5_mkey_seg); 327 break; 328 329 default: 330 return -EINVAL; 331 } 332 333 return size; 334 } 335 336 static int calc_send_wqe(struct ib_qp_init_attr *attr) 337 { 338 int inl_size = 0; 339 int size; 340 341 size = sq_overhead(attr); 342 if (size < 0) 343 return size; 344 345 if (attr->cap.max_inline_data) { 346 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) + 347 attr->cap.max_inline_data; 348 } 349 350 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg); 351 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN && 352 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE) 353 return MLX5_SIG_WQE_SIZE; 354 else 355 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB); 356 } 357 358 static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size) 359 { 360 int max_sge; 361 362 if (attr->qp_type == IB_QPT_RC) 363 max_sge = (min_t(int, wqe_size, 512) - 364 sizeof(struct mlx5_wqe_ctrl_seg) - 365 sizeof(struct mlx5_wqe_raddr_seg)) / 366 sizeof(struct mlx5_wqe_data_seg); 367 else if (attr->qp_type == IB_QPT_XRC_INI) 368 max_sge = (min_t(int, wqe_size, 512) - 369 sizeof(struct mlx5_wqe_ctrl_seg) - 370 sizeof(struct mlx5_wqe_xrc_seg) - 371 sizeof(struct mlx5_wqe_raddr_seg)) / 372 sizeof(struct mlx5_wqe_data_seg); 373 else 374 max_sge = (wqe_size - sq_overhead(attr)) / 375 sizeof(struct mlx5_wqe_data_seg); 376 377 return min_t(int, max_sge, wqe_size - sq_overhead(attr) / 378 sizeof(struct mlx5_wqe_data_seg)); 379 } 380 381 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr, 382 struct mlx5_ib_qp *qp) 383 { 384 int wqe_size; 385 int wq_size; 386 387 if (!attr->cap.max_send_wr) 388 return 0; 389 390 wqe_size = calc_send_wqe(attr); 391 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size); 392 if (wqe_size < 0) 393 return wqe_size; 394 395 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 396 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n", 397 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 398 return -EINVAL; 399 } 400 401 qp->max_inline_data = wqe_size - sq_overhead(attr) - 402 sizeof(struct mlx5_wqe_inline_seg); 403 attr->cap.max_inline_data = qp->max_inline_data; 404 405 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN) 406 qp->signature_en = true; 407 408 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size); 409 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB; 410 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 411 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n", 412 attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB, 413 qp->sq.wqe_cnt, 414 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 415 return -ENOMEM; 416 } 417 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 418 qp->sq.max_gs = get_send_sge(attr, wqe_size); 419 if (qp->sq.max_gs < attr->cap.max_send_sge) 420 return -ENOMEM; 421 422 attr->cap.max_send_sge = qp->sq.max_gs; 423 qp->sq.max_post = wq_size / wqe_size; 424 attr->cap.max_send_wr = qp->sq.max_post; 425 426 return wq_size; 427 } 428 429 static int set_user_buf_size(struct mlx5_ib_dev *dev, 430 struct mlx5_ib_qp *qp, 431 struct mlx5_ib_create_qp *ucmd, 432 struct mlx5_ib_qp_base *base, 433 struct ib_qp_init_attr *attr) 434 { 435 int desc_sz = 1 << qp->sq.wqe_shift; 436 437 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 438 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n", 439 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 440 return -EINVAL; 441 } 442 443 if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) { 444 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n", 445 ucmd->sq_wqe_count, ucmd->sq_wqe_count); 446 return -EINVAL; 447 } 448 449 qp->sq.wqe_cnt = ucmd->sq_wqe_count; 450 451 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 452 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n", 453 qp->sq.wqe_cnt, 454 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 455 return -EINVAL; 456 } 457 458 if (attr->qp_type == IB_QPT_RAW_PACKET || 459 qp->flags & MLX5_IB_QP_UNDERLAY) { 460 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift; 461 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6; 462 } else { 463 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 464 (qp->sq.wqe_cnt << 6); 465 } 466 467 return 0; 468 } 469 470 static int qp_has_rq(struct ib_qp_init_attr *attr) 471 { 472 if (attr->qp_type == IB_QPT_XRC_INI || 473 attr->qp_type == IB_QPT_XRC_TGT || attr->srq || 474 attr->qp_type == MLX5_IB_QPT_REG_UMR || 475 !attr->cap.max_recv_wr) 476 return 0; 477 478 return 1; 479 } 480 481 static int first_med_bfreg(void) 482 { 483 return 1; 484 } 485 486 enum { 487 /* this is the first blue flame register in the array of bfregs assigned 488 * to a processes. Since we do not use it for blue flame but rather 489 * regular 64 bit doorbells, we do not need a lock for maintaiing 490 * "odd/even" order 491 */ 492 NUM_NON_BLUE_FLAME_BFREGS = 1, 493 }; 494 495 static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi) 496 { 497 return get_num_static_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR; 498 } 499 500 static int num_med_bfreg(struct mlx5_ib_dev *dev, 501 struct mlx5_bfreg_info *bfregi) 502 { 503 int n; 504 505 n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs - 506 NUM_NON_BLUE_FLAME_BFREGS; 507 508 return n >= 0 ? n : 0; 509 } 510 511 static int first_hi_bfreg(struct mlx5_ib_dev *dev, 512 struct mlx5_bfreg_info *bfregi) 513 { 514 int med; 515 516 med = num_med_bfreg(dev, bfregi); 517 return ++med; 518 } 519 520 static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev, 521 struct mlx5_bfreg_info *bfregi) 522 { 523 int i; 524 525 for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) { 526 if (!bfregi->count[i]) { 527 bfregi->count[i]++; 528 return i; 529 } 530 } 531 532 return -ENOMEM; 533 } 534 535 static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev, 536 struct mlx5_bfreg_info *bfregi) 537 { 538 int minidx = first_med_bfreg(); 539 int i; 540 541 for (i = first_med_bfreg(); i < first_hi_bfreg(dev, bfregi); i++) { 542 if (bfregi->count[i] < bfregi->count[minidx]) 543 minidx = i; 544 if (!bfregi->count[minidx]) 545 break; 546 } 547 548 bfregi->count[minidx]++; 549 return minidx; 550 } 551 552 static int alloc_bfreg(struct mlx5_ib_dev *dev, 553 struct mlx5_bfreg_info *bfregi, 554 enum mlx5_ib_latency_class lat) 555 { 556 int bfregn = -EINVAL; 557 558 mutex_lock(&bfregi->lock); 559 switch (lat) { 560 case MLX5_IB_LATENCY_CLASS_LOW: 561 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1); 562 bfregn = 0; 563 bfregi->count[bfregn]++; 564 break; 565 566 case MLX5_IB_LATENCY_CLASS_MEDIUM: 567 if (bfregi->ver < 2) 568 bfregn = -ENOMEM; 569 else 570 bfregn = alloc_med_class_bfreg(dev, bfregi); 571 break; 572 573 case MLX5_IB_LATENCY_CLASS_HIGH: 574 if (bfregi->ver < 2) 575 bfregn = -ENOMEM; 576 else 577 bfregn = alloc_high_class_bfreg(dev, bfregi); 578 break; 579 } 580 mutex_unlock(&bfregi->lock); 581 582 return bfregn; 583 } 584 585 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn) 586 { 587 mutex_lock(&bfregi->lock); 588 bfregi->count[bfregn]--; 589 mutex_unlock(&bfregi->lock); 590 } 591 592 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state) 593 { 594 switch (state) { 595 case IB_QPS_RESET: return MLX5_QP_STATE_RST; 596 case IB_QPS_INIT: return MLX5_QP_STATE_INIT; 597 case IB_QPS_RTR: return MLX5_QP_STATE_RTR; 598 case IB_QPS_RTS: return MLX5_QP_STATE_RTS; 599 case IB_QPS_SQD: return MLX5_QP_STATE_SQD; 600 case IB_QPS_SQE: return MLX5_QP_STATE_SQER; 601 case IB_QPS_ERR: return MLX5_QP_STATE_ERR; 602 default: return -1; 603 } 604 } 605 606 static int to_mlx5_st(enum ib_qp_type type) 607 { 608 switch (type) { 609 case IB_QPT_RC: return MLX5_QP_ST_RC; 610 case IB_QPT_UC: return MLX5_QP_ST_UC; 611 case IB_QPT_UD: return MLX5_QP_ST_UD; 612 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR; 613 case IB_QPT_XRC_INI: 614 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC; 615 case IB_QPT_SMI: return MLX5_QP_ST_QP0; 616 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1; 617 case MLX5_IB_QPT_DCI: return MLX5_QP_ST_DCI; 618 case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6; 619 case IB_QPT_RAW_PACKET: 620 case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE; 621 case IB_QPT_MAX: 622 default: return -EINVAL; 623 } 624 } 625 626 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, 627 struct mlx5_ib_cq *recv_cq); 628 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, 629 struct mlx5_ib_cq *recv_cq); 630 631 static int bfregn_to_uar_index(struct mlx5_ib_dev *dev, 632 struct mlx5_bfreg_info *bfregi, int bfregn, 633 bool dyn_bfreg) 634 { 635 int bfregs_per_sys_page; 636 int index_of_sys_page; 637 int offset; 638 639 bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * 640 MLX5_NON_FP_BFREGS_PER_UAR; 641 index_of_sys_page = bfregn / bfregs_per_sys_page; 642 643 if (dyn_bfreg) { 644 index_of_sys_page += bfregi->num_static_sys_pages; 645 if (bfregn > bfregi->num_dyn_bfregs || 646 bfregi->sys_pages[index_of_sys_page] == MLX5_IB_INVALID_UAR_INDEX) { 647 mlx5_ib_dbg(dev, "Invalid dynamic uar index\n"); 648 return -EINVAL; 649 } 650 } 651 652 offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR; 653 return bfregi->sys_pages[index_of_sys_page] + offset; 654 } 655 656 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev, 657 struct ib_pd *pd, 658 unsigned long addr, size_t size, 659 struct ib_umem **umem, 660 int *npages, int *page_shift, int *ncont, 661 u32 *offset) 662 { 663 int err; 664 665 *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0); 666 if (IS_ERR(*umem)) { 667 mlx5_ib_dbg(dev, "umem_get failed\n"); 668 return PTR_ERR(*umem); 669 } 670 671 mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL); 672 673 err = mlx5_ib_get_buf_offset(addr, *page_shift, offset); 674 if (err) { 675 mlx5_ib_warn(dev, "bad offset\n"); 676 goto err_umem; 677 } 678 679 mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n", 680 addr, size, *npages, *page_shift, *ncont, *offset); 681 682 return 0; 683 684 err_umem: 685 ib_umem_release(*umem); 686 *umem = NULL; 687 688 return err; 689 } 690 691 static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd, 692 struct mlx5_ib_rwq *rwq) 693 { 694 struct mlx5_ib_ucontext *context; 695 696 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP) 697 atomic_dec(&dev->delay_drop.rqs_cnt); 698 699 context = to_mucontext(pd->uobject->context); 700 mlx5_ib_db_unmap_user(context, &rwq->db); 701 if (rwq->umem) 702 ib_umem_release(rwq->umem); 703 } 704 705 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd, 706 struct mlx5_ib_rwq *rwq, 707 struct mlx5_ib_create_wq *ucmd) 708 { 709 struct mlx5_ib_ucontext *context; 710 int page_shift = 0; 711 int npages; 712 u32 offset = 0; 713 int ncont = 0; 714 int err; 715 716 if (!ucmd->buf_addr) 717 return -EINVAL; 718 719 context = to_mucontext(pd->uobject->context); 720 rwq->umem = ib_umem_get(pd->uobject->context, ucmd->buf_addr, 721 rwq->buf_size, 0, 0); 722 if (IS_ERR(rwq->umem)) { 723 mlx5_ib_dbg(dev, "umem_get failed\n"); 724 err = PTR_ERR(rwq->umem); 725 return err; 726 } 727 728 mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift, 729 &ncont, NULL); 730 err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift, 731 &rwq->rq_page_offset); 732 if (err) { 733 mlx5_ib_warn(dev, "bad offset\n"); 734 goto err_umem; 735 } 736 737 rwq->rq_num_pas = ncont; 738 rwq->page_shift = page_shift; 739 rwq->log_page_size = page_shift - MLX5_ADAPTER_PAGE_SHIFT; 740 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE); 741 742 mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n", 743 (unsigned long long)ucmd->buf_addr, rwq->buf_size, 744 npages, page_shift, ncont, offset); 745 746 err = mlx5_ib_db_map_user(context, ucmd->db_addr, &rwq->db); 747 if (err) { 748 mlx5_ib_dbg(dev, "map failed\n"); 749 goto err_umem; 750 } 751 752 rwq->create_type = MLX5_WQ_USER; 753 return 0; 754 755 err_umem: 756 ib_umem_release(rwq->umem); 757 return err; 758 } 759 760 static int adjust_bfregn(struct mlx5_ib_dev *dev, 761 struct mlx5_bfreg_info *bfregi, int bfregn) 762 { 763 return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR + 764 bfregn % MLX5_NON_FP_BFREGS_PER_UAR; 765 } 766 767 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 768 struct mlx5_ib_qp *qp, struct ib_udata *udata, 769 struct ib_qp_init_attr *attr, 770 u32 **in, 771 struct mlx5_ib_create_qp_resp *resp, int *inlen, 772 struct mlx5_ib_qp_base *base) 773 { 774 struct mlx5_ib_ucontext *context; 775 struct mlx5_ib_create_qp ucmd; 776 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer; 777 int page_shift = 0; 778 int uar_index = 0; 779 int npages; 780 u32 offset = 0; 781 int bfregn; 782 int ncont = 0; 783 __be64 *pas; 784 void *qpc; 785 int err; 786 787 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd)); 788 if (err) { 789 mlx5_ib_dbg(dev, "copy failed\n"); 790 return err; 791 } 792 793 context = to_mucontext(pd->uobject->context); 794 if (ucmd.flags & MLX5_QP_FLAG_BFREG_INDEX) { 795 uar_index = bfregn_to_uar_index(dev, &context->bfregi, 796 ucmd.bfreg_index, true); 797 if (uar_index < 0) 798 return uar_index; 799 800 bfregn = MLX5_IB_INVALID_BFREG; 801 } else if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) { 802 /* 803 * TBD: should come from the verbs when we have the API 804 */ 805 /* In CROSS_CHANNEL CQ and QP must use the same UAR */ 806 bfregn = MLX5_CROSS_CHANNEL_BFREG; 807 } 808 else { 809 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_HIGH); 810 if (bfregn < 0) { 811 mlx5_ib_dbg(dev, "failed to allocate low latency BFREG\n"); 812 mlx5_ib_dbg(dev, "reverting to medium latency\n"); 813 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_MEDIUM); 814 if (bfregn < 0) { 815 mlx5_ib_dbg(dev, "failed to allocate medium latency BFREG\n"); 816 mlx5_ib_dbg(dev, "reverting to high latency\n"); 817 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_LOW); 818 if (bfregn < 0) { 819 mlx5_ib_warn(dev, "bfreg allocation failed\n"); 820 return bfregn; 821 } 822 } 823 } 824 } 825 826 mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index); 827 if (bfregn != MLX5_IB_INVALID_BFREG) 828 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn, 829 false); 830 831 qp->rq.offset = 0; 832 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 833 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 834 835 err = set_user_buf_size(dev, qp, &ucmd, base, attr); 836 if (err) 837 goto err_bfreg; 838 839 if (ucmd.buf_addr && ubuffer->buf_size) { 840 ubuffer->buf_addr = ucmd.buf_addr; 841 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, 842 ubuffer->buf_size, 843 &ubuffer->umem, &npages, &page_shift, 844 &ncont, &offset); 845 if (err) 846 goto err_bfreg; 847 } else { 848 ubuffer->umem = NULL; 849 } 850 851 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + 852 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont; 853 *in = kvzalloc(*inlen, GFP_KERNEL); 854 if (!*in) { 855 err = -ENOMEM; 856 goto err_umem; 857 } 858 859 pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas); 860 if (ubuffer->umem) 861 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0); 862 863 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); 864 865 MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT); 866 MLX5_SET(qpc, qpc, page_offset, offset); 867 868 MLX5_SET(qpc, qpc, uar_page, uar_index); 869 if (bfregn != MLX5_IB_INVALID_BFREG) 870 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn); 871 else 872 resp->bfreg_index = MLX5_IB_INVALID_BFREG; 873 qp->bfregn = bfregn; 874 875 err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db); 876 if (err) { 877 mlx5_ib_dbg(dev, "map failed\n"); 878 goto err_free; 879 } 880 881 err = ib_copy_to_udata(udata, resp, sizeof(*resp)); 882 if (err) { 883 mlx5_ib_dbg(dev, "copy failed\n"); 884 goto err_unmap; 885 } 886 qp->create_type = MLX5_QP_USER; 887 888 return 0; 889 890 err_unmap: 891 mlx5_ib_db_unmap_user(context, &qp->db); 892 893 err_free: 894 kvfree(*in); 895 896 err_umem: 897 if (ubuffer->umem) 898 ib_umem_release(ubuffer->umem); 899 900 err_bfreg: 901 if (bfregn != MLX5_IB_INVALID_BFREG) 902 mlx5_ib_free_bfreg(dev, &context->bfregi, bfregn); 903 return err; 904 } 905 906 static void destroy_qp_user(struct mlx5_ib_dev *dev, struct ib_pd *pd, 907 struct mlx5_ib_qp *qp, struct mlx5_ib_qp_base *base) 908 { 909 struct mlx5_ib_ucontext *context; 910 911 context = to_mucontext(pd->uobject->context); 912 mlx5_ib_db_unmap_user(context, &qp->db); 913 if (base->ubuffer.umem) 914 ib_umem_release(base->ubuffer.umem); 915 916 /* 917 * Free only the BFREGs which are handled by the kernel. 918 * BFREGs of UARs allocated dynamically are handled by user. 919 */ 920 if (qp->bfregn != MLX5_IB_INVALID_BFREG) 921 mlx5_ib_free_bfreg(dev, &context->bfregi, qp->bfregn); 922 } 923 924 static int create_kernel_qp(struct mlx5_ib_dev *dev, 925 struct ib_qp_init_attr *init_attr, 926 struct mlx5_ib_qp *qp, 927 u32 **in, int *inlen, 928 struct mlx5_ib_qp_base *base) 929 { 930 int uar_index; 931 void *qpc; 932 int err; 933 934 if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN | 935 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK | 936 IB_QP_CREATE_IPOIB_UD_LSO | 937 IB_QP_CREATE_NETIF_QP | 938 mlx5_ib_create_qp_sqpn_qp1())) 939 return -EINVAL; 940 941 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR) 942 qp->bf.bfreg = &dev->fp_bfreg; 943 else 944 qp->bf.bfreg = &dev->bfreg; 945 946 /* We need to divide by two since each register is comprised of 947 * two buffers of identical size, namely odd and even 948 */ 949 qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2; 950 uar_index = qp->bf.bfreg->index; 951 952 err = calc_sq_size(dev, init_attr, qp); 953 if (err < 0) { 954 mlx5_ib_dbg(dev, "err %d\n", err); 955 return err; 956 } 957 958 qp->rq.offset = 0; 959 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 960 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift); 961 962 err = mlx5_buf_alloc(dev->mdev, base->ubuffer.buf_size, &qp->buf); 963 if (err) { 964 mlx5_ib_dbg(dev, "err %d\n", err); 965 return err; 966 } 967 968 qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt); 969 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + 970 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages; 971 *in = kvzalloc(*inlen, GFP_KERNEL); 972 if (!*in) { 973 err = -ENOMEM; 974 goto err_buf; 975 } 976 977 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); 978 MLX5_SET(qpc, qpc, uar_page, uar_index); 979 MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT); 980 981 /* Set "fast registration enabled" for all kernel QPs */ 982 MLX5_SET(qpc, qpc, fre, 1); 983 MLX5_SET(qpc, qpc, rlky, 1); 984 985 if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) { 986 MLX5_SET(qpc, qpc, deth_sqpn, 1); 987 qp->flags |= MLX5_IB_QP_SQPN_QP1; 988 } 989 990 mlx5_fill_page_array(&qp->buf, 991 (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas)); 992 993 err = mlx5_db_alloc(dev->mdev, &qp->db); 994 if (err) { 995 mlx5_ib_dbg(dev, "err %d\n", err); 996 goto err_free; 997 } 998 999 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt, 1000 sizeof(*qp->sq.wrid), GFP_KERNEL); 1001 qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt, 1002 sizeof(*qp->sq.wr_data), GFP_KERNEL); 1003 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt, 1004 sizeof(*qp->rq.wrid), GFP_KERNEL); 1005 qp->sq.w_list = kvmalloc_array(qp->sq.wqe_cnt, 1006 sizeof(*qp->sq.w_list), GFP_KERNEL); 1007 qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt, 1008 sizeof(*qp->sq.wqe_head), GFP_KERNEL); 1009 1010 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid || 1011 !qp->sq.w_list || !qp->sq.wqe_head) { 1012 err = -ENOMEM; 1013 goto err_wrid; 1014 } 1015 qp->create_type = MLX5_QP_KERNEL; 1016 1017 return 0; 1018 1019 err_wrid: 1020 kvfree(qp->sq.wqe_head); 1021 kvfree(qp->sq.w_list); 1022 kvfree(qp->sq.wrid); 1023 kvfree(qp->sq.wr_data); 1024 kvfree(qp->rq.wrid); 1025 mlx5_db_free(dev->mdev, &qp->db); 1026 1027 err_free: 1028 kvfree(*in); 1029 1030 err_buf: 1031 mlx5_buf_free(dev->mdev, &qp->buf); 1032 return err; 1033 } 1034 1035 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 1036 { 1037 kvfree(qp->sq.wqe_head); 1038 kvfree(qp->sq.w_list); 1039 kvfree(qp->sq.wrid); 1040 kvfree(qp->sq.wr_data); 1041 kvfree(qp->rq.wrid); 1042 mlx5_db_free(dev->mdev, &qp->db); 1043 mlx5_buf_free(dev->mdev, &qp->buf); 1044 } 1045 1046 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr) 1047 { 1048 if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) || 1049 (attr->qp_type == MLX5_IB_QPT_DCI) || 1050 (attr->qp_type == IB_QPT_XRC_INI)) 1051 return MLX5_SRQ_RQ; 1052 else if (!qp->has_rq) 1053 return MLX5_ZERO_LEN_RQ; 1054 else 1055 return MLX5_NON_ZERO_RQ; 1056 } 1057 1058 static int is_connected(enum ib_qp_type qp_type) 1059 { 1060 if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC) 1061 return 1; 1062 1063 return 0; 1064 } 1065 1066 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 1067 struct mlx5_ib_qp *qp, 1068 struct mlx5_ib_sq *sq, u32 tdn) 1069 { 1070 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0}; 1071 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); 1072 1073 MLX5_SET(tisc, tisc, transport_domain, tdn); 1074 if (qp->flags & MLX5_IB_QP_UNDERLAY) 1075 MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn); 1076 1077 return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn); 1078 } 1079 1080 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 1081 struct mlx5_ib_sq *sq) 1082 { 1083 mlx5_core_destroy_tis(dev->mdev, sq->tisn); 1084 } 1085 1086 static void destroy_flow_rule_vport_sq(struct mlx5_ib_dev *dev, 1087 struct mlx5_ib_sq *sq) 1088 { 1089 if (sq->flow_rule) 1090 mlx5_del_flow_rules(sq->flow_rule); 1091 } 1092 1093 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 1094 struct mlx5_ib_sq *sq, void *qpin, 1095 struct ib_pd *pd) 1096 { 1097 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer; 1098 __be64 *pas; 1099 void *in; 1100 void *sqc; 1101 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 1102 void *wq; 1103 int inlen; 1104 int err; 1105 int page_shift = 0; 1106 int npages; 1107 int ncont = 0; 1108 u32 offset = 0; 1109 1110 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size, 1111 &sq->ubuffer.umem, &npages, &page_shift, 1112 &ncont, &offset); 1113 if (err) 1114 return err; 1115 1116 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont; 1117 in = kvzalloc(inlen, GFP_KERNEL); 1118 if (!in) { 1119 err = -ENOMEM; 1120 goto err_umem; 1121 } 1122 1123 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); 1124 MLX5_SET(sqc, sqc, flush_in_error_en, 1); 1125 if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe)) 1126 MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1); 1127 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST); 1128 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1129 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd)); 1130 MLX5_SET(sqc, sqc, tis_lst_sz, 1); 1131 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn); 1132 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 1133 MLX5_CAP_ETH(dev->mdev, swp)) 1134 MLX5_SET(sqc, sqc, allow_swp, 1); 1135 1136 wq = MLX5_ADDR_OF(sqc, sqc, wq); 1137 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1138 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1139 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page)); 1140 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1141 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB)); 1142 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size)); 1143 MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT); 1144 MLX5_SET(wq, wq, page_offset, offset); 1145 1146 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 1147 mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0); 1148 1149 err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp); 1150 1151 kvfree(in); 1152 1153 if (err) 1154 goto err_umem; 1155 1156 err = create_flow_rule_vport_sq(dev, sq); 1157 if (err) 1158 goto err_flow; 1159 1160 return 0; 1161 1162 err_flow: 1163 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp); 1164 1165 err_umem: 1166 ib_umem_release(sq->ubuffer.umem); 1167 sq->ubuffer.umem = NULL; 1168 1169 return err; 1170 } 1171 1172 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 1173 struct mlx5_ib_sq *sq) 1174 { 1175 destroy_flow_rule_vport_sq(dev, sq); 1176 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp); 1177 ib_umem_release(sq->ubuffer.umem); 1178 } 1179 1180 static size_t get_rq_pas_size(void *qpc) 1181 { 1182 u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12; 1183 u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride); 1184 u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size); 1185 u32 page_offset = MLX5_GET(qpc, qpc, page_offset); 1186 u32 po_quanta = 1 << (log_page_size - 6); 1187 u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride); 1188 u32 page_size = 1 << log_page_size; 1189 u32 rq_sz_po = rq_sz + (page_offset * po_quanta); 1190 u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size; 1191 1192 return rq_num_pas * sizeof(u64); 1193 } 1194 1195 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1196 struct mlx5_ib_rq *rq, void *qpin, 1197 size_t qpinlen) 1198 { 1199 struct mlx5_ib_qp *mqp = rq->base.container_mibqp; 1200 __be64 *pas; 1201 __be64 *qp_pas; 1202 void *in; 1203 void *rqc; 1204 void *wq; 1205 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 1206 size_t rq_pas_size = get_rq_pas_size(qpc); 1207 size_t inlen; 1208 int err; 1209 1210 if (qpinlen < rq_pas_size + MLX5_BYTE_OFF(create_qp_in, pas)) 1211 return -EINVAL; 1212 1213 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size; 1214 in = kvzalloc(inlen, GFP_KERNEL); 1215 if (!in) 1216 return -ENOMEM; 1217 1218 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 1219 if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING)) 1220 MLX5_SET(rqc, rqc, vsd, 1); 1221 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE); 1222 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 1223 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 1224 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1225 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv)); 1226 1227 if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS) 1228 MLX5_SET(rqc, rqc, scatter_fcs, 1); 1229 1230 wq = MLX5_ADDR_OF(rqc, rqc, wq); 1231 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1232 if (rq->flags & MLX5_IB_RQ_PCI_WRITE_END_PADDING) 1233 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 1234 MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset)); 1235 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1236 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1237 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4); 1238 MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size)); 1239 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size)); 1240 1241 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 1242 qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas); 1243 memcpy(pas, qp_pas, rq_pas_size); 1244 1245 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp); 1246 1247 kvfree(in); 1248 1249 return err; 1250 } 1251 1252 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1253 struct mlx5_ib_rq *rq) 1254 { 1255 mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp); 1256 } 1257 1258 static bool tunnel_offload_supported(struct mlx5_core_dev *dev) 1259 { 1260 return (MLX5_CAP_ETH(dev, tunnel_stateless_vxlan) || 1261 MLX5_CAP_ETH(dev, tunnel_stateless_gre) || 1262 MLX5_CAP_ETH(dev, tunnel_stateless_geneve_rx)); 1263 } 1264 1265 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1266 struct mlx5_ib_rq *rq, u32 tdn, 1267 bool tunnel_offload_en) 1268 { 1269 u32 *in; 1270 void *tirc; 1271 int inlen; 1272 int err; 1273 1274 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 1275 in = kvzalloc(inlen, GFP_KERNEL); 1276 if (!in) 1277 return -ENOMEM; 1278 1279 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); 1280 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT); 1281 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn); 1282 MLX5_SET(tirc, tirc, transport_domain, tdn); 1283 if (tunnel_offload_en) 1284 MLX5_SET(tirc, tirc, tunneled_offload_en, 1); 1285 1286 if (dev->rep) 1287 MLX5_SET(tirc, tirc, self_lb_block, 1288 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_); 1289 1290 err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn); 1291 1292 kvfree(in); 1293 1294 return err; 1295 } 1296 1297 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1298 struct mlx5_ib_rq *rq) 1299 { 1300 mlx5_core_destroy_tir(dev->mdev, rq->tirn); 1301 } 1302 1303 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1304 u32 *in, size_t inlen, 1305 struct ib_pd *pd) 1306 { 1307 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1308 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1309 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1310 struct ib_uobject *uobj = pd->uobject; 1311 struct ib_ucontext *ucontext = uobj->context; 1312 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext); 1313 int err; 1314 u32 tdn = mucontext->tdn; 1315 1316 if (qp->sq.wqe_cnt) { 1317 err = create_raw_packet_qp_tis(dev, qp, sq, tdn); 1318 if (err) 1319 return err; 1320 1321 err = create_raw_packet_qp_sq(dev, sq, in, pd); 1322 if (err) 1323 goto err_destroy_tis; 1324 1325 sq->base.container_mibqp = qp; 1326 sq->base.mqp.event = mlx5_ib_qp_event; 1327 } 1328 1329 if (qp->rq.wqe_cnt) { 1330 rq->base.container_mibqp = qp; 1331 1332 if (qp->flags & MLX5_IB_QP_CVLAN_STRIPPING) 1333 rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING; 1334 if (qp->flags & MLX5_IB_QP_PCI_WRITE_END_PADDING) 1335 rq->flags |= MLX5_IB_RQ_PCI_WRITE_END_PADDING; 1336 err = create_raw_packet_qp_rq(dev, rq, in, inlen); 1337 if (err) 1338 goto err_destroy_sq; 1339 1340 1341 err = create_raw_packet_qp_tir(dev, rq, tdn, 1342 qp->tunnel_offload_en); 1343 if (err) 1344 goto err_destroy_rq; 1345 } 1346 1347 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn : 1348 rq->base.mqp.qpn; 1349 1350 return 0; 1351 1352 err_destroy_rq: 1353 destroy_raw_packet_qp_rq(dev, rq); 1354 err_destroy_sq: 1355 if (!qp->sq.wqe_cnt) 1356 return err; 1357 destroy_raw_packet_qp_sq(dev, sq); 1358 err_destroy_tis: 1359 destroy_raw_packet_qp_tis(dev, sq); 1360 1361 return err; 1362 } 1363 1364 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev, 1365 struct mlx5_ib_qp *qp) 1366 { 1367 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1368 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1369 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1370 1371 if (qp->rq.wqe_cnt) { 1372 destroy_raw_packet_qp_tir(dev, rq); 1373 destroy_raw_packet_qp_rq(dev, rq); 1374 } 1375 1376 if (qp->sq.wqe_cnt) { 1377 destroy_raw_packet_qp_sq(dev, sq); 1378 destroy_raw_packet_qp_tis(dev, sq); 1379 } 1380 } 1381 1382 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp, 1383 struct mlx5_ib_raw_packet_qp *raw_packet_qp) 1384 { 1385 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1386 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1387 1388 sq->sq = &qp->sq; 1389 rq->rq = &qp->rq; 1390 sq->doorbell = &qp->db; 1391 rq->doorbell = &qp->db; 1392 } 1393 1394 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 1395 { 1396 mlx5_core_destroy_tir(dev->mdev, qp->rss_qp.tirn); 1397 } 1398 1399 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1400 struct ib_pd *pd, 1401 struct ib_qp_init_attr *init_attr, 1402 struct ib_udata *udata) 1403 { 1404 struct ib_uobject *uobj = pd->uobject; 1405 struct ib_ucontext *ucontext = uobj->context; 1406 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext); 1407 struct mlx5_ib_create_qp_resp resp = {}; 1408 int inlen; 1409 int err; 1410 u32 *in; 1411 void *tirc; 1412 void *hfso; 1413 u32 selected_fields = 0; 1414 size_t min_resp_len; 1415 u32 tdn = mucontext->tdn; 1416 struct mlx5_ib_create_qp_rss ucmd = {}; 1417 size_t required_cmd_sz; 1418 1419 if (init_attr->qp_type != IB_QPT_RAW_PACKET) 1420 return -EOPNOTSUPP; 1421 1422 if (init_attr->create_flags || init_attr->send_cq) 1423 return -EINVAL; 1424 1425 min_resp_len = offsetof(typeof(resp), bfreg_index) + sizeof(resp.bfreg_index); 1426 if (udata->outlen < min_resp_len) 1427 return -EINVAL; 1428 1429 required_cmd_sz = offsetof(typeof(ucmd), flags) + sizeof(ucmd.flags); 1430 if (udata->inlen < required_cmd_sz) { 1431 mlx5_ib_dbg(dev, "invalid inlen\n"); 1432 return -EINVAL; 1433 } 1434 1435 if (udata->inlen > sizeof(ucmd) && 1436 !ib_is_udata_cleared(udata, sizeof(ucmd), 1437 udata->inlen - sizeof(ucmd))) { 1438 mlx5_ib_dbg(dev, "inlen is not supported\n"); 1439 return -EOPNOTSUPP; 1440 } 1441 1442 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) { 1443 mlx5_ib_dbg(dev, "copy failed\n"); 1444 return -EFAULT; 1445 } 1446 1447 if (ucmd.comp_mask) { 1448 mlx5_ib_dbg(dev, "invalid comp mask\n"); 1449 return -EOPNOTSUPP; 1450 } 1451 1452 if (ucmd.flags & ~MLX5_QP_FLAG_TUNNEL_OFFLOADS) { 1453 mlx5_ib_dbg(dev, "invalid flags\n"); 1454 return -EOPNOTSUPP; 1455 } 1456 1457 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS && 1458 !tunnel_offload_supported(dev->mdev)) { 1459 mlx5_ib_dbg(dev, "tunnel offloads isn't supported\n"); 1460 return -EOPNOTSUPP; 1461 } 1462 1463 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER && 1464 !(ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)) { 1465 mlx5_ib_dbg(dev, "Tunnel offloads must be set for inner RSS\n"); 1466 return -EOPNOTSUPP; 1467 } 1468 1469 err = ib_copy_to_udata(udata, &resp, min_resp_len); 1470 if (err) { 1471 mlx5_ib_dbg(dev, "copy failed\n"); 1472 return -EINVAL; 1473 } 1474 1475 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 1476 in = kvzalloc(inlen, GFP_KERNEL); 1477 if (!in) 1478 return -ENOMEM; 1479 1480 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); 1481 MLX5_SET(tirc, tirc, disp_type, 1482 MLX5_TIRC_DISP_TYPE_INDIRECT); 1483 MLX5_SET(tirc, tirc, indirect_table, 1484 init_attr->rwq_ind_tbl->ind_tbl_num); 1485 MLX5_SET(tirc, tirc, transport_domain, tdn); 1486 1487 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 1488 1489 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) 1490 MLX5_SET(tirc, tirc, tunneled_offload_en, 1); 1491 1492 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER) 1493 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner); 1494 else 1495 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 1496 1497 switch (ucmd.rx_hash_function) { 1498 case MLX5_RX_HASH_FUNC_TOEPLITZ: 1499 { 1500 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key); 1501 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key); 1502 1503 if (len != ucmd.rx_key_len) { 1504 err = -EINVAL; 1505 goto err; 1506 } 1507 1508 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ); 1509 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1); 1510 memcpy(rss_key, ucmd.rx_hash_key, len); 1511 break; 1512 } 1513 default: 1514 err = -EOPNOTSUPP; 1515 goto err; 1516 } 1517 1518 if (!ucmd.rx_hash_fields_mask) { 1519 /* special case when this TIR serves as steering entry without hashing */ 1520 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size) 1521 goto create_tir; 1522 err = -EINVAL; 1523 goto err; 1524 } 1525 1526 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1527 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) && 1528 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || 1529 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) { 1530 err = -EINVAL; 1531 goto err; 1532 } 1533 1534 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */ 1535 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1536 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) 1537 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 1538 MLX5_L3_PROT_TYPE_IPV4); 1539 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || 1540 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) 1541 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 1542 MLX5_L3_PROT_TYPE_IPV6); 1543 1544 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1545 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) && 1546 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || 1547 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))) { 1548 err = -EINVAL; 1549 goto err; 1550 } 1551 1552 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */ 1553 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1554 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) 1555 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 1556 MLX5_L4_PROT_TYPE_TCP); 1557 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || 1558 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1559 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 1560 MLX5_L4_PROT_TYPE_UDP); 1561 1562 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1563 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6)) 1564 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP; 1565 1566 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) || 1567 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) 1568 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP; 1569 1570 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1571 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP)) 1572 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT; 1573 1574 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) || 1575 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1576 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT; 1577 1578 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields); 1579 1580 create_tir: 1581 if (dev->rep) 1582 MLX5_SET(tirc, tirc, self_lb_block, 1583 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_); 1584 1585 err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn); 1586 1587 if (err) 1588 goto err; 1589 1590 kvfree(in); 1591 /* qpn is reserved for that QP */ 1592 qp->trans_qp.base.mqp.qpn = 0; 1593 qp->flags |= MLX5_IB_QP_RSS; 1594 return 0; 1595 1596 err: 1597 kvfree(in); 1598 return err; 1599 } 1600 1601 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd, 1602 struct ib_qp_init_attr *init_attr, 1603 struct ib_udata *udata, struct mlx5_ib_qp *qp) 1604 { 1605 struct mlx5_ib_resources *devr = &dev->devr; 1606 int inlen = MLX5_ST_SZ_BYTES(create_qp_in); 1607 struct mlx5_core_dev *mdev = dev->mdev; 1608 struct mlx5_ib_create_qp_resp resp; 1609 struct mlx5_ib_cq *send_cq; 1610 struct mlx5_ib_cq *recv_cq; 1611 unsigned long flags; 1612 u32 uidx = MLX5_IB_DEFAULT_UIDX; 1613 struct mlx5_ib_create_qp ucmd; 1614 struct mlx5_ib_qp_base *base; 1615 int mlx5_st; 1616 void *qpc; 1617 u32 *in; 1618 int err; 1619 1620 mutex_init(&qp->mutex); 1621 spin_lock_init(&qp->sq.lock); 1622 spin_lock_init(&qp->rq.lock); 1623 1624 mlx5_st = to_mlx5_st(init_attr->qp_type); 1625 if (mlx5_st < 0) 1626 return -EINVAL; 1627 1628 if (init_attr->rwq_ind_tbl) { 1629 if (!udata) 1630 return -ENOSYS; 1631 1632 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata); 1633 return err; 1634 } 1635 1636 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) { 1637 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) { 1638 mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n"); 1639 return -EINVAL; 1640 } else { 1641 qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK; 1642 } 1643 } 1644 1645 if (init_attr->create_flags & 1646 (IB_QP_CREATE_CROSS_CHANNEL | 1647 IB_QP_CREATE_MANAGED_SEND | 1648 IB_QP_CREATE_MANAGED_RECV)) { 1649 if (!MLX5_CAP_GEN(mdev, cd)) { 1650 mlx5_ib_dbg(dev, "cross-channel isn't supported\n"); 1651 return -EINVAL; 1652 } 1653 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL) 1654 qp->flags |= MLX5_IB_QP_CROSS_CHANNEL; 1655 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND) 1656 qp->flags |= MLX5_IB_QP_MANAGED_SEND; 1657 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV) 1658 qp->flags |= MLX5_IB_QP_MANAGED_RECV; 1659 } 1660 1661 if (init_attr->qp_type == IB_QPT_UD && 1662 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) 1663 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { 1664 mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n"); 1665 return -EOPNOTSUPP; 1666 } 1667 1668 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) { 1669 if (init_attr->qp_type != IB_QPT_RAW_PACKET) { 1670 mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs"); 1671 return -EOPNOTSUPP; 1672 } 1673 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) || 1674 !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) { 1675 mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n"); 1676 return -EOPNOTSUPP; 1677 } 1678 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS; 1679 } 1680 1681 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) 1682 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; 1683 1684 if (init_attr->create_flags & IB_QP_CREATE_CVLAN_STRIPPING) { 1685 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 1686 MLX5_CAP_ETH(dev->mdev, vlan_cap)) || 1687 (init_attr->qp_type != IB_QPT_RAW_PACKET)) 1688 return -EOPNOTSUPP; 1689 qp->flags |= MLX5_IB_QP_CVLAN_STRIPPING; 1690 } 1691 1692 if (pd && pd->uobject) { 1693 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) { 1694 mlx5_ib_dbg(dev, "copy failed\n"); 1695 return -EFAULT; 1696 } 1697 1698 err = get_qp_user_index(to_mucontext(pd->uobject->context), 1699 &ucmd, udata->inlen, &uidx); 1700 if (err) 1701 return err; 1702 1703 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE); 1704 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE); 1705 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) { 1706 if (init_attr->qp_type != IB_QPT_RAW_PACKET || 1707 !tunnel_offload_supported(mdev)) { 1708 mlx5_ib_dbg(dev, "Tunnel offload isn't supported\n"); 1709 return -EOPNOTSUPP; 1710 } 1711 qp->tunnel_offload_en = true; 1712 } 1713 1714 if (init_attr->create_flags & IB_QP_CREATE_SOURCE_QPN) { 1715 if (init_attr->qp_type != IB_QPT_UD || 1716 (MLX5_CAP_GEN(dev->mdev, port_type) != 1717 MLX5_CAP_PORT_TYPE_IB) || 1718 !mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) { 1719 mlx5_ib_dbg(dev, "Source QP option isn't supported\n"); 1720 return -EOPNOTSUPP; 1721 } 1722 1723 qp->flags |= MLX5_IB_QP_UNDERLAY; 1724 qp->underlay_qpn = init_attr->source_qpn; 1725 } 1726 } else { 1727 qp->wq_sig = !!wq_signature; 1728 } 1729 1730 base = (init_attr->qp_type == IB_QPT_RAW_PACKET || 1731 qp->flags & MLX5_IB_QP_UNDERLAY) ? 1732 &qp->raw_packet_qp.rq.base : 1733 &qp->trans_qp.base; 1734 1735 qp->has_rq = qp_has_rq(init_attr); 1736 err = set_rq_size(dev, &init_attr->cap, qp->has_rq, 1737 qp, (pd && pd->uobject) ? &ucmd : NULL); 1738 if (err) { 1739 mlx5_ib_dbg(dev, "err %d\n", err); 1740 return err; 1741 } 1742 1743 if (pd) { 1744 if (pd->uobject) { 1745 __u32 max_wqes = 1746 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 1747 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count); 1748 if (ucmd.rq_wqe_shift != qp->rq.wqe_shift || 1749 ucmd.rq_wqe_count != qp->rq.wqe_cnt) { 1750 mlx5_ib_dbg(dev, "invalid rq params\n"); 1751 return -EINVAL; 1752 } 1753 if (ucmd.sq_wqe_count > max_wqes) { 1754 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n", 1755 ucmd.sq_wqe_count, max_wqes); 1756 return -EINVAL; 1757 } 1758 if (init_attr->create_flags & 1759 mlx5_ib_create_qp_sqpn_qp1()) { 1760 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n"); 1761 return -EINVAL; 1762 } 1763 err = create_user_qp(dev, pd, qp, udata, init_attr, &in, 1764 &resp, &inlen, base); 1765 if (err) 1766 mlx5_ib_dbg(dev, "err %d\n", err); 1767 } else { 1768 err = create_kernel_qp(dev, init_attr, qp, &in, &inlen, 1769 base); 1770 if (err) 1771 mlx5_ib_dbg(dev, "err %d\n", err); 1772 } 1773 1774 if (err) 1775 return err; 1776 } else { 1777 in = kvzalloc(inlen, GFP_KERNEL); 1778 if (!in) 1779 return -ENOMEM; 1780 1781 qp->create_type = MLX5_QP_EMPTY; 1782 } 1783 1784 if (is_sqp(init_attr->qp_type)) 1785 qp->port = init_attr->port_num; 1786 1787 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 1788 1789 MLX5_SET(qpc, qpc, st, mlx5_st); 1790 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 1791 1792 if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR) 1793 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn); 1794 else 1795 MLX5_SET(qpc, qpc, latency_sensitive, 1); 1796 1797 1798 if (qp->wq_sig) 1799 MLX5_SET(qpc, qpc, wq_signature, 1); 1800 1801 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK) 1802 MLX5_SET(qpc, qpc, block_lb_mc, 1); 1803 1804 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) 1805 MLX5_SET(qpc, qpc, cd_master, 1); 1806 if (qp->flags & MLX5_IB_QP_MANAGED_SEND) 1807 MLX5_SET(qpc, qpc, cd_slave_send, 1); 1808 if (qp->flags & MLX5_IB_QP_MANAGED_RECV) 1809 MLX5_SET(qpc, qpc, cd_slave_receive, 1); 1810 1811 if (qp->scat_cqe && is_connected(init_attr->qp_type)) { 1812 int rcqe_sz; 1813 int scqe_sz; 1814 1815 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq); 1816 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq); 1817 1818 if (rcqe_sz == 128) 1819 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE); 1820 else 1821 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA32_CQE); 1822 1823 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) { 1824 if (scqe_sz == 128) 1825 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE); 1826 else 1827 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE); 1828 } 1829 } 1830 1831 if (qp->rq.wqe_cnt) { 1832 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4); 1833 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt)); 1834 } 1835 1836 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr)); 1837 1838 if (qp->sq.wqe_cnt) { 1839 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt)); 1840 } else { 1841 MLX5_SET(qpc, qpc, no_sq, 1); 1842 if (init_attr->srq && 1843 init_attr->srq->srq_type == IB_SRQT_TM) 1844 MLX5_SET(qpc, qpc, offload_type, 1845 MLX5_QPC_OFFLOAD_TYPE_RNDV); 1846 } 1847 1848 /* Set default resources */ 1849 switch (init_attr->qp_type) { 1850 case IB_QPT_XRC_TGT: 1851 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); 1852 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn); 1853 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn); 1854 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn); 1855 break; 1856 case IB_QPT_XRC_INI: 1857 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); 1858 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn); 1859 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn); 1860 break; 1861 default: 1862 if (init_attr->srq) { 1863 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn); 1864 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn); 1865 } else { 1866 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn); 1867 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn); 1868 } 1869 } 1870 1871 if (init_attr->send_cq) 1872 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn); 1873 1874 if (init_attr->recv_cq) 1875 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn); 1876 1877 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 1878 1879 /* 0xffffff means we ask to work with cqe version 0 */ 1880 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) 1881 MLX5_SET(qpc, qpc, user_index, uidx); 1882 1883 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */ 1884 if (init_attr->qp_type == IB_QPT_UD && 1885 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) { 1886 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1); 1887 qp->flags |= MLX5_IB_QP_LSO; 1888 } 1889 1890 if (init_attr->create_flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) { 1891 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) { 1892 mlx5_ib_dbg(dev, "scatter end padding is not supported\n"); 1893 err = -EOPNOTSUPP; 1894 goto err; 1895 } else if (init_attr->qp_type != IB_QPT_RAW_PACKET) { 1896 MLX5_SET(qpc, qpc, end_padding_mode, 1897 MLX5_WQ_END_PAD_MODE_ALIGN); 1898 } else { 1899 qp->flags |= MLX5_IB_QP_PCI_WRITE_END_PADDING; 1900 } 1901 } 1902 1903 if (inlen < 0) { 1904 err = -EINVAL; 1905 goto err; 1906 } 1907 1908 if (init_attr->qp_type == IB_QPT_RAW_PACKET || 1909 qp->flags & MLX5_IB_QP_UNDERLAY) { 1910 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr; 1911 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp); 1912 err = create_raw_packet_qp(dev, qp, in, inlen, pd); 1913 } else { 1914 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen); 1915 } 1916 1917 if (err) { 1918 mlx5_ib_dbg(dev, "create qp failed\n"); 1919 goto err_create; 1920 } 1921 1922 kvfree(in); 1923 1924 base->container_mibqp = qp; 1925 base->mqp.event = mlx5_ib_qp_event; 1926 1927 get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq, 1928 &send_cq, &recv_cq); 1929 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 1930 mlx5_ib_lock_cqs(send_cq, recv_cq); 1931 /* Maintain device to QPs access, needed for further handling via reset 1932 * flow 1933 */ 1934 list_add_tail(&qp->qps_list, &dev->qp_list); 1935 /* Maintain CQ to QPs access, needed for further handling via reset flow 1936 */ 1937 if (send_cq) 1938 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp); 1939 if (recv_cq) 1940 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp); 1941 mlx5_ib_unlock_cqs(send_cq, recv_cq); 1942 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 1943 1944 return 0; 1945 1946 err_create: 1947 if (qp->create_type == MLX5_QP_USER) 1948 destroy_qp_user(dev, pd, qp, base); 1949 else if (qp->create_type == MLX5_QP_KERNEL) 1950 destroy_qp_kernel(dev, qp); 1951 1952 err: 1953 kvfree(in); 1954 return err; 1955 } 1956 1957 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 1958 __acquires(&send_cq->lock) __acquires(&recv_cq->lock) 1959 { 1960 if (send_cq) { 1961 if (recv_cq) { 1962 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 1963 spin_lock(&send_cq->lock); 1964 spin_lock_nested(&recv_cq->lock, 1965 SINGLE_DEPTH_NESTING); 1966 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 1967 spin_lock(&send_cq->lock); 1968 __acquire(&recv_cq->lock); 1969 } else { 1970 spin_lock(&recv_cq->lock); 1971 spin_lock_nested(&send_cq->lock, 1972 SINGLE_DEPTH_NESTING); 1973 } 1974 } else { 1975 spin_lock(&send_cq->lock); 1976 __acquire(&recv_cq->lock); 1977 } 1978 } else if (recv_cq) { 1979 spin_lock(&recv_cq->lock); 1980 __acquire(&send_cq->lock); 1981 } else { 1982 __acquire(&send_cq->lock); 1983 __acquire(&recv_cq->lock); 1984 } 1985 } 1986 1987 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 1988 __releases(&send_cq->lock) __releases(&recv_cq->lock) 1989 { 1990 if (send_cq) { 1991 if (recv_cq) { 1992 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 1993 spin_unlock(&recv_cq->lock); 1994 spin_unlock(&send_cq->lock); 1995 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 1996 __release(&recv_cq->lock); 1997 spin_unlock(&send_cq->lock); 1998 } else { 1999 spin_unlock(&send_cq->lock); 2000 spin_unlock(&recv_cq->lock); 2001 } 2002 } else { 2003 __release(&recv_cq->lock); 2004 spin_unlock(&send_cq->lock); 2005 } 2006 } else if (recv_cq) { 2007 __release(&send_cq->lock); 2008 spin_unlock(&recv_cq->lock); 2009 } else { 2010 __release(&recv_cq->lock); 2011 __release(&send_cq->lock); 2012 } 2013 } 2014 2015 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp) 2016 { 2017 return to_mpd(qp->ibqp.pd); 2018 } 2019 2020 static void get_cqs(enum ib_qp_type qp_type, 2021 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, 2022 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq) 2023 { 2024 switch (qp_type) { 2025 case IB_QPT_XRC_TGT: 2026 *send_cq = NULL; 2027 *recv_cq = NULL; 2028 break; 2029 case MLX5_IB_QPT_REG_UMR: 2030 case IB_QPT_XRC_INI: 2031 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; 2032 *recv_cq = NULL; 2033 break; 2034 2035 case IB_QPT_SMI: 2036 case MLX5_IB_QPT_HW_GSI: 2037 case IB_QPT_RC: 2038 case IB_QPT_UC: 2039 case IB_QPT_UD: 2040 case IB_QPT_RAW_IPV6: 2041 case IB_QPT_RAW_ETHERTYPE: 2042 case IB_QPT_RAW_PACKET: 2043 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; 2044 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL; 2045 break; 2046 2047 case IB_QPT_MAX: 2048 default: 2049 *send_cq = NULL; 2050 *recv_cq = NULL; 2051 break; 2052 } 2053 } 2054 2055 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2056 const struct mlx5_modify_raw_qp_param *raw_qp_param, 2057 u8 lag_tx_affinity); 2058 2059 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 2060 { 2061 struct mlx5_ib_cq *send_cq, *recv_cq; 2062 struct mlx5_ib_qp_base *base; 2063 unsigned long flags; 2064 int err; 2065 2066 if (qp->ibqp.rwq_ind_tbl) { 2067 destroy_rss_raw_qp_tir(dev, qp); 2068 return; 2069 } 2070 2071 base = (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || 2072 qp->flags & MLX5_IB_QP_UNDERLAY) ? 2073 &qp->raw_packet_qp.rq.base : 2074 &qp->trans_qp.base; 2075 2076 if (qp->state != IB_QPS_RESET) { 2077 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET && 2078 !(qp->flags & MLX5_IB_QP_UNDERLAY)) { 2079 err = mlx5_core_qp_modify(dev->mdev, 2080 MLX5_CMD_OP_2RST_QP, 0, 2081 NULL, &base->mqp); 2082 } else { 2083 struct mlx5_modify_raw_qp_param raw_qp_param = { 2084 .operation = MLX5_CMD_OP_2RST_QP 2085 }; 2086 2087 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0); 2088 } 2089 if (err) 2090 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n", 2091 base->mqp.qpn); 2092 } 2093 2094 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq, 2095 &send_cq, &recv_cq); 2096 2097 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 2098 mlx5_ib_lock_cqs(send_cq, recv_cq); 2099 /* del from lists under both locks above to protect reset flow paths */ 2100 list_del(&qp->qps_list); 2101 if (send_cq) 2102 list_del(&qp->cq_send_list); 2103 2104 if (recv_cq) 2105 list_del(&qp->cq_recv_list); 2106 2107 if (qp->create_type == MLX5_QP_KERNEL) { 2108 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 2109 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL); 2110 if (send_cq != recv_cq) 2111 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn, 2112 NULL); 2113 } 2114 mlx5_ib_unlock_cqs(send_cq, recv_cq); 2115 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 2116 2117 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || 2118 qp->flags & MLX5_IB_QP_UNDERLAY) { 2119 destroy_raw_packet_qp(dev, qp); 2120 } else { 2121 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp); 2122 if (err) 2123 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n", 2124 base->mqp.qpn); 2125 } 2126 2127 if (qp->create_type == MLX5_QP_KERNEL) 2128 destroy_qp_kernel(dev, qp); 2129 else if (qp->create_type == MLX5_QP_USER) 2130 destroy_qp_user(dev, &get_pd(qp)->ibpd, qp, base); 2131 } 2132 2133 static const char *ib_qp_type_str(enum ib_qp_type type) 2134 { 2135 switch (type) { 2136 case IB_QPT_SMI: 2137 return "IB_QPT_SMI"; 2138 case IB_QPT_GSI: 2139 return "IB_QPT_GSI"; 2140 case IB_QPT_RC: 2141 return "IB_QPT_RC"; 2142 case IB_QPT_UC: 2143 return "IB_QPT_UC"; 2144 case IB_QPT_UD: 2145 return "IB_QPT_UD"; 2146 case IB_QPT_RAW_IPV6: 2147 return "IB_QPT_RAW_IPV6"; 2148 case IB_QPT_RAW_ETHERTYPE: 2149 return "IB_QPT_RAW_ETHERTYPE"; 2150 case IB_QPT_XRC_INI: 2151 return "IB_QPT_XRC_INI"; 2152 case IB_QPT_XRC_TGT: 2153 return "IB_QPT_XRC_TGT"; 2154 case IB_QPT_RAW_PACKET: 2155 return "IB_QPT_RAW_PACKET"; 2156 case MLX5_IB_QPT_REG_UMR: 2157 return "MLX5_IB_QPT_REG_UMR"; 2158 case IB_QPT_DRIVER: 2159 return "IB_QPT_DRIVER"; 2160 case IB_QPT_MAX: 2161 default: 2162 return "Invalid QP type"; 2163 } 2164 } 2165 2166 static struct ib_qp *mlx5_ib_create_dct(struct ib_pd *pd, 2167 struct ib_qp_init_attr *attr, 2168 struct mlx5_ib_create_qp *ucmd) 2169 { 2170 struct mlx5_ib_qp *qp; 2171 int err = 0; 2172 u32 uidx = MLX5_IB_DEFAULT_UIDX; 2173 void *dctc; 2174 2175 if (!attr->srq || !attr->recv_cq) 2176 return ERR_PTR(-EINVAL); 2177 2178 err = get_qp_user_index(to_mucontext(pd->uobject->context), 2179 ucmd, sizeof(*ucmd), &uidx); 2180 if (err) 2181 return ERR_PTR(err); 2182 2183 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 2184 if (!qp) 2185 return ERR_PTR(-ENOMEM); 2186 2187 qp->dct.in = kzalloc(MLX5_ST_SZ_BYTES(create_dct_in), GFP_KERNEL); 2188 if (!qp->dct.in) { 2189 err = -ENOMEM; 2190 goto err_free; 2191 } 2192 2193 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry); 2194 qp->qp_sub_type = MLX5_IB_QPT_DCT; 2195 MLX5_SET(dctc, dctc, pd, to_mpd(pd)->pdn); 2196 MLX5_SET(dctc, dctc, srqn_xrqn, to_msrq(attr->srq)->msrq.srqn); 2197 MLX5_SET(dctc, dctc, cqn, to_mcq(attr->recv_cq)->mcq.cqn); 2198 MLX5_SET64(dctc, dctc, dc_access_key, ucmd->access_key); 2199 MLX5_SET(dctc, dctc, user_index, uidx); 2200 2201 qp->state = IB_QPS_RESET; 2202 2203 return &qp->ibqp; 2204 err_free: 2205 kfree(qp); 2206 return ERR_PTR(err); 2207 } 2208 2209 static int set_mlx_qp_type(struct mlx5_ib_dev *dev, 2210 struct ib_qp_init_attr *init_attr, 2211 struct mlx5_ib_create_qp *ucmd, 2212 struct ib_udata *udata) 2213 { 2214 enum { MLX_QP_FLAGS = MLX5_QP_FLAG_TYPE_DCT | MLX5_QP_FLAG_TYPE_DCI }; 2215 int err; 2216 2217 if (!udata) 2218 return -EINVAL; 2219 2220 if (udata->inlen < sizeof(*ucmd)) { 2221 mlx5_ib_dbg(dev, "create_qp user command is smaller than expected\n"); 2222 return -EINVAL; 2223 } 2224 err = ib_copy_from_udata(ucmd, udata, sizeof(*ucmd)); 2225 if (err) 2226 return err; 2227 2228 if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCI) { 2229 init_attr->qp_type = MLX5_IB_QPT_DCI; 2230 } else { 2231 if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCT) { 2232 init_attr->qp_type = MLX5_IB_QPT_DCT; 2233 } else { 2234 mlx5_ib_dbg(dev, "Invalid QP flags\n"); 2235 return -EINVAL; 2236 } 2237 } 2238 2239 if (!MLX5_CAP_GEN(dev->mdev, dct)) { 2240 mlx5_ib_dbg(dev, "DC transport is not supported\n"); 2241 return -EOPNOTSUPP; 2242 } 2243 2244 return 0; 2245 } 2246 2247 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, 2248 struct ib_qp_init_attr *verbs_init_attr, 2249 struct ib_udata *udata) 2250 { 2251 struct mlx5_ib_dev *dev; 2252 struct mlx5_ib_qp *qp; 2253 u16 xrcdn = 0; 2254 int err; 2255 struct ib_qp_init_attr mlx_init_attr; 2256 struct ib_qp_init_attr *init_attr = verbs_init_attr; 2257 2258 if (pd) { 2259 dev = to_mdev(pd->device); 2260 2261 if (init_attr->qp_type == IB_QPT_RAW_PACKET) { 2262 if (!pd->uobject) { 2263 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n"); 2264 return ERR_PTR(-EINVAL); 2265 } else if (!to_mucontext(pd->uobject->context)->cqe_version) { 2266 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n"); 2267 return ERR_PTR(-EINVAL); 2268 } 2269 } 2270 } else { 2271 /* being cautious here */ 2272 if (init_attr->qp_type != IB_QPT_XRC_TGT && 2273 init_attr->qp_type != MLX5_IB_QPT_REG_UMR) { 2274 pr_warn("%s: no PD for transport %s\n", __func__, 2275 ib_qp_type_str(init_attr->qp_type)); 2276 return ERR_PTR(-EINVAL); 2277 } 2278 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device); 2279 } 2280 2281 if (init_attr->qp_type == IB_QPT_DRIVER) { 2282 struct mlx5_ib_create_qp ucmd; 2283 2284 init_attr = &mlx_init_attr; 2285 memcpy(init_attr, verbs_init_attr, sizeof(*verbs_init_attr)); 2286 err = set_mlx_qp_type(dev, init_attr, &ucmd, udata); 2287 if (err) 2288 return ERR_PTR(err); 2289 2290 if (init_attr->qp_type == MLX5_IB_QPT_DCI) { 2291 if (init_attr->cap.max_recv_wr || 2292 init_attr->cap.max_recv_sge) { 2293 mlx5_ib_dbg(dev, "DCI QP requires zero size receive queue\n"); 2294 return ERR_PTR(-EINVAL); 2295 } 2296 } else { 2297 return mlx5_ib_create_dct(pd, init_attr, &ucmd); 2298 } 2299 } 2300 2301 switch (init_attr->qp_type) { 2302 case IB_QPT_XRC_TGT: 2303 case IB_QPT_XRC_INI: 2304 if (!MLX5_CAP_GEN(dev->mdev, xrc)) { 2305 mlx5_ib_dbg(dev, "XRC not supported\n"); 2306 return ERR_PTR(-ENOSYS); 2307 } 2308 init_attr->recv_cq = NULL; 2309 if (init_attr->qp_type == IB_QPT_XRC_TGT) { 2310 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn; 2311 init_attr->send_cq = NULL; 2312 } 2313 2314 /* fall through */ 2315 case IB_QPT_RAW_PACKET: 2316 case IB_QPT_RC: 2317 case IB_QPT_UC: 2318 case IB_QPT_UD: 2319 case IB_QPT_SMI: 2320 case MLX5_IB_QPT_HW_GSI: 2321 case MLX5_IB_QPT_REG_UMR: 2322 case MLX5_IB_QPT_DCI: 2323 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 2324 if (!qp) 2325 return ERR_PTR(-ENOMEM); 2326 2327 err = create_qp_common(dev, pd, init_attr, udata, qp); 2328 if (err) { 2329 mlx5_ib_dbg(dev, "create_qp_common failed\n"); 2330 kfree(qp); 2331 return ERR_PTR(err); 2332 } 2333 2334 if (is_qp0(init_attr->qp_type)) 2335 qp->ibqp.qp_num = 0; 2336 else if (is_qp1(init_attr->qp_type)) 2337 qp->ibqp.qp_num = 1; 2338 else 2339 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn; 2340 2341 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n", 2342 qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn, 2343 init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1, 2344 init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1); 2345 2346 qp->trans_qp.xrcdn = xrcdn; 2347 2348 break; 2349 2350 case IB_QPT_GSI: 2351 return mlx5_ib_gsi_create_qp(pd, init_attr); 2352 2353 case IB_QPT_RAW_IPV6: 2354 case IB_QPT_RAW_ETHERTYPE: 2355 case IB_QPT_MAX: 2356 default: 2357 mlx5_ib_dbg(dev, "unsupported qp type %d\n", 2358 init_attr->qp_type); 2359 /* Don't support raw QPs */ 2360 return ERR_PTR(-EINVAL); 2361 } 2362 2363 if (verbs_init_attr->qp_type == IB_QPT_DRIVER) 2364 qp->qp_sub_type = init_attr->qp_type; 2365 2366 return &qp->ibqp; 2367 } 2368 2369 static int mlx5_ib_destroy_dct(struct mlx5_ib_qp *mqp) 2370 { 2371 struct mlx5_ib_dev *dev = to_mdev(mqp->ibqp.device); 2372 2373 if (mqp->state == IB_QPS_RTR) { 2374 int err; 2375 2376 err = mlx5_core_destroy_dct(dev->mdev, &mqp->dct.mdct); 2377 if (err) { 2378 mlx5_ib_warn(dev, "failed to destroy DCT %d\n", err); 2379 return err; 2380 } 2381 } 2382 2383 kfree(mqp->dct.in); 2384 kfree(mqp); 2385 return 0; 2386 } 2387 2388 int mlx5_ib_destroy_qp(struct ib_qp *qp) 2389 { 2390 struct mlx5_ib_dev *dev = to_mdev(qp->device); 2391 struct mlx5_ib_qp *mqp = to_mqp(qp); 2392 2393 if (unlikely(qp->qp_type == IB_QPT_GSI)) 2394 return mlx5_ib_gsi_destroy_qp(qp); 2395 2396 if (mqp->qp_sub_type == MLX5_IB_QPT_DCT) 2397 return mlx5_ib_destroy_dct(mqp); 2398 2399 destroy_qp_common(dev, mqp); 2400 2401 kfree(mqp); 2402 2403 return 0; 2404 } 2405 2406 static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr, 2407 int attr_mask) 2408 { 2409 u32 hw_access_flags = 0; 2410 u8 dest_rd_atomic; 2411 u32 access_flags; 2412 2413 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 2414 dest_rd_atomic = attr->max_dest_rd_atomic; 2415 else 2416 dest_rd_atomic = qp->trans_qp.resp_depth; 2417 2418 if (attr_mask & IB_QP_ACCESS_FLAGS) 2419 access_flags = attr->qp_access_flags; 2420 else 2421 access_flags = qp->trans_qp.atomic_rd_en; 2422 2423 if (!dest_rd_atomic) 2424 access_flags &= IB_ACCESS_REMOTE_WRITE; 2425 2426 if (access_flags & IB_ACCESS_REMOTE_READ) 2427 hw_access_flags |= MLX5_QP_BIT_RRE; 2428 if (access_flags & IB_ACCESS_REMOTE_ATOMIC) 2429 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX); 2430 if (access_flags & IB_ACCESS_REMOTE_WRITE) 2431 hw_access_flags |= MLX5_QP_BIT_RWE; 2432 2433 return cpu_to_be32(hw_access_flags); 2434 } 2435 2436 enum { 2437 MLX5_PATH_FLAG_FL = 1 << 0, 2438 MLX5_PATH_FLAG_FREE_AR = 1 << 1, 2439 MLX5_PATH_FLAG_COUNTER = 1 << 2, 2440 }; 2441 2442 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate) 2443 { 2444 if (rate == IB_RATE_PORT_CURRENT) { 2445 return 0; 2446 } else if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS) { 2447 return -EINVAL; 2448 } else { 2449 while (rate != IB_RATE_2_5_GBPS && 2450 !(1 << (rate + MLX5_STAT_RATE_OFFSET) & 2451 MLX5_CAP_GEN(dev->mdev, stat_rate_support))) 2452 --rate; 2453 } 2454 2455 return rate + MLX5_STAT_RATE_OFFSET; 2456 } 2457 2458 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev, 2459 struct mlx5_ib_sq *sq, u8 sl) 2460 { 2461 void *in; 2462 void *tisc; 2463 int inlen; 2464 int err; 2465 2466 inlen = MLX5_ST_SZ_BYTES(modify_tis_in); 2467 in = kvzalloc(inlen, GFP_KERNEL); 2468 if (!in) 2469 return -ENOMEM; 2470 2471 MLX5_SET(modify_tis_in, in, bitmask.prio, 1); 2472 2473 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); 2474 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1)); 2475 2476 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen); 2477 2478 kvfree(in); 2479 2480 return err; 2481 } 2482 2483 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev, 2484 struct mlx5_ib_sq *sq, u8 tx_affinity) 2485 { 2486 void *in; 2487 void *tisc; 2488 int inlen; 2489 int err; 2490 2491 inlen = MLX5_ST_SZ_BYTES(modify_tis_in); 2492 in = kvzalloc(inlen, GFP_KERNEL); 2493 if (!in) 2494 return -ENOMEM; 2495 2496 MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1); 2497 2498 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); 2499 MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity); 2500 2501 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen); 2502 2503 kvfree(in); 2504 2505 return err; 2506 } 2507 2508 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2509 const struct rdma_ah_attr *ah, 2510 struct mlx5_qp_path *path, u8 port, int attr_mask, 2511 u32 path_flags, const struct ib_qp_attr *attr, 2512 bool alt) 2513 { 2514 const struct ib_global_route *grh = rdma_ah_read_grh(ah); 2515 int err; 2516 enum ib_gid_type gid_type; 2517 u8 ah_flags = rdma_ah_get_ah_flags(ah); 2518 u8 sl = rdma_ah_get_sl(ah); 2519 2520 if (attr_mask & IB_QP_PKEY_INDEX) 2521 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index : 2522 attr->pkey_index); 2523 2524 if (ah_flags & IB_AH_GRH) { 2525 if (grh->sgid_index >= 2526 dev->mdev->port_caps[port - 1].gid_table_len) { 2527 pr_err("sgid_index (%u) too large. max is %d\n", 2528 grh->sgid_index, 2529 dev->mdev->port_caps[port - 1].gid_table_len); 2530 return -EINVAL; 2531 } 2532 } 2533 2534 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) { 2535 if (!(ah_flags & IB_AH_GRH)) 2536 return -EINVAL; 2537 err = mlx5_get_roce_gid_type(dev, port, grh->sgid_index, 2538 &gid_type); 2539 if (err) 2540 return err; 2541 memcpy(path->rmac, ah->roce.dmac, sizeof(ah->roce.dmac)); 2542 if (qp->ibqp.qp_type == IB_QPT_RC || 2543 qp->ibqp.qp_type == IB_QPT_UC || 2544 qp->ibqp.qp_type == IB_QPT_XRC_INI || 2545 qp->ibqp.qp_type == IB_QPT_XRC_TGT) 2546 path->udp_sport = mlx5_get_roce_udp_sport(dev, port, 2547 grh->sgid_index); 2548 path->dci_cfi_prio_sl = (sl & 0x7) << 4; 2549 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) 2550 path->ecn_dscp = (grh->traffic_class >> 2) & 0x3f; 2551 } else { 2552 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0; 2553 path->fl_free_ar |= 2554 (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0; 2555 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah)); 2556 path->grh_mlid = rdma_ah_get_path_bits(ah) & 0x7f; 2557 if (ah_flags & IB_AH_GRH) 2558 path->grh_mlid |= 1 << 7; 2559 path->dci_cfi_prio_sl = sl & 0xf; 2560 } 2561 2562 if (ah_flags & IB_AH_GRH) { 2563 path->mgid_index = grh->sgid_index; 2564 path->hop_limit = grh->hop_limit; 2565 path->tclass_flowlabel = 2566 cpu_to_be32((grh->traffic_class << 20) | 2567 (grh->flow_label)); 2568 memcpy(path->rgid, grh->dgid.raw, 16); 2569 } 2570 2571 err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah)); 2572 if (err < 0) 2573 return err; 2574 path->static_rate = err; 2575 path->port = port; 2576 2577 if (attr_mask & IB_QP_TIMEOUT) 2578 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3; 2579 2580 if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt) 2581 return modify_raw_packet_eth_prio(dev->mdev, 2582 &qp->raw_packet_qp.sq, 2583 sl & 0xf); 2584 2585 return 0; 2586 } 2587 2588 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = { 2589 [MLX5_QP_STATE_INIT] = { 2590 [MLX5_QP_STATE_INIT] = { 2591 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 2592 MLX5_QP_OPTPAR_RAE | 2593 MLX5_QP_OPTPAR_RWE | 2594 MLX5_QP_OPTPAR_PKEY_INDEX | 2595 MLX5_QP_OPTPAR_PRI_PORT, 2596 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 2597 MLX5_QP_OPTPAR_PKEY_INDEX | 2598 MLX5_QP_OPTPAR_PRI_PORT, 2599 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 2600 MLX5_QP_OPTPAR_Q_KEY | 2601 MLX5_QP_OPTPAR_PRI_PORT, 2602 }, 2603 [MLX5_QP_STATE_RTR] = { 2604 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2605 MLX5_QP_OPTPAR_RRE | 2606 MLX5_QP_OPTPAR_RAE | 2607 MLX5_QP_OPTPAR_RWE | 2608 MLX5_QP_OPTPAR_PKEY_INDEX, 2609 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2610 MLX5_QP_OPTPAR_RWE | 2611 MLX5_QP_OPTPAR_PKEY_INDEX, 2612 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 2613 MLX5_QP_OPTPAR_Q_KEY, 2614 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX | 2615 MLX5_QP_OPTPAR_Q_KEY, 2616 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2617 MLX5_QP_OPTPAR_RRE | 2618 MLX5_QP_OPTPAR_RAE | 2619 MLX5_QP_OPTPAR_RWE | 2620 MLX5_QP_OPTPAR_PKEY_INDEX, 2621 }, 2622 }, 2623 [MLX5_QP_STATE_RTR] = { 2624 [MLX5_QP_STATE_RTS] = { 2625 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2626 MLX5_QP_OPTPAR_RRE | 2627 MLX5_QP_OPTPAR_RAE | 2628 MLX5_QP_OPTPAR_RWE | 2629 MLX5_QP_OPTPAR_PM_STATE | 2630 MLX5_QP_OPTPAR_RNR_TIMEOUT, 2631 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2632 MLX5_QP_OPTPAR_RWE | 2633 MLX5_QP_OPTPAR_PM_STATE, 2634 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 2635 }, 2636 }, 2637 [MLX5_QP_STATE_RTS] = { 2638 [MLX5_QP_STATE_RTS] = { 2639 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 2640 MLX5_QP_OPTPAR_RAE | 2641 MLX5_QP_OPTPAR_RWE | 2642 MLX5_QP_OPTPAR_RNR_TIMEOUT | 2643 MLX5_QP_OPTPAR_PM_STATE | 2644 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 2645 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 2646 MLX5_QP_OPTPAR_PM_STATE | 2647 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 2648 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY | 2649 MLX5_QP_OPTPAR_SRQN | 2650 MLX5_QP_OPTPAR_CQN_RCV, 2651 }, 2652 }, 2653 [MLX5_QP_STATE_SQER] = { 2654 [MLX5_QP_STATE_RTS] = { 2655 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 2656 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY, 2657 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE, 2658 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT | 2659 MLX5_QP_OPTPAR_RWE | 2660 MLX5_QP_OPTPAR_RAE | 2661 MLX5_QP_OPTPAR_RRE, 2662 }, 2663 }, 2664 }; 2665 2666 static int ib_nr_to_mlx5_nr(int ib_mask) 2667 { 2668 switch (ib_mask) { 2669 case IB_QP_STATE: 2670 return 0; 2671 case IB_QP_CUR_STATE: 2672 return 0; 2673 case IB_QP_EN_SQD_ASYNC_NOTIFY: 2674 return 0; 2675 case IB_QP_ACCESS_FLAGS: 2676 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE | 2677 MLX5_QP_OPTPAR_RAE; 2678 case IB_QP_PKEY_INDEX: 2679 return MLX5_QP_OPTPAR_PKEY_INDEX; 2680 case IB_QP_PORT: 2681 return MLX5_QP_OPTPAR_PRI_PORT; 2682 case IB_QP_QKEY: 2683 return MLX5_QP_OPTPAR_Q_KEY; 2684 case IB_QP_AV: 2685 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH | 2686 MLX5_QP_OPTPAR_PRI_PORT; 2687 case IB_QP_PATH_MTU: 2688 return 0; 2689 case IB_QP_TIMEOUT: 2690 return MLX5_QP_OPTPAR_ACK_TIMEOUT; 2691 case IB_QP_RETRY_CNT: 2692 return MLX5_QP_OPTPAR_RETRY_COUNT; 2693 case IB_QP_RNR_RETRY: 2694 return MLX5_QP_OPTPAR_RNR_RETRY; 2695 case IB_QP_RQ_PSN: 2696 return 0; 2697 case IB_QP_MAX_QP_RD_ATOMIC: 2698 return MLX5_QP_OPTPAR_SRA_MAX; 2699 case IB_QP_ALT_PATH: 2700 return MLX5_QP_OPTPAR_ALT_ADDR_PATH; 2701 case IB_QP_MIN_RNR_TIMER: 2702 return MLX5_QP_OPTPAR_RNR_TIMEOUT; 2703 case IB_QP_SQ_PSN: 2704 return 0; 2705 case IB_QP_MAX_DEST_RD_ATOMIC: 2706 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE | 2707 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE; 2708 case IB_QP_PATH_MIG_STATE: 2709 return MLX5_QP_OPTPAR_PM_STATE; 2710 case IB_QP_CAP: 2711 return 0; 2712 case IB_QP_DEST_QPN: 2713 return 0; 2714 } 2715 return 0; 2716 } 2717 2718 static int ib_mask_to_mlx5_opt(int ib_mask) 2719 { 2720 int result = 0; 2721 int i; 2722 2723 for (i = 0; i < 8 * sizeof(int); i++) { 2724 if ((1 << i) & ib_mask) 2725 result |= ib_nr_to_mlx5_nr(1 << i); 2726 } 2727 2728 return result; 2729 } 2730 2731 static int modify_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 2732 struct mlx5_ib_rq *rq, int new_state, 2733 const struct mlx5_modify_raw_qp_param *raw_qp_param) 2734 { 2735 void *in; 2736 void *rqc; 2737 int inlen; 2738 int err; 2739 2740 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 2741 in = kvzalloc(inlen, GFP_KERNEL); 2742 if (!in) 2743 return -ENOMEM; 2744 2745 MLX5_SET(modify_rq_in, in, rq_state, rq->state); 2746 2747 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 2748 MLX5_SET(rqc, rqc, state, new_state); 2749 2750 if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) { 2751 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) { 2752 MLX5_SET64(modify_rq_in, in, modify_bitmask, 2753 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID); 2754 MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id); 2755 } else 2756 pr_info_once("%s: RAW PACKET QP counters are not supported on current FW\n", 2757 dev->ib_dev.name); 2758 } 2759 2760 err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in, inlen); 2761 if (err) 2762 goto out; 2763 2764 rq->state = new_state; 2765 2766 out: 2767 kvfree(in); 2768 return err; 2769 } 2770 2771 static int modify_raw_packet_qp_sq(struct mlx5_core_dev *dev, 2772 struct mlx5_ib_sq *sq, 2773 int new_state, 2774 const struct mlx5_modify_raw_qp_param *raw_qp_param) 2775 { 2776 struct mlx5_ib_qp *ibqp = sq->base.container_mibqp; 2777 u32 old_rate = ibqp->rate_limit; 2778 u32 new_rate = old_rate; 2779 u16 rl_index = 0; 2780 void *in; 2781 void *sqc; 2782 int inlen; 2783 int err; 2784 2785 inlen = MLX5_ST_SZ_BYTES(modify_sq_in); 2786 in = kvzalloc(inlen, GFP_KERNEL); 2787 if (!in) 2788 return -ENOMEM; 2789 2790 MLX5_SET(modify_sq_in, in, sq_state, sq->state); 2791 2792 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx); 2793 MLX5_SET(sqc, sqc, state, new_state); 2794 2795 if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) { 2796 if (new_state != MLX5_SQC_STATE_RDY) 2797 pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n", 2798 __func__); 2799 else 2800 new_rate = raw_qp_param->rate_limit; 2801 } 2802 2803 if (old_rate != new_rate) { 2804 if (new_rate) { 2805 err = mlx5_rl_add_rate(dev, new_rate, &rl_index); 2806 if (err) { 2807 pr_err("Failed configuring rate %u: %d\n", 2808 new_rate, err); 2809 goto out; 2810 } 2811 } 2812 2813 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1); 2814 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index); 2815 } 2816 2817 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen); 2818 if (err) { 2819 /* Remove new rate from table if failed */ 2820 if (new_rate && 2821 old_rate != new_rate) 2822 mlx5_rl_remove_rate(dev, new_rate); 2823 goto out; 2824 } 2825 2826 /* Only remove the old rate after new rate was set */ 2827 if ((old_rate && 2828 (old_rate != new_rate)) || 2829 (new_state != MLX5_SQC_STATE_RDY)) 2830 mlx5_rl_remove_rate(dev, old_rate); 2831 2832 ibqp->rate_limit = new_rate; 2833 sq->state = new_state; 2834 2835 out: 2836 kvfree(in); 2837 return err; 2838 } 2839 2840 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2841 const struct mlx5_modify_raw_qp_param *raw_qp_param, 2842 u8 tx_affinity) 2843 { 2844 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 2845 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 2846 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 2847 int modify_rq = !!qp->rq.wqe_cnt; 2848 int modify_sq = !!qp->sq.wqe_cnt; 2849 int rq_state; 2850 int sq_state; 2851 int err; 2852 2853 switch (raw_qp_param->operation) { 2854 case MLX5_CMD_OP_RST2INIT_QP: 2855 rq_state = MLX5_RQC_STATE_RDY; 2856 sq_state = MLX5_SQC_STATE_RDY; 2857 break; 2858 case MLX5_CMD_OP_2ERR_QP: 2859 rq_state = MLX5_RQC_STATE_ERR; 2860 sq_state = MLX5_SQC_STATE_ERR; 2861 break; 2862 case MLX5_CMD_OP_2RST_QP: 2863 rq_state = MLX5_RQC_STATE_RST; 2864 sq_state = MLX5_SQC_STATE_RST; 2865 break; 2866 case MLX5_CMD_OP_RTR2RTS_QP: 2867 case MLX5_CMD_OP_RTS2RTS_QP: 2868 if (raw_qp_param->set_mask == 2869 MLX5_RAW_QP_RATE_LIMIT) { 2870 modify_rq = 0; 2871 sq_state = sq->state; 2872 } else { 2873 return raw_qp_param->set_mask ? -EINVAL : 0; 2874 } 2875 break; 2876 case MLX5_CMD_OP_INIT2INIT_QP: 2877 case MLX5_CMD_OP_INIT2RTR_QP: 2878 if (raw_qp_param->set_mask) 2879 return -EINVAL; 2880 else 2881 return 0; 2882 default: 2883 WARN_ON(1); 2884 return -EINVAL; 2885 } 2886 2887 if (modify_rq) { 2888 err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param); 2889 if (err) 2890 return err; 2891 } 2892 2893 if (modify_sq) { 2894 if (tx_affinity) { 2895 err = modify_raw_packet_tx_affinity(dev->mdev, sq, 2896 tx_affinity); 2897 if (err) 2898 return err; 2899 } 2900 2901 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state, raw_qp_param); 2902 } 2903 2904 return 0; 2905 } 2906 2907 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp, 2908 const struct ib_qp_attr *attr, int attr_mask, 2909 enum ib_qp_state cur_state, enum ib_qp_state new_state) 2910 { 2911 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = { 2912 [MLX5_QP_STATE_RST] = { 2913 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2914 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2915 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP, 2916 }, 2917 [MLX5_QP_STATE_INIT] = { 2918 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2919 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2920 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP, 2921 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP, 2922 }, 2923 [MLX5_QP_STATE_RTR] = { 2924 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2925 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2926 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP, 2927 }, 2928 [MLX5_QP_STATE_RTS] = { 2929 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2930 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2931 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP, 2932 }, 2933 [MLX5_QP_STATE_SQD] = { 2934 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2935 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2936 }, 2937 [MLX5_QP_STATE_SQER] = { 2938 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2939 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2940 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP, 2941 }, 2942 [MLX5_QP_STATE_ERR] = { 2943 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2944 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2945 } 2946 }; 2947 2948 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2949 struct mlx5_ib_qp *qp = to_mqp(ibqp); 2950 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 2951 struct mlx5_ib_cq *send_cq, *recv_cq; 2952 struct mlx5_qp_context *context; 2953 struct mlx5_ib_pd *pd; 2954 struct mlx5_ib_port *mibport = NULL; 2955 enum mlx5_qp_state mlx5_cur, mlx5_new; 2956 enum mlx5_qp_optpar optpar; 2957 int mlx5_st; 2958 int err; 2959 u16 op; 2960 u8 tx_affinity = 0; 2961 2962 context = kzalloc(sizeof(*context), GFP_KERNEL); 2963 if (!context) 2964 return -ENOMEM; 2965 2966 err = to_mlx5_st(ibqp->qp_type == IB_QPT_DRIVER ? 2967 qp->qp_sub_type : ibqp->qp_type); 2968 if (err < 0) { 2969 mlx5_ib_dbg(dev, "unsupported qp type %d\n", ibqp->qp_type); 2970 goto out; 2971 } 2972 2973 context->flags = cpu_to_be32(err << 16); 2974 2975 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) { 2976 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11); 2977 } else { 2978 switch (attr->path_mig_state) { 2979 case IB_MIG_MIGRATED: 2980 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11); 2981 break; 2982 case IB_MIG_REARM: 2983 context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11); 2984 break; 2985 case IB_MIG_ARMED: 2986 context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11); 2987 break; 2988 } 2989 } 2990 2991 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) { 2992 if ((ibqp->qp_type == IB_QPT_RC) || 2993 (ibqp->qp_type == IB_QPT_UD && 2994 !(qp->flags & MLX5_IB_QP_SQPN_QP1)) || 2995 (ibqp->qp_type == IB_QPT_UC) || 2996 (ibqp->qp_type == IB_QPT_RAW_PACKET) || 2997 (ibqp->qp_type == IB_QPT_XRC_INI) || 2998 (ibqp->qp_type == IB_QPT_XRC_TGT)) { 2999 if (mlx5_lag_is_active(dev->mdev)) { 3000 u8 p = mlx5_core_native_port_num(dev->mdev); 3001 tx_affinity = (unsigned int)atomic_add_return(1, 3002 &dev->roce[p].next_port) % 3003 MLX5_MAX_PORTS + 1; 3004 context->flags |= cpu_to_be32(tx_affinity << 24); 3005 } 3006 } 3007 } 3008 3009 if (is_sqp(ibqp->qp_type)) { 3010 context->mtu_msgmax = (IB_MTU_256 << 5) | 8; 3011 } else if ((ibqp->qp_type == IB_QPT_UD && 3012 !(qp->flags & MLX5_IB_QP_UNDERLAY)) || 3013 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) { 3014 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12; 3015 } else if (attr_mask & IB_QP_PATH_MTU) { 3016 if (attr->path_mtu < IB_MTU_256 || 3017 attr->path_mtu > IB_MTU_4096) { 3018 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu); 3019 err = -EINVAL; 3020 goto out; 3021 } 3022 context->mtu_msgmax = (attr->path_mtu << 5) | 3023 (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg); 3024 } 3025 3026 if (attr_mask & IB_QP_DEST_QPN) 3027 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num); 3028 3029 if (attr_mask & IB_QP_PKEY_INDEX) 3030 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index); 3031 3032 /* todo implement counter_index functionality */ 3033 3034 if (is_sqp(ibqp->qp_type)) 3035 context->pri_path.port = qp->port; 3036 3037 if (attr_mask & IB_QP_PORT) 3038 context->pri_path.port = attr->port_num; 3039 3040 if (attr_mask & IB_QP_AV) { 3041 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path, 3042 attr_mask & IB_QP_PORT ? attr->port_num : qp->port, 3043 attr_mask, 0, attr, false); 3044 if (err) 3045 goto out; 3046 } 3047 3048 if (attr_mask & IB_QP_TIMEOUT) 3049 context->pri_path.ackto_lt |= attr->timeout << 3; 3050 3051 if (attr_mask & IB_QP_ALT_PATH) { 3052 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr, 3053 &context->alt_path, 3054 attr->alt_port_num, 3055 attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT, 3056 0, attr, true); 3057 if (err) 3058 goto out; 3059 } 3060 3061 pd = get_pd(qp); 3062 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq, 3063 &send_cq, &recv_cq); 3064 3065 context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn); 3066 context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0; 3067 context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0; 3068 context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28); 3069 3070 if (attr_mask & IB_QP_RNR_RETRY) 3071 context->params1 |= cpu_to_be32(attr->rnr_retry << 13); 3072 3073 if (attr_mask & IB_QP_RETRY_CNT) 3074 context->params1 |= cpu_to_be32(attr->retry_cnt << 16); 3075 3076 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) { 3077 if (attr->max_rd_atomic) 3078 context->params1 |= 3079 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21); 3080 } 3081 3082 if (attr_mask & IB_QP_SQ_PSN) 3083 context->next_send_psn = cpu_to_be32(attr->sq_psn); 3084 3085 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) { 3086 if (attr->max_dest_rd_atomic) 3087 context->params2 |= 3088 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21); 3089 } 3090 3091 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) 3092 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask); 3093 3094 if (attr_mask & IB_QP_MIN_RNR_TIMER) 3095 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24); 3096 3097 if (attr_mask & IB_QP_RQ_PSN) 3098 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn); 3099 3100 if (attr_mask & IB_QP_QKEY) 3101 context->qkey = cpu_to_be32(attr->qkey); 3102 3103 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 3104 context->db_rec_addr = cpu_to_be64(qp->db.dma); 3105 3106 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 3107 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num : 3108 qp->port) - 1; 3109 3110 /* Underlay port should be used - index 0 function per port */ 3111 if (qp->flags & MLX5_IB_QP_UNDERLAY) 3112 port_num = 0; 3113 3114 mibport = &dev->port[port_num]; 3115 context->qp_counter_set_usr_page |= 3116 cpu_to_be32((u32)(mibport->cnts.set_id) << 24); 3117 } 3118 3119 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 3120 context->sq_crq_size |= cpu_to_be16(1 << 4); 3121 3122 if (qp->flags & MLX5_IB_QP_SQPN_QP1) 3123 context->deth_sqpn = cpu_to_be32(1); 3124 3125 mlx5_cur = to_mlx5_state(cur_state); 3126 mlx5_new = to_mlx5_state(new_state); 3127 mlx5_st = to_mlx5_st(ibqp->qp_type == IB_QPT_DRIVER ? 3128 qp->qp_sub_type : ibqp->qp_type); 3129 if (mlx5_st < 0) 3130 goto out; 3131 3132 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE || 3133 !optab[mlx5_cur][mlx5_new]) { 3134 err = -EINVAL; 3135 goto out; 3136 } 3137 3138 op = optab[mlx5_cur][mlx5_new]; 3139 optpar = ib_mask_to_mlx5_opt(attr_mask); 3140 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st]; 3141 3142 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || 3143 qp->flags & MLX5_IB_QP_UNDERLAY) { 3144 struct mlx5_modify_raw_qp_param raw_qp_param = {}; 3145 3146 raw_qp_param.operation = op; 3147 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 3148 raw_qp_param.rq_q_ctr_id = mibport->cnts.set_id; 3149 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID; 3150 } 3151 3152 if (attr_mask & IB_QP_RATE_LIMIT) { 3153 raw_qp_param.rate_limit = attr->rate_limit; 3154 raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT; 3155 } 3156 3157 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity); 3158 } else { 3159 err = mlx5_core_qp_modify(dev->mdev, op, optpar, context, 3160 &base->mqp); 3161 } 3162 3163 if (err) 3164 goto out; 3165 3166 qp->state = new_state; 3167 3168 if (attr_mask & IB_QP_ACCESS_FLAGS) 3169 qp->trans_qp.atomic_rd_en = attr->qp_access_flags; 3170 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 3171 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic; 3172 if (attr_mask & IB_QP_PORT) 3173 qp->port = attr->port_num; 3174 if (attr_mask & IB_QP_ALT_PATH) 3175 qp->trans_qp.alt_port = attr->alt_port_num; 3176 3177 /* 3178 * If we moved a kernel QP to RESET, clean up all old CQ 3179 * entries and reinitialize the QP. 3180 */ 3181 if (new_state == IB_QPS_RESET && !ibqp->uobject) { 3182 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 3183 ibqp->srq ? to_msrq(ibqp->srq) : NULL); 3184 if (send_cq != recv_cq) 3185 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL); 3186 3187 qp->rq.head = 0; 3188 qp->rq.tail = 0; 3189 qp->sq.head = 0; 3190 qp->sq.tail = 0; 3191 qp->sq.cur_post = 0; 3192 qp->sq.last_poll = 0; 3193 qp->db.db[MLX5_RCV_DBR] = 0; 3194 qp->db.db[MLX5_SND_DBR] = 0; 3195 } 3196 3197 out: 3198 kfree(context); 3199 return err; 3200 } 3201 3202 static inline bool is_valid_mask(int mask, int req, int opt) 3203 { 3204 if ((mask & req) != req) 3205 return false; 3206 3207 if (mask & ~(req | opt)) 3208 return false; 3209 3210 return true; 3211 } 3212 3213 /* check valid transition for driver QP types 3214 * for now the only QP type that this function supports is DCI 3215 */ 3216 static bool modify_dci_qp_is_ok(enum ib_qp_state cur_state, enum ib_qp_state new_state, 3217 enum ib_qp_attr_mask attr_mask) 3218 { 3219 int req = IB_QP_STATE; 3220 int opt = 0; 3221 3222 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 3223 req |= IB_QP_PKEY_INDEX | IB_QP_PORT; 3224 return is_valid_mask(attr_mask, req, opt); 3225 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) { 3226 opt = IB_QP_PKEY_INDEX | IB_QP_PORT; 3227 return is_valid_mask(attr_mask, req, opt); 3228 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 3229 req |= IB_QP_PATH_MTU; 3230 opt = IB_QP_PKEY_INDEX; 3231 return is_valid_mask(attr_mask, req, opt); 3232 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) { 3233 req |= IB_QP_TIMEOUT | IB_QP_RETRY_CNT | IB_QP_RNR_RETRY | 3234 IB_QP_MAX_QP_RD_ATOMIC | IB_QP_SQ_PSN; 3235 opt = IB_QP_MIN_RNR_TIMER; 3236 return is_valid_mask(attr_mask, req, opt); 3237 } else if (cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) { 3238 opt = IB_QP_MIN_RNR_TIMER; 3239 return is_valid_mask(attr_mask, req, opt); 3240 } else if (cur_state != IB_QPS_RESET && new_state == IB_QPS_ERR) { 3241 return is_valid_mask(attr_mask, req, opt); 3242 } 3243 return false; 3244 } 3245 3246 /* mlx5_ib_modify_dct: modify a DCT QP 3247 * valid transitions are: 3248 * RESET to INIT: must set access_flags, pkey_index and port 3249 * INIT to RTR : must set min_rnr_timer, tclass, flow_label, 3250 * mtu, gid_index and hop_limit 3251 * Other transitions and attributes are illegal 3252 */ 3253 static int mlx5_ib_modify_dct(struct ib_qp *ibqp, struct ib_qp_attr *attr, 3254 int attr_mask, struct ib_udata *udata) 3255 { 3256 struct mlx5_ib_qp *qp = to_mqp(ibqp); 3257 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 3258 enum ib_qp_state cur_state, new_state; 3259 int err = 0; 3260 int required = IB_QP_STATE; 3261 void *dctc; 3262 3263 if (!(attr_mask & IB_QP_STATE)) 3264 return -EINVAL; 3265 3266 cur_state = qp->state; 3267 new_state = attr->qp_state; 3268 3269 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry); 3270 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 3271 required |= IB_QP_ACCESS_FLAGS | IB_QP_PKEY_INDEX | IB_QP_PORT; 3272 if (!is_valid_mask(attr_mask, required, 0)) 3273 return -EINVAL; 3274 3275 if (attr->port_num == 0 || 3276 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports)) { 3277 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n", 3278 attr->port_num, dev->num_ports); 3279 return -EINVAL; 3280 } 3281 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ) 3282 MLX5_SET(dctc, dctc, rre, 1); 3283 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE) 3284 MLX5_SET(dctc, dctc, rwe, 1); 3285 if (attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC) { 3286 if (!mlx5_ib_dc_atomic_is_supported(dev)) 3287 return -EOPNOTSUPP; 3288 MLX5_SET(dctc, dctc, rae, 1); 3289 MLX5_SET(dctc, dctc, atomic_mode, MLX5_ATOMIC_MODE_DCT_CX); 3290 } 3291 MLX5_SET(dctc, dctc, pkey_index, attr->pkey_index); 3292 MLX5_SET(dctc, dctc, port, attr->port_num); 3293 MLX5_SET(dctc, dctc, counter_set_id, dev->port[attr->port_num - 1].cnts.set_id); 3294 3295 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 3296 struct mlx5_ib_modify_qp_resp resp = {}; 3297 u32 min_resp_len = offsetof(typeof(resp), dctn) + 3298 sizeof(resp.dctn); 3299 3300 if (udata->outlen < min_resp_len) 3301 return -EINVAL; 3302 resp.response_length = min_resp_len; 3303 3304 required |= IB_QP_MIN_RNR_TIMER | IB_QP_AV | IB_QP_PATH_MTU; 3305 if (!is_valid_mask(attr_mask, required, 0)) 3306 return -EINVAL; 3307 MLX5_SET(dctc, dctc, min_rnr_nak, attr->min_rnr_timer); 3308 MLX5_SET(dctc, dctc, tclass, attr->ah_attr.grh.traffic_class); 3309 MLX5_SET(dctc, dctc, flow_label, attr->ah_attr.grh.flow_label); 3310 MLX5_SET(dctc, dctc, mtu, attr->path_mtu); 3311 MLX5_SET(dctc, dctc, my_addr_index, attr->ah_attr.grh.sgid_index); 3312 MLX5_SET(dctc, dctc, hop_limit, attr->ah_attr.grh.hop_limit); 3313 3314 err = mlx5_core_create_dct(dev->mdev, &qp->dct.mdct, qp->dct.in, 3315 MLX5_ST_SZ_BYTES(create_dct_in)); 3316 if (err) 3317 return err; 3318 resp.dctn = qp->dct.mdct.mqp.qpn; 3319 err = ib_copy_to_udata(udata, &resp, resp.response_length); 3320 if (err) { 3321 mlx5_core_destroy_dct(dev->mdev, &qp->dct.mdct); 3322 return err; 3323 } 3324 } else { 3325 mlx5_ib_warn(dev, "Modify DCT: Invalid transition from %d to %d\n", cur_state, new_state); 3326 return -EINVAL; 3327 } 3328 if (err) 3329 qp->state = IB_QPS_ERR; 3330 else 3331 qp->state = new_state; 3332 return err; 3333 } 3334 3335 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 3336 int attr_mask, struct ib_udata *udata) 3337 { 3338 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 3339 struct mlx5_ib_qp *qp = to_mqp(ibqp); 3340 enum ib_qp_type qp_type; 3341 enum ib_qp_state cur_state, new_state; 3342 int err = -EINVAL; 3343 int port; 3344 enum rdma_link_layer ll = IB_LINK_LAYER_UNSPECIFIED; 3345 3346 if (ibqp->rwq_ind_tbl) 3347 return -ENOSYS; 3348 3349 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 3350 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask); 3351 3352 if (ibqp->qp_type == IB_QPT_DRIVER) 3353 qp_type = qp->qp_sub_type; 3354 else 3355 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ? 3356 IB_QPT_GSI : ibqp->qp_type; 3357 3358 if (qp_type == MLX5_IB_QPT_DCT) 3359 return mlx5_ib_modify_dct(ibqp, attr, attr_mask, udata); 3360 3361 mutex_lock(&qp->mutex); 3362 3363 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state; 3364 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state; 3365 3366 if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) { 3367 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 3368 ll = dev->ib_dev.get_link_layer(&dev->ib_dev, port); 3369 } 3370 3371 if (qp->flags & MLX5_IB_QP_UNDERLAY) { 3372 if (attr_mask & ~(IB_QP_STATE | IB_QP_CUR_STATE)) { 3373 mlx5_ib_dbg(dev, "invalid attr_mask 0x%x when underlay QP is used\n", 3374 attr_mask); 3375 goto out; 3376 } 3377 } else if (qp_type != MLX5_IB_QPT_REG_UMR && 3378 qp_type != MLX5_IB_QPT_DCI && 3379 !ib_modify_qp_is_ok(cur_state, new_state, qp_type, attr_mask, ll)) { 3380 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n", 3381 cur_state, new_state, ibqp->qp_type, attr_mask); 3382 goto out; 3383 } else if (qp_type == MLX5_IB_QPT_DCI && 3384 !modify_dci_qp_is_ok(cur_state, new_state, attr_mask)) { 3385 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n", 3386 cur_state, new_state, qp_type, attr_mask); 3387 goto out; 3388 } 3389 3390 if ((attr_mask & IB_QP_PORT) && 3391 (attr->port_num == 0 || 3392 attr->port_num > dev->num_ports)) { 3393 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n", 3394 attr->port_num, dev->num_ports); 3395 goto out; 3396 } 3397 3398 if (attr_mask & IB_QP_PKEY_INDEX) { 3399 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 3400 if (attr->pkey_index >= 3401 dev->mdev->port_caps[port - 1].pkey_table_len) { 3402 mlx5_ib_dbg(dev, "invalid pkey index %d\n", 3403 attr->pkey_index); 3404 goto out; 3405 } 3406 } 3407 3408 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && 3409 attr->max_rd_atomic > 3410 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) { 3411 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n", 3412 attr->max_rd_atomic); 3413 goto out; 3414 } 3415 3416 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && 3417 attr->max_dest_rd_atomic > 3418 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) { 3419 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n", 3420 attr->max_dest_rd_atomic); 3421 goto out; 3422 } 3423 3424 if (cur_state == new_state && cur_state == IB_QPS_RESET) { 3425 err = 0; 3426 goto out; 3427 } 3428 3429 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state); 3430 3431 out: 3432 mutex_unlock(&qp->mutex); 3433 return err; 3434 } 3435 3436 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq) 3437 { 3438 struct mlx5_ib_cq *cq; 3439 unsigned cur; 3440 3441 cur = wq->head - wq->tail; 3442 if (likely(cur + nreq < wq->max_post)) 3443 return 0; 3444 3445 cq = to_mcq(ib_cq); 3446 spin_lock(&cq->lock); 3447 cur = wq->head - wq->tail; 3448 spin_unlock(&cq->lock); 3449 3450 return cur + nreq >= wq->max_post; 3451 } 3452 3453 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg, 3454 u64 remote_addr, u32 rkey) 3455 { 3456 rseg->raddr = cpu_to_be64(remote_addr); 3457 rseg->rkey = cpu_to_be32(rkey); 3458 rseg->reserved = 0; 3459 } 3460 3461 static void *set_eth_seg(struct mlx5_wqe_eth_seg *eseg, 3462 struct ib_send_wr *wr, void *qend, 3463 struct mlx5_ib_qp *qp, int *size) 3464 { 3465 void *seg = eseg; 3466 3467 memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg)); 3468 3469 if (wr->send_flags & IB_SEND_IP_CSUM) 3470 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM | 3471 MLX5_ETH_WQE_L4_CSUM; 3472 3473 seg += sizeof(struct mlx5_wqe_eth_seg); 3474 *size += sizeof(struct mlx5_wqe_eth_seg) / 16; 3475 3476 if (wr->opcode == IB_WR_LSO) { 3477 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr); 3478 int size_of_inl_hdr_start = sizeof(eseg->inline_hdr.start); 3479 u64 left, leftlen, copysz; 3480 void *pdata = ud_wr->header; 3481 3482 left = ud_wr->hlen; 3483 eseg->mss = cpu_to_be16(ud_wr->mss); 3484 eseg->inline_hdr.sz = cpu_to_be16(left); 3485 3486 /* 3487 * check if there is space till the end of queue, if yes, 3488 * copy all in one shot, otherwise copy till the end of queue, 3489 * rollback and than the copy the left 3490 */ 3491 leftlen = qend - (void *)eseg->inline_hdr.start; 3492 copysz = min_t(u64, leftlen, left); 3493 3494 memcpy(seg - size_of_inl_hdr_start, pdata, copysz); 3495 3496 if (likely(copysz > size_of_inl_hdr_start)) { 3497 seg += ALIGN(copysz - size_of_inl_hdr_start, 16); 3498 *size += ALIGN(copysz - size_of_inl_hdr_start, 16) / 16; 3499 } 3500 3501 if (unlikely(copysz < left)) { /* the last wqe in the queue */ 3502 seg = mlx5_get_send_wqe(qp, 0); 3503 left -= copysz; 3504 pdata += copysz; 3505 memcpy(seg, pdata, left); 3506 seg += ALIGN(left, 16); 3507 *size += ALIGN(left, 16) / 16; 3508 } 3509 } 3510 3511 return seg; 3512 } 3513 3514 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg, 3515 struct ib_send_wr *wr) 3516 { 3517 memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av)); 3518 dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV); 3519 dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey); 3520 } 3521 3522 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg) 3523 { 3524 dseg->byte_count = cpu_to_be32(sg->length); 3525 dseg->lkey = cpu_to_be32(sg->lkey); 3526 dseg->addr = cpu_to_be64(sg->addr); 3527 } 3528 3529 static u64 get_xlt_octo(u64 bytes) 3530 { 3531 return ALIGN(bytes, MLX5_IB_UMR_XLT_ALIGNMENT) / 3532 MLX5_IB_UMR_OCTOWORD; 3533 } 3534 3535 static __be64 frwr_mkey_mask(void) 3536 { 3537 u64 result; 3538 3539 result = MLX5_MKEY_MASK_LEN | 3540 MLX5_MKEY_MASK_PAGE_SIZE | 3541 MLX5_MKEY_MASK_START_ADDR | 3542 MLX5_MKEY_MASK_EN_RINVAL | 3543 MLX5_MKEY_MASK_KEY | 3544 MLX5_MKEY_MASK_LR | 3545 MLX5_MKEY_MASK_LW | 3546 MLX5_MKEY_MASK_RR | 3547 MLX5_MKEY_MASK_RW | 3548 MLX5_MKEY_MASK_A | 3549 MLX5_MKEY_MASK_SMALL_FENCE | 3550 MLX5_MKEY_MASK_FREE; 3551 3552 return cpu_to_be64(result); 3553 } 3554 3555 static __be64 sig_mkey_mask(void) 3556 { 3557 u64 result; 3558 3559 result = MLX5_MKEY_MASK_LEN | 3560 MLX5_MKEY_MASK_PAGE_SIZE | 3561 MLX5_MKEY_MASK_START_ADDR | 3562 MLX5_MKEY_MASK_EN_SIGERR | 3563 MLX5_MKEY_MASK_EN_RINVAL | 3564 MLX5_MKEY_MASK_KEY | 3565 MLX5_MKEY_MASK_LR | 3566 MLX5_MKEY_MASK_LW | 3567 MLX5_MKEY_MASK_RR | 3568 MLX5_MKEY_MASK_RW | 3569 MLX5_MKEY_MASK_SMALL_FENCE | 3570 MLX5_MKEY_MASK_FREE | 3571 MLX5_MKEY_MASK_BSF_EN; 3572 3573 return cpu_to_be64(result); 3574 } 3575 3576 static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr, 3577 struct mlx5_ib_mr *mr) 3578 { 3579 int size = mr->ndescs * mr->desc_size; 3580 3581 memset(umr, 0, sizeof(*umr)); 3582 3583 umr->flags = MLX5_UMR_CHECK_NOT_FREE; 3584 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size)); 3585 umr->mkey_mask = frwr_mkey_mask(); 3586 } 3587 3588 static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr) 3589 { 3590 memset(umr, 0, sizeof(*umr)); 3591 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE); 3592 umr->flags = MLX5_UMR_INLINE; 3593 } 3594 3595 static __be64 get_umr_enable_mr_mask(void) 3596 { 3597 u64 result; 3598 3599 result = MLX5_MKEY_MASK_KEY | 3600 MLX5_MKEY_MASK_FREE; 3601 3602 return cpu_to_be64(result); 3603 } 3604 3605 static __be64 get_umr_disable_mr_mask(void) 3606 { 3607 u64 result; 3608 3609 result = MLX5_MKEY_MASK_FREE; 3610 3611 return cpu_to_be64(result); 3612 } 3613 3614 static __be64 get_umr_update_translation_mask(void) 3615 { 3616 u64 result; 3617 3618 result = MLX5_MKEY_MASK_LEN | 3619 MLX5_MKEY_MASK_PAGE_SIZE | 3620 MLX5_MKEY_MASK_START_ADDR; 3621 3622 return cpu_to_be64(result); 3623 } 3624 3625 static __be64 get_umr_update_access_mask(int atomic) 3626 { 3627 u64 result; 3628 3629 result = MLX5_MKEY_MASK_LR | 3630 MLX5_MKEY_MASK_LW | 3631 MLX5_MKEY_MASK_RR | 3632 MLX5_MKEY_MASK_RW; 3633 3634 if (atomic) 3635 result |= MLX5_MKEY_MASK_A; 3636 3637 return cpu_to_be64(result); 3638 } 3639 3640 static __be64 get_umr_update_pd_mask(void) 3641 { 3642 u64 result; 3643 3644 result = MLX5_MKEY_MASK_PD; 3645 3646 return cpu_to_be64(result); 3647 } 3648 3649 static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr, 3650 struct ib_send_wr *wr, int atomic) 3651 { 3652 struct mlx5_umr_wr *umrwr = umr_wr(wr); 3653 3654 memset(umr, 0, sizeof(*umr)); 3655 3656 if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE) 3657 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */ 3658 else 3659 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */ 3660 3661 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(umrwr->xlt_size)); 3662 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_XLT) { 3663 u64 offset = get_xlt_octo(umrwr->offset); 3664 3665 umr->xlt_offset = cpu_to_be16(offset & 0xffff); 3666 umr->xlt_offset_47_16 = cpu_to_be32(offset >> 16); 3667 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN; 3668 } 3669 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION) 3670 umr->mkey_mask |= get_umr_update_translation_mask(); 3671 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS) { 3672 umr->mkey_mask |= get_umr_update_access_mask(atomic); 3673 umr->mkey_mask |= get_umr_update_pd_mask(); 3674 } 3675 if (wr->send_flags & MLX5_IB_SEND_UMR_ENABLE_MR) 3676 umr->mkey_mask |= get_umr_enable_mr_mask(); 3677 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR) 3678 umr->mkey_mask |= get_umr_disable_mr_mask(); 3679 3680 if (!wr->num_sge) 3681 umr->flags |= MLX5_UMR_INLINE; 3682 } 3683 3684 static u8 get_umr_flags(int acc) 3685 { 3686 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) | 3687 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) | 3688 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) | 3689 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) | 3690 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN; 3691 } 3692 3693 static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg, 3694 struct mlx5_ib_mr *mr, 3695 u32 key, int access) 3696 { 3697 int ndescs = ALIGN(mr->ndescs, 8) >> 1; 3698 3699 memset(seg, 0, sizeof(*seg)); 3700 3701 if (mr->access_mode == MLX5_MKC_ACCESS_MODE_MTT) 3702 seg->log2_page_size = ilog2(mr->ibmr.page_size); 3703 else if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS) 3704 /* KLMs take twice the size of MTTs */ 3705 ndescs *= 2; 3706 3707 seg->flags = get_umr_flags(access) | mr->access_mode; 3708 seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00); 3709 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL); 3710 seg->start_addr = cpu_to_be64(mr->ibmr.iova); 3711 seg->len = cpu_to_be64(mr->ibmr.length); 3712 seg->xlt_oct_size = cpu_to_be32(ndescs); 3713 } 3714 3715 static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg) 3716 { 3717 memset(seg, 0, sizeof(*seg)); 3718 seg->status = MLX5_MKEY_STATUS_FREE; 3719 } 3720 3721 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr) 3722 { 3723 struct mlx5_umr_wr *umrwr = umr_wr(wr); 3724 3725 memset(seg, 0, sizeof(*seg)); 3726 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR) 3727 seg->status = MLX5_MKEY_STATUS_FREE; 3728 3729 seg->flags = convert_access(umrwr->access_flags); 3730 if (umrwr->pd) 3731 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn); 3732 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION && 3733 !umrwr->length) 3734 seg->flags_pd |= cpu_to_be32(MLX5_MKEY_LEN64); 3735 3736 seg->start_addr = cpu_to_be64(umrwr->virt_addr); 3737 seg->len = cpu_to_be64(umrwr->length); 3738 seg->log2_page_size = umrwr->page_shift; 3739 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 | 3740 mlx5_mkey_variant(umrwr->mkey)); 3741 } 3742 3743 static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg, 3744 struct mlx5_ib_mr *mr, 3745 struct mlx5_ib_pd *pd) 3746 { 3747 int bcount = mr->desc_size * mr->ndescs; 3748 3749 dseg->addr = cpu_to_be64(mr->desc_map); 3750 dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64)); 3751 dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey); 3752 } 3753 3754 static __be32 send_ieth(struct ib_send_wr *wr) 3755 { 3756 switch (wr->opcode) { 3757 case IB_WR_SEND_WITH_IMM: 3758 case IB_WR_RDMA_WRITE_WITH_IMM: 3759 return wr->ex.imm_data; 3760 3761 case IB_WR_SEND_WITH_INV: 3762 return cpu_to_be32(wr->ex.invalidate_rkey); 3763 3764 default: 3765 return 0; 3766 } 3767 } 3768 3769 static u8 calc_sig(void *wqe, int size) 3770 { 3771 u8 *p = wqe; 3772 u8 res = 0; 3773 int i; 3774 3775 for (i = 0; i < size; i++) 3776 res ^= p[i]; 3777 3778 return ~res; 3779 } 3780 3781 static u8 wq_sig(void *wqe) 3782 { 3783 return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4); 3784 } 3785 3786 static int set_data_inl_seg(struct mlx5_ib_qp *qp, struct ib_send_wr *wr, 3787 void *wqe, int *sz) 3788 { 3789 struct mlx5_wqe_inline_seg *seg; 3790 void *qend = qp->sq.qend; 3791 void *addr; 3792 int inl = 0; 3793 int copy; 3794 int len; 3795 int i; 3796 3797 seg = wqe; 3798 wqe += sizeof(*seg); 3799 for (i = 0; i < wr->num_sge; i++) { 3800 addr = (void *)(unsigned long)(wr->sg_list[i].addr); 3801 len = wr->sg_list[i].length; 3802 inl += len; 3803 3804 if (unlikely(inl > qp->max_inline_data)) 3805 return -ENOMEM; 3806 3807 if (unlikely(wqe + len > qend)) { 3808 copy = qend - wqe; 3809 memcpy(wqe, addr, copy); 3810 addr += copy; 3811 len -= copy; 3812 wqe = mlx5_get_send_wqe(qp, 0); 3813 } 3814 memcpy(wqe, addr, len); 3815 wqe += len; 3816 } 3817 3818 seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG); 3819 3820 *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16; 3821 3822 return 0; 3823 } 3824 3825 static u16 prot_field_size(enum ib_signature_type type) 3826 { 3827 switch (type) { 3828 case IB_SIG_TYPE_T10_DIF: 3829 return MLX5_DIF_SIZE; 3830 default: 3831 return 0; 3832 } 3833 } 3834 3835 static u8 bs_selector(int block_size) 3836 { 3837 switch (block_size) { 3838 case 512: return 0x1; 3839 case 520: return 0x2; 3840 case 4096: return 0x3; 3841 case 4160: return 0x4; 3842 case 1073741824: return 0x5; 3843 default: return 0; 3844 } 3845 } 3846 3847 static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain, 3848 struct mlx5_bsf_inl *inl) 3849 { 3850 /* Valid inline section and allow BSF refresh */ 3851 inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID | 3852 MLX5_BSF_REFRESH_DIF); 3853 inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag); 3854 inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag); 3855 /* repeating block */ 3856 inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK; 3857 inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ? 3858 MLX5_DIF_CRC : MLX5_DIF_IPCS; 3859 3860 if (domain->sig.dif.ref_remap) 3861 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG; 3862 3863 if (domain->sig.dif.app_escape) { 3864 if (domain->sig.dif.ref_escape) 3865 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE; 3866 else 3867 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE; 3868 } 3869 3870 inl->dif_app_bitmask_check = 3871 cpu_to_be16(domain->sig.dif.apptag_check_mask); 3872 } 3873 3874 static int mlx5_set_bsf(struct ib_mr *sig_mr, 3875 struct ib_sig_attrs *sig_attrs, 3876 struct mlx5_bsf *bsf, u32 data_size) 3877 { 3878 struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig; 3879 struct mlx5_bsf_basic *basic = &bsf->basic; 3880 struct ib_sig_domain *mem = &sig_attrs->mem; 3881 struct ib_sig_domain *wire = &sig_attrs->wire; 3882 3883 memset(bsf, 0, sizeof(*bsf)); 3884 3885 /* Basic + Extended + Inline */ 3886 basic->bsf_size_sbs = 1 << 7; 3887 /* Input domain check byte mask */ 3888 basic->check_byte_mask = sig_attrs->check_mask; 3889 basic->raw_data_size = cpu_to_be32(data_size); 3890 3891 /* Memory domain */ 3892 switch (sig_attrs->mem.sig_type) { 3893 case IB_SIG_TYPE_NONE: 3894 break; 3895 case IB_SIG_TYPE_T10_DIF: 3896 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval); 3897 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx); 3898 mlx5_fill_inl_bsf(mem, &bsf->m_inl); 3899 break; 3900 default: 3901 return -EINVAL; 3902 } 3903 3904 /* Wire domain */ 3905 switch (sig_attrs->wire.sig_type) { 3906 case IB_SIG_TYPE_NONE: 3907 break; 3908 case IB_SIG_TYPE_T10_DIF: 3909 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval && 3910 mem->sig_type == wire->sig_type) { 3911 /* Same block structure */ 3912 basic->bsf_size_sbs |= 1 << 4; 3913 if (mem->sig.dif.bg_type == wire->sig.dif.bg_type) 3914 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK; 3915 if (mem->sig.dif.app_tag == wire->sig.dif.app_tag) 3916 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK; 3917 if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag) 3918 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK; 3919 } else 3920 basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval); 3921 3922 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx); 3923 mlx5_fill_inl_bsf(wire, &bsf->w_inl); 3924 break; 3925 default: 3926 return -EINVAL; 3927 } 3928 3929 return 0; 3930 } 3931 3932 static int set_sig_data_segment(struct ib_sig_handover_wr *wr, 3933 struct mlx5_ib_qp *qp, void **seg, int *size) 3934 { 3935 struct ib_sig_attrs *sig_attrs = wr->sig_attrs; 3936 struct ib_mr *sig_mr = wr->sig_mr; 3937 struct mlx5_bsf *bsf; 3938 u32 data_len = wr->wr.sg_list->length; 3939 u32 data_key = wr->wr.sg_list->lkey; 3940 u64 data_va = wr->wr.sg_list->addr; 3941 int ret; 3942 int wqe_size; 3943 3944 if (!wr->prot || 3945 (data_key == wr->prot->lkey && 3946 data_va == wr->prot->addr && 3947 data_len == wr->prot->length)) { 3948 /** 3949 * Source domain doesn't contain signature information 3950 * or data and protection are interleaved in memory. 3951 * So need construct: 3952 * ------------------ 3953 * | data_klm | 3954 * ------------------ 3955 * | BSF | 3956 * ------------------ 3957 **/ 3958 struct mlx5_klm *data_klm = *seg; 3959 3960 data_klm->bcount = cpu_to_be32(data_len); 3961 data_klm->key = cpu_to_be32(data_key); 3962 data_klm->va = cpu_to_be64(data_va); 3963 wqe_size = ALIGN(sizeof(*data_klm), 64); 3964 } else { 3965 /** 3966 * Source domain contains signature information 3967 * So need construct a strided block format: 3968 * --------------------------- 3969 * | stride_block_ctrl | 3970 * --------------------------- 3971 * | data_klm | 3972 * --------------------------- 3973 * | prot_klm | 3974 * --------------------------- 3975 * | BSF | 3976 * --------------------------- 3977 **/ 3978 struct mlx5_stride_block_ctrl_seg *sblock_ctrl; 3979 struct mlx5_stride_block_entry *data_sentry; 3980 struct mlx5_stride_block_entry *prot_sentry; 3981 u32 prot_key = wr->prot->lkey; 3982 u64 prot_va = wr->prot->addr; 3983 u16 block_size = sig_attrs->mem.sig.dif.pi_interval; 3984 int prot_size; 3985 3986 sblock_ctrl = *seg; 3987 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl); 3988 prot_sentry = (void *)data_sentry + sizeof(*data_sentry); 3989 3990 prot_size = prot_field_size(sig_attrs->mem.sig_type); 3991 if (!prot_size) { 3992 pr_err("Bad block size given: %u\n", block_size); 3993 return -EINVAL; 3994 } 3995 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size + 3996 prot_size); 3997 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP); 3998 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size); 3999 sblock_ctrl->num_entries = cpu_to_be16(2); 4000 4001 data_sentry->bcount = cpu_to_be16(block_size); 4002 data_sentry->key = cpu_to_be32(data_key); 4003 data_sentry->va = cpu_to_be64(data_va); 4004 data_sentry->stride = cpu_to_be16(block_size); 4005 4006 prot_sentry->bcount = cpu_to_be16(prot_size); 4007 prot_sentry->key = cpu_to_be32(prot_key); 4008 prot_sentry->va = cpu_to_be64(prot_va); 4009 prot_sentry->stride = cpu_to_be16(prot_size); 4010 4011 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) + 4012 sizeof(*prot_sentry), 64); 4013 } 4014 4015 *seg += wqe_size; 4016 *size += wqe_size / 16; 4017 if (unlikely((*seg == qp->sq.qend))) 4018 *seg = mlx5_get_send_wqe(qp, 0); 4019 4020 bsf = *seg; 4021 ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len); 4022 if (ret) 4023 return -EINVAL; 4024 4025 *seg += sizeof(*bsf); 4026 *size += sizeof(*bsf) / 16; 4027 if (unlikely((*seg == qp->sq.qend))) 4028 *seg = mlx5_get_send_wqe(qp, 0); 4029 4030 return 0; 4031 } 4032 4033 static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg, 4034 struct ib_sig_handover_wr *wr, u32 size, 4035 u32 length, u32 pdn) 4036 { 4037 struct ib_mr *sig_mr = wr->sig_mr; 4038 u32 sig_key = sig_mr->rkey; 4039 u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1; 4040 4041 memset(seg, 0, sizeof(*seg)); 4042 4043 seg->flags = get_umr_flags(wr->access_flags) | 4044 MLX5_MKC_ACCESS_MODE_KLMS; 4045 seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00); 4046 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 | 4047 MLX5_MKEY_BSF_EN | pdn); 4048 seg->len = cpu_to_be64(length); 4049 seg->xlt_oct_size = cpu_to_be32(get_xlt_octo(size)); 4050 seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE); 4051 } 4052 4053 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr, 4054 u32 size) 4055 { 4056 memset(umr, 0, sizeof(*umr)); 4057 4058 umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE; 4059 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size)); 4060 umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE); 4061 umr->mkey_mask = sig_mkey_mask(); 4062 } 4063 4064 4065 static int set_sig_umr_wr(struct ib_send_wr *send_wr, struct mlx5_ib_qp *qp, 4066 void **seg, int *size) 4067 { 4068 struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr); 4069 struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr); 4070 u32 pdn = get_pd(qp)->pdn; 4071 u32 xlt_size; 4072 int region_len, ret; 4073 4074 if (unlikely(wr->wr.num_sge != 1) || 4075 unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) || 4076 unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) || 4077 unlikely(!sig_mr->sig->sig_status_checked)) 4078 return -EINVAL; 4079 4080 /* length of the protected region, data + protection */ 4081 region_len = wr->wr.sg_list->length; 4082 if (wr->prot && 4083 (wr->prot->lkey != wr->wr.sg_list->lkey || 4084 wr->prot->addr != wr->wr.sg_list->addr || 4085 wr->prot->length != wr->wr.sg_list->length)) 4086 region_len += wr->prot->length; 4087 4088 /** 4089 * KLM octoword size - if protection was provided 4090 * then we use strided block format (3 octowords), 4091 * else we use single KLM (1 octoword) 4092 **/ 4093 xlt_size = wr->prot ? 0x30 : sizeof(struct mlx5_klm); 4094 4095 set_sig_umr_segment(*seg, xlt_size); 4096 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 4097 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 4098 if (unlikely((*seg == qp->sq.qend))) 4099 *seg = mlx5_get_send_wqe(qp, 0); 4100 4101 set_sig_mkey_segment(*seg, wr, xlt_size, region_len, pdn); 4102 *seg += sizeof(struct mlx5_mkey_seg); 4103 *size += sizeof(struct mlx5_mkey_seg) / 16; 4104 if (unlikely((*seg == qp->sq.qend))) 4105 *seg = mlx5_get_send_wqe(qp, 0); 4106 4107 ret = set_sig_data_segment(wr, qp, seg, size); 4108 if (ret) 4109 return ret; 4110 4111 sig_mr->sig->sig_status_checked = false; 4112 return 0; 4113 } 4114 4115 static int set_psv_wr(struct ib_sig_domain *domain, 4116 u32 psv_idx, void **seg, int *size) 4117 { 4118 struct mlx5_seg_set_psv *psv_seg = *seg; 4119 4120 memset(psv_seg, 0, sizeof(*psv_seg)); 4121 psv_seg->psv_num = cpu_to_be32(psv_idx); 4122 switch (domain->sig_type) { 4123 case IB_SIG_TYPE_NONE: 4124 break; 4125 case IB_SIG_TYPE_T10_DIF: 4126 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 | 4127 domain->sig.dif.app_tag); 4128 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag); 4129 break; 4130 default: 4131 pr_err("Bad signature type (%d) is given.\n", 4132 domain->sig_type); 4133 return -EINVAL; 4134 } 4135 4136 *seg += sizeof(*psv_seg); 4137 *size += sizeof(*psv_seg) / 16; 4138 4139 return 0; 4140 } 4141 4142 static int set_reg_wr(struct mlx5_ib_qp *qp, 4143 struct ib_reg_wr *wr, 4144 void **seg, int *size) 4145 { 4146 struct mlx5_ib_mr *mr = to_mmr(wr->mr); 4147 struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd); 4148 4149 if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) { 4150 mlx5_ib_warn(to_mdev(qp->ibqp.device), 4151 "Invalid IB_SEND_INLINE send flag\n"); 4152 return -EINVAL; 4153 } 4154 4155 set_reg_umr_seg(*seg, mr); 4156 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 4157 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 4158 if (unlikely((*seg == qp->sq.qend))) 4159 *seg = mlx5_get_send_wqe(qp, 0); 4160 4161 set_reg_mkey_seg(*seg, mr, wr->key, wr->access); 4162 *seg += sizeof(struct mlx5_mkey_seg); 4163 *size += sizeof(struct mlx5_mkey_seg) / 16; 4164 if (unlikely((*seg == qp->sq.qend))) 4165 *seg = mlx5_get_send_wqe(qp, 0); 4166 4167 set_reg_data_seg(*seg, mr, pd); 4168 *seg += sizeof(struct mlx5_wqe_data_seg); 4169 *size += (sizeof(struct mlx5_wqe_data_seg) / 16); 4170 4171 return 0; 4172 } 4173 4174 static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size) 4175 { 4176 set_linv_umr_seg(*seg); 4177 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 4178 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 4179 if (unlikely((*seg == qp->sq.qend))) 4180 *seg = mlx5_get_send_wqe(qp, 0); 4181 set_linv_mkey_seg(*seg); 4182 *seg += sizeof(struct mlx5_mkey_seg); 4183 *size += sizeof(struct mlx5_mkey_seg) / 16; 4184 if (unlikely((*seg == qp->sq.qend))) 4185 *seg = mlx5_get_send_wqe(qp, 0); 4186 } 4187 4188 static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16) 4189 { 4190 __be32 *p = NULL; 4191 int tidx = idx; 4192 int i, j; 4193 4194 pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx)); 4195 for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) { 4196 if ((i & 0xf) == 0) { 4197 void *buf = mlx5_get_send_wqe(qp, tidx); 4198 tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1); 4199 p = buf; 4200 j = 0; 4201 } 4202 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]), 4203 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]), 4204 be32_to_cpu(p[j + 3])); 4205 } 4206 } 4207 4208 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg, 4209 struct mlx5_wqe_ctrl_seg **ctrl, 4210 struct ib_send_wr *wr, unsigned *idx, 4211 int *size, int nreq) 4212 { 4213 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq))) 4214 return -ENOMEM; 4215 4216 *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1); 4217 *seg = mlx5_get_send_wqe(qp, *idx); 4218 *ctrl = *seg; 4219 *(uint32_t *)(*seg + 8) = 0; 4220 (*ctrl)->imm = send_ieth(wr); 4221 (*ctrl)->fm_ce_se = qp->sq_signal_bits | 4222 (wr->send_flags & IB_SEND_SIGNALED ? 4223 MLX5_WQE_CTRL_CQ_UPDATE : 0) | 4224 (wr->send_flags & IB_SEND_SOLICITED ? 4225 MLX5_WQE_CTRL_SOLICITED : 0); 4226 4227 *seg += sizeof(**ctrl); 4228 *size = sizeof(**ctrl) / 16; 4229 4230 return 0; 4231 } 4232 4233 static void finish_wqe(struct mlx5_ib_qp *qp, 4234 struct mlx5_wqe_ctrl_seg *ctrl, 4235 u8 size, unsigned idx, u64 wr_id, 4236 int nreq, u8 fence, u32 mlx5_opcode) 4237 { 4238 u8 opmod = 0; 4239 4240 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) | 4241 mlx5_opcode | ((u32)opmod << 24)); 4242 ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8)); 4243 ctrl->fm_ce_se |= fence; 4244 if (unlikely(qp->wq_sig)) 4245 ctrl->signature = wq_sig(ctrl); 4246 4247 qp->sq.wrid[idx] = wr_id; 4248 qp->sq.w_list[idx].opcode = mlx5_opcode; 4249 qp->sq.wqe_head[idx] = qp->sq.head + nreq; 4250 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB); 4251 qp->sq.w_list[idx].next = qp->sq.cur_post; 4252 } 4253 4254 4255 int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, 4256 struct ib_send_wr **bad_wr) 4257 { 4258 struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */ 4259 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4260 struct mlx5_core_dev *mdev = dev->mdev; 4261 struct mlx5_ib_qp *qp; 4262 struct mlx5_ib_mr *mr; 4263 struct mlx5_wqe_data_seg *dpseg; 4264 struct mlx5_wqe_xrc_seg *xrc; 4265 struct mlx5_bf *bf; 4266 int uninitialized_var(size); 4267 void *qend; 4268 unsigned long flags; 4269 unsigned idx; 4270 int err = 0; 4271 int num_sge; 4272 void *seg; 4273 int nreq; 4274 int i; 4275 u8 next_fence = 0; 4276 u8 fence; 4277 4278 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 4279 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr); 4280 4281 qp = to_mqp(ibqp); 4282 bf = &qp->bf; 4283 qend = qp->sq.qend; 4284 4285 spin_lock_irqsave(&qp->sq.lock, flags); 4286 4287 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 4288 err = -EIO; 4289 *bad_wr = wr; 4290 nreq = 0; 4291 goto out; 4292 } 4293 4294 for (nreq = 0; wr; nreq++, wr = wr->next) { 4295 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) { 4296 mlx5_ib_warn(dev, "\n"); 4297 err = -EINVAL; 4298 *bad_wr = wr; 4299 goto out; 4300 } 4301 4302 num_sge = wr->num_sge; 4303 if (unlikely(num_sge > qp->sq.max_gs)) { 4304 mlx5_ib_warn(dev, "\n"); 4305 err = -EINVAL; 4306 *bad_wr = wr; 4307 goto out; 4308 } 4309 4310 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq); 4311 if (err) { 4312 mlx5_ib_warn(dev, "\n"); 4313 err = -ENOMEM; 4314 *bad_wr = wr; 4315 goto out; 4316 } 4317 4318 if (wr->opcode == IB_WR_LOCAL_INV || 4319 wr->opcode == IB_WR_REG_MR) { 4320 fence = dev->umr_fence; 4321 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; 4322 } else if (wr->send_flags & IB_SEND_FENCE) { 4323 if (qp->next_fence) 4324 fence = MLX5_FENCE_MODE_SMALL_AND_FENCE; 4325 else 4326 fence = MLX5_FENCE_MODE_FENCE; 4327 } else { 4328 fence = qp->next_fence; 4329 } 4330 4331 switch (ibqp->qp_type) { 4332 case IB_QPT_XRC_INI: 4333 xrc = seg; 4334 seg += sizeof(*xrc); 4335 size += sizeof(*xrc) / 16; 4336 /* fall through */ 4337 case IB_QPT_RC: 4338 switch (wr->opcode) { 4339 case IB_WR_RDMA_READ: 4340 case IB_WR_RDMA_WRITE: 4341 case IB_WR_RDMA_WRITE_WITH_IMM: 4342 set_raddr_seg(seg, rdma_wr(wr)->remote_addr, 4343 rdma_wr(wr)->rkey); 4344 seg += sizeof(struct mlx5_wqe_raddr_seg); 4345 size += sizeof(struct mlx5_wqe_raddr_seg) / 16; 4346 break; 4347 4348 case IB_WR_ATOMIC_CMP_AND_SWP: 4349 case IB_WR_ATOMIC_FETCH_AND_ADD: 4350 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP: 4351 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n"); 4352 err = -ENOSYS; 4353 *bad_wr = wr; 4354 goto out; 4355 4356 case IB_WR_LOCAL_INV: 4357 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV; 4358 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey); 4359 set_linv_wr(qp, &seg, &size); 4360 num_sge = 0; 4361 break; 4362 4363 case IB_WR_REG_MR: 4364 qp->sq.wr_data[idx] = IB_WR_REG_MR; 4365 ctrl->imm = cpu_to_be32(reg_wr(wr)->key); 4366 err = set_reg_wr(qp, reg_wr(wr), &seg, &size); 4367 if (err) { 4368 *bad_wr = wr; 4369 goto out; 4370 } 4371 num_sge = 0; 4372 break; 4373 4374 case IB_WR_REG_SIG_MR: 4375 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR; 4376 mr = to_mmr(sig_handover_wr(wr)->sig_mr); 4377 4378 ctrl->imm = cpu_to_be32(mr->ibmr.rkey); 4379 err = set_sig_umr_wr(wr, qp, &seg, &size); 4380 if (err) { 4381 mlx5_ib_warn(dev, "\n"); 4382 *bad_wr = wr; 4383 goto out; 4384 } 4385 4386 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, 4387 fence, MLX5_OPCODE_UMR); 4388 /* 4389 * SET_PSV WQEs are not signaled and solicited 4390 * on error 4391 */ 4392 wr->send_flags &= ~IB_SEND_SIGNALED; 4393 wr->send_flags |= IB_SEND_SOLICITED; 4394 err = begin_wqe(qp, &seg, &ctrl, wr, 4395 &idx, &size, nreq); 4396 if (err) { 4397 mlx5_ib_warn(dev, "\n"); 4398 err = -ENOMEM; 4399 *bad_wr = wr; 4400 goto out; 4401 } 4402 4403 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem, 4404 mr->sig->psv_memory.psv_idx, &seg, 4405 &size); 4406 if (err) { 4407 mlx5_ib_warn(dev, "\n"); 4408 *bad_wr = wr; 4409 goto out; 4410 } 4411 4412 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, 4413 fence, MLX5_OPCODE_SET_PSV); 4414 err = begin_wqe(qp, &seg, &ctrl, wr, 4415 &idx, &size, nreq); 4416 if (err) { 4417 mlx5_ib_warn(dev, "\n"); 4418 err = -ENOMEM; 4419 *bad_wr = wr; 4420 goto out; 4421 } 4422 4423 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire, 4424 mr->sig->psv_wire.psv_idx, &seg, 4425 &size); 4426 if (err) { 4427 mlx5_ib_warn(dev, "\n"); 4428 *bad_wr = wr; 4429 goto out; 4430 } 4431 4432 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, 4433 fence, MLX5_OPCODE_SET_PSV); 4434 qp->next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; 4435 num_sge = 0; 4436 goto skip_psv; 4437 4438 default: 4439 break; 4440 } 4441 break; 4442 4443 case IB_QPT_UC: 4444 switch (wr->opcode) { 4445 case IB_WR_RDMA_WRITE: 4446 case IB_WR_RDMA_WRITE_WITH_IMM: 4447 set_raddr_seg(seg, rdma_wr(wr)->remote_addr, 4448 rdma_wr(wr)->rkey); 4449 seg += sizeof(struct mlx5_wqe_raddr_seg); 4450 size += sizeof(struct mlx5_wqe_raddr_seg) / 16; 4451 break; 4452 4453 default: 4454 break; 4455 } 4456 break; 4457 4458 case IB_QPT_SMI: 4459 if (unlikely(!mdev->port_caps[qp->port - 1].has_smi)) { 4460 mlx5_ib_warn(dev, "Send SMP MADs is not allowed\n"); 4461 err = -EPERM; 4462 *bad_wr = wr; 4463 goto out; 4464 } 4465 /* fall through */ 4466 case MLX5_IB_QPT_HW_GSI: 4467 set_datagram_seg(seg, wr); 4468 seg += sizeof(struct mlx5_wqe_datagram_seg); 4469 size += sizeof(struct mlx5_wqe_datagram_seg) / 16; 4470 if (unlikely((seg == qend))) 4471 seg = mlx5_get_send_wqe(qp, 0); 4472 break; 4473 case IB_QPT_UD: 4474 set_datagram_seg(seg, wr); 4475 seg += sizeof(struct mlx5_wqe_datagram_seg); 4476 size += sizeof(struct mlx5_wqe_datagram_seg) / 16; 4477 4478 if (unlikely((seg == qend))) 4479 seg = mlx5_get_send_wqe(qp, 0); 4480 4481 /* handle qp that supports ud offload */ 4482 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) { 4483 struct mlx5_wqe_eth_pad *pad; 4484 4485 pad = seg; 4486 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad)); 4487 seg += sizeof(struct mlx5_wqe_eth_pad); 4488 size += sizeof(struct mlx5_wqe_eth_pad) / 16; 4489 4490 seg = set_eth_seg(seg, wr, qend, qp, &size); 4491 4492 if (unlikely((seg == qend))) 4493 seg = mlx5_get_send_wqe(qp, 0); 4494 } 4495 break; 4496 case MLX5_IB_QPT_REG_UMR: 4497 if (wr->opcode != MLX5_IB_WR_UMR) { 4498 err = -EINVAL; 4499 mlx5_ib_warn(dev, "bad opcode\n"); 4500 goto out; 4501 } 4502 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR; 4503 ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey); 4504 set_reg_umr_segment(seg, wr, !!(MLX5_CAP_GEN(mdev, atomic))); 4505 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 4506 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 4507 if (unlikely((seg == qend))) 4508 seg = mlx5_get_send_wqe(qp, 0); 4509 set_reg_mkey_segment(seg, wr); 4510 seg += sizeof(struct mlx5_mkey_seg); 4511 size += sizeof(struct mlx5_mkey_seg) / 16; 4512 if (unlikely((seg == qend))) 4513 seg = mlx5_get_send_wqe(qp, 0); 4514 break; 4515 4516 default: 4517 break; 4518 } 4519 4520 if (wr->send_flags & IB_SEND_INLINE && num_sge) { 4521 int uninitialized_var(sz); 4522 4523 err = set_data_inl_seg(qp, wr, seg, &sz); 4524 if (unlikely(err)) { 4525 mlx5_ib_warn(dev, "\n"); 4526 *bad_wr = wr; 4527 goto out; 4528 } 4529 size += sz; 4530 } else { 4531 dpseg = seg; 4532 for (i = 0; i < num_sge; i++) { 4533 if (unlikely(dpseg == qend)) { 4534 seg = mlx5_get_send_wqe(qp, 0); 4535 dpseg = seg; 4536 } 4537 if (likely(wr->sg_list[i].length)) { 4538 set_data_ptr_seg(dpseg, wr->sg_list + i); 4539 size += sizeof(struct mlx5_wqe_data_seg) / 16; 4540 dpseg++; 4541 } 4542 } 4543 } 4544 4545 qp->next_fence = next_fence; 4546 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, fence, 4547 mlx5_ib_opcode[wr->opcode]); 4548 skip_psv: 4549 if (0) 4550 dump_wqe(qp, idx, size); 4551 } 4552 4553 out: 4554 if (likely(nreq)) { 4555 qp->sq.head += nreq; 4556 4557 /* Make sure that descriptors are written before 4558 * updating doorbell record and ringing the doorbell 4559 */ 4560 wmb(); 4561 4562 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post); 4563 4564 /* Make sure doorbell record is visible to the HCA before 4565 * we hit doorbell */ 4566 wmb(); 4567 4568 /* currently we support only regular doorbells */ 4569 mlx5_write64((__be32 *)ctrl, bf->bfreg->map + bf->offset, NULL); 4570 /* Make sure doorbells don't leak out of SQ spinlock 4571 * and reach the HCA out of order. 4572 */ 4573 mmiowb(); 4574 bf->offset ^= bf->buf_size; 4575 } 4576 4577 spin_unlock_irqrestore(&qp->sq.lock, flags); 4578 4579 return err; 4580 } 4581 4582 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size) 4583 { 4584 sig->signature = calc_sig(sig, size); 4585 } 4586 4587 int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr, 4588 struct ib_recv_wr **bad_wr) 4589 { 4590 struct mlx5_ib_qp *qp = to_mqp(ibqp); 4591 struct mlx5_wqe_data_seg *scat; 4592 struct mlx5_rwqe_sig *sig; 4593 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4594 struct mlx5_core_dev *mdev = dev->mdev; 4595 unsigned long flags; 4596 int err = 0; 4597 int nreq; 4598 int ind; 4599 int i; 4600 4601 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 4602 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr); 4603 4604 spin_lock_irqsave(&qp->rq.lock, flags); 4605 4606 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 4607 err = -EIO; 4608 *bad_wr = wr; 4609 nreq = 0; 4610 goto out; 4611 } 4612 4613 ind = qp->rq.head & (qp->rq.wqe_cnt - 1); 4614 4615 for (nreq = 0; wr; nreq++, wr = wr->next) { 4616 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) { 4617 err = -ENOMEM; 4618 *bad_wr = wr; 4619 goto out; 4620 } 4621 4622 if (unlikely(wr->num_sge > qp->rq.max_gs)) { 4623 err = -EINVAL; 4624 *bad_wr = wr; 4625 goto out; 4626 } 4627 4628 scat = get_recv_wqe(qp, ind); 4629 if (qp->wq_sig) 4630 scat++; 4631 4632 for (i = 0; i < wr->num_sge; i++) 4633 set_data_ptr_seg(scat + i, wr->sg_list + i); 4634 4635 if (i < qp->rq.max_gs) { 4636 scat[i].byte_count = 0; 4637 scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY); 4638 scat[i].addr = 0; 4639 } 4640 4641 if (qp->wq_sig) { 4642 sig = (struct mlx5_rwqe_sig *)scat; 4643 set_sig_seg(sig, (qp->rq.max_gs + 1) << 2); 4644 } 4645 4646 qp->rq.wrid[ind] = wr->wr_id; 4647 4648 ind = (ind + 1) & (qp->rq.wqe_cnt - 1); 4649 } 4650 4651 out: 4652 if (likely(nreq)) { 4653 qp->rq.head += nreq; 4654 4655 /* Make sure that descriptors are written before 4656 * doorbell record. 4657 */ 4658 wmb(); 4659 4660 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff); 4661 } 4662 4663 spin_unlock_irqrestore(&qp->rq.lock, flags); 4664 4665 return err; 4666 } 4667 4668 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state) 4669 { 4670 switch (mlx5_state) { 4671 case MLX5_QP_STATE_RST: return IB_QPS_RESET; 4672 case MLX5_QP_STATE_INIT: return IB_QPS_INIT; 4673 case MLX5_QP_STATE_RTR: return IB_QPS_RTR; 4674 case MLX5_QP_STATE_RTS: return IB_QPS_RTS; 4675 case MLX5_QP_STATE_SQ_DRAINING: 4676 case MLX5_QP_STATE_SQD: return IB_QPS_SQD; 4677 case MLX5_QP_STATE_SQER: return IB_QPS_SQE; 4678 case MLX5_QP_STATE_ERR: return IB_QPS_ERR; 4679 default: return -1; 4680 } 4681 } 4682 4683 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state) 4684 { 4685 switch (mlx5_mig_state) { 4686 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED; 4687 case MLX5_QP_PM_REARM: return IB_MIG_REARM; 4688 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED; 4689 default: return -1; 4690 } 4691 } 4692 4693 static int to_ib_qp_access_flags(int mlx5_flags) 4694 { 4695 int ib_flags = 0; 4696 4697 if (mlx5_flags & MLX5_QP_BIT_RRE) 4698 ib_flags |= IB_ACCESS_REMOTE_READ; 4699 if (mlx5_flags & MLX5_QP_BIT_RWE) 4700 ib_flags |= IB_ACCESS_REMOTE_WRITE; 4701 if (mlx5_flags & MLX5_QP_BIT_RAE) 4702 ib_flags |= IB_ACCESS_REMOTE_ATOMIC; 4703 4704 return ib_flags; 4705 } 4706 4707 static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev, 4708 struct rdma_ah_attr *ah_attr, 4709 struct mlx5_qp_path *path) 4710 { 4711 4712 memset(ah_attr, 0, sizeof(*ah_attr)); 4713 4714 if (!path->port || path->port > ibdev->num_ports) 4715 return; 4716 4717 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, path->port); 4718 4719 rdma_ah_set_port_num(ah_attr, path->port); 4720 rdma_ah_set_sl(ah_attr, path->dci_cfi_prio_sl & 0xf); 4721 4722 rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid)); 4723 rdma_ah_set_path_bits(ah_attr, path->grh_mlid & 0x7f); 4724 rdma_ah_set_static_rate(ah_attr, 4725 path->static_rate ? path->static_rate - 5 : 0); 4726 if (path->grh_mlid & (1 << 7)) { 4727 u32 tc_fl = be32_to_cpu(path->tclass_flowlabel); 4728 4729 rdma_ah_set_grh(ah_attr, NULL, 4730 tc_fl & 0xfffff, 4731 path->mgid_index, 4732 path->hop_limit, 4733 (tc_fl >> 20) & 0xff); 4734 rdma_ah_set_dgid_raw(ah_attr, path->rgid); 4735 } 4736 } 4737 4738 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev, 4739 struct mlx5_ib_sq *sq, 4740 u8 *sq_state) 4741 { 4742 int err; 4743 4744 err = mlx5_core_query_sq_state(dev->mdev, sq->base.mqp.qpn, sq_state); 4745 if (err) 4746 goto out; 4747 sq->state = *sq_state; 4748 4749 out: 4750 return err; 4751 } 4752 4753 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev, 4754 struct mlx5_ib_rq *rq, 4755 u8 *rq_state) 4756 { 4757 void *out; 4758 void *rqc; 4759 int inlen; 4760 int err; 4761 4762 inlen = MLX5_ST_SZ_BYTES(query_rq_out); 4763 out = kvzalloc(inlen, GFP_KERNEL); 4764 if (!out) 4765 return -ENOMEM; 4766 4767 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out); 4768 if (err) 4769 goto out; 4770 4771 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context); 4772 *rq_state = MLX5_GET(rqc, rqc, state); 4773 rq->state = *rq_state; 4774 4775 out: 4776 kvfree(out); 4777 return err; 4778 } 4779 4780 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state, 4781 struct mlx5_ib_qp *qp, u8 *qp_state) 4782 { 4783 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = { 4784 [MLX5_RQC_STATE_RST] = { 4785 [MLX5_SQC_STATE_RST] = IB_QPS_RESET, 4786 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 4787 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD, 4788 [MLX5_SQ_STATE_NA] = IB_QPS_RESET, 4789 }, 4790 [MLX5_RQC_STATE_RDY] = { 4791 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD, 4792 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 4793 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE, 4794 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE, 4795 }, 4796 [MLX5_RQC_STATE_ERR] = { 4797 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD, 4798 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 4799 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR, 4800 [MLX5_SQ_STATE_NA] = IB_QPS_ERR, 4801 }, 4802 [MLX5_RQ_STATE_NA] = { 4803 [MLX5_SQC_STATE_RST] = IB_QPS_RESET, 4804 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 4805 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE, 4806 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD, 4807 }, 4808 }; 4809 4810 *qp_state = sqrq_trans[rq_state][sq_state]; 4811 4812 if (*qp_state == MLX5_QP_STATE_BAD) { 4813 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x", 4814 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state, 4815 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state); 4816 return -EINVAL; 4817 } 4818 4819 if (*qp_state == MLX5_QP_STATE) 4820 *qp_state = qp->state; 4821 4822 return 0; 4823 } 4824 4825 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev, 4826 struct mlx5_ib_qp *qp, 4827 u8 *raw_packet_qp_state) 4828 { 4829 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 4830 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 4831 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 4832 int err; 4833 u8 sq_state = MLX5_SQ_STATE_NA; 4834 u8 rq_state = MLX5_RQ_STATE_NA; 4835 4836 if (qp->sq.wqe_cnt) { 4837 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state); 4838 if (err) 4839 return err; 4840 } 4841 4842 if (qp->rq.wqe_cnt) { 4843 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state); 4844 if (err) 4845 return err; 4846 } 4847 4848 return sqrq_state_to_qp_state(sq_state, rq_state, qp, 4849 raw_packet_qp_state); 4850 } 4851 4852 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 4853 struct ib_qp_attr *qp_attr) 4854 { 4855 int outlen = MLX5_ST_SZ_BYTES(query_qp_out); 4856 struct mlx5_qp_context *context; 4857 int mlx5_state; 4858 u32 *outb; 4859 int err = 0; 4860 4861 outb = kzalloc(outlen, GFP_KERNEL); 4862 if (!outb) 4863 return -ENOMEM; 4864 4865 err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb, 4866 outlen); 4867 if (err) 4868 goto out; 4869 4870 /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */ 4871 context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc); 4872 4873 mlx5_state = be32_to_cpu(context->flags) >> 28; 4874 4875 qp->state = to_ib_qp_state(mlx5_state); 4876 qp_attr->path_mtu = context->mtu_msgmax >> 5; 4877 qp_attr->path_mig_state = 4878 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3); 4879 qp_attr->qkey = be32_to_cpu(context->qkey); 4880 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff; 4881 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff; 4882 qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff; 4883 qp_attr->qp_access_flags = 4884 to_ib_qp_access_flags(be32_to_cpu(context->params2)); 4885 4886 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) { 4887 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path); 4888 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path); 4889 qp_attr->alt_pkey_index = 4890 be16_to_cpu(context->alt_path.pkey_index); 4891 qp_attr->alt_port_num = 4892 rdma_ah_get_port_num(&qp_attr->alt_ah_attr); 4893 } 4894 4895 qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index); 4896 qp_attr->port_num = context->pri_path.port; 4897 4898 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */ 4899 qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING; 4900 4901 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7); 4902 4903 qp_attr->max_dest_rd_atomic = 4904 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7); 4905 qp_attr->min_rnr_timer = 4906 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f; 4907 qp_attr->timeout = context->pri_path.ackto_lt >> 3; 4908 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7; 4909 qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7; 4910 qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3; 4911 4912 out: 4913 kfree(outb); 4914 return err; 4915 } 4916 4917 static int mlx5_ib_dct_query_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *mqp, 4918 struct ib_qp_attr *qp_attr, int qp_attr_mask, 4919 struct ib_qp_init_attr *qp_init_attr) 4920 { 4921 struct mlx5_core_dct *dct = &mqp->dct.mdct; 4922 u32 *out; 4923 u32 access_flags = 0; 4924 int outlen = MLX5_ST_SZ_BYTES(query_dct_out); 4925 void *dctc; 4926 int err; 4927 int supported_mask = IB_QP_STATE | 4928 IB_QP_ACCESS_FLAGS | 4929 IB_QP_PORT | 4930 IB_QP_MIN_RNR_TIMER | 4931 IB_QP_AV | 4932 IB_QP_PATH_MTU | 4933 IB_QP_PKEY_INDEX; 4934 4935 if (qp_attr_mask & ~supported_mask) 4936 return -EINVAL; 4937 if (mqp->state != IB_QPS_RTR) 4938 return -EINVAL; 4939 4940 out = kzalloc(outlen, GFP_KERNEL); 4941 if (!out) 4942 return -ENOMEM; 4943 4944 err = mlx5_core_dct_query(dev->mdev, dct, out, outlen); 4945 if (err) 4946 goto out; 4947 4948 dctc = MLX5_ADDR_OF(query_dct_out, out, dct_context_entry); 4949 4950 if (qp_attr_mask & IB_QP_STATE) 4951 qp_attr->qp_state = IB_QPS_RTR; 4952 4953 if (qp_attr_mask & IB_QP_ACCESS_FLAGS) { 4954 if (MLX5_GET(dctc, dctc, rre)) 4955 access_flags |= IB_ACCESS_REMOTE_READ; 4956 if (MLX5_GET(dctc, dctc, rwe)) 4957 access_flags |= IB_ACCESS_REMOTE_WRITE; 4958 if (MLX5_GET(dctc, dctc, rae)) 4959 access_flags |= IB_ACCESS_REMOTE_ATOMIC; 4960 qp_attr->qp_access_flags = access_flags; 4961 } 4962 4963 if (qp_attr_mask & IB_QP_PORT) 4964 qp_attr->port_num = MLX5_GET(dctc, dctc, port); 4965 if (qp_attr_mask & IB_QP_MIN_RNR_TIMER) 4966 qp_attr->min_rnr_timer = MLX5_GET(dctc, dctc, min_rnr_nak); 4967 if (qp_attr_mask & IB_QP_AV) { 4968 qp_attr->ah_attr.grh.traffic_class = MLX5_GET(dctc, dctc, tclass); 4969 qp_attr->ah_attr.grh.flow_label = MLX5_GET(dctc, dctc, flow_label); 4970 qp_attr->ah_attr.grh.sgid_index = MLX5_GET(dctc, dctc, my_addr_index); 4971 qp_attr->ah_attr.grh.hop_limit = MLX5_GET(dctc, dctc, hop_limit); 4972 } 4973 if (qp_attr_mask & IB_QP_PATH_MTU) 4974 qp_attr->path_mtu = MLX5_GET(dctc, dctc, mtu); 4975 if (qp_attr_mask & IB_QP_PKEY_INDEX) 4976 qp_attr->pkey_index = MLX5_GET(dctc, dctc, pkey_index); 4977 out: 4978 kfree(out); 4979 return err; 4980 } 4981 4982 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 4983 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr) 4984 { 4985 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4986 struct mlx5_ib_qp *qp = to_mqp(ibqp); 4987 int err = 0; 4988 u8 raw_packet_qp_state; 4989 4990 if (ibqp->rwq_ind_tbl) 4991 return -ENOSYS; 4992 4993 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 4994 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask, 4995 qp_init_attr); 4996 4997 /* Not all of output fields are applicable, make sure to zero them */ 4998 memset(qp_init_attr, 0, sizeof(*qp_init_attr)); 4999 memset(qp_attr, 0, sizeof(*qp_attr)); 5000 5001 if (unlikely(qp->qp_sub_type == MLX5_IB_QPT_DCT)) 5002 return mlx5_ib_dct_query_qp(dev, qp, qp_attr, 5003 qp_attr_mask, qp_init_attr); 5004 5005 mutex_lock(&qp->mutex); 5006 5007 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || 5008 qp->flags & MLX5_IB_QP_UNDERLAY) { 5009 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state); 5010 if (err) 5011 goto out; 5012 qp->state = raw_packet_qp_state; 5013 qp_attr->port_num = 1; 5014 } else { 5015 err = query_qp_attr(dev, qp, qp_attr); 5016 if (err) 5017 goto out; 5018 } 5019 5020 qp_attr->qp_state = qp->state; 5021 qp_attr->cur_qp_state = qp_attr->qp_state; 5022 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt; 5023 qp_attr->cap.max_recv_sge = qp->rq.max_gs; 5024 5025 if (!ibqp->uobject) { 5026 qp_attr->cap.max_send_wr = qp->sq.max_post; 5027 qp_attr->cap.max_send_sge = qp->sq.max_gs; 5028 qp_init_attr->qp_context = ibqp->qp_context; 5029 } else { 5030 qp_attr->cap.max_send_wr = 0; 5031 qp_attr->cap.max_send_sge = 0; 5032 } 5033 5034 qp_init_attr->qp_type = ibqp->qp_type; 5035 qp_init_attr->recv_cq = ibqp->recv_cq; 5036 qp_init_attr->send_cq = ibqp->send_cq; 5037 qp_init_attr->srq = ibqp->srq; 5038 qp_attr->cap.max_inline_data = qp->max_inline_data; 5039 5040 qp_init_attr->cap = qp_attr->cap; 5041 5042 qp_init_attr->create_flags = 0; 5043 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK) 5044 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK; 5045 5046 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) 5047 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL; 5048 if (qp->flags & MLX5_IB_QP_MANAGED_SEND) 5049 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND; 5050 if (qp->flags & MLX5_IB_QP_MANAGED_RECV) 5051 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV; 5052 if (qp->flags & MLX5_IB_QP_SQPN_QP1) 5053 qp_init_attr->create_flags |= mlx5_ib_create_qp_sqpn_qp1(); 5054 5055 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ? 5056 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR; 5057 5058 out: 5059 mutex_unlock(&qp->mutex); 5060 return err; 5061 } 5062 5063 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev, 5064 struct ib_ucontext *context, 5065 struct ib_udata *udata) 5066 { 5067 struct mlx5_ib_dev *dev = to_mdev(ibdev); 5068 struct mlx5_ib_xrcd *xrcd; 5069 int err; 5070 5071 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 5072 return ERR_PTR(-ENOSYS); 5073 5074 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL); 5075 if (!xrcd) 5076 return ERR_PTR(-ENOMEM); 5077 5078 err = mlx5_core_xrcd_alloc(dev->mdev, &xrcd->xrcdn); 5079 if (err) { 5080 kfree(xrcd); 5081 return ERR_PTR(-ENOMEM); 5082 } 5083 5084 return &xrcd->ibxrcd; 5085 } 5086 5087 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd) 5088 { 5089 struct mlx5_ib_dev *dev = to_mdev(xrcd->device); 5090 u32 xrcdn = to_mxrcd(xrcd)->xrcdn; 5091 int err; 5092 5093 err = mlx5_core_xrcd_dealloc(dev->mdev, xrcdn); 5094 if (err) 5095 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn); 5096 5097 kfree(xrcd); 5098 return 0; 5099 } 5100 5101 static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type) 5102 { 5103 struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp); 5104 struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device); 5105 struct ib_event event; 5106 5107 if (rwq->ibwq.event_handler) { 5108 event.device = rwq->ibwq.device; 5109 event.element.wq = &rwq->ibwq; 5110 switch (type) { 5111 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 5112 event.event = IB_EVENT_WQ_FATAL; 5113 break; 5114 default: 5115 mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn); 5116 return; 5117 } 5118 5119 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context); 5120 } 5121 } 5122 5123 static int set_delay_drop(struct mlx5_ib_dev *dev) 5124 { 5125 int err = 0; 5126 5127 mutex_lock(&dev->delay_drop.lock); 5128 if (dev->delay_drop.activate) 5129 goto out; 5130 5131 err = mlx5_core_set_delay_drop(dev->mdev, dev->delay_drop.timeout); 5132 if (err) 5133 goto out; 5134 5135 dev->delay_drop.activate = true; 5136 out: 5137 mutex_unlock(&dev->delay_drop.lock); 5138 5139 if (!err) 5140 atomic_inc(&dev->delay_drop.rqs_cnt); 5141 return err; 5142 } 5143 5144 static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd, 5145 struct ib_wq_init_attr *init_attr) 5146 { 5147 struct mlx5_ib_dev *dev; 5148 int has_net_offloads; 5149 __be64 *rq_pas0; 5150 void *in; 5151 void *rqc; 5152 void *wq; 5153 int inlen; 5154 int err; 5155 5156 dev = to_mdev(pd->device); 5157 5158 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas; 5159 in = kvzalloc(inlen, GFP_KERNEL); 5160 if (!in) 5161 return -ENOMEM; 5162 5163 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 5164 MLX5_SET(rqc, rqc, mem_rq_type, 5165 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE); 5166 MLX5_SET(rqc, rqc, user_index, rwq->user_index); 5167 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn); 5168 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 5169 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 5170 wq = MLX5_ADDR_OF(rqc, rqc, wq); 5171 MLX5_SET(wq, wq, wq_type, 5172 rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ ? 5173 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ : MLX5_WQ_TYPE_CYCLIC); 5174 if (init_attr->create_flags & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) { 5175 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) { 5176 mlx5_ib_dbg(dev, "Scatter end padding is not supported\n"); 5177 err = -EOPNOTSUPP; 5178 goto out; 5179 } else { 5180 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 5181 } 5182 } 5183 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride); 5184 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ) { 5185 MLX5_SET(wq, wq, two_byte_shift_en, rwq->two_byte_shift_en); 5186 MLX5_SET(wq, wq, log_wqe_stride_size, 5187 rwq->single_stride_log_num_of_bytes - 5188 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES); 5189 MLX5_SET(wq, wq, log_wqe_num_of_strides, rwq->log_num_strides - 5190 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES); 5191 } 5192 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size); 5193 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn); 5194 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset); 5195 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size); 5196 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig); 5197 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma); 5198 has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads); 5199 if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) { 5200 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) { 5201 mlx5_ib_dbg(dev, "VLAN offloads are not supported\n"); 5202 err = -EOPNOTSUPP; 5203 goto out; 5204 } 5205 } else { 5206 MLX5_SET(rqc, rqc, vsd, 1); 5207 } 5208 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) { 5209 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) { 5210 mlx5_ib_dbg(dev, "Scatter FCS is not supported\n"); 5211 err = -EOPNOTSUPP; 5212 goto out; 5213 } 5214 MLX5_SET(rqc, rqc, scatter_fcs, 1); 5215 } 5216 if (init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) { 5217 if (!(dev->ib_dev.attrs.raw_packet_caps & 5218 IB_RAW_PACKET_CAP_DELAY_DROP)) { 5219 mlx5_ib_dbg(dev, "Delay drop is not supported\n"); 5220 err = -EOPNOTSUPP; 5221 goto out; 5222 } 5223 MLX5_SET(rqc, rqc, delay_drop_en, 1); 5224 } 5225 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 5226 mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0); 5227 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rwq->core_qp); 5228 if (!err && init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) { 5229 err = set_delay_drop(dev); 5230 if (err) { 5231 mlx5_ib_warn(dev, "Failed to enable delay drop err=%d\n", 5232 err); 5233 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp); 5234 } else { 5235 rwq->create_flags |= MLX5_IB_WQ_FLAGS_DELAY_DROP; 5236 } 5237 } 5238 out: 5239 kvfree(in); 5240 return err; 5241 } 5242 5243 static int set_user_rq_size(struct mlx5_ib_dev *dev, 5244 struct ib_wq_init_attr *wq_init_attr, 5245 struct mlx5_ib_create_wq *ucmd, 5246 struct mlx5_ib_rwq *rwq) 5247 { 5248 /* Sanity check RQ size before proceeding */ 5249 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz))) 5250 return -EINVAL; 5251 5252 if (!ucmd->rq_wqe_count) 5253 return -EINVAL; 5254 5255 rwq->wqe_count = ucmd->rq_wqe_count; 5256 rwq->wqe_shift = ucmd->rq_wqe_shift; 5257 rwq->buf_size = (rwq->wqe_count << rwq->wqe_shift); 5258 rwq->log_rq_stride = rwq->wqe_shift; 5259 rwq->log_rq_size = ilog2(rwq->wqe_count); 5260 return 0; 5261 } 5262 5263 static int prepare_user_rq(struct ib_pd *pd, 5264 struct ib_wq_init_attr *init_attr, 5265 struct ib_udata *udata, 5266 struct mlx5_ib_rwq *rwq) 5267 { 5268 struct mlx5_ib_dev *dev = to_mdev(pd->device); 5269 struct mlx5_ib_create_wq ucmd = {}; 5270 int err; 5271 size_t required_cmd_sz; 5272 5273 required_cmd_sz = offsetof(typeof(ucmd), single_stride_log_num_of_bytes) 5274 + sizeof(ucmd.single_stride_log_num_of_bytes); 5275 if (udata->inlen < required_cmd_sz) { 5276 mlx5_ib_dbg(dev, "invalid inlen\n"); 5277 return -EINVAL; 5278 } 5279 5280 if (udata->inlen > sizeof(ucmd) && 5281 !ib_is_udata_cleared(udata, sizeof(ucmd), 5282 udata->inlen - sizeof(ucmd))) { 5283 mlx5_ib_dbg(dev, "inlen is not supported\n"); 5284 return -EOPNOTSUPP; 5285 } 5286 5287 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) { 5288 mlx5_ib_dbg(dev, "copy failed\n"); 5289 return -EFAULT; 5290 } 5291 5292 if (ucmd.comp_mask & (~MLX5_IB_CREATE_WQ_STRIDING_RQ)) { 5293 mlx5_ib_dbg(dev, "invalid comp mask\n"); 5294 return -EOPNOTSUPP; 5295 } else if (ucmd.comp_mask & MLX5_IB_CREATE_WQ_STRIDING_RQ) { 5296 if (!MLX5_CAP_GEN(dev->mdev, striding_rq)) { 5297 mlx5_ib_dbg(dev, "Striding RQ is not supported\n"); 5298 return -EOPNOTSUPP; 5299 } 5300 if ((ucmd.single_stride_log_num_of_bytes < 5301 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES) || 5302 (ucmd.single_stride_log_num_of_bytes > 5303 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES)) { 5304 mlx5_ib_dbg(dev, "Invalid log stride size (%u. Range is %u - %u)\n", 5305 ucmd.single_stride_log_num_of_bytes, 5306 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES, 5307 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES); 5308 return -EINVAL; 5309 } 5310 if ((ucmd.single_wqe_log_num_of_strides > 5311 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES) || 5312 (ucmd.single_wqe_log_num_of_strides < 5313 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) { 5314 mlx5_ib_dbg(dev, "Invalid log num strides (%u. Range is %u - %u)\n", 5315 ucmd.single_wqe_log_num_of_strides, 5316 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES, 5317 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES); 5318 return -EINVAL; 5319 } 5320 rwq->single_stride_log_num_of_bytes = 5321 ucmd.single_stride_log_num_of_bytes; 5322 rwq->log_num_strides = ucmd.single_wqe_log_num_of_strides; 5323 rwq->two_byte_shift_en = !!ucmd.two_byte_shift_en; 5324 rwq->create_flags |= MLX5_IB_WQ_FLAGS_STRIDING_RQ; 5325 } 5326 5327 err = set_user_rq_size(dev, init_attr, &ucmd, rwq); 5328 if (err) { 5329 mlx5_ib_dbg(dev, "err %d\n", err); 5330 return err; 5331 } 5332 5333 err = create_user_rq(dev, pd, rwq, &ucmd); 5334 if (err) { 5335 mlx5_ib_dbg(dev, "err %d\n", err); 5336 if (err) 5337 return err; 5338 } 5339 5340 rwq->user_index = ucmd.user_index; 5341 return 0; 5342 } 5343 5344 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, 5345 struct ib_wq_init_attr *init_attr, 5346 struct ib_udata *udata) 5347 { 5348 struct mlx5_ib_dev *dev; 5349 struct mlx5_ib_rwq *rwq; 5350 struct mlx5_ib_create_wq_resp resp = {}; 5351 size_t min_resp_len; 5352 int err; 5353 5354 if (!udata) 5355 return ERR_PTR(-ENOSYS); 5356 5357 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved); 5358 if (udata->outlen && udata->outlen < min_resp_len) 5359 return ERR_PTR(-EINVAL); 5360 5361 dev = to_mdev(pd->device); 5362 switch (init_attr->wq_type) { 5363 case IB_WQT_RQ: 5364 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL); 5365 if (!rwq) 5366 return ERR_PTR(-ENOMEM); 5367 err = prepare_user_rq(pd, init_attr, udata, rwq); 5368 if (err) 5369 goto err; 5370 err = create_rq(rwq, pd, init_attr); 5371 if (err) 5372 goto err_user_rq; 5373 break; 5374 default: 5375 mlx5_ib_dbg(dev, "unsupported wq type %d\n", 5376 init_attr->wq_type); 5377 return ERR_PTR(-EINVAL); 5378 } 5379 5380 rwq->ibwq.wq_num = rwq->core_qp.qpn; 5381 rwq->ibwq.state = IB_WQS_RESET; 5382 if (udata->outlen) { 5383 resp.response_length = offsetof(typeof(resp), response_length) + 5384 sizeof(resp.response_length); 5385 err = ib_copy_to_udata(udata, &resp, resp.response_length); 5386 if (err) 5387 goto err_copy; 5388 } 5389 5390 rwq->core_qp.event = mlx5_ib_wq_event; 5391 rwq->ibwq.event_handler = init_attr->event_handler; 5392 return &rwq->ibwq; 5393 5394 err_copy: 5395 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp); 5396 err_user_rq: 5397 destroy_user_rq(dev, pd, rwq); 5398 err: 5399 kfree(rwq); 5400 return ERR_PTR(err); 5401 } 5402 5403 int mlx5_ib_destroy_wq(struct ib_wq *wq) 5404 { 5405 struct mlx5_ib_dev *dev = to_mdev(wq->device); 5406 struct mlx5_ib_rwq *rwq = to_mrwq(wq); 5407 5408 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp); 5409 destroy_user_rq(dev, wq->pd, rwq); 5410 kfree(rwq); 5411 5412 return 0; 5413 } 5414 5415 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device, 5416 struct ib_rwq_ind_table_init_attr *init_attr, 5417 struct ib_udata *udata) 5418 { 5419 struct mlx5_ib_dev *dev = to_mdev(device); 5420 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl; 5421 int sz = 1 << init_attr->log_ind_tbl_size; 5422 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {}; 5423 size_t min_resp_len; 5424 int inlen; 5425 int err; 5426 int i; 5427 u32 *in; 5428 void *rqtc; 5429 5430 if (udata->inlen > 0 && 5431 !ib_is_udata_cleared(udata, 0, 5432 udata->inlen)) 5433 return ERR_PTR(-EOPNOTSUPP); 5434 5435 if (init_attr->log_ind_tbl_size > 5436 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) { 5437 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n", 5438 init_attr->log_ind_tbl_size, 5439 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)); 5440 return ERR_PTR(-EINVAL); 5441 } 5442 5443 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved); 5444 if (udata->outlen && udata->outlen < min_resp_len) 5445 return ERR_PTR(-EINVAL); 5446 5447 rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL); 5448 if (!rwq_ind_tbl) 5449 return ERR_PTR(-ENOMEM); 5450 5451 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz; 5452 in = kvzalloc(inlen, GFP_KERNEL); 5453 if (!in) { 5454 err = -ENOMEM; 5455 goto err; 5456 } 5457 5458 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 5459 5460 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); 5461 MLX5_SET(rqtc, rqtc, rqt_max_size, sz); 5462 5463 for (i = 0; i < sz; i++) 5464 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num); 5465 5466 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn); 5467 kvfree(in); 5468 5469 if (err) 5470 goto err; 5471 5472 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn; 5473 if (udata->outlen) { 5474 resp.response_length = offsetof(typeof(resp), response_length) + 5475 sizeof(resp.response_length); 5476 err = ib_copy_to_udata(udata, &resp, resp.response_length); 5477 if (err) 5478 goto err_copy; 5479 } 5480 5481 return &rwq_ind_tbl->ib_rwq_ind_tbl; 5482 5483 err_copy: 5484 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn); 5485 err: 5486 kfree(rwq_ind_tbl); 5487 return ERR_PTR(err); 5488 } 5489 5490 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) 5491 { 5492 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl); 5493 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device); 5494 5495 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn); 5496 5497 kfree(rwq_ind_tbl); 5498 return 0; 5499 } 5500 5501 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, 5502 u32 wq_attr_mask, struct ib_udata *udata) 5503 { 5504 struct mlx5_ib_dev *dev = to_mdev(wq->device); 5505 struct mlx5_ib_rwq *rwq = to_mrwq(wq); 5506 struct mlx5_ib_modify_wq ucmd = {}; 5507 size_t required_cmd_sz; 5508 int curr_wq_state; 5509 int wq_state; 5510 int inlen; 5511 int err; 5512 void *rqc; 5513 void *in; 5514 5515 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved); 5516 if (udata->inlen < required_cmd_sz) 5517 return -EINVAL; 5518 5519 if (udata->inlen > sizeof(ucmd) && 5520 !ib_is_udata_cleared(udata, sizeof(ucmd), 5521 udata->inlen - sizeof(ucmd))) 5522 return -EOPNOTSUPP; 5523 5524 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) 5525 return -EFAULT; 5526 5527 if (ucmd.comp_mask || ucmd.reserved) 5528 return -EOPNOTSUPP; 5529 5530 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 5531 in = kvzalloc(inlen, GFP_KERNEL); 5532 if (!in) 5533 return -ENOMEM; 5534 5535 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 5536 5537 curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ? 5538 wq_attr->curr_wq_state : wq->state; 5539 wq_state = (wq_attr_mask & IB_WQ_STATE) ? 5540 wq_attr->wq_state : curr_wq_state; 5541 if (curr_wq_state == IB_WQS_ERR) 5542 curr_wq_state = MLX5_RQC_STATE_ERR; 5543 if (wq_state == IB_WQS_ERR) 5544 wq_state = MLX5_RQC_STATE_ERR; 5545 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state); 5546 MLX5_SET(rqc, rqc, state, wq_state); 5547 5548 if (wq_attr_mask & IB_WQ_FLAGS) { 5549 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) { 5550 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 5551 MLX5_CAP_ETH(dev->mdev, vlan_cap))) { 5552 mlx5_ib_dbg(dev, "VLAN offloads are not " 5553 "supported\n"); 5554 err = -EOPNOTSUPP; 5555 goto out; 5556 } 5557 MLX5_SET64(modify_rq_in, in, modify_bitmask, 5558 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD); 5559 MLX5_SET(rqc, rqc, vsd, 5560 (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1); 5561 } 5562 5563 if (wq_attr->flags_mask & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) { 5564 mlx5_ib_dbg(dev, "Modifying scatter end padding is not supported\n"); 5565 err = -EOPNOTSUPP; 5566 goto out; 5567 } 5568 } 5569 5570 if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) { 5571 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) { 5572 MLX5_SET64(modify_rq_in, in, modify_bitmask, 5573 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID); 5574 MLX5_SET(rqc, rqc, counter_set_id, 5575 dev->port->cnts.set_id); 5576 } else 5577 pr_info_once("%s: Receive WQ counters are not supported on current FW\n", 5578 dev->ib_dev.name); 5579 } 5580 5581 err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in, inlen); 5582 if (!err) 5583 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state; 5584 5585 out: 5586 kvfree(in); 5587 return err; 5588 } 5589