1 /* 2 * Copyright (C) 2016 Socionext Inc. 3 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #include <linux/stddef.h> 17 18 #include "clk-uniphier.h" 19 20 #define UNIPHIER_LD4_SYS_CLK_SD \ 21 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 8), \ 22 UNIPHIER_CLK_FACTOR("sd-133m", -1, "vpll27a", 1, 2) 23 24 #define UNIPHIER_PRO5_SYS_CLK_SD \ 25 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 12), \ 26 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 18) 27 28 #define UNIPHIER_LD20_SYS_CLK_SD \ 29 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 10), \ 30 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 15) 31 32 /* Denali driver requires clk_x rate (clk: 50MHz, clk_x & ecc_clk: 200MHz) */ 33 #define UNIPHIER_LD4_SYS_CLK_NAND(idx) \ 34 UNIPHIER_CLK_FACTOR("nand-200m", -1, "spll", 1, 8), \ 35 UNIPHIER_CLK_GATE("nand", (idx), "nand-200m", 0x2104, 2) 36 37 #define UNIPHIER_PRO5_SYS_CLK_NAND(idx) \ 38 UNIPHIER_CLK_FACTOR("nand-200m", -1, "spll", 1, 12), \ 39 UNIPHIER_CLK_GATE("nand", (idx), "nand-200m", 0x2104, 2) 40 41 #define UNIPHIER_LD11_SYS_CLK_NAND(idx) \ 42 UNIPHIER_CLK_FACTOR("nand-200m", -1, "spll", 1, 10), \ 43 UNIPHIER_CLK_GATE("nand", (idx), "nand-200m", 0x210c, 0) 44 45 #define UNIPHIER_LD11_SYS_CLK_EMMC(idx) \ 46 UNIPHIER_CLK_GATE("emmc", (idx), NULL, 0x210c, 2) 47 48 #define UNIPHIER_LD4_SYS_CLK_STDMAC(idx) \ 49 UNIPHIER_CLK_GATE("stdmac", (idx), NULL, 0x2104, 10) 50 51 #define UNIPHIER_LD11_SYS_CLK_STDMAC(idx) \ 52 UNIPHIER_CLK_GATE("stdmac", (idx), NULL, 0x210c, 8) 53 54 #define UNIPHIER_PRO4_SYS_CLK_GIO(idx) \ 55 UNIPHIER_CLK_GATE("gio", (idx), NULL, 0x2104, 6) 56 57 #define UNIPHIER_PRO4_SYS_CLK_USB3(idx, ch) \ 58 UNIPHIER_CLK_GATE("usb3" #ch, (idx), NULL, 0x2104, 16 + (ch)) 59 60 #define UNIPHIER_PRO4_SYS_CLK_AIO(idx) \ 61 UNIPHIER_CLK_FACTOR("aio-io200m", -1, "spll", 1, 8), \ 62 UNIPHIER_CLK_GATE("aio", (idx), "aio-io200m", 0x2104, 13) 63 64 #define UNIPHIER_PRO5_SYS_CLK_AIO(idx) \ 65 UNIPHIER_CLK_FACTOR("aio-io200m", -1, "spll", 1, 12), \ 66 UNIPHIER_CLK_GATE("aio", (idx), "aio-io200m", 0x2104, 13) 67 68 #define UNIPHIER_LD11_SYS_CLK_AIO(idx) \ 69 UNIPHIER_CLK_FACTOR("aio-io200m", -1, "spll", 1, 10), \ 70 UNIPHIER_CLK_GATE("aio", (idx), "aio-io200m", 0x2108, 0) 71 72 #define UNIPHIER_LD11_SYS_CLK_EVEA(idx) \ 73 UNIPHIER_CLK_FACTOR("evea-io100m", -1, "spll", 1, 20), \ 74 UNIPHIER_CLK_GATE("evea", (idx), "evea-io100m", 0x2108, 1) 75 76 #define UNIPHIER_LD11_SYS_CLK_EXIV(idx) \ 77 UNIPHIER_CLK_FACTOR("exiv-io200m", -1, "spll", 1, 10), \ 78 UNIPHIER_CLK_GATE("exiv", (idx), "exiv-io200m", 0x2110, 2) 79 80 #define UNIPHIER_PRO4_SYS_CLK_ETHER(idx) \ 81 UNIPHIER_CLK_GATE("ether", (idx), NULL, 0x2104, 12) 82 83 #define UNIPHIER_LD11_SYS_CLK_ETHER(idx) \ 84 UNIPHIER_CLK_GATE("ether", (idx), NULL, 0x210c, 6) 85 86 const struct uniphier_clk_data uniphier_ld4_sys_clk_data[] = { 87 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 65, 1), /* 1597.44 MHz */ 88 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 6000, 512), /* 288 MHz */ 89 UNIPHIER_CLK_FACTOR("a2pll", -1, "ref", 24, 1), /* 589.824 MHz */ 90 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 5625, 512), /* 270 MHz */ 91 UNIPHIER_CLK_FACTOR("uart", 0, "a2pll", 1, 16), 92 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 16), 93 UNIPHIER_LD4_SYS_CLK_NAND(2), 94 UNIPHIER_LD4_SYS_CLK_SD, 95 UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12), 96 UNIPHIER_LD4_SYS_CLK_STDMAC(8), /* Ether, HSC, MIO */ 97 { /* sentinel */ } 98 }; 99 100 const struct uniphier_clk_data uniphier_pro4_sys_clk_data[] = { 101 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1), /* 1600 MHz */ 102 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 288, 25), /* 288 MHz */ 103 UNIPHIER_CLK_FACTOR("a2pll", -1, "upll", 256, 125), /* 589.824 MHz */ 104 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 270, 25), /* 270 MHz */ 105 UNIPHIER_CLK_FACTOR("gpll", -1, "ref", 10, 1), /* 250 MHz */ 106 UNIPHIER_CLK_FACTOR("uart", 0, "a2pll", 1, 8), 107 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 32), 108 UNIPHIER_LD4_SYS_CLK_NAND(2), 109 UNIPHIER_LD4_SYS_CLK_SD, 110 UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12), 111 UNIPHIER_PRO4_SYS_CLK_ETHER(6), 112 UNIPHIER_CLK_GATE("ether-gb", 7, "gpll", 0x2104, 5), 113 UNIPHIER_LD4_SYS_CLK_STDMAC(8), /* HSC, MIO, RLE */ 114 UNIPHIER_CLK_GATE("ether-phy", 10, "ref", 0x2260, 0), 115 UNIPHIER_PRO4_SYS_CLK_GIO(12), /* Ether, SATA, USB3 */ 116 UNIPHIER_PRO4_SYS_CLK_USB3(14, 0), 117 UNIPHIER_PRO4_SYS_CLK_USB3(15, 1), 118 UNIPHIER_CLK_GATE("sata0", 28, NULL, 0x2104, 18), 119 UNIPHIER_CLK_GATE("sata1", 29, NULL, 0x2104, 19), 120 UNIPHIER_PRO4_SYS_CLK_AIO(40), 121 { /* sentinel */ } 122 }; 123 124 const struct uniphier_clk_data uniphier_sld8_sys_clk_data[] = { 125 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1), /* 1600 MHz */ 126 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 288, 25), /* 288 MHz */ 127 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 270, 25), /* 270 MHz */ 128 UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 20), 129 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 16), 130 UNIPHIER_LD4_SYS_CLK_NAND(2), 131 UNIPHIER_LD4_SYS_CLK_SD, 132 UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12), 133 UNIPHIER_LD4_SYS_CLK_STDMAC(8), /* Ether, HSC, MIO */ 134 { /* sentinel */ } 135 }; 136 137 const struct uniphier_clk_data uniphier_pro5_sys_clk_data[] = { 138 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 120, 1), /* 2400 MHz */ 139 UNIPHIER_CLK_FACTOR("dapll1", -1, "ref", 128, 1), /* 2560 MHz */ 140 UNIPHIER_CLK_FACTOR("dapll2", -1, "dapll1", 144, 125), /* 2949.12 MHz */ 141 UNIPHIER_CLK_FACTOR("uart", 0, "dapll2", 1, 40), 142 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 48), 143 UNIPHIER_PRO5_SYS_CLK_NAND(2), 144 UNIPHIER_PRO5_SYS_CLK_SD, 145 UNIPHIER_LD4_SYS_CLK_STDMAC(8), /* HSC */ 146 UNIPHIER_PRO4_SYS_CLK_GIO(12), /* PCIe, USB3 */ 147 UNIPHIER_PRO4_SYS_CLK_USB3(14, 0), 148 UNIPHIER_PRO4_SYS_CLK_USB3(15, 1), 149 UNIPHIER_CLK_GATE("pcie", 24, NULL, 0x2108, 2), 150 UNIPHIER_PRO5_SYS_CLK_AIO(40), 151 { /* sentinel */ } 152 }; 153 154 const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = { 155 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 96, 1), /* 2400 MHz */ 156 UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 27), 157 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 48), 158 UNIPHIER_PRO5_SYS_CLK_NAND(2), 159 UNIPHIER_PRO5_SYS_CLK_SD, 160 UNIPHIER_PRO4_SYS_CLK_ETHER(6), 161 UNIPHIER_LD4_SYS_CLK_STDMAC(8), /* HSC, RLE */ 162 /* GIO is always clock-enabled: no function for 0x2104 bit6 */ 163 UNIPHIER_PRO4_SYS_CLK_USB3(14, 0), 164 UNIPHIER_PRO4_SYS_CLK_USB3(15, 1), 165 /* The document mentions 0x2104 bit 18, but not functional */ 166 UNIPHIER_CLK_GATE("usb30-phy", 16, NULL, 0x2104, 19), 167 UNIPHIER_CLK_GATE("usb31-phy", 20, NULL, 0x2104, 20), 168 UNIPHIER_CLK_GATE("sata0", 28, NULL, 0x2104, 22), 169 UNIPHIER_PRO5_SYS_CLK_AIO(40), 170 { /* sentinel */ } 171 }; 172 173 const struct uniphier_clk_data uniphier_ld11_sys_clk_data[] = { 174 UNIPHIER_CLK_FACTOR("cpll", -1, "ref", 392, 5), /* 1960 MHz */ 175 UNIPHIER_CLK_FACTOR("mpll", -1, "ref", 64, 1), /* 1600 MHz */ 176 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 80, 1), /* 2000 MHz */ 177 UNIPHIER_CLK_FACTOR("vspll", -1, "ref", 80, 1), /* 2000 MHz */ 178 UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 34), 179 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 40), 180 UNIPHIER_LD11_SYS_CLK_NAND(2), 181 UNIPHIER_LD11_SYS_CLK_EMMC(4), 182 /* Index 5 reserved for eMMC PHY */ 183 UNIPHIER_LD11_SYS_CLK_ETHER(6), 184 UNIPHIER_LD11_SYS_CLK_STDMAC(8), /* HSC, MIO */ 185 UNIPHIER_CLK_FACTOR("usb2", -1, "ref", 24, 25), 186 UNIPHIER_LD11_SYS_CLK_AIO(40), 187 UNIPHIER_LD11_SYS_CLK_EVEA(41), 188 UNIPHIER_LD11_SYS_CLK_EXIV(42), 189 /* CPU gears */ 190 UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8), 191 UNIPHIER_CLK_DIV4("mpll", 2, 3, 4, 8), 192 UNIPHIER_CLK_DIV3("spll", 3, 4, 8), 193 /* Note: both gear1 and gear4 are spll/4. This is not a bug. */ 194 UNIPHIER_CLK_CPUGEAR("cpu-ca53", 33, 0x8080, 0xf, 8, 195 "cpll/2", "spll/4", "cpll/3", "spll/3", 196 "spll/4", "spll/8", "cpll/4", "cpll/8"), 197 UNIPHIER_CLK_CPUGEAR("cpu-ipp", 34, 0x8100, 0xf, 8, 198 "mpll/2", "spll/4", "mpll/3", "spll/3", 199 "spll/4", "spll/8", "mpll/4", "mpll/8"), 200 { /* sentinel */ } 201 }; 202 203 const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = { 204 UNIPHIER_CLK_FACTOR("cpll", -1, "ref", 88, 1), /* ARM: 2200 MHz */ 205 UNIPHIER_CLK_FACTOR("gppll", -1, "ref", 52, 1), /* Mali: 1300 MHz */ 206 UNIPHIER_CLK_FACTOR("mpll", -1, "ref", 64, 1), /* Codec: 1600 MHz */ 207 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 80, 1), /* 2000 MHz */ 208 UNIPHIER_CLK_FACTOR("s2pll", -1, "ref", 88, 1), /* IPP: 2200 MHz */ 209 UNIPHIER_CLK_FACTOR("vppll", -1, "ref", 504, 5), /* 2520 MHz */ 210 UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 34), 211 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 40), 212 UNIPHIER_LD11_SYS_CLK_NAND(2), 213 UNIPHIER_LD11_SYS_CLK_EMMC(4), 214 /* Index 5 reserved for eMMC PHY */ 215 UNIPHIER_LD20_SYS_CLK_SD, 216 UNIPHIER_LD11_SYS_CLK_ETHER(6), 217 UNIPHIER_LD11_SYS_CLK_STDMAC(8), /* HSC */ 218 /* GIO is always clock-enabled: no function for 0x210c bit5 */ 219 /* 220 * clock for USB Link is enabled by the logic "OR" of bit 14 and bit 15. 221 * We do not use bit 15 here. 222 */ 223 UNIPHIER_CLK_GATE("usb30", 14, NULL, 0x210c, 14), 224 UNIPHIER_CLK_GATE("usb30-phy0", 16, NULL, 0x210c, 12), 225 UNIPHIER_CLK_GATE("usb30-phy1", 17, NULL, 0x210c, 13), 226 UNIPHIER_CLK_GATE("pcie", 24, NULL, 0x210c, 4), 227 UNIPHIER_LD11_SYS_CLK_AIO(40), 228 UNIPHIER_LD11_SYS_CLK_EVEA(41), 229 UNIPHIER_LD11_SYS_CLK_EXIV(42), 230 /* CPU gears */ 231 UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8), 232 UNIPHIER_CLK_DIV4("spll", 2, 3, 4, 8), 233 UNIPHIER_CLK_DIV4("s2pll", 2, 3, 4, 8), 234 UNIPHIER_CLK_CPUGEAR("cpu-ca72", 32, 0x8000, 0xf, 8, 235 "cpll/2", "spll/2", "cpll/3", "spll/3", 236 "spll/4", "spll/8", "cpll/4", "cpll/8"), 237 UNIPHIER_CLK_CPUGEAR("cpu-ca53", 33, 0x8080, 0xf, 8, 238 "cpll/2", "spll/2", "cpll/3", "spll/3", 239 "spll/4", "spll/8", "cpll/4", "cpll/8"), 240 UNIPHIER_CLK_CPUGEAR("cpu-ipp", 34, 0x8100, 0xf, 8, 241 "s2pll/2", "spll/2", "s2pll/3", "spll/3", 242 "spll/4", "spll/8", "s2pll/4", "s2pll/8"), 243 { /* sentinel */ } 244 }; 245 246 const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[] = { 247 UNIPHIER_CLK_FACTOR("cpll", -1, "ref", 104, 1), /* ARM: 2600 MHz */ 248 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 80, 1), /* 2000 MHz */ 249 UNIPHIER_CLK_FACTOR("s2pll", -1, "ref", 88, 1), /* IPP: 2400 MHz */ 250 UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 34), 251 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 40), 252 UNIPHIER_LD20_SYS_CLK_SD, 253 UNIPHIER_LD11_SYS_CLK_NAND(2), 254 UNIPHIER_LD11_SYS_CLK_EMMC(4), 255 UNIPHIER_CLK_GATE("ether0", 6, NULL, 0x210c, 9), 256 UNIPHIER_CLK_GATE("ether1", 7, NULL, 0x210c, 10), 257 UNIPHIER_CLK_GATE("usb30", 12, NULL, 0x210c, 4), /* =GIO0 */ 258 UNIPHIER_CLK_GATE("usb31-0", 13, NULL, 0x210c, 5), /* =GIO1 */ 259 UNIPHIER_CLK_GATE("usb31-1", 14, NULL, 0x210c, 6), /* =GIO1-1 */ 260 UNIPHIER_CLK_GATE("usb30-phy0", 16, NULL, 0x210c, 16), 261 UNIPHIER_CLK_GATE("usb30-phy1", 17, NULL, 0x210c, 18), 262 UNIPHIER_CLK_GATE("usb30-phy2", 18, NULL, 0x210c, 20), 263 UNIPHIER_CLK_GATE("usb31-phy0", 20, NULL, 0x210c, 17), 264 UNIPHIER_CLK_GATE("usb31-phy1", 21, NULL, 0x210c, 19), 265 UNIPHIER_CLK_GATE("pcie", 24, NULL, 0x210c, 3), 266 UNIPHIER_CLK_GATE("sata0", 28, NULL, 0x210c, 7), 267 UNIPHIER_CLK_GATE("sata1", 29, NULL, 0x210c, 8), 268 UNIPHIER_CLK_GATE("sata-phy", 30, NULL, 0x210c, 21), 269 /* CPU gears */ 270 UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8), 271 UNIPHIER_CLK_DIV4("spll", 2, 3, 4, 8), 272 UNIPHIER_CLK_DIV4("s2pll", 2, 3, 4, 8), 273 UNIPHIER_CLK_CPUGEAR("cpu-ca53", 33, 0x8080, 0xf, 8, 274 "cpll/2", "spll/2", "cpll/3", "spll/3", 275 "spll/4", "spll/8", "cpll/4", "cpll/8"), 276 UNIPHIER_CLK_CPUGEAR("cpu-ipp", 34, 0x8100, 0xf, 8, 277 "s2pll/2", "spll/2", "s2pll/3", "spll/3", 278 "spll/4", "spll/8", "s2pll/4", "s2pll/8"), 279 { /* sentinel */ } 280 }; 281