1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2017 Amlogic, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/interrupt-controller/irq.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/axg-clkc.h> 10 11/ { 12 compatible = "amlogic,meson-axg"; 13 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 reserved-memory { 19 #address-cells = <2>; 20 #size-cells = <2>; 21 ranges; 22 23 /* 16 MiB reserved for Hardware ROM Firmware */ 24 hwrom_reserved: hwrom@0 { 25 reg = <0x0 0x0 0x0 0x1000000>; 26 no-map; 27 }; 28 29 /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */ 30 secmon_reserved: secmon@5000000 { 31 reg = <0x0 0x05000000 0x0 0x300000>; 32 no-map; 33 }; 34 }; 35 36 cpus { 37 #address-cells = <0x2>; 38 #size-cells = <0x0>; 39 40 cpu0: cpu@0 { 41 device_type = "cpu"; 42 compatible = "arm,cortex-a53", "arm,armv8"; 43 reg = <0x0 0x0>; 44 enable-method = "psci"; 45 next-level-cache = <&l2>; 46 }; 47 48 cpu1: cpu@1 { 49 device_type = "cpu"; 50 compatible = "arm,cortex-a53", "arm,armv8"; 51 reg = <0x0 0x1>; 52 enable-method = "psci"; 53 next-level-cache = <&l2>; 54 }; 55 56 cpu2: cpu@2 { 57 device_type = "cpu"; 58 compatible = "arm,cortex-a53", "arm,armv8"; 59 reg = <0x0 0x2>; 60 enable-method = "psci"; 61 next-level-cache = <&l2>; 62 }; 63 64 cpu3: cpu@3 { 65 device_type = "cpu"; 66 compatible = "arm,cortex-a53", "arm,armv8"; 67 reg = <0x0 0x3>; 68 enable-method = "psci"; 69 next-level-cache = <&l2>; 70 }; 71 72 l2: l2-cache0 { 73 compatible = "cache"; 74 }; 75 }; 76 77 arm-pmu { 78 compatible = "arm,cortex-a53-pmu"; 79 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 80 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 83 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 84 }; 85 86 psci { 87 compatible = "arm,psci-1.0"; 88 method = "smc"; 89 }; 90 91 timer { 92 compatible = "arm,armv8-timer"; 93 interrupts = <GIC_PPI 13 94 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 95 <GIC_PPI 14 96 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 97 <GIC_PPI 11 98 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 99 <GIC_PPI 10 100 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 101 }; 102 103 xtal: xtal-clk { 104 compatible = "fixed-clock"; 105 clock-frequency = <24000000>; 106 clock-output-names = "xtal"; 107 #clock-cells = <0>; 108 }; 109 110 soc { 111 compatible = "simple-bus"; 112 #address-cells = <2>; 113 #size-cells = <2>; 114 ranges; 115 116 cbus: bus@ffd00000 { 117 compatible = "simple-bus"; 118 reg = <0x0 0xffd00000 0x0 0x25000>; 119 #address-cells = <2>; 120 #size-cells = <2>; 121 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>; 122 123 pwm_ab: pwm@1b000 { 124 compatible = "amlogic,meson-axg-ee-pwm"; 125 reg = <0x0 0x1b000 0x0 0x20>; 126 #pwm-cells = <3>; 127 status = "disabled"; 128 }; 129 130 pwm_cd: pwm@1a000 { 131 compatible = "amlogic,meson-axg-ee-pwm"; 132 reg = <0x0 0x1a000 0x0 0x20>; 133 #pwm-cells = <3>; 134 status = "disabled"; 135 }; 136 137 reset: reset-controller@1004 { 138 compatible = "amlogic,meson-axg-reset"; 139 reg = <0x0 0x01004 0x0 0x9c>; 140 #reset-cells = <1>; 141 }; 142 143 spicc0: spi@13000 { 144 compatible = "amlogic,meson-axg-spicc"; 145 reg = <0x0 0x13000 0x0 0x3c>; 146 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 147 clocks = <&clkc CLKID_SPICC0>; 148 clock-names = "core"; 149 #address-cells = <1>; 150 #size-cells = <0>; 151 status = "disabled"; 152 }; 153 154 spicc1: spi@15000 { 155 compatible = "amlogic,meson-axg-spicc"; 156 reg = <0x0 0x15000 0x0 0x3c>; 157 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 158 clocks = <&clkc CLKID_SPICC1>; 159 clock-names = "core"; 160 #address-cells = <1>; 161 #size-cells = <0>; 162 status = "disabled"; 163 }; 164 165 i2c0: i2c@1f000 { 166 compatible = "amlogic,meson-axg-i2c"; 167 status = "disabled"; 168 reg = <0x0 0x1f000 0x0 0x20>; 169 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, 170 <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>; 171 #address-cells = <1>; 172 #size-cells = <0>; 173 clocks = <&clkc CLKID_I2C>; 174 clock-names = "clk_i2c"; 175 }; 176 177 i2c1: i2c@1e000 { 178 compatible = "amlogic,meson-axg-i2c"; 179 #address-cells = <1>; 180 #size-cells = <0>; 181 reg = <0x0 0x1e000 0x0 0x20>; 182 status = "disabled"; 183 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>, 184 <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>; 185 clocks = <&clkc CLKID_I2C>; 186 clock-names = "clk_i2c"; 187 }; 188 189 i2c2: i2c@1d000 { 190 compatible = "amlogic,meson-axg-i2c"; 191 status = "disabled"; 192 reg = <0x0 0x1d000 0x0 0x20>; 193 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>, 194 <GIC_SPI 49 IRQ_TYPE_EDGE_RISING>; 195 #address-cells = <1>; 196 #size-cells = <0>; 197 clocks = <&clkc CLKID_I2C>; 198 clock-names = "clk_i2c"; 199 }; 200 201 i2c3: i2c@1c000 { 202 compatible = "amlogic,meson-axg-i2c"; 203 status = "disabled"; 204 reg = <0x0 0x1c000 0x0 0x20>; 205 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>, 206 <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>; 207 #address-cells = <1>; 208 #size-cells = <0>; 209 clocks = <&clkc CLKID_I2C>; 210 clock-names = "clk_i2c"; 211 }; 212 213 uart_A: serial@24000 { 214 compatible = "amlogic,meson-gx-uart"; 215 reg = <0x0 0x24000 0x0 0x18>; 216 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 217 status = "disabled"; 218 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; 219 clock-names = "xtal", "pclk", "baud"; 220 }; 221 222 uart_B: serial@23000 { 223 compatible = "amlogic,meson-gx-uart"; 224 reg = <0x0 0x23000 0x0 0x18>; 225 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; 226 status = "disabled"; 227 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; 228 clock-names = "xtal", "pclk", "baud"; 229 }; 230 }; 231 232 ethmac: ethernet@ff3f0000 { 233 compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac"; 234 reg = <0x0 0xff3f0000 0x0 0x10000 235 0x0 0xff634540 0x0 0x8>; 236 interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>; 237 interrupt-names = "macirq"; 238 clocks = <&clkc CLKID_ETH>, 239 <&clkc CLKID_FCLK_DIV2>, 240 <&clkc CLKID_MPLL2>; 241 clock-names = "stmmaceth", "clkin0", "clkin1"; 242 status = "disabled"; 243 }; 244 245 gic: interrupt-controller@ffc01000 { 246 compatible = "arm,gic-400"; 247 reg = <0x0 0xffc01000 0 0x1000>, 248 <0x0 0xffc02000 0 0x2000>, 249 <0x0 0xffc04000 0 0x2000>, 250 <0x0 0xffc06000 0 0x2000>; 251 interrupt-controller; 252 interrupts = <GIC_PPI 9 253 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 254 #interrupt-cells = <3>; 255 #address-cells = <0>; 256 }; 257 258 hiubus: bus@ff63c000 { 259 compatible = "simple-bus"; 260 reg = <0x0 0xff63c000 0x0 0x1c00>; 261 #address-cells = <2>; 262 #size-cells = <2>; 263 ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>; 264 265 clkc: clock-controller@0 { 266 compatible = "amlogic,axg-clkc"; 267 #clock-cells = <1>; 268 reg = <0x0 0x0 0x0 0x320>; 269 }; 270 }; 271 272 mailbox: mailbox@ff63dc00 { 273 compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu"; 274 reg = <0 0xff63dc00 0 0x400>; 275 interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>, 276 <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>, 277 <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>; 278 #mbox-cells = <1>; 279 }; 280 281 periphs: periphs@ff634000 { 282 compatible = "simple-bus"; 283 reg = <0x0 0xff634000 0x0 0x2000>; 284 #address-cells = <2>; 285 #size-cells = <2>; 286 ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>; 287 288 hwrng: rng { 289 compatible = "amlogic,meson-rng"; 290 reg = <0x0 0x18 0x0 0x4>; 291 clocks = <&clkc CLKID_RNG0>; 292 clock-names = "core"; 293 }; 294 295 pinctrl_periphs: pinctrl@480 { 296 compatible = "amlogic,meson-axg-periphs-pinctrl"; 297 #address-cells = <2>; 298 #size-cells = <2>; 299 ranges; 300 301 gpio: bank@480 { 302 reg = <0x0 0x00480 0x0 0x40>, 303 <0x0 0x004e8 0x0 0x14>, 304 <0x0 0x00520 0x0 0x14>, 305 <0x0 0x00430 0x0 0x3c>; 306 reg-names = "mux", "pull", "pull-enable", "gpio"; 307 gpio-controller; 308 #gpio-cells = <2>; 309 gpio-ranges = <&pinctrl_periphs 0 0 86>; 310 }; 311 312 eth_rmii_x_pins: eth-x-rmii { 313 mux { 314 groups = "eth_mdio_x", 315 "eth_mdc_x", 316 "eth_rgmii_rx_clk_x", 317 "eth_rx_dv_x", 318 "eth_rxd0_x", 319 "eth_rxd1_x", 320 "eth_txen_x", 321 "eth_txd0_x", 322 "eth_txd1_x"; 323 function = "eth"; 324 }; 325 }; 326 327 eth_rmii_y_pins: eth-y-rmii { 328 mux { 329 groups = "eth_mdio_y", 330 "eth_mdc_y", 331 "eth_rgmii_rx_clk_y", 332 "eth_rx_dv_y", 333 "eth_rxd0_y", 334 "eth_rxd1_y", 335 "eth_txen_y", 336 "eth_txd0_y", 337 "eth_txd1_y"; 338 function = "eth"; 339 }; 340 }; 341 342 eth_rgmii_x_pins: eth-x-rgmii { 343 mux { 344 groups = "eth_mdio_x", 345 "eth_mdc_x", 346 "eth_rgmii_rx_clk_x", 347 "eth_rx_dv_x", 348 "eth_rxd0_x", 349 "eth_rxd1_x", 350 "eth_rxd2_rgmii", 351 "eth_rxd3_rgmii", 352 "eth_rgmii_tx_clk", 353 "eth_txen_x", 354 "eth_txd0_x", 355 "eth_txd1_x", 356 "eth_txd2_rgmii", 357 "eth_txd3_rgmii"; 358 function = "eth"; 359 }; 360 }; 361 362 eth_rgmii_y_pins: eth-y-rgmii { 363 mux { 364 groups = "eth_mdio_y", 365 "eth_mdc_y", 366 "eth_rgmii_rx_clk_y", 367 "eth_rx_dv_y", 368 "eth_rxd0_y", 369 "eth_rxd1_y", 370 "eth_rxd2_rgmii", 371 "eth_rxd3_rgmii", 372 "eth_rgmii_tx_clk", 373 "eth_txen_y", 374 "eth_txd0_y", 375 "eth_txd1_y", 376 "eth_txd2_rgmii", 377 "eth_txd3_rgmii"; 378 function = "eth"; 379 }; 380 }; 381 382 pwm_a_a_pins: pwm_a_a { 383 mux { 384 groups = "pwm_a_a"; 385 function = "pwm_a"; 386 }; 387 }; 388 389 pwm_a_x18_pins: pwm_a_x18 { 390 mux { 391 groups = "pwm_a_x18"; 392 function = "pwm_a"; 393 }; 394 }; 395 396 pwm_a_x20_pins: pwm_a_x20 { 397 mux { 398 groups = "pwm_a_x20"; 399 function = "pwm_a"; 400 }; 401 }; 402 403 pwm_a_z_pins: pwm_a_z { 404 mux { 405 groups = "pwm_a_z"; 406 function = "pwm_a"; 407 }; 408 }; 409 410 pwm_b_a_pins: pwm_b_a { 411 mux { 412 groups = "pwm_b_a"; 413 function = "pwm_b"; 414 }; 415 }; 416 417 pwm_b_x_pins: pwm_b_x { 418 mux { 419 groups = "pwm_b_x"; 420 function = "pwm_b"; 421 }; 422 }; 423 424 pwm_b_z_pins: pwm_b_z { 425 mux { 426 groups = "pwm_b_z"; 427 function = "pwm_b"; 428 }; 429 }; 430 431 pwm_c_a_pins: pwm_c_a { 432 mux { 433 groups = "pwm_c_a"; 434 function = "pwm_c"; 435 }; 436 }; 437 438 pwm_c_x10_pins: pwm_c_x10 { 439 mux { 440 groups = "pwm_c_x10"; 441 function = "pwm_c"; 442 }; 443 }; 444 445 pwm_c_x17_pins: pwm_c_x17 { 446 mux { 447 groups = "pwm_c_x17"; 448 function = "pwm_c"; 449 }; 450 }; 451 452 pwm_d_x11_pins: pwm_d_x11 { 453 mux { 454 groups = "pwm_d_x11"; 455 function = "pwm_d"; 456 }; 457 }; 458 459 pwm_d_x16_pins: pwm_d_x16 { 460 mux { 461 groups = "pwm_d_x16"; 462 function = "pwm_d"; 463 }; 464 }; 465 466 spi0_pins: spi0 { 467 mux { 468 groups = "spi0_miso", 469 "spi0_mosi", 470 "spi0_clk"; 471 function = "spi0"; 472 }; 473 }; 474 475 spi0_ss0_pins: spi0_ss0 { 476 mux { 477 groups = "spi0_ss0"; 478 function = "spi0"; 479 }; 480 }; 481 482 spi0_ss1_pins: spi0_ss1 { 483 mux { 484 groups = "spi0_ss1"; 485 function = "spi0"; 486 }; 487 }; 488 489 spi0_ss2_pins: spi0_ss2 { 490 mux { 491 groups = "spi0_ss2"; 492 function = "spi0"; 493 }; 494 }; 495 496 497 spi1_a_pins: spi1_a { 498 mux { 499 groups = "spi1_miso_a", 500 "spi1_mosi_a", 501 "spi1_clk_a"; 502 function = "spi1"; 503 }; 504 }; 505 506 spi1_ss0_a_pins: spi1_ss0_a { 507 mux { 508 groups = "spi1_ss0_a"; 509 function = "spi1"; 510 }; 511 }; 512 513 spi1_ss1_pins: spi1_ss1 { 514 mux { 515 groups = "spi1_ss1"; 516 function = "spi1"; 517 }; 518 }; 519 520 spi1_x_pins: spi1_x { 521 mux { 522 groups = "spi1_miso_x", 523 "spi1_mosi_x", 524 "spi1_clk_x"; 525 function = "spi1"; 526 }; 527 }; 528 529 spi1_ss0_x_pins: spi1_ss0_x { 530 mux { 531 groups = "spi1_ss0_x"; 532 function = "spi1"; 533 }; 534 }; 535 536 i2c0_pins: i2c0 { 537 mux { 538 groups = "i2c0_sck", 539 "i2c0_sda"; 540 function = "i2c0"; 541 }; 542 }; 543 544 i2c1_z_pins: i2c1_z { 545 mux { 546 groups = "i2c1_sck_z", 547 "i2c1_sda_z"; 548 function = "i2c1"; 549 }; 550 }; 551 552 i2c1_x_pins: i2c1_x { 553 mux { 554 groups = "i2c1_sck_x", 555 "i2c1_sda_x"; 556 function = "i2c1"; 557 }; 558 }; 559 560 i2c2_x_pins: i2c2_x { 561 mux { 562 groups = "i2c2_sck_x", 563 "i2c2_sda_x"; 564 function = "i2c2"; 565 }; 566 }; 567 568 i2c2_a_pins: i2c2_a { 569 mux { 570 groups = "i2c2_sck_a", 571 "i2c2_sda_a"; 572 function = "i2c2"; 573 }; 574 }; 575 576 i2c3_a6_pins: i2c3_a6 { 577 mux { 578 groups = "i2c3_sda_a6", 579 "i2c3_sck_a7"; 580 function = "i2c3"; 581 }; 582 }; 583 584 i2c3_a12_pins: i2c3_a12 { 585 mux { 586 groups = "i2c3_sda_a12", 587 "i2c3_sck_a13"; 588 function = "i2c3"; 589 }; 590 }; 591 592 i2c3_a19_pins: i2c3_a19 { 593 mux { 594 groups = "i2c3_sda_a19", 595 "i2c3_sck_a20"; 596 function = "i2c3"; 597 }; 598 }; 599 600 uart_a_pins: uart_a { 601 mux { 602 groups = "uart_tx_a", 603 "uart_rx_a"; 604 function = "uart_a"; 605 }; 606 }; 607 608 uart_a_cts_rts_pins: uart_a_cts_rts { 609 mux { 610 groups = "uart_cts_a", 611 "uart_rts_a"; 612 function = "uart_a"; 613 }; 614 }; 615 616 uart_b_x_pins: uart_b_x { 617 mux { 618 groups = "uart_tx_b_x", 619 "uart_rx_b_x"; 620 function = "uart_b"; 621 }; 622 }; 623 624 uart_b_x_cts_rts_pins: uart_b_x_cts_rts { 625 mux { 626 groups = "uart_cts_b_x", 627 "uart_rts_b_x"; 628 function = "uart_b"; 629 }; 630 }; 631 632 uart_b_z_pins: uart_b_z { 633 mux { 634 groups = "uart_tx_b_z", 635 "uart_rx_b_z"; 636 function = "uart_b"; 637 }; 638 }; 639 640 uart_b_z_cts_rts_pins: uart_b_z_cts_rts { 641 mux { 642 groups = "uart_cts_b_z", 643 "uart_rts_b_z"; 644 function = "uart_b"; 645 }; 646 }; 647 648 uart_ao_b_z_pins: uart_ao_b_z { 649 mux { 650 groups = "uart_ao_tx_b_z", 651 "uart_ao_rx_b_z"; 652 function = "uart_ao_b_z"; 653 }; 654 }; 655 656 uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts { 657 mux { 658 groups = "uart_ao_cts_b_z", 659 "uart_ao_rts_b_z"; 660 function = "uart_ao_b_z"; 661 }; 662 }; 663 }; 664 }; 665 666 sram: sram@fffc0000 { 667 compatible = "amlogic,meson-axg-sram", "mmio-sram"; 668 reg = <0x0 0xfffc0000 0x0 0x20000>; 669 #address-cells = <1>; 670 #size-cells = <1>; 671 ranges = <0 0x0 0xfffc0000 0x20000>; 672 673 cpu_scp_lpri: scp-shmem@0 { 674 compatible = "amlogic,meson-axg-scp-shmem"; 675 reg = <0x13000 0x400>; 676 }; 677 678 cpu_scp_hpri: scp-shmem@200 { 679 compatible = "amlogic,meson-axg-scp-shmem"; 680 reg = <0x13400 0x400>; 681 }; 682 }; 683 684 aobus: bus@ff800000 { 685 compatible = "simple-bus"; 686 reg = <0x0 0xff800000 0x0 0x100000>; 687 #address-cells = <2>; 688 #size-cells = <2>; 689 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; 690 691 pinctrl_aobus: pinctrl@14 { 692 compatible = "amlogic,meson-axg-aobus-pinctrl"; 693 #address-cells = <2>; 694 #size-cells = <2>; 695 ranges; 696 697 gpio_ao: bank@14 { 698 reg = <0x0 0x00014 0x0 0x8>, 699 <0x0 0x0002c 0x0 0x4>, 700 <0x0 0x00024 0x0 0x8>; 701 reg-names = "mux", "pull", "gpio"; 702 gpio-controller; 703 #gpio-cells = <2>; 704 gpio-ranges = <&pinctrl_aobus 0 0 15>; 705 }; 706 707 remote_input_ao_pins: remote_input_ao { 708 mux { 709 groups = "remote_input_ao"; 710 function = "remote_input_ao"; 711 }; 712 }; 713 714 uart_ao_a_pins: uart_ao_a { 715 mux { 716 groups = "uart_ao_tx_a", 717 "uart_ao_rx_a"; 718 function = "uart_ao_a"; 719 }; 720 }; 721 722 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts { 723 mux { 724 groups = "uart_ao_cts_a", 725 "uart_ao_rts_a"; 726 function = "uart_ao_a"; 727 }; 728 }; 729 730 uart_ao_b_pins: uart_ao_b { 731 mux { 732 groups = "uart_ao_tx_b", 733 "uart_ao_rx_b"; 734 function = "uart_ao_b"; 735 }; 736 }; 737 738 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts { 739 mux { 740 groups = "uart_ao_cts_b", 741 "uart_ao_rts_b"; 742 function = "uart_ao_b"; 743 }; 744 }; 745 }; 746 747 sec_AO: ao-secure@140 { 748 compatible = "amlogic,meson-gx-ao-secure", "syscon"; 749 reg = <0x0 0x140 0x0 0x140>; 750 amlogic,has-chip-id; 751 }; 752 753 pwm_AO_ab: pwm@7000 { 754 compatible = "amlogic,meson-axg-ao-pwm"; 755 reg = <0x0 0x07000 0x0 0x20>; 756 #pwm-cells = <3>; 757 status = "disabled"; 758 }; 759 760 pwm_AO_cd: pwm@2000 { 761 compatible = "amlogic,meson-axg-ao-pwm"; 762 reg = <0x0 0x02000 0x0 0x20>; 763 #pwm-cells = <3>; 764 status = "disabled"; 765 }; 766 767 i2c_AO: i2c@5000 { 768 compatible = "amlogic,meson-axg-i2c"; 769 status = "disabled"; 770 reg = <0x0 0x05000 0x0 0x20>; 771 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>; 772 #address-cells = <1>; 773 #size-cells = <0>; 774 clocks = <&clkc CLKID_I2C>; 775 clock-names = "clk_i2c"; 776 }; 777 778 uart_AO: serial@3000 { 779 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; 780 reg = <0x0 0x3000 0x0 0x18>; 781 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 782 clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>; 783 clock-names = "xtal", "pclk", "baud"; 784 status = "disabled"; 785 }; 786 787 uart_AO_B: serial@4000 { 788 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; 789 reg = <0x0 0x4000 0x0 0x18>; 790 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 791 clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>; 792 clock-names = "xtal", "pclk", "baud"; 793 status = "disabled"; 794 }; 795 796 ir: ir@8000 { 797 compatible = "amlogic,meson-gxbb-ir"; 798 reg = <0x0 0x8000 0x0 0x20>; 799 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; 800 status = "disabled"; 801 }; 802 }; 803 }; 804}; 805