1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <drm/drmP.h> 28 #include "amdgpu.h" 29 #include "amdgpu_psp.h" 30 #include "amdgpu_ucode.h" 31 #include "soc15_common.h" 32 #include "psp_v3_1.h" 33 34 #include "mp/mp_9_0_offset.h" 35 #include "mp/mp_9_0_sh_mask.h" 36 #include "gc/gc_9_0_offset.h" 37 #include "sdma0/sdma0_4_0_offset.h" 38 #include "nbio/nbio_6_1_offset.h" 39 40 MODULE_FIRMWARE("amdgpu/vega10_sos.bin"); 41 MODULE_FIRMWARE("amdgpu/vega10_asd.bin"); 42 MODULE_FIRMWARE("amdgpu/vega12_sos.bin"); 43 MODULE_FIRMWARE("amdgpu/vega12_asd.bin"); 44 45 #define smnMP1_FIRMWARE_FLAGS 0x3010028 46 47 static int 48 psp_v3_1_get_fw_type(struct amdgpu_firmware_info *ucode, enum psp_gfx_fw_type *type) 49 { 50 switch(ucode->ucode_id) { 51 case AMDGPU_UCODE_ID_SDMA0: 52 *type = GFX_FW_TYPE_SDMA0; 53 break; 54 case AMDGPU_UCODE_ID_SDMA1: 55 *type = GFX_FW_TYPE_SDMA1; 56 break; 57 case AMDGPU_UCODE_ID_CP_CE: 58 *type = GFX_FW_TYPE_CP_CE; 59 break; 60 case AMDGPU_UCODE_ID_CP_PFP: 61 *type = GFX_FW_TYPE_CP_PFP; 62 break; 63 case AMDGPU_UCODE_ID_CP_ME: 64 *type = GFX_FW_TYPE_CP_ME; 65 break; 66 case AMDGPU_UCODE_ID_CP_MEC1: 67 *type = GFX_FW_TYPE_CP_MEC; 68 break; 69 case AMDGPU_UCODE_ID_CP_MEC1_JT: 70 *type = GFX_FW_TYPE_CP_MEC_ME1; 71 break; 72 case AMDGPU_UCODE_ID_CP_MEC2: 73 *type = GFX_FW_TYPE_CP_MEC; 74 break; 75 case AMDGPU_UCODE_ID_CP_MEC2_JT: 76 *type = GFX_FW_TYPE_CP_MEC_ME2; 77 break; 78 case AMDGPU_UCODE_ID_RLC_G: 79 *type = GFX_FW_TYPE_RLC_G; 80 break; 81 case AMDGPU_UCODE_ID_SMC: 82 *type = GFX_FW_TYPE_SMU; 83 break; 84 case AMDGPU_UCODE_ID_UVD: 85 *type = GFX_FW_TYPE_UVD; 86 break; 87 case AMDGPU_UCODE_ID_VCE: 88 *type = GFX_FW_TYPE_VCE; 89 break; 90 case AMDGPU_UCODE_ID_MAXIMUM: 91 default: 92 return -EINVAL; 93 } 94 95 return 0; 96 } 97 98 static int psp_v3_1_init_microcode(struct psp_context *psp) 99 { 100 struct amdgpu_device *adev = psp->adev; 101 const char *chip_name; 102 char fw_name[30]; 103 int err = 0; 104 const struct psp_firmware_header_v1_0 *hdr; 105 106 DRM_DEBUG("\n"); 107 108 switch (adev->asic_type) { 109 case CHIP_VEGA10: 110 chip_name = "vega10"; 111 break; 112 case CHIP_VEGA12: 113 chip_name = "vega12"; 114 break; 115 default: BUG(); 116 } 117 118 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); 119 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev); 120 if (err) 121 goto out; 122 123 err = amdgpu_ucode_validate(adev->psp.sos_fw); 124 if (err) 125 goto out; 126 127 hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 128 adev->psp.sos_fw_version = le32_to_cpu(hdr->header.ucode_version); 129 adev->psp.sos_feature_version = le32_to_cpu(hdr->ucode_feature_version); 130 adev->psp.sos_bin_size = le32_to_cpu(hdr->sos_size_bytes); 131 adev->psp.sys_bin_size = le32_to_cpu(hdr->header.ucode_size_bytes) - 132 le32_to_cpu(hdr->sos_size_bytes); 133 adev->psp.sys_start_addr = (uint8_t *)hdr + 134 le32_to_cpu(hdr->header.ucode_array_offset_bytes); 135 adev->psp.sos_start_addr = (uint8_t *)adev->psp.sys_start_addr + 136 le32_to_cpu(hdr->sos_offset_bytes); 137 138 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 139 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev); 140 if (err) 141 goto out; 142 143 err = amdgpu_ucode_validate(adev->psp.asd_fw); 144 if (err) 145 goto out; 146 147 hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 148 adev->psp.asd_fw_version = le32_to_cpu(hdr->header.ucode_version); 149 adev->psp.asd_feature_version = le32_to_cpu(hdr->ucode_feature_version); 150 adev->psp.asd_ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes); 151 adev->psp.asd_start_addr = (uint8_t *)hdr + 152 le32_to_cpu(hdr->header.ucode_array_offset_bytes); 153 154 return 0; 155 out: 156 if (err) { 157 dev_err(adev->dev, 158 "psp v3.1: Failed to load firmware \"%s\"\n", 159 fw_name); 160 release_firmware(adev->psp.sos_fw); 161 adev->psp.sos_fw = NULL; 162 release_firmware(adev->psp.asd_fw); 163 adev->psp.asd_fw = NULL; 164 } 165 166 return err; 167 } 168 169 static int psp_v3_1_bootloader_load_sysdrv(struct psp_context *psp) 170 { 171 int ret; 172 uint32_t psp_gfxdrv_command_reg = 0; 173 struct amdgpu_device *adev = psp->adev; 174 uint32_t sol_reg; 175 176 /* Check sOS sign of life register to confirm sys driver and sOS 177 * are already been loaded. 178 */ 179 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 180 if (sol_reg) 181 return 0; 182 183 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ 184 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 185 0x80000000, 0x80000000, false); 186 if (ret) 187 return ret; 188 189 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 190 191 /* Copy PSP System Driver binary to memory */ 192 memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size); 193 194 /* Provide the sys driver to bootrom */ 195 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 196 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 197 psp_gfxdrv_command_reg = 1 << 16; 198 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 199 psp_gfxdrv_command_reg); 200 201 /* there might be handshake issue with hardware which needs delay */ 202 mdelay(20); 203 204 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 205 0x80000000, 0x80000000, false); 206 207 return ret; 208 } 209 210 static int psp_v3_1_bootloader_load_sos(struct psp_context *psp) 211 { 212 int ret; 213 unsigned int psp_gfxdrv_command_reg = 0; 214 struct amdgpu_device *adev = psp->adev; 215 uint32_t sol_reg; 216 217 /* Check sOS sign of life register to confirm sys driver and sOS 218 * are already been loaded. 219 */ 220 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 221 if (sol_reg) 222 return 0; 223 224 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ 225 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 226 0x80000000, 0x80000000, false); 227 if (ret) 228 return ret; 229 230 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 231 232 /* Copy Secure OS binary to PSP memory */ 233 memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size); 234 235 /* Provide the PSP secure OS to bootrom */ 236 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 237 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 238 psp_gfxdrv_command_reg = 2 << 16; 239 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 240 psp_gfxdrv_command_reg); 241 242 /* there might be handshake issue with hardware which needs delay */ 243 mdelay(20); 244 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81), 245 RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), 246 0, true); 247 248 return ret; 249 } 250 251 static int psp_v3_1_prep_cmd_buf(struct amdgpu_firmware_info *ucode, 252 struct psp_gfx_cmd_resp *cmd) 253 { 254 int ret; 255 uint64_t fw_mem_mc_addr = ucode->mc_addr; 256 257 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 258 259 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 260 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 261 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 262 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 263 264 ret = psp_v3_1_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 265 if (ret) 266 DRM_ERROR("Unknown firmware type\n"); 267 268 return ret; 269 } 270 271 static int psp_v3_1_ring_init(struct psp_context *psp, 272 enum psp_ring_type ring_type) 273 { 274 int ret = 0; 275 struct psp_ring *ring; 276 struct amdgpu_device *adev = psp->adev; 277 278 ring = &psp->km_ring; 279 280 ring->ring_type = ring_type; 281 282 /* allocate 4k Page of Local Frame Buffer memory for ring */ 283 ring->ring_size = 0x1000; 284 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 285 AMDGPU_GEM_DOMAIN_VRAM, 286 &adev->firmware.rbuf, 287 &ring->ring_mem_mc_addr, 288 (void **)&ring->ring_mem); 289 if (ret) { 290 ring->ring_size = 0; 291 return ret; 292 } 293 294 return 0; 295 } 296 297 static int psp_v3_1_ring_create(struct psp_context *psp, 298 enum psp_ring_type ring_type) 299 { 300 int ret = 0; 301 unsigned int psp_ring_reg = 0; 302 struct psp_ring *ring = &psp->km_ring; 303 struct amdgpu_device *adev = psp->adev; 304 305 /* Write low address of the ring to C2PMSG_69 */ 306 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 307 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg); 308 /* Write high address of the ring to C2PMSG_70 */ 309 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 310 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg); 311 /* Write size of ring to C2PMSG_71 */ 312 psp_ring_reg = ring->ring_size; 313 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg); 314 /* Write the ring initialization command to C2PMSG_64 */ 315 psp_ring_reg = ring_type; 316 psp_ring_reg = psp_ring_reg << 16; 317 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); 318 319 /* there might be handshake issue with hardware which needs delay */ 320 mdelay(20); 321 322 /* Wait for response flag (bit 31) in C2PMSG_64 */ 323 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 324 0x80000000, 0x8000FFFF, false); 325 326 return ret; 327 } 328 329 static int psp_v3_1_ring_stop(struct psp_context *psp, 330 enum psp_ring_type ring_type) 331 { 332 int ret = 0; 333 struct psp_ring *ring; 334 unsigned int psp_ring_reg = 0; 335 struct amdgpu_device *adev = psp->adev; 336 337 ring = &psp->km_ring; 338 339 /* Write the ring destroy command to C2PMSG_64 */ 340 psp_ring_reg = 3 << 16; 341 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); 342 343 /* there might be handshake issue with hardware which needs delay */ 344 mdelay(20); 345 346 /* Wait for response flag (bit 31) in C2PMSG_64 */ 347 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 348 0x80000000, 0x80000000, false); 349 350 return ret; 351 } 352 353 static int psp_v3_1_ring_destroy(struct psp_context *psp, 354 enum psp_ring_type ring_type) 355 { 356 int ret = 0; 357 struct psp_ring *ring = &psp->km_ring; 358 struct amdgpu_device *adev = psp->adev; 359 360 ret = psp_v3_1_ring_stop(psp, ring_type); 361 if (ret) 362 DRM_ERROR("Fail to stop psp ring\n"); 363 364 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 365 &ring->ring_mem_mc_addr, 366 (void **)&ring->ring_mem); 367 368 return ret; 369 } 370 371 static int psp_v3_1_cmd_submit(struct psp_context *psp, 372 struct amdgpu_firmware_info *ucode, 373 uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr, 374 int index) 375 { 376 unsigned int psp_write_ptr_reg = 0; 377 struct psp_gfx_rb_frame * write_frame = psp->km_ring.ring_mem; 378 struct psp_ring *ring = &psp->km_ring; 379 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 380 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 381 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 382 struct amdgpu_device *adev = psp->adev; 383 uint32_t ring_size_dw = ring->ring_size / 4; 384 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 385 386 /* KM (GPCOM) prepare write pointer */ 387 psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67); 388 389 /* Update KM RB frame pointer to new frame */ 390 /* write_frame ptr increments by size of rb_frame in bytes */ 391 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 392 if ((psp_write_ptr_reg % ring_size_dw) == 0) 393 write_frame = ring_buffer_start; 394 else 395 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 396 /* Check invalid write_frame ptr address */ 397 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 398 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 399 ring_buffer_start, ring_buffer_end, write_frame); 400 DRM_ERROR("write_frame is pointing to address out of bounds\n"); 401 return -EINVAL; 402 } 403 404 /* Initialize KM RB frame */ 405 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 406 407 /* Update KM RB frame */ 408 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 409 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 410 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 411 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 412 write_frame->fence_value = index; 413 414 /* Update the write Pointer in DWORDs */ 415 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 416 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg); 417 418 return 0; 419 } 420 421 static int 422 psp_v3_1_sram_map(struct amdgpu_device *adev, 423 unsigned int *sram_offset, unsigned int *sram_addr_reg_offset, 424 unsigned int *sram_data_reg_offset, 425 enum AMDGPU_UCODE_ID ucode_id) 426 { 427 int ret = 0; 428 429 switch(ucode_id) { 430 /* TODO: needs to confirm */ 431 #if 0 432 case AMDGPU_UCODE_ID_SMC: 433 *sram_offset = 0; 434 *sram_addr_reg_offset = 0; 435 *sram_data_reg_offset = 0; 436 break; 437 #endif 438 439 case AMDGPU_UCODE_ID_CP_CE: 440 *sram_offset = 0x0; 441 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR); 442 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA); 443 break; 444 445 case AMDGPU_UCODE_ID_CP_PFP: 446 *sram_offset = 0x0; 447 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR); 448 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA); 449 break; 450 451 case AMDGPU_UCODE_ID_CP_ME: 452 *sram_offset = 0x0; 453 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR); 454 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA); 455 break; 456 457 case AMDGPU_UCODE_ID_CP_MEC1: 458 *sram_offset = 0x10000; 459 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR); 460 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA); 461 break; 462 463 case AMDGPU_UCODE_ID_CP_MEC2: 464 *sram_offset = 0x10000; 465 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR); 466 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA); 467 break; 468 469 case AMDGPU_UCODE_ID_RLC_G: 470 *sram_offset = 0x2000; 471 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR); 472 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA); 473 break; 474 475 case AMDGPU_UCODE_ID_SDMA0: 476 *sram_offset = 0x0; 477 *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR); 478 *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA); 479 break; 480 481 /* TODO: needs to confirm */ 482 #if 0 483 case AMDGPU_UCODE_ID_SDMA1: 484 *sram_offset = ; 485 *sram_addr_reg_offset = ; 486 break; 487 488 case AMDGPU_UCODE_ID_UVD: 489 *sram_offset = ; 490 *sram_addr_reg_offset = ; 491 break; 492 493 case AMDGPU_UCODE_ID_VCE: 494 *sram_offset = ; 495 *sram_addr_reg_offset = ; 496 break; 497 #endif 498 499 case AMDGPU_UCODE_ID_MAXIMUM: 500 default: 501 ret = -EINVAL; 502 break; 503 } 504 505 return ret; 506 } 507 508 static bool psp_v3_1_compare_sram_data(struct psp_context *psp, 509 struct amdgpu_firmware_info *ucode, 510 enum AMDGPU_UCODE_ID ucode_type) 511 { 512 int err = 0; 513 unsigned int fw_sram_reg_val = 0; 514 unsigned int fw_sram_addr_reg_offset = 0; 515 unsigned int fw_sram_data_reg_offset = 0; 516 unsigned int ucode_size; 517 uint32_t *ucode_mem = NULL; 518 struct amdgpu_device *adev = psp->adev; 519 520 err = psp_v3_1_sram_map(adev, &fw_sram_reg_val, &fw_sram_addr_reg_offset, 521 &fw_sram_data_reg_offset, ucode_type); 522 if (err) 523 return false; 524 525 WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val); 526 527 ucode_size = ucode->ucode_size; 528 ucode_mem = (uint32_t *)ucode->kaddr; 529 while (ucode_size) { 530 fw_sram_reg_val = RREG32(fw_sram_data_reg_offset); 531 532 if (*ucode_mem != fw_sram_reg_val) 533 return false; 534 535 ucode_mem++; 536 /* 4 bytes */ 537 ucode_size -= 4; 538 } 539 540 return true; 541 } 542 543 static bool psp_v3_1_smu_reload_quirk(struct psp_context *psp) 544 { 545 struct amdgpu_device *adev = psp->adev; 546 uint32_t reg; 547 548 reg = smnMP1_FIRMWARE_FLAGS | 0x03b00000; 549 WREG32_SOC15(NBIO, 0, mmPCIE_INDEX2, reg); 550 reg = RREG32_SOC15(NBIO, 0, mmPCIE_DATA2); 551 return (reg & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) ? true : false; 552 } 553 554 static int psp_v3_1_mode1_reset(struct psp_context *psp) 555 { 556 int ret; 557 uint32_t offset; 558 struct amdgpu_device *adev = psp->adev; 559 560 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64); 561 562 ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false); 563 564 if (ret) { 565 DRM_INFO("psp is not working correctly before mode1 reset!\n"); 566 return -EINVAL; 567 } 568 569 /*send the mode 1 reset command*/ 570 WREG32(offset, 0x70000); 571 572 mdelay(1000); 573 574 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33); 575 576 ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false); 577 578 if (ret) { 579 DRM_INFO("psp mode 1 reset failed!\n"); 580 return -EINVAL; 581 } 582 583 DRM_INFO("psp mode1 reset succeed \n"); 584 585 return 0; 586 } 587 588 static const struct psp_funcs psp_v3_1_funcs = { 589 .init_microcode = psp_v3_1_init_microcode, 590 .bootloader_load_sysdrv = psp_v3_1_bootloader_load_sysdrv, 591 .bootloader_load_sos = psp_v3_1_bootloader_load_sos, 592 .prep_cmd_buf = psp_v3_1_prep_cmd_buf, 593 .ring_init = psp_v3_1_ring_init, 594 .ring_create = psp_v3_1_ring_create, 595 .ring_stop = psp_v3_1_ring_stop, 596 .ring_destroy = psp_v3_1_ring_destroy, 597 .cmd_submit = psp_v3_1_cmd_submit, 598 .compare_sram_data = psp_v3_1_compare_sram_data, 599 .smu_reload_quirk = psp_v3_1_smu_reload_quirk, 600 .mode1_reset = psp_v3_1_mode1_reset, 601 }; 602 603 void psp_v3_1_set_psp_funcs(struct psp_context *psp) 604 { 605 psp->funcs = &psp_v3_1_funcs; 606 } 607