1 /* 2 * Copyright (c) 2016-2017 Hisilicon Limited. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 */ 9 10 #include <linux/acpi.h> 11 #include <linux/device.h> 12 #include <linux/etherdevice.h> 13 #include <linux/init.h> 14 #include <linux/interrupt.h> 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/netdevice.h> 18 #include <linux/pci.h> 19 #include <linux/platform_device.h> 20 #include <linux/if_vlan.h> 21 #include <net/rtnetlink.h> 22 #include "hclge_cmd.h" 23 #include "hclge_dcb.h" 24 #include "hclge_main.h" 25 #include "hclge_mbx.h" 26 #include "hclge_mdio.h" 27 #include "hclge_tm.h" 28 #include "hnae3.h" 29 30 #define HCLGE_NAME "hclge" 31 #define HCLGE_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset)))) 32 #define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f)) 33 #define HCLGE_64BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_64_bit_stats, f)) 34 #define HCLGE_32BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_32_bit_stats, f)) 35 36 static int hclge_set_mta_filter_mode(struct hclge_dev *hdev, 37 enum hclge_mta_dmac_sel_type mta_mac_sel, 38 bool enable); 39 static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu); 40 static int hclge_init_vlan_config(struct hclge_dev *hdev); 41 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev); 42 static int hclge_update_led_status(struct hclge_dev *hdev); 43 44 static struct hnae3_ae_algo ae_algo; 45 46 static const struct pci_device_id ae_algo_pci_tbl[] = { 47 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0}, 48 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0}, 49 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0}, 50 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0}, 51 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0}, 52 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0}, 53 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0}, 54 /* required last entry */ 55 {0, } 56 }; 57 58 static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = { 59 "Mac Loopback test", 60 "Serdes Loopback test", 61 "Phy Loopback test" 62 }; 63 64 static const struct hclge_comm_stats_str g_all_64bit_stats_string[] = { 65 {"igu_rx_oversize_pkt", 66 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_oversize_pkt)}, 67 {"igu_rx_undersize_pkt", 68 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_undersize_pkt)}, 69 {"igu_rx_out_all_pkt", 70 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_out_all_pkt)}, 71 {"igu_rx_uni_pkt", 72 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_uni_pkt)}, 73 {"igu_rx_multi_pkt", 74 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_multi_pkt)}, 75 {"igu_rx_broad_pkt", 76 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_broad_pkt)}, 77 {"egu_tx_out_all_pkt", 78 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_out_all_pkt)}, 79 {"egu_tx_uni_pkt", 80 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_uni_pkt)}, 81 {"egu_tx_multi_pkt", 82 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_multi_pkt)}, 83 {"egu_tx_broad_pkt", 84 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_broad_pkt)}, 85 {"ssu_ppp_mac_key_num", 86 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_mac_key_num)}, 87 {"ssu_ppp_host_key_num", 88 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_host_key_num)}, 89 {"ppp_ssu_mac_rlt_num", 90 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_mac_rlt_num)}, 91 {"ppp_ssu_host_rlt_num", 92 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_host_rlt_num)}, 93 {"ssu_tx_in_num", 94 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_in_num)}, 95 {"ssu_tx_out_num", 96 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_out_num)}, 97 {"ssu_rx_in_num", 98 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_in_num)}, 99 {"ssu_rx_out_num", 100 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_out_num)} 101 }; 102 103 static const struct hclge_comm_stats_str g_all_32bit_stats_string[] = { 104 {"igu_rx_err_pkt", 105 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_err_pkt)}, 106 {"igu_rx_no_eof_pkt", 107 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_eof_pkt)}, 108 {"igu_rx_no_sof_pkt", 109 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_sof_pkt)}, 110 {"egu_tx_1588_pkt", 111 HCLGE_32BIT_STATS_FIELD_OFF(egu_tx_1588_pkt)}, 112 {"ssu_full_drop_num", 113 HCLGE_32BIT_STATS_FIELD_OFF(ssu_full_drop_num)}, 114 {"ssu_part_drop_num", 115 HCLGE_32BIT_STATS_FIELD_OFF(ssu_part_drop_num)}, 116 {"ppp_key_drop_num", 117 HCLGE_32BIT_STATS_FIELD_OFF(ppp_key_drop_num)}, 118 {"ppp_rlt_drop_num", 119 HCLGE_32BIT_STATS_FIELD_OFF(ppp_rlt_drop_num)}, 120 {"ssu_key_drop_num", 121 HCLGE_32BIT_STATS_FIELD_OFF(ssu_key_drop_num)}, 122 {"pkt_curr_buf_cnt", 123 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_cnt)}, 124 {"qcn_fb_rcv_cnt", 125 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_rcv_cnt)}, 126 {"qcn_fb_drop_cnt", 127 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_drop_cnt)}, 128 {"qcn_fb_invaild_cnt", 129 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_invaild_cnt)}, 130 {"rx_packet_tc0_in_cnt", 131 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_in_cnt)}, 132 {"rx_packet_tc1_in_cnt", 133 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_in_cnt)}, 134 {"rx_packet_tc2_in_cnt", 135 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_in_cnt)}, 136 {"rx_packet_tc3_in_cnt", 137 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_in_cnt)}, 138 {"rx_packet_tc4_in_cnt", 139 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_in_cnt)}, 140 {"rx_packet_tc5_in_cnt", 141 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_in_cnt)}, 142 {"rx_packet_tc6_in_cnt", 143 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_in_cnt)}, 144 {"rx_packet_tc7_in_cnt", 145 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_in_cnt)}, 146 {"rx_packet_tc0_out_cnt", 147 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_out_cnt)}, 148 {"rx_packet_tc1_out_cnt", 149 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_out_cnt)}, 150 {"rx_packet_tc2_out_cnt", 151 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_out_cnt)}, 152 {"rx_packet_tc3_out_cnt", 153 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_out_cnt)}, 154 {"rx_packet_tc4_out_cnt", 155 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_out_cnt)}, 156 {"rx_packet_tc5_out_cnt", 157 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_out_cnt)}, 158 {"rx_packet_tc6_out_cnt", 159 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_out_cnt)}, 160 {"rx_packet_tc7_out_cnt", 161 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_out_cnt)}, 162 {"tx_packet_tc0_in_cnt", 163 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_in_cnt)}, 164 {"tx_packet_tc1_in_cnt", 165 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_in_cnt)}, 166 {"tx_packet_tc2_in_cnt", 167 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_in_cnt)}, 168 {"tx_packet_tc3_in_cnt", 169 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_in_cnt)}, 170 {"tx_packet_tc4_in_cnt", 171 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_in_cnt)}, 172 {"tx_packet_tc5_in_cnt", 173 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_in_cnt)}, 174 {"tx_packet_tc6_in_cnt", 175 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_in_cnt)}, 176 {"tx_packet_tc7_in_cnt", 177 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_in_cnt)}, 178 {"tx_packet_tc0_out_cnt", 179 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_out_cnt)}, 180 {"tx_packet_tc1_out_cnt", 181 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_out_cnt)}, 182 {"tx_packet_tc2_out_cnt", 183 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_out_cnt)}, 184 {"tx_packet_tc3_out_cnt", 185 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_out_cnt)}, 186 {"tx_packet_tc4_out_cnt", 187 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_out_cnt)}, 188 {"tx_packet_tc5_out_cnt", 189 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_out_cnt)}, 190 {"tx_packet_tc6_out_cnt", 191 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_out_cnt)}, 192 {"tx_packet_tc7_out_cnt", 193 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_out_cnt)}, 194 {"pkt_curr_buf_tc0_cnt", 195 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc0_cnt)}, 196 {"pkt_curr_buf_tc1_cnt", 197 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc1_cnt)}, 198 {"pkt_curr_buf_tc2_cnt", 199 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc2_cnt)}, 200 {"pkt_curr_buf_tc3_cnt", 201 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc3_cnt)}, 202 {"pkt_curr_buf_tc4_cnt", 203 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc4_cnt)}, 204 {"pkt_curr_buf_tc5_cnt", 205 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc5_cnt)}, 206 {"pkt_curr_buf_tc6_cnt", 207 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc6_cnt)}, 208 {"pkt_curr_buf_tc7_cnt", 209 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc7_cnt)}, 210 {"mb_uncopy_num", 211 HCLGE_32BIT_STATS_FIELD_OFF(mb_uncopy_num)}, 212 {"lo_pri_unicast_rlt_drop_num", 213 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_unicast_rlt_drop_num)}, 214 {"hi_pri_multicast_rlt_drop_num", 215 HCLGE_32BIT_STATS_FIELD_OFF(hi_pri_multicast_rlt_drop_num)}, 216 {"lo_pri_multicast_rlt_drop_num", 217 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_multicast_rlt_drop_num)}, 218 {"rx_oq_drop_pkt_cnt", 219 HCLGE_32BIT_STATS_FIELD_OFF(rx_oq_drop_pkt_cnt)}, 220 {"tx_oq_drop_pkt_cnt", 221 HCLGE_32BIT_STATS_FIELD_OFF(tx_oq_drop_pkt_cnt)}, 222 {"nic_l2_err_drop_pkt_cnt", 223 HCLGE_32BIT_STATS_FIELD_OFF(nic_l2_err_drop_pkt_cnt)}, 224 {"roc_l2_err_drop_pkt_cnt", 225 HCLGE_32BIT_STATS_FIELD_OFF(roc_l2_err_drop_pkt_cnt)} 226 }; 227 228 static const struct hclge_comm_stats_str g_mac_stats_string[] = { 229 {"mac_tx_mac_pause_num", 230 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)}, 231 {"mac_rx_mac_pause_num", 232 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)}, 233 {"mac_tx_pfc_pri0_pkt_num", 234 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)}, 235 {"mac_tx_pfc_pri1_pkt_num", 236 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)}, 237 {"mac_tx_pfc_pri2_pkt_num", 238 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)}, 239 {"mac_tx_pfc_pri3_pkt_num", 240 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)}, 241 {"mac_tx_pfc_pri4_pkt_num", 242 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)}, 243 {"mac_tx_pfc_pri5_pkt_num", 244 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)}, 245 {"mac_tx_pfc_pri6_pkt_num", 246 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)}, 247 {"mac_tx_pfc_pri7_pkt_num", 248 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)}, 249 {"mac_rx_pfc_pri0_pkt_num", 250 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)}, 251 {"mac_rx_pfc_pri1_pkt_num", 252 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)}, 253 {"mac_rx_pfc_pri2_pkt_num", 254 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)}, 255 {"mac_rx_pfc_pri3_pkt_num", 256 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)}, 257 {"mac_rx_pfc_pri4_pkt_num", 258 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)}, 259 {"mac_rx_pfc_pri5_pkt_num", 260 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)}, 261 {"mac_rx_pfc_pri6_pkt_num", 262 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)}, 263 {"mac_rx_pfc_pri7_pkt_num", 264 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)}, 265 {"mac_tx_total_pkt_num", 266 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)}, 267 {"mac_tx_total_oct_num", 268 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)}, 269 {"mac_tx_good_pkt_num", 270 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)}, 271 {"mac_tx_bad_pkt_num", 272 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)}, 273 {"mac_tx_good_oct_num", 274 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)}, 275 {"mac_tx_bad_oct_num", 276 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)}, 277 {"mac_tx_uni_pkt_num", 278 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)}, 279 {"mac_tx_multi_pkt_num", 280 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)}, 281 {"mac_tx_broad_pkt_num", 282 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)}, 283 {"mac_tx_undersize_pkt_num", 284 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)}, 285 {"mac_tx_oversize_pkt_num", 286 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num)}, 287 {"mac_tx_64_oct_pkt_num", 288 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)}, 289 {"mac_tx_65_127_oct_pkt_num", 290 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)}, 291 {"mac_tx_128_255_oct_pkt_num", 292 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)}, 293 {"mac_tx_256_511_oct_pkt_num", 294 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)}, 295 {"mac_tx_512_1023_oct_pkt_num", 296 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)}, 297 {"mac_tx_1024_1518_oct_pkt_num", 298 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)}, 299 {"mac_tx_1519_2047_oct_pkt_num", 300 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_2047_oct_pkt_num)}, 301 {"mac_tx_2048_4095_oct_pkt_num", 302 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_2048_4095_oct_pkt_num)}, 303 {"mac_tx_4096_8191_oct_pkt_num", 304 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_4096_8191_oct_pkt_num)}, 305 {"mac_tx_8192_12287_oct_pkt_num", 306 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_12287_oct_pkt_num)}, 307 {"mac_tx_8192_9216_oct_pkt_num", 308 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_9216_oct_pkt_num)}, 309 {"mac_tx_9217_12287_oct_pkt_num", 310 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_9217_12287_oct_pkt_num)}, 311 {"mac_tx_12288_16383_oct_pkt_num", 312 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_12288_16383_oct_pkt_num)}, 313 {"mac_tx_1519_max_good_pkt_num", 314 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_good_oct_pkt_num)}, 315 {"mac_tx_1519_max_bad_pkt_num", 316 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_bad_oct_pkt_num)}, 317 {"mac_rx_total_pkt_num", 318 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)}, 319 {"mac_rx_total_oct_num", 320 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)}, 321 {"mac_rx_good_pkt_num", 322 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)}, 323 {"mac_rx_bad_pkt_num", 324 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)}, 325 {"mac_rx_good_oct_num", 326 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)}, 327 {"mac_rx_bad_oct_num", 328 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)}, 329 {"mac_rx_uni_pkt_num", 330 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)}, 331 {"mac_rx_multi_pkt_num", 332 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)}, 333 {"mac_rx_broad_pkt_num", 334 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)}, 335 {"mac_rx_undersize_pkt_num", 336 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)}, 337 {"mac_rx_oversize_pkt_num", 338 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num)}, 339 {"mac_rx_64_oct_pkt_num", 340 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)}, 341 {"mac_rx_65_127_oct_pkt_num", 342 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)}, 343 {"mac_rx_128_255_oct_pkt_num", 344 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)}, 345 {"mac_rx_256_511_oct_pkt_num", 346 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)}, 347 {"mac_rx_512_1023_oct_pkt_num", 348 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)}, 349 {"mac_rx_1024_1518_oct_pkt_num", 350 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)}, 351 {"mac_rx_1519_2047_oct_pkt_num", 352 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_2047_oct_pkt_num)}, 353 {"mac_rx_2048_4095_oct_pkt_num", 354 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_2048_4095_oct_pkt_num)}, 355 {"mac_rx_4096_8191_oct_pkt_num", 356 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_4096_8191_oct_pkt_num)}, 357 {"mac_rx_8192_12287_oct_pkt_num", 358 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_12287_oct_pkt_num)}, 359 {"mac_rx_8192_9216_oct_pkt_num", 360 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_9216_oct_pkt_num)}, 361 {"mac_rx_9217_12287_oct_pkt_num", 362 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_9217_12287_oct_pkt_num)}, 363 {"mac_rx_12288_16383_oct_pkt_num", 364 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_12288_16383_oct_pkt_num)}, 365 {"mac_rx_1519_max_good_pkt_num", 366 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_good_oct_pkt_num)}, 367 {"mac_rx_1519_max_bad_pkt_num", 368 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_bad_oct_pkt_num)}, 369 370 {"mac_tx_fragment_pkt_num", 371 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num)}, 372 {"mac_tx_undermin_pkt_num", 373 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num)}, 374 {"mac_tx_jabber_pkt_num", 375 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num)}, 376 {"mac_tx_err_all_pkt_num", 377 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num)}, 378 {"mac_tx_from_app_good_pkt_num", 379 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num)}, 380 {"mac_tx_from_app_bad_pkt_num", 381 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num)}, 382 {"mac_rx_fragment_pkt_num", 383 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num)}, 384 {"mac_rx_undermin_pkt_num", 385 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num)}, 386 {"mac_rx_jabber_pkt_num", 387 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num)}, 388 {"mac_rx_fcs_err_pkt_num", 389 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num)}, 390 {"mac_rx_send_app_good_pkt_num", 391 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num)}, 392 {"mac_rx_send_app_bad_pkt_num", 393 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num)} 394 }; 395 396 static const struct hclge_mac_mgr_tbl_entry_cmd hclge_mgr_table[] = { 397 { 398 .flags = HCLGE_MAC_MGR_MASK_VLAN_B, 399 .ethter_type = cpu_to_le16(HCLGE_MAC_ETHERTYPE_LLDP), 400 .mac_addr_hi32 = cpu_to_le32(htonl(0x0180C200)), 401 .mac_addr_lo16 = cpu_to_le16(htons(0x000E)), 402 .i_port_bitmap = 0x1, 403 }, 404 }; 405 406 static int hclge_64_bit_update_stats(struct hclge_dev *hdev) 407 { 408 #define HCLGE_64_BIT_CMD_NUM 5 409 #define HCLGE_64_BIT_RTN_DATANUM 4 410 u64 *data = (u64 *)(&hdev->hw_stats.all_64_bit_stats); 411 struct hclge_desc desc[HCLGE_64_BIT_CMD_NUM]; 412 __le64 *desc_data; 413 int i, k, n; 414 int ret; 415 416 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_64_BIT, true); 417 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_64_BIT_CMD_NUM); 418 if (ret) { 419 dev_err(&hdev->pdev->dev, 420 "Get 64 bit pkt stats fail, status = %d.\n", ret); 421 return ret; 422 } 423 424 for (i = 0; i < HCLGE_64_BIT_CMD_NUM; i++) { 425 if (unlikely(i == 0)) { 426 desc_data = (__le64 *)(&desc[i].data[0]); 427 n = HCLGE_64_BIT_RTN_DATANUM - 1; 428 } else { 429 desc_data = (__le64 *)(&desc[i]); 430 n = HCLGE_64_BIT_RTN_DATANUM; 431 } 432 for (k = 0; k < n; k++) { 433 *data++ += le64_to_cpu(*desc_data); 434 desc_data++; 435 } 436 } 437 438 return 0; 439 } 440 441 static void hclge_reset_partial_32bit_counter(struct hclge_32_bit_stats *stats) 442 { 443 stats->pkt_curr_buf_cnt = 0; 444 stats->pkt_curr_buf_tc0_cnt = 0; 445 stats->pkt_curr_buf_tc1_cnt = 0; 446 stats->pkt_curr_buf_tc2_cnt = 0; 447 stats->pkt_curr_buf_tc3_cnt = 0; 448 stats->pkt_curr_buf_tc4_cnt = 0; 449 stats->pkt_curr_buf_tc5_cnt = 0; 450 stats->pkt_curr_buf_tc6_cnt = 0; 451 stats->pkt_curr_buf_tc7_cnt = 0; 452 } 453 454 static int hclge_32_bit_update_stats(struct hclge_dev *hdev) 455 { 456 #define HCLGE_32_BIT_CMD_NUM 8 457 #define HCLGE_32_BIT_RTN_DATANUM 8 458 459 struct hclge_desc desc[HCLGE_32_BIT_CMD_NUM]; 460 struct hclge_32_bit_stats *all_32_bit_stats; 461 __le32 *desc_data; 462 int i, k, n; 463 u64 *data; 464 int ret; 465 466 all_32_bit_stats = &hdev->hw_stats.all_32_bit_stats; 467 data = (u64 *)(&all_32_bit_stats->egu_tx_1588_pkt); 468 469 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_32_BIT, true); 470 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_32_BIT_CMD_NUM); 471 if (ret) { 472 dev_err(&hdev->pdev->dev, 473 "Get 32 bit pkt stats fail, status = %d.\n", ret); 474 475 return ret; 476 } 477 478 hclge_reset_partial_32bit_counter(all_32_bit_stats); 479 for (i = 0; i < HCLGE_32_BIT_CMD_NUM; i++) { 480 if (unlikely(i == 0)) { 481 __le16 *desc_data_16bit; 482 483 all_32_bit_stats->igu_rx_err_pkt += 484 le32_to_cpu(desc[i].data[0]); 485 486 desc_data_16bit = (__le16 *)&desc[i].data[1]; 487 all_32_bit_stats->igu_rx_no_eof_pkt += 488 le16_to_cpu(*desc_data_16bit); 489 490 desc_data_16bit++; 491 all_32_bit_stats->igu_rx_no_sof_pkt += 492 le16_to_cpu(*desc_data_16bit); 493 494 desc_data = &desc[i].data[2]; 495 n = HCLGE_32_BIT_RTN_DATANUM - 4; 496 } else { 497 desc_data = (__le32 *)&desc[i]; 498 n = HCLGE_32_BIT_RTN_DATANUM; 499 } 500 for (k = 0; k < n; k++) { 501 *data++ += le32_to_cpu(*desc_data); 502 desc_data++; 503 } 504 } 505 506 return 0; 507 } 508 509 static int hclge_mac_get_traffic_stats(struct hclge_dev *hdev) 510 { 511 struct hclge_mac_stats *mac_stats = &hdev->hw_stats.mac_stats; 512 struct hclge_desc desc; 513 __le64 *desc_data; 514 int ret; 515 516 /* for fiber port, need to query the total rx/tx packets statstics, 517 * used for data transferring checking. 518 */ 519 if (hdev->hw.mac.media_type != HNAE3_MEDIA_TYPE_FIBER) 520 return 0; 521 522 if (test_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state)) 523 return 0; 524 525 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_STATS_MAC_TRAFFIC, true); 526 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 527 if (ret) { 528 dev_err(&hdev->pdev->dev, 529 "Get MAC total pkt stats fail, ret = %d\n", ret); 530 531 return ret; 532 } 533 534 desc_data = (__le64 *)(&desc.data[0]); 535 mac_stats->mac_tx_total_pkt_num += le64_to_cpu(*desc_data++); 536 mac_stats->mac_rx_total_pkt_num += le64_to_cpu(*desc_data); 537 538 return 0; 539 } 540 541 static int hclge_mac_update_stats(struct hclge_dev *hdev) 542 { 543 #define HCLGE_MAC_CMD_NUM 21 544 #define HCLGE_RTN_DATA_NUM 4 545 546 u64 *data = (u64 *)(&hdev->hw_stats.mac_stats); 547 struct hclge_desc desc[HCLGE_MAC_CMD_NUM]; 548 __le64 *desc_data; 549 int i, k, n; 550 int ret; 551 552 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true); 553 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM); 554 if (ret) { 555 dev_err(&hdev->pdev->dev, 556 "Get MAC pkt stats fail, status = %d.\n", ret); 557 558 return ret; 559 } 560 561 for (i = 0; i < HCLGE_MAC_CMD_NUM; i++) { 562 if (unlikely(i == 0)) { 563 desc_data = (__le64 *)(&desc[i].data[0]); 564 n = HCLGE_RTN_DATA_NUM - 2; 565 } else { 566 desc_data = (__le64 *)(&desc[i]); 567 n = HCLGE_RTN_DATA_NUM; 568 } 569 for (k = 0; k < n; k++) { 570 *data++ += le64_to_cpu(*desc_data); 571 desc_data++; 572 } 573 } 574 575 return 0; 576 } 577 578 static int hclge_tqps_update_stats(struct hnae3_handle *handle) 579 { 580 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 581 struct hclge_vport *vport = hclge_get_vport(handle); 582 struct hclge_dev *hdev = vport->back; 583 struct hnae3_queue *queue; 584 struct hclge_desc desc[1]; 585 struct hclge_tqp *tqp; 586 int ret, i; 587 588 for (i = 0; i < kinfo->num_tqps; i++) { 589 queue = handle->kinfo.tqp[i]; 590 tqp = container_of(queue, struct hclge_tqp, q); 591 /* command : HCLGE_OPC_QUERY_IGU_STAT */ 592 hclge_cmd_setup_basic_desc(&desc[0], 593 HCLGE_OPC_QUERY_RX_STATUS, 594 true); 595 596 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff)); 597 ret = hclge_cmd_send(&hdev->hw, desc, 1); 598 if (ret) { 599 dev_err(&hdev->pdev->dev, 600 "Query tqp stat fail, status = %d,queue = %d\n", 601 ret, i); 602 return ret; 603 } 604 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd += 605 le32_to_cpu(desc[0].data[1]); 606 } 607 608 for (i = 0; i < kinfo->num_tqps; i++) { 609 queue = handle->kinfo.tqp[i]; 610 tqp = container_of(queue, struct hclge_tqp, q); 611 /* command : HCLGE_OPC_QUERY_IGU_STAT */ 612 hclge_cmd_setup_basic_desc(&desc[0], 613 HCLGE_OPC_QUERY_TX_STATUS, 614 true); 615 616 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff)); 617 ret = hclge_cmd_send(&hdev->hw, desc, 1); 618 if (ret) { 619 dev_err(&hdev->pdev->dev, 620 "Query tqp stat fail, status = %d,queue = %d\n", 621 ret, i); 622 return ret; 623 } 624 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd += 625 le32_to_cpu(desc[0].data[1]); 626 } 627 628 return 0; 629 } 630 631 static u64 *hclge_tqps_get_stats(struct hnae3_handle *handle, u64 *data) 632 { 633 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 634 struct hclge_tqp *tqp; 635 u64 *buff = data; 636 int i; 637 638 for (i = 0; i < kinfo->num_tqps; i++) { 639 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q); 640 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd; 641 } 642 643 for (i = 0; i < kinfo->num_tqps; i++) { 644 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q); 645 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd; 646 } 647 648 return buff; 649 } 650 651 static int hclge_tqps_get_sset_count(struct hnae3_handle *handle, int stringset) 652 { 653 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 654 655 return kinfo->num_tqps * (2); 656 } 657 658 static u8 *hclge_tqps_get_strings(struct hnae3_handle *handle, u8 *data) 659 { 660 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 661 u8 *buff = data; 662 int i = 0; 663 664 for (i = 0; i < kinfo->num_tqps; i++) { 665 struct hclge_tqp *tqp = container_of(handle->kinfo.tqp[i], 666 struct hclge_tqp, q); 667 snprintf(buff, ETH_GSTRING_LEN, "txq#%d_pktnum_rcd", 668 tqp->index); 669 buff = buff + ETH_GSTRING_LEN; 670 } 671 672 for (i = 0; i < kinfo->num_tqps; i++) { 673 struct hclge_tqp *tqp = container_of(kinfo->tqp[i], 674 struct hclge_tqp, q); 675 snprintf(buff, ETH_GSTRING_LEN, "rxq#%d_pktnum_rcd", 676 tqp->index); 677 buff = buff + ETH_GSTRING_LEN; 678 } 679 680 return buff; 681 } 682 683 static u64 *hclge_comm_get_stats(void *comm_stats, 684 const struct hclge_comm_stats_str strs[], 685 int size, u64 *data) 686 { 687 u64 *buf = data; 688 u32 i; 689 690 for (i = 0; i < size; i++) 691 buf[i] = HCLGE_STATS_READ(comm_stats, strs[i].offset); 692 693 return buf + size; 694 } 695 696 static u8 *hclge_comm_get_strings(u32 stringset, 697 const struct hclge_comm_stats_str strs[], 698 int size, u8 *data) 699 { 700 char *buff = (char *)data; 701 u32 i; 702 703 if (stringset != ETH_SS_STATS) 704 return buff; 705 706 for (i = 0; i < size; i++) { 707 snprintf(buff, ETH_GSTRING_LEN, 708 strs[i].desc); 709 buff = buff + ETH_GSTRING_LEN; 710 } 711 712 return (u8 *)buff; 713 } 714 715 static void hclge_update_netstat(struct hclge_hw_stats *hw_stats, 716 struct net_device_stats *net_stats) 717 { 718 net_stats->tx_dropped = 0; 719 net_stats->rx_dropped = hw_stats->all_32_bit_stats.ssu_full_drop_num; 720 net_stats->rx_dropped += hw_stats->all_32_bit_stats.ppp_key_drop_num; 721 net_stats->rx_dropped += hw_stats->all_32_bit_stats.ssu_key_drop_num; 722 723 net_stats->rx_errors = hw_stats->mac_stats.mac_rx_oversize_pkt_num; 724 net_stats->rx_errors += hw_stats->mac_stats.mac_rx_undersize_pkt_num; 725 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_eof_pkt; 726 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_sof_pkt; 727 net_stats->rx_errors += hw_stats->mac_stats.mac_rx_fcs_err_pkt_num; 728 729 net_stats->multicast = hw_stats->mac_stats.mac_tx_multi_pkt_num; 730 net_stats->multicast += hw_stats->mac_stats.mac_rx_multi_pkt_num; 731 732 net_stats->rx_crc_errors = hw_stats->mac_stats.mac_rx_fcs_err_pkt_num; 733 net_stats->rx_length_errors = 734 hw_stats->mac_stats.mac_rx_undersize_pkt_num; 735 net_stats->rx_length_errors += 736 hw_stats->mac_stats.mac_rx_oversize_pkt_num; 737 net_stats->rx_over_errors = 738 hw_stats->mac_stats.mac_rx_oversize_pkt_num; 739 } 740 741 static void hclge_update_stats_for_all(struct hclge_dev *hdev) 742 { 743 struct hnae3_handle *handle; 744 int status; 745 746 handle = &hdev->vport[0].nic; 747 if (handle->client) { 748 status = hclge_tqps_update_stats(handle); 749 if (status) { 750 dev_err(&hdev->pdev->dev, 751 "Update TQPS stats fail, status = %d.\n", 752 status); 753 } 754 } 755 756 status = hclge_mac_update_stats(hdev); 757 if (status) 758 dev_err(&hdev->pdev->dev, 759 "Update MAC stats fail, status = %d.\n", status); 760 761 status = hclge_32_bit_update_stats(hdev); 762 if (status) 763 dev_err(&hdev->pdev->dev, 764 "Update 32 bit stats fail, status = %d.\n", 765 status); 766 767 hclge_update_netstat(&hdev->hw_stats, &handle->kinfo.netdev->stats); 768 } 769 770 static void hclge_update_stats(struct hnae3_handle *handle, 771 struct net_device_stats *net_stats) 772 { 773 struct hclge_vport *vport = hclge_get_vport(handle); 774 struct hclge_dev *hdev = vport->back; 775 struct hclge_hw_stats *hw_stats = &hdev->hw_stats; 776 int status; 777 778 if (test_and_set_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state)) 779 return; 780 781 status = hclge_mac_update_stats(hdev); 782 if (status) 783 dev_err(&hdev->pdev->dev, 784 "Update MAC stats fail, status = %d.\n", 785 status); 786 787 status = hclge_32_bit_update_stats(hdev); 788 if (status) 789 dev_err(&hdev->pdev->dev, 790 "Update 32 bit stats fail, status = %d.\n", 791 status); 792 793 status = hclge_64_bit_update_stats(hdev); 794 if (status) 795 dev_err(&hdev->pdev->dev, 796 "Update 64 bit stats fail, status = %d.\n", 797 status); 798 799 status = hclge_tqps_update_stats(handle); 800 if (status) 801 dev_err(&hdev->pdev->dev, 802 "Update TQPS stats fail, status = %d.\n", 803 status); 804 805 hclge_update_netstat(hw_stats, net_stats); 806 807 clear_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state); 808 } 809 810 static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset) 811 { 812 #define HCLGE_LOOPBACK_TEST_FLAGS 0x7 813 814 struct hclge_vport *vport = hclge_get_vport(handle); 815 struct hclge_dev *hdev = vport->back; 816 int count = 0; 817 818 /* Loopback test support rules: 819 * mac: only GE mode support 820 * serdes: all mac mode will support include GE/XGE/LGE/CGE 821 * phy: only support when phy device exist on board 822 */ 823 if (stringset == ETH_SS_TEST) { 824 /* clear loopback bit flags at first */ 825 handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS)); 826 if (hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M || 827 hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M || 828 hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) { 829 count += 1; 830 handle->flags |= HNAE3_SUPPORT_MAC_LOOPBACK; 831 } else { 832 count = -EOPNOTSUPP; 833 } 834 } else if (stringset == ETH_SS_STATS) { 835 count = ARRAY_SIZE(g_mac_stats_string) + 836 ARRAY_SIZE(g_all_32bit_stats_string) + 837 ARRAY_SIZE(g_all_64bit_stats_string) + 838 hclge_tqps_get_sset_count(handle, stringset); 839 } 840 841 return count; 842 } 843 844 static void hclge_get_strings(struct hnae3_handle *handle, 845 u32 stringset, 846 u8 *data) 847 { 848 u8 *p = (char *)data; 849 int size; 850 851 if (stringset == ETH_SS_STATS) { 852 size = ARRAY_SIZE(g_mac_stats_string); 853 p = hclge_comm_get_strings(stringset, 854 g_mac_stats_string, 855 size, 856 p); 857 size = ARRAY_SIZE(g_all_32bit_stats_string); 858 p = hclge_comm_get_strings(stringset, 859 g_all_32bit_stats_string, 860 size, 861 p); 862 size = ARRAY_SIZE(g_all_64bit_stats_string); 863 p = hclge_comm_get_strings(stringset, 864 g_all_64bit_stats_string, 865 size, 866 p); 867 p = hclge_tqps_get_strings(handle, p); 868 } else if (stringset == ETH_SS_TEST) { 869 if (handle->flags & HNAE3_SUPPORT_MAC_LOOPBACK) { 870 memcpy(p, 871 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_MAC], 872 ETH_GSTRING_LEN); 873 p += ETH_GSTRING_LEN; 874 } 875 if (handle->flags & HNAE3_SUPPORT_SERDES_LOOPBACK) { 876 memcpy(p, 877 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_SERDES], 878 ETH_GSTRING_LEN); 879 p += ETH_GSTRING_LEN; 880 } 881 if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) { 882 memcpy(p, 883 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_PHY], 884 ETH_GSTRING_LEN); 885 p += ETH_GSTRING_LEN; 886 } 887 } 888 } 889 890 static void hclge_get_stats(struct hnae3_handle *handle, u64 *data) 891 { 892 struct hclge_vport *vport = hclge_get_vport(handle); 893 struct hclge_dev *hdev = vport->back; 894 u64 *p; 895 896 p = hclge_comm_get_stats(&hdev->hw_stats.mac_stats, 897 g_mac_stats_string, 898 ARRAY_SIZE(g_mac_stats_string), 899 data); 900 p = hclge_comm_get_stats(&hdev->hw_stats.all_32_bit_stats, 901 g_all_32bit_stats_string, 902 ARRAY_SIZE(g_all_32bit_stats_string), 903 p); 904 p = hclge_comm_get_stats(&hdev->hw_stats.all_64_bit_stats, 905 g_all_64bit_stats_string, 906 ARRAY_SIZE(g_all_64bit_stats_string), 907 p); 908 p = hclge_tqps_get_stats(handle, p); 909 } 910 911 static int hclge_parse_func_status(struct hclge_dev *hdev, 912 struct hclge_func_status_cmd *status) 913 { 914 if (!(status->pf_state & HCLGE_PF_STATE_DONE)) 915 return -EINVAL; 916 917 /* Set the pf to main pf */ 918 if (status->pf_state & HCLGE_PF_STATE_MAIN) 919 hdev->flag |= HCLGE_FLAG_MAIN; 920 else 921 hdev->flag &= ~HCLGE_FLAG_MAIN; 922 923 return 0; 924 } 925 926 static int hclge_query_function_status(struct hclge_dev *hdev) 927 { 928 struct hclge_func_status_cmd *req; 929 struct hclge_desc desc; 930 int timeout = 0; 931 int ret; 932 933 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true); 934 req = (struct hclge_func_status_cmd *)desc.data; 935 936 do { 937 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 938 if (ret) { 939 dev_err(&hdev->pdev->dev, 940 "query function status failed %d.\n", 941 ret); 942 943 return ret; 944 } 945 946 /* Check pf reset is done */ 947 if (req->pf_state) 948 break; 949 usleep_range(1000, 2000); 950 } while (timeout++ < 5); 951 952 ret = hclge_parse_func_status(hdev, req); 953 954 return ret; 955 } 956 957 static int hclge_query_pf_resource(struct hclge_dev *hdev) 958 { 959 struct hclge_pf_res_cmd *req; 960 struct hclge_desc desc; 961 int ret; 962 963 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true); 964 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 965 if (ret) { 966 dev_err(&hdev->pdev->dev, 967 "query pf resource failed %d.\n", ret); 968 return ret; 969 } 970 971 req = (struct hclge_pf_res_cmd *)desc.data; 972 hdev->num_tqps = __le16_to_cpu(req->tqp_num); 973 hdev->pkt_buf_size = __le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S; 974 975 if (hnae3_dev_roce_supported(hdev)) { 976 hdev->num_roce_msi = 977 hnae_get_field(__le16_to_cpu(req->pf_intr_vector_number), 978 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S); 979 980 /* PF should have NIC vectors and Roce vectors, 981 * NIC vectors are queued before Roce vectors. 982 */ 983 hdev->num_msi = hdev->num_roce_msi + HCLGE_ROCE_VECTOR_OFFSET; 984 } else { 985 hdev->num_msi = 986 hnae_get_field(__le16_to_cpu(req->pf_intr_vector_number), 987 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S); 988 } 989 990 return 0; 991 } 992 993 static int hclge_parse_speed(int speed_cmd, int *speed) 994 { 995 switch (speed_cmd) { 996 case 6: 997 *speed = HCLGE_MAC_SPEED_10M; 998 break; 999 case 7: 1000 *speed = HCLGE_MAC_SPEED_100M; 1001 break; 1002 case 0: 1003 *speed = HCLGE_MAC_SPEED_1G; 1004 break; 1005 case 1: 1006 *speed = HCLGE_MAC_SPEED_10G; 1007 break; 1008 case 2: 1009 *speed = HCLGE_MAC_SPEED_25G; 1010 break; 1011 case 3: 1012 *speed = HCLGE_MAC_SPEED_40G; 1013 break; 1014 case 4: 1015 *speed = HCLGE_MAC_SPEED_50G; 1016 break; 1017 case 5: 1018 *speed = HCLGE_MAC_SPEED_100G; 1019 break; 1020 default: 1021 return -EINVAL; 1022 } 1023 1024 return 0; 1025 } 1026 1027 static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc) 1028 { 1029 struct hclge_cfg_param_cmd *req; 1030 u64 mac_addr_tmp_high; 1031 u64 mac_addr_tmp; 1032 int i; 1033 1034 req = (struct hclge_cfg_param_cmd *)desc[0].data; 1035 1036 /* get the configuration */ 1037 cfg->vmdq_vport_num = hnae_get_field(__le32_to_cpu(req->param[0]), 1038 HCLGE_CFG_VMDQ_M, 1039 HCLGE_CFG_VMDQ_S); 1040 cfg->tc_num = hnae_get_field(__le32_to_cpu(req->param[0]), 1041 HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S); 1042 cfg->tqp_desc_num = hnae_get_field(__le32_to_cpu(req->param[0]), 1043 HCLGE_CFG_TQP_DESC_N_M, 1044 HCLGE_CFG_TQP_DESC_N_S); 1045 1046 cfg->phy_addr = hnae_get_field(__le32_to_cpu(req->param[1]), 1047 HCLGE_CFG_PHY_ADDR_M, 1048 HCLGE_CFG_PHY_ADDR_S); 1049 cfg->media_type = hnae_get_field(__le32_to_cpu(req->param[1]), 1050 HCLGE_CFG_MEDIA_TP_M, 1051 HCLGE_CFG_MEDIA_TP_S); 1052 cfg->rx_buf_len = hnae_get_field(__le32_to_cpu(req->param[1]), 1053 HCLGE_CFG_RX_BUF_LEN_M, 1054 HCLGE_CFG_RX_BUF_LEN_S); 1055 /* get mac_address */ 1056 mac_addr_tmp = __le32_to_cpu(req->param[2]); 1057 mac_addr_tmp_high = hnae_get_field(__le32_to_cpu(req->param[3]), 1058 HCLGE_CFG_MAC_ADDR_H_M, 1059 HCLGE_CFG_MAC_ADDR_H_S); 1060 1061 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1; 1062 1063 cfg->default_speed = hnae_get_field(__le32_to_cpu(req->param[3]), 1064 HCLGE_CFG_DEFAULT_SPEED_M, 1065 HCLGE_CFG_DEFAULT_SPEED_S); 1066 cfg->rss_size_max = hnae_get_field(__le32_to_cpu(req->param[3]), 1067 HCLGE_CFG_RSS_SIZE_M, 1068 HCLGE_CFG_RSS_SIZE_S); 1069 1070 for (i = 0; i < ETH_ALEN; i++) 1071 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff; 1072 1073 req = (struct hclge_cfg_param_cmd *)desc[1].data; 1074 cfg->numa_node_map = __le32_to_cpu(req->param[0]); 1075 } 1076 1077 /* hclge_get_cfg: query the static parameter from flash 1078 * @hdev: pointer to struct hclge_dev 1079 * @hcfg: the config structure to be getted 1080 */ 1081 static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg) 1082 { 1083 struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM]; 1084 struct hclge_cfg_param_cmd *req; 1085 int i, ret; 1086 1087 for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) { 1088 u32 offset = 0; 1089 1090 req = (struct hclge_cfg_param_cmd *)desc[i].data; 1091 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM, 1092 true); 1093 hnae_set_field(offset, HCLGE_CFG_OFFSET_M, 1094 HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES); 1095 /* Len should be united by 4 bytes when send to hardware */ 1096 hnae_set_field(offset, HCLGE_CFG_RD_LEN_M, HCLGE_CFG_RD_LEN_S, 1097 HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT); 1098 req->offset = cpu_to_le32(offset); 1099 } 1100 1101 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM); 1102 if (ret) { 1103 dev_err(&hdev->pdev->dev, 1104 "get config failed %d.\n", ret); 1105 return ret; 1106 } 1107 1108 hclge_parse_cfg(hcfg, desc); 1109 return 0; 1110 } 1111 1112 static int hclge_get_cap(struct hclge_dev *hdev) 1113 { 1114 int ret; 1115 1116 ret = hclge_query_function_status(hdev); 1117 if (ret) { 1118 dev_err(&hdev->pdev->dev, 1119 "query function status error %d.\n", ret); 1120 return ret; 1121 } 1122 1123 /* get pf resource */ 1124 ret = hclge_query_pf_resource(hdev); 1125 if (ret) { 1126 dev_err(&hdev->pdev->dev, 1127 "query pf resource error %d.\n", ret); 1128 return ret; 1129 } 1130 1131 return 0; 1132 } 1133 1134 static int hclge_configure(struct hclge_dev *hdev) 1135 { 1136 struct hclge_cfg cfg; 1137 int ret, i; 1138 1139 ret = hclge_get_cfg(hdev, &cfg); 1140 if (ret) { 1141 dev_err(&hdev->pdev->dev, "get mac mode error %d.\n", ret); 1142 return ret; 1143 } 1144 1145 hdev->num_vmdq_vport = cfg.vmdq_vport_num; 1146 hdev->base_tqp_pid = 0; 1147 hdev->rss_size_max = cfg.rss_size_max; 1148 hdev->rx_buf_len = cfg.rx_buf_len; 1149 ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr); 1150 hdev->hw.mac.media_type = cfg.media_type; 1151 hdev->hw.mac.phy_addr = cfg.phy_addr; 1152 hdev->num_desc = cfg.tqp_desc_num; 1153 hdev->tm_info.num_pg = 1; 1154 hdev->tc_max = cfg.tc_num; 1155 hdev->tm_info.hw_pfc_map = 0; 1156 1157 ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed); 1158 if (ret) { 1159 dev_err(&hdev->pdev->dev, "Get wrong speed ret=%d.\n", ret); 1160 return ret; 1161 } 1162 1163 if ((hdev->tc_max > HNAE3_MAX_TC) || 1164 (hdev->tc_max < 1)) { 1165 dev_warn(&hdev->pdev->dev, "TC num = %d.\n", 1166 hdev->tc_max); 1167 hdev->tc_max = 1; 1168 } 1169 1170 /* Dev does not support DCB */ 1171 if (!hnae3_dev_dcb_supported(hdev)) { 1172 hdev->tc_max = 1; 1173 hdev->pfc_max = 0; 1174 } else { 1175 hdev->pfc_max = hdev->tc_max; 1176 } 1177 1178 hdev->tm_info.num_tc = hdev->tc_max; 1179 1180 /* Currently not support uncontiuous tc */ 1181 for (i = 0; i < hdev->tm_info.num_tc; i++) 1182 hnae_set_bit(hdev->hw_tc_map, i, 1); 1183 1184 hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE; 1185 1186 return ret; 1187 } 1188 1189 static int hclge_config_tso(struct hclge_dev *hdev, int tso_mss_min, 1190 int tso_mss_max) 1191 { 1192 struct hclge_cfg_tso_status_cmd *req; 1193 struct hclge_desc desc; 1194 u16 tso_mss; 1195 1196 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false); 1197 1198 req = (struct hclge_cfg_tso_status_cmd *)desc.data; 1199 1200 tso_mss = 0; 1201 hnae_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M, 1202 HCLGE_TSO_MSS_MIN_S, tso_mss_min); 1203 req->tso_mss_min = cpu_to_le16(tso_mss); 1204 1205 tso_mss = 0; 1206 hnae_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M, 1207 HCLGE_TSO_MSS_MIN_S, tso_mss_max); 1208 req->tso_mss_max = cpu_to_le16(tso_mss); 1209 1210 return hclge_cmd_send(&hdev->hw, &desc, 1); 1211 } 1212 1213 static int hclge_alloc_tqps(struct hclge_dev *hdev) 1214 { 1215 struct hclge_tqp *tqp; 1216 int i; 1217 1218 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 1219 sizeof(struct hclge_tqp), GFP_KERNEL); 1220 if (!hdev->htqp) 1221 return -ENOMEM; 1222 1223 tqp = hdev->htqp; 1224 1225 for (i = 0; i < hdev->num_tqps; i++) { 1226 tqp->dev = &hdev->pdev->dev; 1227 tqp->index = i; 1228 1229 tqp->q.ae_algo = &ae_algo; 1230 tqp->q.buf_size = hdev->rx_buf_len; 1231 tqp->q.desc_num = hdev->num_desc; 1232 tqp->q.io_base = hdev->hw.io_base + HCLGE_TQP_REG_OFFSET + 1233 i * HCLGE_TQP_REG_SIZE; 1234 1235 tqp++; 1236 } 1237 1238 return 0; 1239 } 1240 1241 static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id, 1242 u16 tqp_pid, u16 tqp_vid, bool is_pf) 1243 { 1244 struct hclge_tqp_map_cmd *req; 1245 struct hclge_desc desc; 1246 int ret; 1247 1248 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false); 1249 1250 req = (struct hclge_tqp_map_cmd *)desc.data; 1251 req->tqp_id = cpu_to_le16(tqp_pid); 1252 req->tqp_vf = func_id; 1253 req->tqp_flag = !is_pf << HCLGE_TQP_MAP_TYPE_B | 1254 1 << HCLGE_TQP_MAP_EN_B; 1255 req->tqp_vid = cpu_to_le16(tqp_vid); 1256 1257 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1258 if (ret) { 1259 dev_err(&hdev->pdev->dev, "TQP map failed %d.\n", 1260 ret); 1261 return ret; 1262 } 1263 1264 return 0; 1265 } 1266 1267 static int hclge_assign_tqp(struct hclge_vport *vport, 1268 struct hnae3_queue **tqp, u16 num_tqps) 1269 { 1270 struct hclge_dev *hdev = vport->back; 1271 int i, alloced; 1272 1273 for (i = 0, alloced = 0; i < hdev->num_tqps && 1274 alloced < num_tqps; i++) { 1275 if (!hdev->htqp[i].alloced) { 1276 hdev->htqp[i].q.handle = &vport->nic; 1277 hdev->htqp[i].q.tqp_index = alloced; 1278 tqp[alloced] = &hdev->htqp[i].q; 1279 hdev->htqp[i].alloced = true; 1280 alloced++; 1281 } 1282 } 1283 vport->alloc_tqps = num_tqps; 1284 1285 return 0; 1286 } 1287 1288 static int hclge_knic_setup(struct hclge_vport *vport, u16 num_tqps) 1289 { 1290 struct hnae3_handle *nic = &vport->nic; 1291 struct hnae3_knic_private_info *kinfo = &nic->kinfo; 1292 struct hclge_dev *hdev = vport->back; 1293 int i, ret; 1294 1295 kinfo->num_desc = hdev->num_desc; 1296 kinfo->rx_buf_len = hdev->rx_buf_len; 1297 kinfo->num_tc = min_t(u16, num_tqps, hdev->tm_info.num_tc); 1298 kinfo->rss_size 1299 = min_t(u16, hdev->rss_size_max, num_tqps / kinfo->num_tc); 1300 kinfo->num_tqps = kinfo->rss_size * kinfo->num_tc; 1301 1302 for (i = 0; i < HNAE3_MAX_TC; i++) { 1303 if (hdev->hw_tc_map & BIT(i)) { 1304 kinfo->tc_info[i].enable = true; 1305 kinfo->tc_info[i].tqp_offset = i * kinfo->rss_size; 1306 kinfo->tc_info[i].tqp_count = kinfo->rss_size; 1307 kinfo->tc_info[i].tc = i; 1308 } else { 1309 /* Set to default queue if TC is disable */ 1310 kinfo->tc_info[i].enable = false; 1311 kinfo->tc_info[i].tqp_offset = 0; 1312 kinfo->tc_info[i].tqp_count = 1; 1313 kinfo->tc_info[i].tc = 0; 1314 } 1315 } 1316 1317 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps, 1318 sizeof(struct hnae3_queue *), GFP_KERNEL); 1319 if (!kinfo->tqp) 1320 return -ENOMEM; 1321 1322 ret = hclge_assign_tqp(vport, kinfo->tqp, kinfo->num_tqps); 1323 if (ret) { 1324 dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret); 1325 return -EINVAL; 1326 } 1327 1328 return 0; 1329 } 1330 1331 static int hclge_map_tqp_to_vport(struct hclge_dev *hdev, 1332 struct hclge_vport *vport) 1333 { 1334 struct hnae3_handle *nic = &vport->nic; 1335 struct hnae3_knic_private_info *kinfo; 1336 u16 i; 1337 1338 kinfo = &nic->kinfo; 1339 for (i = 0; i < kinfo->num_tqps; i++) { 1340 struct hclge_tqp *q = 1341 container_of(kinfo->tqp[i], struct hclge_tqp, q); 1342 bool is_pf; 1343 int ret; 1344 1345 is_pf = !(vport->vport_id); 1346 ret = hclge_map_tqps_to_func(hdev, vport->vport_id, q->index, 1347 i, is_pf); 1348 if (ret) 1349 return ret; 1350 } 1351 1352 return 0; 1353 } 1354 1355 static int hclge_map_tqp(struct hclge_dev *hdev) 1356 { 1357 struct hclge_vport *vport = hdev->vport; 1358 u16 i, num_vport; 1359 1360 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1; 1361 for (i = 0; i < num_vport; i++) { 1362 int ret; 1363 1364 ret = hclge_map_tqp_to_vport(hdev, vport); 1365 if (ret) 1366 return ret; 1367 1368 vport++; 1369 } 1370 1371 return 0; 1372 } 1373 1374 static void hclge_unic_setup(struct hclge_vport *vport, u16 num_tqps) 1375 { 1376 /* this would be initialized later */ 1377 } 1378 1379 static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps) 1380 { 1381 struct hnae3_handle *nic = &vport->nic; 1382 struct hclge_dev *hdev = vport->back; 1383 int ret; 1384 1385 nic->pdev = hdev->pdev; 1386 nic->ae_algo = &ae_algo; 1387 nic->numa_node_mask = hdev->numa_node_mask; 1388 1389 if (hdev->ae_dev->dev_type == HNAE3_DEV_KNIC) { 1390 ret = hclge_knic_setup(vport, num_tqps); 1391 if (ret) { 1392 dev_err(&hdev->pdev->dev, "knic setup failed %d\n", 1393 ret); 1394 return ret; 1395 } 1396 } else { 1397 hclge_unic_setup(vport, num_tqps); 1398 } 1399 1400 return 0; 1401 } 1402 1403 static int hclge_alloc_vport(struct hclge_dev *hdev) 1404 { 1405 struct pci_dev *pdev = hdev->pdev; 1406 struct hclge_vport *vport; 1407 u32 tqp_main_vport; 1408 u32 tqp_per_vport; 1409 int num_vport, i; 1410 int ret; 1411 1412 /* We need to alloc a vport for main NIC of PF */ 1413 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1; 1414 1415 if (hdev->num_tqps < num_vport) 1416 num_vport = hdev->num_tqps; 1417 1418 /* Alloc the same number of TQPs for every vport */ 1419 tqp_per_vport = hdev->num_tqps / num_vport; 1420 tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport; 1421 1422 vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport), 1423 GFP_KERNEL); 1424 if (!vport) 1425 return -ENOMEM; 1426 1427 hdev->vport = vport; 1428 hdev->num_alloc_vport = num_vport; 1429 1430 #ifdef CONFIG_PCI_IOV 1431 /* Enable SRIOV */ 1432 if (hdev->num_req_vfs) { 1433 dev_info(&pdev->dev, "active VFs(%d) found, enabling SRIOV\n", 1434 hdev->num_req_vfs); 1435 ret = pci_enable_sriov(hdev->pdev, hdev->num_req_vfs); 1436 if (ret) { 1437 hdev->num_alloc_vfs = 0; 1438 dev_err(&pdev->dev, "SRIOV enable failed %d\n", 1439 ret); 1440 return ret; 1441 } 1442 } 1443 hdev->num_alloc_vfs = hdev->num_req_vfs; 1444 #endif 1445 1446 for (i = 0; i < num_vport; i++) { 1447 vport->back = hdev; 1448 vport->vport_id = i; 1449 1450 if (i == 0) 1451 ret = hclge_vport_setup(vport, tqp_main_vport); 1452 else 1453 ret = hclge_vport_setup(vport, tqp_per_vport); 1454 if (ret) { 1455 dev_err(&pdev->dev, 1456 "vport setup failed for vport %d, %d\n", 1457 i, ret); 1458 return ret; 1459 } 1460 1461 vport++; 1462 } 1463 1464 return 0; 1465 } 1466 1467 static int hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev, 1468 struct hclge_pkt_buf_alloc *buf_alloc) 1469 { 1470 /* TX buffer size is unit by 128 byte */ 1471 #define HCLGE_BUF_SIZE_UNIT_SHIFT 7 1472 #define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15) 1473 struct hclge_tx_buff_alloc_cmd *req; 1474 struct hclge_desc desc; 1475 int ret; 1476 u8 i; 1477 1478 req = (struct hclge_tx_buff_alloc_cmd *)desc.data; 1479 1480 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0); 1481 for (i = 0; i < HCLGE_TC_NUM; i++) { 1482 u32 buf_size = buf_alloc->priv_buf[i].tx_buf_size; 1483 1484 req->tx_pkt_buff[i] = 1485 cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) | 1486 HCLGE_BUF_SIZE_UPDATE_EN_MSK); 1487 } 1488 1489 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1490 if (ret) { 1491 dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n", 1492 ret); 1493 return ret; 1494 } 1495 1496 return 0; 1497 } 1498 1499 static int hclge_tx_buffer_alloc(struct hclge_dev *hdev, 1500 struct hclge_pkt_buf_alloc *buf_alloc) 1501 { 1502 int ret = hclge_cmd_alloc_tx_buff(hdev, buf_alloc); 1503 1504 if (ret) { 1505 dev_err(&hdev->pdev->dev, 1506 "tx buffer alloc failed %d\n", ret); 1507 return ret; 1508 } 1509 1510 return 0; 1511 } 1512 1513 static int hclge_get_tc_num(struct hclge_dev *hdev) 1514 { 1515 int i, cnt = 0; 1516 1517 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) 1518 if (hdev->hw_tc_map & BIT(i)) 1519 cnt++; 1520 return cnt; 1521 } 1522 1523 static int hclge_get_pfc_enalbe_num(struct hclge_dev *hdev) 1524 { 1525 int i, cnt = 0; 1526 1527 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) 1528 if (hdev->hw_tc_map & BIT(i) && 1529 hdev->tm_info.hw_pfc_map & BIT(i)) 1530 cnt++; 1531 return cnt; 1532 } 1533 1534 /* Get the number of pfc enabled TCs, which have private buffer */ 1535 static int hclge_get_pfc_priv_num(struct hclge_dev *hdev, 1536 struct hclge_pkt_buf_alloc *buf_alloc) 1537 { 1538 struct hclge_priv_buf *priv; 1539 int i, cnt = 0; 1540 1541 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1542 priv = &buf_alloc->priv_buf[i]; 1543 if ((hdev->tm_info.hw_pfc_map & BIT(i)) && 1544 priv->enable) 1545 cnt++; 1546 } 1547 1548 return cnt; 1549 } 1550 1551 /* Get the number of pfc disabled TCs, which have private buffer */ 1552 static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev, 1553 struct hclge_pkt_buf_alloc *buf_alloc) 1554 { 1555 struct hclge_priv_buf *priv; 1556 int i, cnt = 0; 1557 1558 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1559 priv = &buf_alloc->priv_buf[i]; 1560 if (hdev->hw_tc_map & BIT(i) && 1561 !(hdev->tm_info.hw_pfc_map & BIT(i)) && 1562 priv->enable) 1563 cnt++; 1564 } 1565 1566 return cnt; 1567 } 1568 1569 static u32 hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc) 1570 { 1571 struct hclge_priv_buf *priv; 1572 u32 rx_priv = 0; 1573 int i; 1574 1575 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1576 priv = &buf_alloc->priv_buf[i]; 1577 if (priv->enable) 1578 rx_priv += priv->buf_size; 1579 } 1580 return rx_priv; 1581 } 1582 1583 static u32 hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc) 1584 { 1585 u32 i, total_tx_size = 0; 1586 1587 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) 1588 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size; 1589 1590 return total_tx_size; 1591 } 1592 1593 static bool hclge_is_rx_buf_ok(struct hclge_dev *hdev, 1594 struct hclge_pkt_buf_alloc *buf_alloc, 1595 u32 rx_all) 1596 { 1597 u32 shared_buf_min, shared_buf_tc, shared_std; 1598 int tc_num, pfc_enable_num; 1599 u32 shared_buf; 1600 u32 rx_priv; 1601 int i; 1602 1603 tc_num = hclge_get_tc_num(hdev); 1604 pfc_enable_num = hclge_get_pfc_enalbe_num(hdev); 1605 1606 if (hnae3_dev_dcb_supported(hdev)) 1607 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_DV; 1608 else 1609 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_NON_DCB_DV; 1610 1611 shared_buf_tc = pfc_enable_num * hdev->mps + 1612 (tc_num - pfc_enable_num) * hdev->mps / 2 + 1613 hdev->mps; 1614 shared_std = max_t(u32, shared_buf_min, shared_buf_tc); 1615 1616 rx_priv = hclge_get_rx_priv_buff_alloced(buf_alloc); 1617 if (rx_all <= rx_priv + shared_std) 1618 return false; 1619 1620 shared_buf = rx_all - rx_priv; 1621 buf_alloc->s_buf.buf_size = shared_buf; 1622 buf_alloc->s_buf.self.high = shared_buf; 1623 buf_alloc->s_buf.self.low = 2 * hdev->mps; 1624 1625 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1626 if ((hdev->hw_tc_map & BIT(i)) && 1627 (hdev->tm_info.hw_pfc_map & BIT(i))) { 1628 buf_alloc->s_buf.tc_thrd[i].low = hdev->mps; 1629 buf_alloc->s_buf.tc_thrd[i].high = 2 * hdev->mps; 1630 } else { 1631 buf_alloc->s_buf.tc_thrd[i].low = 0; 1632 buf_alloc->s_buf.tc_thrd[i].high = hdev->mps; 1633 } 1634 } 1635 1636 return true; 1637 } 1638 1639 static int hclge_tx_buffer_calc(struct hclge_dev *hdev, 1640 struct hclge_pkt_buf_alloc *buf_alloc) 1641 { 1642 u32 i, total_size; 1643 1644 total_size = hdev->pkt_buf_size; 1645 1646 /* alloc tx buffer for all enabled tc */ 1647 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1648 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 1649 1650 if (total_size < HCLGE_DEFAULT_TX_BUF) 1651 return -ENOMEM; 1652 1653 if (hdev->hw_tc_map & BIT(i)) 1654 priv->tx_buf_size = HCLGE_DEFAULT_TX_BUF; 1655 else 1656 priv->tx_buf_size = 0; 1657 1658 total_size -= priv->tx_buf_size; 1659 } 1660 1661 return 0; 1662 } 1663 1664 /* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs 1665 * @hdev: pointer to struct hclge_dev 1666 * @buf_alloc: pointer to buffer calculation data 1667 * @return: 0: calculate sucessful, negative: fail 1668 */ 1669 static int hclge_rx_buffer_calc(struct hclge_dev *hdev, 1670 struct hclge_pkt_buf_alloc *buf_alloc) 1671 { 1672 u32 rx_all = hdev->pkt_buf_size; 1673 int no_pfc_priv_num, pfc_priv_num; 1674 struct hclge_priv_buf *priv; 1675 int i; 1676 1677 rx_all -= hclge_get_tx_buff_alloced(buf_alloc); 1678 1679 /* When DCB is not supported, rx private 1680 * buffer is not allocated. 1681 */ 1682 if (!hnae3_dev_dcb_supported(hdev)) { 1683 if (!hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all)) 1684 return -ENOMEM; 1685 1686 return 0; 1687 } 1688 1689 /* step 1, try to alloc private buffer for all enabled tc */ 1690 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1691 priv = &buf_alloc->priv_buf[i]; 1692 if (hdev->hw_tc_map & BIT(i)) { 1693 priv->enable = 1; 1694 if (hdev->tm_info.hw_pfc_map & BIT(i)) { 1695 priv->wl.low = hdev->mps; 1696 priv->wl.high = priv->wl.low + hdev->mps; 1697 priv->buf_size = priv->wl.high + 1698 HCLGE_DEFAULT_DV; 1699 } else { 1700 priv->wl.low = 0; 1701 priv->wl.high = 2 * hdev->mps; 1702 priv->buf_size = priv->wl.high; 1703 } 1704 } else { 1705 priv->enable = 0; 1706 priv->wl.low = 0; 1707 priv->wl.high = 0; 1708 priv->buf_size = 0; 1709 } 1710 } 1711 1712 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all)) 1713 return 0; 1714 1715 /* step 2, try to decrease the buffer size of 1716 * no pfc TC's private buffer 1717 */ 1718 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1719 priv = &buf_alloc->priv_buf[i]; 1720 1721 priv->enable = 0; 1722 priv->wl.low = 0; 1723 priv->wl.high = 0; 1724 priv->buf_size = 0; 1725 1726 if (!(hdev->hw_tc_map & BIT(i))) 1727 continue; 1728 1729 priv->enable = 1; 1730 1731 if (hdev->tm_info.hw_pfc_map & BIT(i)) { 1732 priv->wl.low = 128; 1733 priv->wl.high = priv->wl.low + hdev->mps; 1734 priv->buf_size = priv->wl.high + HCLGE_DEFAULT_DV; 1735 } else { 1736 priv->wl.low = 0; 1737 priv->wl.high = hdev->mps; 1738 priv->buf_size = priv->wl.high; 1739 } 1740 } 1741 1742 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all)) 1743 return 0; 1744 1745 /* step 3, try to reduce the number of pfc disabled TCs, 1746 * which have private buffer 1747 */ 1748 /* get the total no pfc enable TC number, which have private buffer */ 1749 no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev, buf_alloc); 1750 1751 /* let the last to be cleared first */ 1752 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) { 1753 priv = &buf_alloc->priv_buf[i]; 1754 1755 if (hdev->hw_tc_map & BIT(i) && 1756 !(hdev->tm_info.hw_pfc_map & BIT(i))) { 1757 /* Clear the no pfc TC private buffer */ 1758 priv->wl.low = 0; 1759 priv->wl.high = 0; 1760 priv->buf_size = 0; 1761 priv->enable = 0; 1762 no_pfc_priv_num--; 1763 } 1764 1765 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) || 1766 no_pfc_priv_num == 0) 1767 break; 1768 } 1769 1770 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all)) 1771 return 0; 1772 1773 /* step 4, try to reduce the number of pfc enabled TCs 1774 * which have private buffer. 1775 */ 1776 pfc_priv_num = hclge_get_pfc_priv_num(hdev, buf_alloc); 1777 1778 /* let the last to be cleared first */ 1779 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) { 1780 priv = &buf_alloc->priv_buf[i]; 1781 1782 if (hdev->hw_tc_map & BIT(i) && 1783 hdev->tm_info.hw_pfc_map & BIT(i)) { 1784 /* Reduce the number of pfc TC with private buffer */ 1785 priv->wl.low = 0; 1786 priv->enable = 0; 1787 priv->wl.high = 0; 1788 priv->buf_size = 0; 1789 pfc_priv_num--; 1790 } 1791 1792 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) || 1793 pfc_priv_num == 0) 1794 break; 1795 } 1796 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all)) 1797 return 0; 1798 1799 return -ENOMEM; 1800 } 1801 1802 static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev, 1803 struct hclge_pkt_buf_alloc *buf_alloc) 1804 { 1805 struct hclge_rx_priv_buff_cmd *req; 1806 struct hclge_desc desc; 1807 int ret; 1808 int i; 1809 1810 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false); 1811 req = (struct hclge_rx_priv_buff_cmd *)desc.data; 1812 1813 /* Alloc private buffer TCs */ 1814 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1815 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 1816 1817 req->buf_num[i] = 1818 cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S); 1819 req->buf_num[i] |= 1820 cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B); 1821 } 1822 1823 req->shared_buf = 1824 cpu_to_le16((buf_alloc->s_buf.buf_size >> HCLGE_BUF_UNIT_S) | 1825 (1 << HCLGE_TC0_PRI_BUF_EN_B)); 1826 1827 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1828 if (ret) { 1829 dev_err(&hdev->pdev->dev, 1830 "rx private buffer alloc cmd failed %d\n", ret); 1831 return ret; 1832 } 1833 1834 return 0; 1835 } 1836 1837 #define HCLGE_PRIV_ENABLE(a) ((a) > 0 ? 1 : 0) 1838 1839 static int hclge_rx_priv_wl_config(struct hclge_dev *hdev, 1840 struct hclge_pkt_buf_alloc *buf_alloc) 1841 { 1842 struct hclge_rx_priv_wl_buf *req; 1843 struct hclge_priv_buf *priv; 1844 struct hclge_desc desc[2]; 1845 int i, j; 1846 int ret; 1847 1848 for (i = 0; i < 2; i++) { 1849 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC, 1850 false); 1851 req = (struct hclge_rx_priv_wl_buf *)desc[i].data; 1852 1853 /* The first descriptor set the NEXT bit to 1 */ 1854 if (i == 0) 1855 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 1856 else 1857 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 1858 1859 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) { 1860 u32 idx = i * HCLGE_TC_NUM_ONE_DESC + j; 1861 1862 priv = &buf_alloc->priv_buf[idx]; 1863 req->tc_wl[j].high = 1864 cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S); 1865 req->tc_wl[j].high |= 1866 cpu_to_le16(HCLGE_PRIV_ENABLE(priv->wl.high) << 1867 HCLGE_RX_PRIV_EN_B); 1868 req->tc_wl[j].low = 1869 cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S); 1870 req->tc_wl[j].low |= 1871 cpu_to_le16(HCLGE_PRIV_ENABLE(priv->wl.low) << 1872 HCLGE_RX_PRIV_EN_B); 1873 } 1874 } 1875 1876 /* Send 2 descriptor at one time */ 1877 ret = hclge_cmd_send(&hdev->hw, desc, 2); 1878 if (ret) { 1879 dev_err(&hdev->pdev->dev, 1880 "rx private waterline config cmd failed %d\n", 1881 ret); 1882 return ret; 1883 } 1884 return 0; 1885 } 1886 1887 static int hclge_common_thrd_config(struct hclge_dev *hdev, 1888 struct hclge_pkt_buf_alloc *buf_alloc) 1889 { 1890 struct hclge_shared_buf *s_buf = &buf_alloc->s_buf; 1891 struct hclge_rx_com_thrd *req; 1892 struct hclge_desc desc[2]; 1893 struct hclge_tc_thrd *tc; 1894 int i, j; 1895 int ret; 1896 1897 for (i = 0; i < 2; i++) { 1898 hclge_cmd_setup_basic_desc(&desc[i], 1899 HCLGE_OPC_RX_COM_THRD_ALLOC, false); 1900 req = (struct hclge_rx_com_thrd *)&desc[i].data; 1901 1902 /* The first descriptor set the NEXT bit to 1 */ 1903 if (i == 0) 1904 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 1905 else 1906 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 1907 1908 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) { 1909 tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j]; 1910 1911 req->com_thrd[j].high = 1912 cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S); 1913 req->com_thrd[j].high |= 1914 cpu_to_le16(HCLGE_PRIV_ENABLE(tc->high) << 1915 HCLGE_RX_PRIV_EN_B); 1916 req->com_thrd[j].low = 1917 cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S); 1918 req->com_thrd[j].low |= 1919 cpu_to_le16(HCLGE_PRIV_ENABLE(tc->low) << 1920 HCLGE_RX_PRIV_EN_B); 1921 } 1922 } 1923 1924 /* Send 2 descriptors at one time */ 1925 ret = hclge_cmd_send(&hdev->hw, desc, 2); 1926 if (ret) { 1927 dev_err(&hdev->pdev->dev, 1928 "common threshold config cmd failed %d\n", ret); 1929 return ret; 1930 } 1931 return 0; 1932 } 1933 1934 static int hclge_common_wl_config(struct hclge_dev *hdev, 1935 struct hclge_pkt_buf_alloc *buf_alloc) 1936 { 1937 struct hclge_shared_buf *buf = &buf_alloc->s_buf; 1938 struct hclge_rx_com_wl *req; 1939 struct hclge_desc desc; 1940 int ret; 1941 1942 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false); 1943 1944 req = (struct hclge_rx_com_wl *)desc.data; 1945 req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S); 1946 req->com_wl.high |= 1947 cpu_to_le16(HCLGE_PRIV_ENABLE(buf->self.high) << 1948 HCLGE_RX_PRIV_EN_B); 1949 1950 req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S); 1951 req->com_wl.low |= 1952 cpu_to_le16(HCLGE_PRIV_ENABLE(buf->self.low) << 1953 HCLGE_RX_PRIV_EN_B); 1954 1955 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1956 if (ret) { 1957 dev_err(&hdev->pdev->dev, 1958 "common waterline config cmd failed %d\n", ret); 1959 return ret; 1960 } 1961 1962 return 0; 1963 } 1964 1965 int hclge_buffer_alloc(struct hclge_dev *hdev) 1966 { 1967 struct hclge_pkt_buf_alloc *pkt_buf; 1968 int ret; 1969 1970 pkt_buf = kzalloc(sizeof(*pkt_buf), GFP_KERNEL); 1971 if (!pkt_buf) 1972 return -ENOMEM; 1973 1974 ret = hclge_tx_buffer_calc(hdev, pkt_buf); 1975 if (ret) { 1976 dev_err(&hdev->pdev->dev, 1977 "could not calc tx buffer size for all TCs %d\n", ret); 1978 goto out; 1979 } 1980 1981 ret = hclge_tx_buffer_alloc(hdev, pkt_buf); 1982 if (ret) { 1983 dev_err(&hdev->pdev->dev, 1984 "could not alloc tx buffers %d\n", ret); 1985 goto out; 1986 } 1987 1988 ret = hclge_rx_buffer_calc(hdev, pkt_buf); 1989 if (ret) { 1990 dev_err(&hdev->pdev->dev, 1991 "could not calc rx priv buffer size for all TCs %d\n", 1992 ret); 1993 goto out; 1994 } 1995 1996 ret = hclge_rx_priv_buf_alloc(hdev, pkt_buf); 1997 if (ret) { 1998 dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n", 1999 ret); 2000 goto out; 2001 } 2002 2003 if (hnae3_dev_dcb_supported(hdev)) { 2004 ret = hclge_rx_priv_wl_config(hdev, pkt_buf); 2005 if (ret) { 2006 dev_err(&hdev->pdev->dev, 2007 "could not configure rx private waterline %d\n", 2008 ret); 2009 goto out; 2010 } 2011 2012 ret = hclge_common_thrd_config(hdev, pkt_buf); 2013 if (ret) { 2014 dev_err(&hdev->pdev->dev, 2015 "could not configure common threshold %d\n", 2016 ret); 2017 goto out; 2018 } 2019 } 2020 2021 ret = hclge_common_wl_config(hdev, pkt_buf); 2022 if (ret) 2023 dev_err(&hdev->pdev->dev, 2024 "could not configure common waterline %d\n", ret); 2025 2026 out: 2027 kfree(pkt_buf); 2028 return ret; 2029 } 2030 2031 static int hclge_init_roce_base_info(struct hclge_vport *vport) 2032 { 2033 struct hnae3_handle *roce = &vport->roce; 2034 struct hnae3_handle *nic = &vport->nic; 2035 2036 roce->rinfo.num_vectors = vport->back->num_roce_msi; 2037 2038 if (vport->back->num_msi_left < vport->roce.rinfo.num_vectors || 2039 vport->back->num_msi_left == 0) 2040 return -EINVAL; 2041 2042 roce->rinfo.base_vector = vport->back->roce_base_vector; 2043 2044 roce->rinfo.netdev = nic->kinfo.netdev; 2045 roce->rinfo.roce_io_base = vport->back->hw.io_base; 2046 2047 roce->pdev = nic->pdev; 2048 roce->ae_algo = nic->ae_algo; 2049 roce->numa_node_mask = nic->numa_node_mask; 2050 2051 return 0; 2052 } 2053 2054 static int hclge_init_msi(struct hclge_dev *hdev) 2055 { 2056 struct pci_dev *pdev = hdev->pdev; 2057 int vectors; 2058 int i; 2059 2060 vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi, 2061 PCI_IRQ_MSI | PCI_IRQ_MSIX); 2062 if (vectors < 0) { 2063 dev_err(&pdev->dev, 2064 "failed(%d) to allocate MSI/MSI-X vectors\n", 2065 vectors); 2066 return vectors; 2067 } 2068 if (vectors < hdev->num_msi) 2069 dev_warn(&hdev->pdev->dev, 2070 "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n", 2071 hdev->num_msi, vectors); 2072 2073 hdev->num_msi = vectors; 2074 hdev->num_msi_left = vectors; 2075 hdev->base_msi_vector = pdev->irq; 2076 hdev->roce_base_vector = hdev->base_msi_vector + 2077 HCLGE_ROCE_VECTOR_OFFSET; 2078 2079 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2080 sizeof(u16), GFP_KERNEL); 2081 if (!hdev->vector_status) { 2082 pci_free_irq_vectors(pdev); 2083 return -ENOMEM; 2084 } 2085 2086 for (i = 0; i < hdev->num_msi; i++) 2087 hdev->vector_status[i] = HCLGE_INVALID_VPORT; 2088 2089 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2090 sizeof(int), GFP_KERNEL); 2091 if (!hdev->vector_irq) { 2092 pci_free_irq_vectors(pdev); 2093 return -ENOMEM; 2094 } 2095 2096 return 0; 2097 } 2098 2099 static void hclge_check_speed_dup(struct hclge_dev *hdev, int duplex, int speed) 2100 { 2101 struct hclge_mac *mac = &hdev->hw.mac; 2102 2103 if ((speed == HCLGE_MAC_SPEED_10M) || (speed == HCLGE_MAC_SPEED_100M)) 2104 mac->duplex = (u8)duplex; 2105 else 2106 mac->duplex = HCLGE_MAC_FULL; 2107 2108 mac->speed = speed; 2109 } 2110 2111 int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex) 2112 { 2113 struct hclge_config_mac_speed_dup_cmd *req; 2114 struct hclge_desc desc; 2115 int ret; 2116 2117 req = (struct hclge_config_mac_speed_dup_cmd *)desc.data; 2118 2119 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false); 2120 2121 hnae_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, !!duplex); 2122 2123 switch (speed) { 2124 case HCLGE_MAC_SPEED_10M: 2125 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, 2126 HCLGE_CFG_SPEED_S, 6); 2127 break; 2128 case HCLGE_MAC_SPEED_100M: 2129 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, 2130 HCLGE_CFG_SPEED_S, 7); 2131 break; 2132 case HCLGE_MAC_SPEED_1G: 2133 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, 2134 HCLGE_CFG_SPEED_S, 0); 2135 break; 2136 case HCLGE_MAC_SPEED_10G: 2137 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, 2138 HCLGE_CFG_SPEED_S, 1); 2139 break; 2140 case HCLGE_MAC_SPEED_25G: 2141 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, 2142 HCLGE_CFG_SPEED_S, 2); 2143 break; 2144 case HCLGE_MAC_SPEED_40G: 2145 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, 2146 HCLGE_CFG_SPEED_S, 3); 2147 break; 2148 case HCLGE_MAC_SPEED_50G: 2149 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, 2150 HCLGE_CFG_SPEED_S, 4); 2151 break; 2152 case HCLGE_MAC_SPEED_100G: 2153 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, 2154 HCLGE_CFG_SPEED_S, 5); 2155 break; 2156 default: 2157 dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed); 2158 return -EINVAL; 2159 } 2160 2161 hnae_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B, 2162 1); 2163 2164 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2165 if (ret) { 2166 dev_err(&hdev->pdev->dev, 2167 "mac speed/duplex config cmd failed %d.\n", ret); 2168 return ret; 2169 } 2170 2171 hclge_check_speed_dup(hdev, duplex, speed); 2172 2173 return 0; 2174 } 2175 2176 static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed, 2177 u8 duplex) 2178 { 2179 struct hclge_vport *vport = hclge_get_vport(handle); 2180 struct hclge_dev *hdev = vport->back; 2181 2182 return hclge_cfg_mac_speed_dup(hdev, speed, duplex); 2183 } 2184 2185 static int hclge_query_mac_an_speed_dup(struct hclge_dev *hdev, int *speed, 2186 u8 *duplex) 2187 { 2188 struct hclge_query_an_speed_dup_cmd *req; 2189 struct hclge_desc desc; 2190 int speed_tmp; 2191 int ret; 2192 2193 req = (struct hclge_query_an_speed_dup_cmd *)desc.data; 2194 2195 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_AN_RESULT, true); 2196 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2197 if (ret) { 2198 dev_err(&hdev->pdev->dev, 2199 "mac speed/autoneg/duplex query cmd failed %d\n", 2200 ret); 2201 return ret; 2202 } 2203 2204 *duplex = hnae_get_bit(req->an_syn_dup_speed, HCLGE_QUERY_DUPLEX_B); 2205 speed_tmp = hnae_get_field(req->an_syn_dup_speed, HCLGE_QUERY_SPEED_M, 2206 HCLGE_QUERY_SPEED_S); 2207 2208 ret = hclge_parse_speed(speed_tmp, speed); 2209 if (ret) { 2210 dev_err(&hdev->pdev->dev, 2211 "could not parse speed(=%d), %d\n", speed_tmp, ret); 2212 return -EIO; 2213 } 2214 2215 return 0; 2216 } 2217 2218 static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable) 2219 { 2220 struct hclge_config_auto_neg_cmd *req; 2221 struct hclge_desc desc; 2222 u32 flag = 0; 2223 int ret; 2224 2225 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false); 2226 2227 req = (struct hclge_config_auto_neg_cmd *)desc.data; 2228 hnae_set_bit(flag, HCLGE_MAC_CFG_AN_EN_B, !!enable); 2229 req->cfg_an_cmd_flag = cpu_to_le32(flag); 2230 2231 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2232 if (ret) { 2233 dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n", 2234 ret); 2235 return ret; 2236 } 2237 2238 return 0; 2239 } 2240 2241 static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable) 2242 { 2243 struct hclge_vport *vport = hclge_get_vport(handle); 2244 struct hclge_dev *hdev = vport->back; 2245 2246 return hclge_set_autoneg_en(hdev, enable); 2247 } 2248 2249 static int hclge_get_autoneg(struct hnae3_handle *handle) 2250 { 2251 struct hclge_vport *vport = hclge_get_vport(handle); 2252 struct hclge_dev *hdev = vport->back; 2253 struct phy_device *phydev = hdev->hw.mac.phydev; 2254 2255 if (phydev) 2256 return phydev->autoneg; 2257 2258 return hdev->hw.mac.autoneg; 2259 } 2260 2261 static int hclge_set_default_mac_vlan_mask(struct hclge_dev *hdev, 2262 bool mask_vlan, 2263 u8 *mac_mask) 2264 { 2265 struct hclge_mac_vlan_mask_entry_cmd *req; 2266 struct hclge_desc desc; 2267 int status; 2268 2269 req = (struct hclge_mac_vlan_mask_entry_cmd *)desc.data; 2270 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_MASK_SET, false); 2271 2272 hnae_set_bit(req->vlan_mask, HCLGE_VLAN_MASK_EN_B, 2273 mask_vlan ? 1 : 0); 2274 ether_addr_copy(req->mac_mask, mac_mask); 2275 2276 status = hclge_cmd_send(&hdev->hw, &desc, 1); 2277 if (status) 2278 dev_err(&hdev->pdev->dev, 2279 "Config mac_vlan_mask failed for cmd_send, ret =%d\n", 2280 status); 2281 2282 return status; 2283 } 2284 2285 static int hclge_mac_init(struct hclge_dev *hdev) 2286 { 2287 struct hnae3_handle *handle = &hdev->vport[0].nic; 2288 struct net_device *netdev = handle->kinfo.netdev; 2289 struct hclge_mac *mac = &hdev->hw.mac; 2290 u8 mac_mask[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; 2291 int mtu; 2292 int ret; 2293 2294 ret = hclge_cfg_mac_speed_dup(hdev, hdev->hw.mac.speed, HCLGE_MAC_FULL); 2295 if (ret) { 2296 dev_err(&hdev->pdev->dev, 2297 "Config mac speed dup fail ret=%d\n", ret); 2298 return ret; 2299 } 2300 2301 mac->link = 0; 2302 2303 /* Initialize the MTA table work mode */ 2304 hdev->accept_mta_mc = true; 2305 hdev->enable_mta = true; 2306 hdev->mta_mac_sel_type = HCLGE_MAC_ADDR_47_36; 2307 2308 ret = hclge_set_mta_filter_mode(hdev, 2309 hdev->mta_mac_sel_type, 2310 hdev->enable_mta); 2311 if (ret) { 2312 dev_err(&hdev->pdev->dev, "set mta filter mode failed %d\n", 2313 ret); 2314 return ret; 2315 } 2316 2317 ret = hclge_cfg_func_mta_filter(hdev, 0, hdev->accept_mta_mc); 2318 if (ret) { 2319 dev_err(&hdev->pdev->dev, 2320 "set mta filter mode fail ret=%d\n", ret); 2321 return ret; 2322 } 2323 2324 ret = hclge_set_default_mac_vlan_mask(hdev, true, mac_mask); 2325 if (ret) { 2326 dev_err(&hdev->pdev->dev, 2327 "set default mac_vlan_mask fail ret=%d\n", ret); 2328 return ret; 2329 } 2330 2331 if (netdev) 2332 mtu = netdev->mtu; 2333 else 2334 mtu = ETH_DATA_LEN; 2335 2336 ret = hclge_set_mtu(handle, mtu); 2337 if (ret) { 2338 dev_err(&hdev->pdev->dev, 2339 "set mtu failed ret=%d\n", ret); 2340 return ret; 2341 } 2342 2343 return 0; 2344 } 2345 2346 static void hclge_mbx_task_schedule(struct hclge_dev *hdev) 2347 { 2348 if (!test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state)) 2349 schedule_work(&hdev->mbx_service_task); 2350 } 2351 2352 static void hclge_reset_task_schedule(struct hclge_dev *hdev) 2353 { 2354 if (!test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state)) 2355 schedule_work(&hdev->rst_service_task); 2356 } 2357 2358 static void hclge_task_schedule(struct hclge_dev *hdev) 2359 { 2360 if (!test_bit(HCLGE_STATE_DOWN, &hdev->state) && 2361 !test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 2362 !test_and_set_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state)) 2363 (void)schedule_work(&hdev->service_task); 2364 } 2365 2366 static int hclge_get_mac_link_status(struct hclge_dev *hdev) 2367 { 2368 struct hclge_link_status_cmd *req; 2369 struct hclge_desc desc; 2370 int link_status; 2371 int ret; 2372 2373 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true); 2374 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2375 if (ret) { 2376 dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n", 2377 ret); 2378 return ret; 2379 } 2380 2381 req = (struct hclge_link_status_cmd *)desc.data; 2382 link_status = req->status & HCLGE_LINK_STATUS; 2383 2384 return !!link_status; 2385 } 2386 2387 static int hclge_get_mac_phy_link(struct hclge_dev *hdev) 2388 { 2389 int mac_state; 2390 int link_stat; 2391 2392 mac_state = hclge_get_mac_link_status(hdev); 2393 2394 if (hdev->hw.mac.phydev) { 2395 if (!genphy_read_status(hdev->hw.mac.phydev)) 2396 link_stat = mac_state & 2397 hdev->hw.mac.phydev->link; 2398 else 2399 link_stat = 0; 2400 2401 } else { 2402 link_stat = mac_state; 2403 } 2404 2405 return !!link_stat; 2406 } 2407 2408 static void hclge_update_link_status(struct hclge_dev *hdev) 2409 { 2410 struct hnae3_client *client = hdev->nic_client; 2411 struct hnae3_handle *handle; 2412 int state; 2413 int i; 2414 2415 if (!client) 2416 return; 2417 state = hclge_get_mac_phy_link(hdev); 2418 if (state != hdev->hw.mac.link) { 2419 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) { 2420 handle = &hdev->vport[i].nic; 2421 client->ops->link_status_change(handle, state); 2422 } 2423 hdev->hw.mac.link = state; 2424 } 2425 } 2426 2427 static int hclge_update_speed_duplex(struct hclge_dev *hdev) 2428 { 2429 struct hclge_mac mac = hdev->hw.mac; 2430 u8 duplex; 2431 int speed; 2432 int ret; 2433 2434 /* get the speed and duplex as autoneg'result from mac cmd when phy 2435 * doesn't exit. 2436 */ 2437 if (mac.phydev || !mac.autoneg) 2438 return 0; 2439 2440 ret = hclge_query_mac_an_speed_dup(hdev, &speed, &duplex); 2441 if (ret) { 2442 dev_err(&hdev->pdev->dev, 2443 "mac autoneg/speed/duplex query failed %d\n", ret); 2444 return ret; 2445 } 2446 2447 if ((mac.speed != speed) || (mac.duplex != duplex)) { 2448 ret = hclge_cfg_mac_speed_dup(hdev, speed, duplex); 2449 if (ret) { 2450 dev_err(&hdev->pdev->dev, 2451 "mac speed/duplex config failed %d\n", ret); 2452 return ret; 2453 } 2454 } 2455 2456 return 0; 2457 } 2458 2459 static int hclge_update_speed_duplex_h(struct hnae3_handle *handle) 2460 { 2461 struct hclge_vport *vport = hclge_get_vport(handle); 2462 struct hclge_dev *hdev = vport->back; 2463 2464 return hclge_update_speed_duplex(hdev); 2465 } 2466 2467 static int hclge_get_status(struct hnae3_handle *handle) 2468 { 2469 struct hclge_vport *vport = hclge_get_vport(handle); 2470 struct hclge_dev *hdev = vport->back; 2471 2472 hclge_update_link_status(hdev); 2473 2474 return hdev->hw.mac.link; 2475 } 2476 2477 static void hclge_service_timer(struct timer_list *t) 2478 { 2479 struct hclge_dev *hdev = from_timer(hdev, t, service_timer); 2480 2481 mod_timer(&hdev->service_timer, jiffies + HZ); 2482 hdev->hw_stats.stats_timer++; 2483 hclge_task_schedule(hdev); 2484 } 2485 2486 static void hclge_service_complete(struct hclge_dev *hdev) 2487 { 2488 WARN_ON(!test_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state)); 2489 2490 /* Flush memory before next watchdog */ 2491 smp_mb__before_atomic(); 2492 clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state); 2493 } 2494 2495 static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval) 2496 { 2497 u32 rst_src_reg; 2498 u32 cmdq_src_reg; 2499 2500 /* fetch the events from their corresponding regs */ 2501 rst_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG); 2502 cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG); 2503 2504 /* Assumption: If by any chance reset and mailbox events are reported 2505 * together then we will only process reset event in this go and will 2506 * defer the processing of the mailbox events. Since, we would have not 2507 * cleared RX CMDQ event this time we would receive again another 2508 * interrupt from H/W just for the mailbox. 2509 */ 2510 2511 /* check for vector0 reset event sources */ 2512 if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & rst_src_reg) { 2513 set_bit(HNAE3_GLOBAL_RESET, &hdev->reset_pending); 2514 *clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B); 2515 return HCLGE_VECTOR0_EVENT_RST; 2516 } 2517 2518 if (BIT(HCLGE_VECTOR0_CORERESET_INT_B) & rst_src_reg) { 2519 set_bit(HNAE3_CORE_RESET, &hdev->reset_pending); 2520 *clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B); 2521 return HCLGE_VECTOR0_EVENT_RST; 2522 } 2523 2524 if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & rst_src_reg) { 2525 set_bit(HNAE3_IMP_RESET, &hdev->reset_pending); 2526 *clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B); 2527 return HCLGE_VECTOR0_EVENT_RST; 2528 } 2529 2530 /* check for vector0 mailbox(=CMDQ RX) event source */ 2531 if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) { 2532 cmdq_src_reg &= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B); 2533 *clearval = cmdq_src_reg; 2534 return HCLGE_VECTOR0_EVENT_MBX; 2535 } 2536 2537 return HCLGE_VECTOR0_EVENT_OTHER; 2538 } 2539 2540 static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type, 2541 u32 regclr) 2542 { 2543 switch (event_type) { 2544 case HCLGE_VECTOR0_EVENT_RST: 2545 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr); 2546 break; 2547 case HCLGE_VECTOR0_EVENT_MBX: 2548 hclge_write_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG, regclr); 2549 break; 2550 } 2551 } 2552 2553 static void hclge_enable_vector(struct hclge_misc_vector *vector, bool enable) 2554 { 2555 writel(enable ? 1 : 0, vector->addr); 2556 } 2557 2558 static irqreturn_t hclge_misc_irq_handle(int irq, void *data) 2559 { 2560 struct hclge_dev *hdev = data; 2561 u32 event_cause; 2562 u32 clearval; 2563 2564 hclge_enable_vector(&hdev->misc_vector, false); 2565 event_cause = hclge_check_event_cause(hdev, &clearval); 2566 2567 /* vector 0 interrupt is shared with reset and mailbox source events.*/ 2568 switch (event_cause) { 2569 case HCLGE_VECTOR0_EVENT_RST: 2570 hclge_reset_task_schedule(hdev); 2571 break; 2572 case HCLGE_VECTOR0_EVENT_MBX: 2573 /* If we are here then, 2574 * 1. Either we are not handling any mbx task and we are not 2575 * scheduled as well 2576 * OR 2577 * 2. We could be handling a mbx task but nothing more is 2578 * scheduled. 2579 * In both cases, we should schedule mbx task as there are more 2580 * mbx messages reported by this interrupt. 2581 */ 2582 hclge_mbx_task_schedule(hdev); 2583 2584 default: 2585 dev_dbg(&hdev->pdev->dev, 2586 "received unknown or unhandled event of vector0\n"); 2587 break; 2588 } 2589 2590 /* we should clear the source of interrupt */ 2591 hclge_clear_event_cause(hdev, event_cause, clearval); 2592 hclge_enable_vector(&hdev->misc_vector, true); 2593 2594 return IRQ_HANDLED; 2595 } 2596 2597 static void hclge_free_vector(struct hclge_dev *hdev, int vector_id) 2598 { 2599 hdev->vector_status[vector_id] = HCLGE_INVALID_VPORT; 2600 hdev->num_msi_left += 1; 2601 hdev->num_msi_used -= 1; 2602 } 2603 2604 static void hclge_get_misc_vector(struct hclge_dev *hdev) 2605 { 2606 struct hclge_misc_vector *vector = &hdev->misc_vector; 2607 2608 vector->vector_irq = pci_irq_vector(hdev->pdev, 0); 2609 2610 vector->addr = hdev->hw.io_base + HCLGE_MISC_VECTOR_REG_BASE; 2611 hdev->vector_status[0] = 0; 2612 2613 hdev->num_msi_left -= 1; 2614 hdev->num_msi_used += 1; 2615 } 2616 2617 static int hclge_misc_irq_init(struct hclge_dev *hdev) 2618 { 2619 int ret; 2620 2621 hclge_get_misc_vector(hdev); 2622 2623 /* this would be explicitly freed in the end */ 2624 ret = request_irq(hdev->misc_vector.vector_irq, hclge_misc_irq_handle, 2625 0, "hclge_misc", hdev); 2626 if (ret) { 2627 hclge_free_vector(hdev, 0); 2628 dev_err(&hdev->pdev->dev, "request misc irq(%d) fail\n", 2629 hdev->misc_vector.vector_irq); 2630 } 2631 2632 return ret; 2633 } 2634 2635 static void hclge_misc_irq_uninit(struct hclge_dev *hdev) 2636 { 2637 free_irq(hdev->misc_vector.vector_irq, hdev); 2638 hclge_free_vector(hdev, 0); 2639 } 2640 2641 static int hclge_notify_client(struct hclge_dev *hdev, 2642 enum hnae3_reset_notify_type type) 2643 { 2644 struct hnae3_client *client = hdev->nic_client; 2645 u16 i; 2646 2647 if (!client->ops->reset_notify) 2648 return -EOPNOTSUPP; 2649 2650 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) { 2651 struct hnae3_handle *handle = &hdev->vport[i].nic; 2652 int ret; 2653 2654 ret = client->ops->reset_notify(handle, type); 2655 if (ret) 2656 return ret; 2657 } 2658 2659 return 0; 2660 } 2661 2662 static int hclge_reset_wait(struct hclge_dev *hdev) 2663 { 2664 #define HCLGE_RESET_WATI_MS 100 2665 #define HCLGE_RESET_WAIT_CNT 5 2666 u32 val, reg, reg_bit; 2667 u32 cnt = 0; 2668 2669 switch (hdev->reset_type) { 2670 case HNAE3_GLOBAL_RESET: 2671 reg = HCLGE_GLOBAL_RESET_REG; 2672 reg_bit = HCLGE_GLOBAL_RESET_BIT; 2673 break; 2674 case HNAE3_CORE_RESET: 2675 reg = HCLGE_GLOBAL_RESET_REG; 2676 reg_bit = HCLGE_CORE_RESET_BIT; 2677 break; 2678 case HNAE3_FUNC_RESET: 2679 reg = HCLGE_FUN_RST_ING; 2680 reg_bit = HCLGE_FUN_RST_ING_B; 2681 break; 2682 default: 2683 dev_err(&hdev->pdev->dev, 2684 "Wait for unsupported reset type: %d\n", 2685 hdev->reset_type); 2686 return -EINVAL; 2687 } 2688 2689 val = hclge_read_dev(&hdev->hw, reg); 2690 while (hnae_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) { 2691 msleep(HCLGE_RESET_WATI_MS); 2692 val = hclge_read_dev(&hdev->hw, reg); 2693 cnt++; 2694 } 2695 2696 if (cnt >= HCLGE_RESET_WAIT_CNT) { 2697 dev_warn(&hdev->pdev->dev, 2698 "Wait for reset timeout: %d\n", hdev->reset_type); 2699 return -EBUSY; 2700 } 2701 2702 return 0; 2703 } 2704 2705 static int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id) 2706 { 2707 struct hclge_desc desc; 2708 struct hclge_reset_cmd *req = (struct hclge_reset_cmd *)desc.data; 2709 int ret; 2710 2711 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false); 2712 hnae_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_MAC_B, 0); 2713 hnae_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_FUNC_B, 1); 2714 req->fun_reset_vfid = func_id; 2715 2716 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2717 if (ret) 2718 dev_err(&hdev->pdev->dev, 2719 "send function reset cmd fail, status =%d\n", ret); 2720 2721 return ret; 2722 } 2723 2724 static void hclge_do_reset(struct hclge_dev *hdev) 2725 { 2726 struct pci_dev *pdev = hdev->pdev; 2727 u32 val; 2728 2729 switch (hdev->reset_type) { 2730 case HNAE3_GLOBAL_RESET: 2731 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG); 2732 hnae_set_bit(val, HCLGE_GLOBAL_RESET_BIT, 1); 2733 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val); 2734 dev_info(&pdev->dev, "Global Reset requested\n"); 2735 break; 2736 case HNAE3_CORE_RESET: 2737 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG); 2738 hnae_set_bit(val, HCLGE_CORE_RESET_BIT, 1); 2739 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val); 2740 dev_info(&pdev->dev, "Core Reset requested\n"); 2741 break; 2742 case HNAE3_FUNC_RESET: 2743 dev_info(&pdev->dev, "PF Reset requested\n"); 2744 hclge_func_reset_cmd(hdev, 0); 2745 /* schedule again to check later */ 2746 set_bit(HNAE3_FUNC_RESET, &hdev->reset_pending); 2747 hclge_reset_task_schedule(hdev); 2748 break; 2749 default: 2750 dev_warn(&pdev->dev, 2751 "Unsupported reset type: %d\n", hdev->reset_type); 2752 break; 2753 } 2754 } 2755 2756 static enum hnae3_reset_type hclge_get_reset_level(struct hclge_dev *hdev, 2757 unsigned long *addr) 2758 { 2759 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 2760 2761 /* return the highest priority reset level amongst all */ 2762 if (test_bit(HNAE3_GLOBAL_RESET, addr)) 2763 rst_level = HNAE3_GLOBAL_RESET; 2764 else if (test_bit(HNAE3_CORE_RESET, addr)) 2765 rst_level = HNAE3_CORE_RESET; 2766 else if (test_bit(HNAE3_IMP_RESET, addr)) 2767 rst_level = HNAE3_IMP_RESET; 2768 else if (test_bit(HNAE3_FUNC_RESET, addr)) 2769 rst_level = HNAE3_FUNC_RESET; 2770 2771 /* now, clear all other resets */ 2772 clear_bit(HNAE3_GLOBAL_RESET, addr); 2773 clear_bit(HNAE3_CORE_RESET, addr); 2774 clear_bit(HNAE3_IMP_RESET, addr); 2775 clear_bit(HNAE3_FUNC_RESET, addr); 2776 2777 return rst_level; 2778 } 2779 2780 static void hclge_reset(struct hclge_dev *hdev) 2781 { 2782 /* perform reset of the stack & ae device for a client */ 2783 2784 hclge_notify_client(hdev, HNAE3_DOWN_CLIENT); 2785 2786 if (!hclge_reset_wait(hdev)) { 2787 rtnl_lock(); 2788 hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT); 2789 hclge_reset_ae_dev(hdev->ae_dev); 2790 hclge_notify_client(hdev, HNAE3_INIT_CLIENT); 2791 rtnl_unlock(); 2792 } else { 2793 /* schedule again to check pending resets later */ 2794 set_bit(hdev->reset_type, &hdev->reset_pending); 2795 hclge_reset_task_schedule(hdev); 2796 } 2797 2798 hclge_notify_client(hdev, HNAE3_UP_CLIENT); 2799 } 2800 2801 static void hclge_reset_event(struct hnae3_handle *handle, 2802 enum hnae3_reset_type reset) 2803 { 2804 struct hclge_vport *vport = hclge_get_vport(handle); 2805 struct hclge_dev *hdev = vport->back; 2806 2807 dev_info(&hdev->pdev->dev, 2808 "Receive reset event , reset_type is %d", reset); 2809 2810 switch (reset) { 2811 case HNAE3_FUNC_RESET: 2812 case HNAE3_CORE_RESET: 2813 case HNAE3_GLOBAL_RESET: 2814 /* request reset & schedule reset task */ 2815 set_bit(reset, &hdev->reset_request); 2816 hclge_reset_task_schedule(hdev); 2817 break; 2818 default: 2819 dev_warn(&hdev->pdev->dev, "Unsupported reset event:%d", reset); 2820 break; 2821 } 2822 } 2823 2824 static void hclge_reset_subtask(struct hclge_dev *hdev) 2825 { 2826 /* check if there is any ongoing reset in the hardware. This status can 2827 * be checked from reset_pending. If there is then, we need to wait for 2828 * hardware to complete reset. 2829 * a. If we are able to figure out in reasonable time that hardware 2830 * has fully resetted then, we can proceed with driver, client 2831 * reset. 2832 * b. else, we can come back later to check this status so re-sched 2833 * now. 2834 */ 2835 hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_pending); 2836 if (hdev->reset_type != HNAE3_NONE_RESET) 2837 hclge_reset(hdev); 2838 2839 /* check if we got any *new* reset requests to be honored */ 2840 hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_request); 2841 if (hdev->reset_type != HNAE3_NONE_RESET) 2842 hclge_do_reset(hdev); 2843 2844 hdev->reset_type = HNAE3_NONE_RESET; 2845 } 2846 2847 static void hclge_reset_service_task(struct work_struct *work) 2848 { 2849 struct hclge_dev *hdev = 2850 container_of(work, struct hclge_dev, rst_service_task); 2851 2852 if (test_and_set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 2853 return; 2854 2855 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state); 2856 2857 hclge_reset_subtask(hdev); 2858 2859 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 2860 } 2861 2862 static void hclge_mailbox_service_task(struct work_struct *work) 2863 { 2864 struct hclge_dev *hdev = 2865 container_of(work, struct hclge_dev, mbx_service_task); 2866 2867 if (test_and_set_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state)) 2868 return; 2869 2870 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state); 2871 2872 hclge_mbx_handler(hdev); 2873 2874 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state); 2875 } 2876 2877 static void hclge_service_task(struct work_struct *work) 2878 { 2879 struct hclge_dev *hdev = 2880 container_of(work, struct hclge_dev, service_task); 2881 2882 /* The total rx/tx packets statstics are wanted to be updated 2883 * per second. Both hclge_update_stats_for_all() and 2884 * hclge_mac_get_traffic_stats() can do it. 2885 */ 2886 if (hdev->hw_stats.stats_timer >= HCLGE_STATS_TIMER_INTERVAL) { 2887 hclge_update_stats_for_all(hdev); 2888 hdev->hw_stats.stats_timer = 0; 2889 } else { 2890 hclge_mac_get_traffic_stats(hdev); 2891 } 2892 2893 hclge_update_speed_duplex(hdev); 2894 hclge_update_link_status(hdev); 2895 hclge_update_led_status(hdev); 2896 hclge_service_complete(hdev); 2897 } 2898 2899 static void hclge_disable_sriov(struct hclge_dev *hdev) 2900 { 2901 /* If our VFs are assigned we cannot shut down SR-IOV 2902 * without causing issues, so just leave the hardware 2903 * available but disabled 2904 */ 2905 if (pci_vfs_assigned(hdev->pdev)) { 2906 dev_warn(&hdev->pdev->dev, 2907 "disabling driver while VFs are assigned\n"); 2908 return; 2909 } 2910 2911 pci_disable_sriov(hdev->pdev); 2912 } 2913 2914 struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle) 2915 { 2916 /* VF handle has no client */ 2917 if (!handle->client) 2918 return container_of(handle, struct hclge_vport, nic); 2919 else if (handle->client->type == HNAE3_CLIENT_ROCE) 2920 return container_of(handle, struct hclge_vport, roce); 2921 else 2922 return container_of(handle, struct hclge_vport, nic); 2923 } 2924 2925 static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num, 2926 struct hnae3_vector_info *vector_info) 2927 { 2928 struct hclge_vport *vport = hclge_get_vport(handle); 2929 struct hnae3_vector_info *vector = vector_info; 2930 struct hclge_dev *hdev = vport->back; 2931 int alloc = 0; 2932 int i, j; 2933 2934 vector_num = min(hdev->num_msi_left, vector_num); 2935 2936 for (j = 0; j < vector_num; j++) { 2937 for (i = 1; i < hdev->num_msi; i++) { 2938 if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) { 2939 vector->vector = pci_irq_vector(hdev->pdev, i); 2940 vector->io_addr = hdev->hw.io_base + 2941 HCLGE_VECTOR_REG_BASE + 2942 (i - 1) * HCLGE_VECTOR_REG_OFFSET + 2943 vport->vport_id * 2944 HCLGE_VECTOR_VF_OFFSET; 2945 hdev->vector_status[i] = vport->vport_id; 2946 hdev->vector_irq[i] = vector->vector; 2947 2948 vector++; 2949 alloc++; 2950 2951 break; 2952 } 2953 } 2954 } 2955 hdev->num_msi_left -= alloc; 2956 hdev->num_msi_used += alloc; 2957 2958 return alloc; 2959 } 2960 2961 static int hclge_get_vector_index(struct hclge_dev *hdev, int vector) 2962 { 2963 int i; 2964 2965 for (i = 0; i < hdev->num_msi; i++) 2966 if (vector == hdev->vector_irq[i]) 2967 return i; 2968 2969 return -EINVAL; 2970 } 2971 2972 static u32 hclge_get_rss_key_size(struct hnae3_handle *handle) 2973 { 2974 return HCLGE_RSS_KEY_SIZE; 2975 } 2976 2977 static u32 hclge_get_rss_indir_size(struct hnae3_handle *handle) 2978 { 2979 return HCLGE_RSS_IND_TBL_SIZE; 2980 } 2981 2982 static int hclge_get_rss_algo(struct hclge_dev *hdev) 2983 { 2984 struct hclge_rss_config_cmd *req; 2985 struct hclge_desc desc; 2986 int rss_hash_algo; 2987 int ret; 2988 2989 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_GENERIC_CONFIG, true); 2990 2991 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2992 if (ret) { 2993 dev_err(&hdev->pdev->dev, 2994 "Get link status error, status =%d\n", ret); 2995 return ret; 2996 } 2997 2998 req = (struct hclge_rss_config_cmd *)desc.data; 2999 rss_hash_algo = (req->hash_config & HCLGE_RSS_HASH_ALGO_MASK); 3000 3001 if (rss_hash_algo == HCLGE_RSS_HASH_ALGO_TOEPLITZ) 3002 return ETH_RSS_HASH_TOP; 3003 3004 return -EINVAL; 3005 } 3006 3007 static int hclge_set_rss_algo_key(struct hclge_dev *hdev, 3008 const u8 hfunc, const u8 *key) 3009 { 3010 struct hclge_rss_config_cmd *req; 3011 struct hclge_desc desc; 3012 int key_offset; 3013 int key_size; 3014 int ret; 3015 3016 req = (struct hclge_rss_config_cmd *)desc.data; 3017 3018 for (key_offset = 0; key_offset < 3; key_offset++) { 3019 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_GENERIC_CONFIG, 3020 false); 3021 3022 req->hash_config |= (hfunc & HCLGE_RSS_HASH_ALGO_MASK); 3023 req->hash_config |= (key_offset << HCLGE_RSS_HASH_KEY_OFFSET_B); 3024 3025 if (key_offset == 2) 3026 key_size = 3027 HCLGE_RSS_KEY_SIZE - HCLGE_RSS_HASH_KEY_NUM * 2; 3028 else 3029 key_size = HCLGE_RSS_HASH_KEY_NUM; 3030 3031 memcpy(req->hash_key, 3032 key + key_offset * HCLGE_RSS_HASH_KEY_NUM, key_size); 3033 3034 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3035 if (ret) { 3036 dev_err(&hdev->pdev->dev, 3037 "Configure RSS config fail, status = %d\n", 3038 ret); 3039 return ret; 3040 } 3041 } 3042 return 0; 3043 } 3044 3045 static int hclge_set_rss_indir_table(struct hclge_dev *hdev, const u32 *indir) 3046 { 3047 struct hclge_rss_indirection_table_cmd *req; 3048 struct hclge_desc desc; 3049 int i, j; 3050 int ret; 3051 3052 req = (struct hclge_rss_indirection_table_cmd *)desc.data; 3053 3054 for (i = 0; i < HCLGE_RSS_CFG_TBL_NUM; i++) { 3055 hclge_cmd_setup_basic_desc 3056 (&desc, HCLGE_OPC_RSS_INDIR_TABLE, false); 3057 3058 req->start_table_index = 3059 cpu_to_le16(i * HCLGE_RSS_CFG_TBL_SIZE); 3060 req->rss_set_bitmap = cpu_to_le16(HCLGE_RSS_SET_BITMAP_MSK); 3061 3062 for (j = 0; j < HCLGE_RSS_CFG_TBL_SIZE; j++) 3063 req->rss_result[j] = 3064 indir[i * HCLGE_RSS_CFG_TBL_SIZE + j]; 3065 3066 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3067 if (ret) { 3068 dev_err(&hdev->pdev->dev, 3069 "Configure rss indir table fail,status = %d\n", 3070 ret); 3071 return ret; 3072 } 3073 } 3074 return 0; 3075 } 3076 3077 static int hclge_set_rss_tc_mode(struct hclge_dev *hdev, u16 *tc_valid, 3078 u16 *tc_size, u16 *tc_offset) 3079 { 3080 struct hclge_rss_tc_mode_cmd *req; 3081 struct hclge_desc desc; 3082 int ret; 3083 int i; 3084 3085 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_TC_MODE, false); 3086 req = (struct hclge_rss_tc_mode_cmd *)desc.data; 3087 3088 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 3089 u16 mode = 0; 3090 3091 hnae_set_bit(mode, HCLGE_RSS_TC_VALID_B, (tc_valid[i] & 0x1)); 3092 hnae_set_field(mode, HCLGE_RSS_TC_SIZE_M, 3093 HCLGE_RSS_TC_SIZE_S, tc_size[i]); 3094 hnae_set_field(mode, HCLGE_RSS_TC_OFFSET_M, 3095 HCLGE_RSS_TC_OFFSET_S, tc_offset[i]); 3096 3097 req->rss_tc_mode[i] = cpu_to_le16(mode); 3098 } 3099 3100 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3101 if (ret) { 3102 dev_err(&hdev->pdev->dev, 3103 "Configure rss tc mode fail, status = %d\n", ret); 3104 return ret; 3105 } 3106 3107 return 0; 3108 } 3109 3110 static int hclge_set_rss_input_tuple(struct hclge_dev *hdev) 3111 { 3112 struct hclge_rss_input_tuple_cmd *req; 3113 struct hclge_desc desc; 3114 int ret; 3115 3116 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false); 3117 3118 req = (struct hclge_rss_input_tuple_cmd *)desc.data; 3119 req->ipv4_tcp_en = HCLGE_RSS_INPUT_TUPLE_OTHER; 3120 req->ipv4_udp_en = HCLGE_RSS_INPUT_TUPLE_OTHER; 3121 req->ipv4_sctp_en = HCLGE_RSS_INPUT_TUPLE_SCTP; 3122 req->ipv4_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER; 3123 req->ipv6_tcp_en = HCLGE_RSS_INPUT_TUPLE_OTHER; 3124 req->ipv6_udp_en = HCLGE_RSS_INPUT_TUPLE_OTHER; 3125 req->ipv6_sctp_en = HCLGE_RSS_INPUT_TUPLE_SCTP; 3126 req->ipv6_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER; 3127 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3128 if (ret) { 3129 dev_err(&hdev->pdev->dev, 3130 "Configure rss input fail, status = %d\n", ret); 3131 return ret; 3132 } 3133 3134 return 0; 3135 } 3136 3137 static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir, 3138 u8 *key, u8 *hfunc) 3139 { 3140 struct hclge_vport *vport = hclge_get_vport(handle); 3141 struct hclge_dev *hdev = vport->back; 3142 int i; 3143 3144 /* Get hash algorithm */ 3145 if (hfunc) 3146 *hfunc = hclge_get_rss_algo(hdev); 3147 3148 /* Get the RSS Key required by the user */ 3149 if (key) 3150 memcpy(key, vport->rss_hash_key, HCLGE_RSS_KEY_SIZE); 3151 3152 /* Get indirect table */ 3153 if (indir) 3154 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++) 3155 indir[i] = vport->rss_indirection_tbl[i]; 3156 3157 return 0; 3158 } 3159 3160 static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir, 3161 const u8 *key, const u8 hfunc) 3162 { 3163 struct hclge_vport *vport = hclge_get_vport(handle); 3164 struct hclge_dev *hdev = vport->back; 3165 u8 hash_algo; 3166 int ret, i; 3167 3168 /* Set the RSS Hash Key if specififed by the user */ 3169 if (key) { 3170 /* Update the shadow RSS key with user specified qids */ 3171 memcpy(vport->rss_hash_key, key, HCLGE_RSS_KEY_SIZE); 3172 3173 if (hfunc == ETH_RSS_HASH_TOP || 3174 hfunc == ETH_RSS_HASH_NO_CHANGE) 3175 hash_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ; 3176 else 3177 return -EINVAL; 3178 ret = hclge_set_rss_algo_key(hdev, hash_algo, key); 3179 if (ret) 3180 return ret; 3181 } 3182 3183 /* Update the shadow RSS table with user specified qids */ 3184 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++) 3185 vport->rss_indirection_tbl[i] = indir[i]; 3186 3187 /* Update the hardware */ 3188 ret = hclge_set_rss_indir_table(hdev, indir); 3189 return ret; 3190 } 3191 3192 static u8 hclge_get_rss_hash_bits(struct ethtool_rxnfc *nfc) 3193 { 3194 u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGE_S_PORT_BIT : 0; 3195 3196 if (nfc->data & RXH_L4_B_2_3) 3197 hash_sets |= HCLGE_D_PORT_BIT; 3198 else 3199 hash_sets &= ~HCLGE_D_PORT_BIT; 3200 3201 if (nfc->data & RXH_IP_SRC) 3202 hash_sets |= HCLGE_S_IP_BIT; 3203 else 3204 hash_sets &= ~HCLGE_S_IP_BIT; 3205 3206 if (nfc->data & RXH_IP_DST) 3207 hash_sets |= HCLGE_D_IP_BIT; 3208 else 3209 hash_sets &= ~HCLGE_D_IP_BIT; 3210 3211 if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW) 3212 hash_sets |= HCLGE_V_TAG_BIT; 3213 3214 return hash_sets; 3215 } 3216 3217 static int hclge_set_rss_tuple(struct hnae3_handle *handle, 3218 struct ethtool_rxnfc *nfc) 3219 { 3220 struct hclge_vport *vport = hclge_get_vport(handle); 3221 struct hclge_dev *hdev = vport->back; 3222 struct hclge_rss_input_tuple_cmd *req; 3223 struct hclge_desc desc; 3224 u8 tuple_sets; 3225 int ret; 3226 3227 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST | 3228 RXH_L4_B_0_1 | RXH_L4_B_2_3)) 3229 return -EINVAL; 3230 3231 req = (struct hclge_rss_input_tuple_cmd *)desc.data; 3232 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, true); 3233 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3234 if (ret) { 3235 dev_err(&hdev->pdev->dev, 3236 "Read rss tuple fail, status = %d\n", ret); 3237 return ret; 3238 } 3239 3240 hclge_cmd_reuse_desc(&desc, false); 3241 3242 tuple_sets = hclge_get_rss_hash_bits(nfc); 3243 switch (nfc->flow_type) { 3244 case TCP_V4_FLOW: 3245 req->ipv4_tcp_en = tuple_sets; 3246 break; 3247 case TCP_V6_FLOW: 3248 req->ipv6_tcp_en = tuple_sets; 3249 break; 3250 case UDP_V4_FLOW: 3251 req->ipv4_udp_en = tuple_sets; 3252 break; 3253 case UDP_V6_FLOW: 3254 req->ipv6_udp_en = tuple_sets; 3255 break; 3256 case SCTP_V4_FLOW: 3257 req->ipv4_sctp_en = tuple_sets; 3258 break; 3259 case SCTP_V6_FLOW: 3260 if ((nfc->data & RXH_L4_B_0_1) || 3261 (nfc->data & RXH_L4_B_2_3)) 3262 return -EINVAL; 3263 3264 req->ipv6_sctp_en = tuple_sets; 3265 break; 3266 case IPV4_FLOW: 3267 req->ipv4_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER; 3268 break; 3269 case IPV6_FLOW: 3270 req->ipv6_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER; 3271 break; 3272 default: 3273 return -EINVAL; 3274 } 3275 3276 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3277 if (ret) 3278 dev_err(&hdev->pdev->dev, 3279 "Set rss tuple fail, status = %d\n", ret); 3280 3281 return ret; 3282 } 3283 3284 static int hclge_get_rss_tuple(struct hnae3_handle *handle, 3285 struct ethtool_rxnfc *nfc) 3286 { 3287 struct hclge_vport *vport = hclge_get_vport(handle); 3288 struct hclge_dev *hdev = vport->back; 3289 struct hclge_rss_input_tuple_cmd *req; 3290 struct hclge_desc desc; 3291 u8 tuple_sets; 3292 int ret; 3293 3294 nfc->data = 0; 3295 3296 req = (struct hclge_rss_input_tuple_cmd *)desc.data; 3297 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, true); 3298 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3299 if (ret) { 3300 dev_err(&hdev->pdev->dev, 3301 "Read rss tuple fail, status = %d\n", ret); 3302 return ret; 3303 } 3304 3305 switch (nfc->flow_type) { 3306 case TCP_V4_FLOW: 3307 tuple_sets = req->ipv4_tcp_en; 3308 break; 3309 case UDP_V4_FLOW: 3310 tuple_sets = req->ipv4_udp_en; 3311 break; 3312 case TCP_V6_FLOW: 3313 tuple_sets = req->ipv6_tcp_en; 3314 break; 3315 case UDP_V6_FLOW: 3316 tuple_sets = req->ipv6_udp_en; 3317 break; 3318 case SCTP_V4_FLOW: 3319 tuple_sets = req->ipv4_sctp_en; 3320 break; 3321 case SCTP_V6_FLOW: 3322 tuple_sets = req->ipv6_sctp_en; 3323 break; 3324 case IPV4_FLOW: 3325 case IPV6_FLOW: 3326 tuple_sets = HCLGE_S_IP_BIT | HCLGE_D_IP_BIT; 3327 break; 3328 default: 3329 return -EINVAL; 3330 } 3331 3332 if (!tuple_sets) 3333 return 0; 3334 3335 if (tuple_sets & HCLGE_D_PORT_BIT) 3336 nfc->data |= RXH_L4_B_2_3; 3337 if (tuple_sets & HCLGE_S_PORT_BIT) 3338 nfc->data |= RXH_L4_B_0_1; 3339 if (tuple_sets & HCLGE_D_IP_BIT) 3340 nfc->data |= RXH_IP_DST; 3341 if (tuple_sets & HCLGE_S_IP_BIT) 3342 nfc->data |= RXH_IP_SRC; 3343 3344 return 0; 3345 } 3346 3347 static int hclge_get_tc_size(struct hnae3_handle *handle) 3348 { 3349 struct hclge_vport *vport = hclge_get_vport(handle); 3350 struct hclge_dev *hdev = vport->back; 3351 3352 return hdev->rss_size_max; 3353 } 3354 3355 int hclge_rss_init_hw(struct hclge_dev *hdev) 3356 { 3357 const u8 hfunc = HCLGE_RSS_HASH_ALGO_TOEPLITZ; 3358 struct hclge_vport *vport = hdev->vport; 3359 u16 tc_offset[HCLGE_MAX_TC_NUM]; 3360 u8 rss_key[HCLGE_RSS_KEY_SIZE]; 3361 u16 tc_valid[HCLGE_MAX_TC_NUM]; 3362 u16 tc_size[HCLGE_MAX_TC_NUM]; 3363 u32 *rss_indir = NULL; 3364 u16 rss_size = 0, roundup_size; 3365 const u8 *key; 3366 int i, ret, j; 3367 3368 rss_indir = kcalloc(HCLGE_RSS_IND_TBL_SIZE, sizeof(u32), GFP_KERNEL); 3369 if (!rss_indir) 3370 return -ENOMEM; 3371 3372 /* Get default RSS key */ 3373 netdev_rss_key_fill(rss_key, HCLGE_RSS_KEY_SIZE); 3374 3375 /* Initialize RSS indirect table for each vport */ 3376 for (j = 0; j < hdev->num_vmdq_vport + 1; j++) { 3377 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++) { 3378 vport[j].rss_indirection_tbl[i] = 3379 i % vport[j].alloc_rss_size; 3380 3381 /* vport 0 is for PF */ 3382 if (j != 0) 3383 continue; 3384 3385 rss_size = vport[j].alloc_rss_size; 3386 rss_indir[i] = vport[j].rss_indirection_tbl[i]; 3387 } 3388 } 3389 ret = hclge_set_rss_indir_table(hdev, rss_indir); 3390 if (ret) 3391 goto err; 3392 3393 key = rss_key; 3394 ret = hclge_set_rss_algo_key(hdev, hfunc, key); 3395 if (ret) 3396 goto err; 3397 3398 ret = hclge_set_rss_input_tuple(hdev); 3399 if (ret) 3400 goto err; 3401 3402 /* Each TC have the same queue size, and tc_size set to hardware is 3403 * the log2 of roundup power of two of rss_size, the acutal queue 3404 * size is limited by indirection table. 3405 */ 3406 if (rss_size > HCLGE_RSS_TC_SIZE_7 || rss_size == 0) { 3407 dev_err(&hdev->pdev->dev, 3408 "Configure rss tc size failed, invalid TC_SIZE = %d\n", 3409 rss_size); 3410 ret = -EINVAL; 3411 goto err; 3412 } 3413 3414 roundup_size = roundup_pow_of_two(rss_size); 3415 roundup_size = ilog2(roundup_size); 3416 3417 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 3418 tc_valid[i] = 0; 3419 3420 if (!(hdev->hw_tc_map & BIT(i))) 3421 continue; 3422 3423 tc_valid[i] = 1; 3424 tc_size[i] = roundup_size; 3425 tc_offset[i] = rss_size * i; 3426 } 3427 3428 ret = hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset); 3429 3430 err: 3431 kfree(rss_indir); 3432 3433 return ret; 3434 } 3435 3436 int hclge_bind_ring_with_vector(struct hclge_vport *vport, 3437 int vector_id, bool en, 3438 struct hnae3_ring_chain_node *ring_chain) 3439 { 3440 struct hclge_dev *hdev = vport->back; 3441 struct hnae3_ring_chain_node *node; 3442 struct hclge_desc desc; 3443 struct hclge_ctrl_vector_chain_cmd *req 3444 = (struct hclge_ctrl_vector_chain_cmd *)desc.data; 3445 enum hclge_cmd_status status; 3446 enum hclge_opcode_type op; 3447 u16 tqp_type_and_id; 3448 int i; 3449 3450 op = en ? HCLGE_OPC_ADD_RING_TO_VECTOR : HCLGE_OPC_DEL_RING_TO_VECTOR; 3451 hclge_cmd_setup_basic_desc(&desc, op, false); 3452 req->int_vector_id = vector_id; 3453 3454 i = 0; 3455 for (node = ring_chain; node; node = node->next) { 3456 tqp_type_and_id = le16_to_cpu(req->tqp_type_and_id[i]); 3457 hnae_set_field(tqp_type_and_id, HCLGE_INT_TYPE_M, 3458 HCLGE_INT_TYPE_S, 3459 hnae_get_bit(node->flag, HNAE3_RING_TYPE_B)); 3460 hnae_set_field(tqp_type_and_id, HCLGE_TQP_ID_M, 3461 HCLGE_TQP_ID_S, node->tqp_index); 3462 hnae_set_field(tqp_type_and_id, HCLGE_INT_GL_IDX_M, 3463 HCLGE_INT_GL_IDX_S, 3464 hnae_get_field(node->int_gl_idx, 3465 HNAE3_RING_GL_IDX_M, 3466 HNAE3_RING_GL_IDX_S)); 3467 req->tqp_type_and_id[i] = cpu_to_le16(tqp_type_and_id); 3468 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) { 3469 req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD; 3470 req->vfid = vport->vport_id; 3471 3472 status = hclge_cmd_send(&hdev->hw, &desc, 1); 3473 if (status) { 3474 dev_err(&hdev->pdev->dev, 3475 "Map TQP fail, status is %d.\n", 3476 status); 3477 return -EIO; 3478 } 3479 i = 0; 3480 3481 hclge_cmd_setup_basic_desc(&desc, 3482 op, 3483 false); 3484 req->int_vector_id = vector_id; 3485 } 3486 } 3487 3488 if (i > 0) { 3489 req->int_cause_num = i; 3490 req->vfid = vport->vport_id; 3491 status = hclge_cmd_send(&hdev->hw, &desc, 1); 3492 if (status) { 3493 dev_err(&hdev->pdev->dev, 3494 "Map TQP fail, status is %d.\n", status); 3495 return -EIO; 3496 } 3497 } 3498 3499 return 0; 3500 } 3501 3502 static int hclge_map_ring_to_vector(struct hnae3_handle *handle, 3503 int vector, 3504 struct hnae3_ring_chain_node *ring_chain) 3505 { 3506 struct hclge_vport *vport = hclge_get_vport(handle); 3507 struct hclge_dev *hdev = vport->back; 3508 int vector_id; 3509 3510 vector_id = hclge_get_vector_index(hdev, vector); 3511 if (vector_id < 0) { 3512 dev_err(&hdev->pdev->dev, 3513 "Get vector index fail. vector_id =%d\n", vector_id); 3514 return vector_id; 3515 } 3516 3517 return hclge_bind_ring_with_vector(vport, vector_id, true, ring_chain); 3518 } 3519 3520 static int hclge_unmap_ring_frm_vector(struct hnae3_handle *handle, 3521 int vector, 3522 struct hnae3_ring_chain_node *ring_chain) 3523 { 3524 struct hclge_vport *vport = hclge_get_vport(handle); 3525 struct hclge_dev *hdev = vport->back; 3526 int vector_id, ret; 3527 3528 vector_id = hclge_get_vector_index(hdev, vector); 3529 if (vector_id < 0) { 3530 dev_err(&handle->pdev->dev, 3531 "Get vector index fail. ret =%d\n", vector_id); 3532 return vector_id; 3533 } 3534 3535 ret = hclge_bind_ring_with_vector(vport, vector_id, false, ring_chain); 3536 if (ret) { 3537 dev_err(&handle->pdev->dev, 3538 "Unmap ring from vector fail. vectorid=%d, ret =%d\n", 3539 vector_id, 3540 ret); 3541 return ret; 3542 } 3543 3544 /* Free this MSIX or MSI vector */ 3545 hclge_free_vector(hdev, vector_id); 3546 3547 return 0; 3548 } 3549 3550 int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev, 3551 struct hclge_promisc_param *param) 3552 { 3553 struct hclge_promisc_cfg_cmd *req; 3554 struct hclge_desc desc; 3555 int ret; 3556 3557 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PROMISC_MODE, false); 3558 3559 req = (struct hclge_promisc_cfg_cmd *)desc.data; 3560 req->vf_id = param->vf_id; 3561 req->flag = (param->enable << HCLGE_PROMISC_EN_B); 3562 3563 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3564 if (ret) { 3565 dev_err(&hdev->pdev->dev, 3566 "Set promisc mode fail, status is %d.\n", ret); 3567 return ret; 3568 } 3569 return 0; 3570 } 3571 3572 void hclge_promisc_param_init(struct hclge_promisc_param *param, bool en_uc, 3573 bool en_mc, bool en_bc, int vport_id) 3574 { 3575 if (!param) 3576 return; 3577 3578 memset(param, 0, sizeof(struct hclge_promisc_param)); 3579 if (en_uc) 3580 param->enable = HCLGE_PROMISC_EN_UC; 3581 if (en_mc) 3582 param->enable |= HCLGE_PROMISC_EN_MC; 3583 if (en_bc) 3584 param->enable |= HCLGE_PROMISC_EN_BC; 3585 param->vf_id = vport_id; 3586 } 3587 3588 static void hclge_set_promisc_mode(struct hnae3_handle *handle, u32 en) 3589 { 3590 struct hclge_vport *vport = hclge_get_vport(handle); 3591 struct hclge_dev *hdev = vport->back; 3592 struct hclge_promisc_param param; 3593 3594 hclge_promisc_param_init(¶m, en, en, true, vport->vport_id); 3595 hclge_cmd_set_promisc_mode(hdev, ¶m); 3596 } 3597 3598 static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable) 3599 { 3600 struct hclge_desc desc; 3601 struct hclge_config_mac_mode_cmd *req = 3602 (struct hclge_config_mac_mode_cmd *)desc.data; 3603 u32 loop_en = 0; 3604 int ret; 3605 3606 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false); 3607 hnae_set_bit(loop_en, HCLGE_MAC_TX_EN_B, enable); 3608 hnae_set_bit(loop_en, HCLGE_MAC_RX_EN_B, enable); 3609 hnae_set_bit(loop_en, HCLGE_MAC_PAD_TX_B, enable); 3610 hnae_set_bit(loop_en, HCLGE_MAC_PAD_RX_B, enable); 3611 hnae_set_bit(loop_en, HCLGE_MAC_1588_TX_B, 0); 3612 hnae_set_bit(loop_en, HCLGE_MAC_1588_RX_B, 0); 3613 hnae_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 0); 3614 hnae_set_bit(loop_en, HCLGE_MAC_LINE_LP_B, 0); 3615 hnae_set_bit(loop_en, HCLGE_MAC_FCS_TX_B, enable); 3616 hnae_set_bit(loop_en, HCLGE_MAC_RX_FCS_B, enable); 3617 hnae_set_bit(loop_en, HCLGE_MAC_RX_FCS_STRIP_B, enable); 3618 hnae_set_bit(loop_en, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, enable); 3619 hnae_set_bit(loop_en, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, enable); 3620 hnae_set_bit(loop_en, HCLGE_MAC_TX_UNDER_MIN_ERR_B, enable); 3621 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en); 3622 3623 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3624 if (ret) 3625 dev_err(&hdev->pdev->dev, 3626 "mac enable fail, ret =%d.\n", ret); 3627 } 3628 3629 static int hclge_set_loopback(struct hnae3_handle *handle, 3630 enum hnae3_loop loop_mode, bool en) 3631 { 3632 struct hclge_vport *vport = hclge_get_vport(handle); 3633 struct hclge_config_mac_mode_cmd *req; 3634 struct hclge_dev *hdev = vport->back; 3635 struct hclge_desc desc; 3636 u32 loop_en; 3637 int ret; 3638 3639 switch (loop_mode) { 3640 case HNAE3_MAC_INTER_LOOP_MAC: 3641 req = (struct hclge_config_mac_mode_cmd *)&desc.data[0]; 3642 /* 1 Read out the MAC mode config at first */ 3643 hclge_cmd_setup_basic_desc(&desc, 3644 HCLGE_OPC_CONFIG_MAC_MODE, 3645 true); 3646 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3647 if (ret) { 3648 dev_err(&hdev->pdev->dev, 3649 "mac loopback get fail, ret =%d.\n", 3650 ret); 3651 return ret; 3652 } 3653 3654 /* 2 Then setup the loopback flag */ 3655 loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en); 3656 if (en) 3657 hnae_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 1); 3658 else 3659 hnae_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 0); 3660 3661 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en); 3662 3663 /* 3 Config mac work mode with loopback flag 3664 * and its original configure parameters 3665 */ 3666 hclge_cmd_reuse_desc(&desc, false); 3667 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3668 if (ret) 3669 dev_err(&hdev->pdev->dev, 3670 "mac loopback set fail, ret =%d.\n", ret); 3671 break; 3672 default: 3673 ret = -ENOTSUPP; 3674 dev_err(&hdev->pdev->dev, 3675 "loop_mode %d is not supported\n", loop_mode); 3676 break; 3677 } 3678 3679 return ret; 3680 } 3681 3682 static int hclge_tqp_enable(struct hclge_dev *hdev, int tqp_id, 3683 int stream_id, bool enable) 3684 { 3685 struct hclge_desc desc; 3686 struct hclge_cfg_com_tqp_queue_cmd *req = 3687 (struct hclge_cfg_com_tqp_queue_cmd *)desc.data; 3688 int ret; 3689 3690 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false); 3691 req->tqp_id = cpu_to_le16(tqp_id & HCLGE_RING_ID_MASK); 3692 req->stream_id = cpu_to_le16(stream_id); 3693 req->enable |= enable << HCLGE_TQP_ENABLE_B; 3694 3695 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3696 if (ret) 3697 dev_err(&hdev->pdev->dev, 3698 "Tqp enable fail, status =%d.\n", ret); 3699 return ret; 3700 } 3701 3702 static void hclge_reset_tqp_stats(struct hnae3_handle *handle) 3703 { 3704 struct hclge_vport *vport = hclge_get_vport(handle); 3705 struct hnae3_queue *queue; 3706 struct hclge_tqp *tqp; 3707 int i; 3708 3709 for (i = 0; i < vport->alloc_tqps; i++) { 3710 queue = handle->kinfo.tqp[i]; 3711 tqp = container_of(queue, struct hclge_tqp, q); 3712 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats)); 3713 } 3714 } 3715 3716 static int hclge_ae_start(struct hnae3_handle *handle) 3717 { 3718 struct hclge_vport *vport = hclge_get_vport(handle); 3719 struct hclge_dev *hdev = vport->back; 3720 int i, queue_id, ret; 3721 3722 for (i = 0; i < vport->alloc_tqps; i++) { 3723 /* todo clear interrupt */ 3724 /* ring enable */ 3725 queue_id = hclge_get_queue_id(handle->kinfo.tqp[i]); 3726 if (queue_id < 0) { 3727 dev_warn(&hdev->pdev->dev, 3728 "Get invalid queue id, ignore it\n"); 3729 continue; 3730 } 3731 3732 hclge_tqp_enable(hdev, queue_id, 0, true); 3733 } 3734 /* mac enable */ 3735 hclge_cfg_mac_mode(hdev, true); 3736 clear_bit(HCLGE_STATE_DOWN, &hdev->state); 3737 mod_timer(&hdev->service_timer, jiffies + HZ); 3738 3739 ret = hclge_mac_start_phy(hdev); 3740 if (ret) 3741 return ret; 3742 3743 /* reset tqp stats */ 3744 hclge_reset_tqp_stats(handle); 3745 3746 return 0; 3747 } 3748 3749 static void hclge_ae_stop(struct hnae3_handle *handle) 3750 { 3751 struct hclge_vport *vport = hclge_get_vport(handle); 3752 struct hclge_dev *hdev = vport->back; 3753 int i, queue_id; 3754 3755 for (i = 0; i < vport->alloc_tqps; i++) { 3756 /* Ring disable */ 3757 queue_id = hclge_get_queue_id(handle->kinfo.tqp[i]); 3758 if (queue_id < 0) { 3759 dev_warn(&hdev->pdev->dev, 3760 "Get invalid queue id, ignore it\n"); 3761 continue; 3762 } 3763 3764 hclge_tqp_enable(hdev, queue_id, 0, false); 3765 } 3766 /* Mac disable */ 3767 hclge_cfg_mac_mode(hdev, false); 3768 3769 hclge_mac_stop_phy(hdev); 3770 3771 /* reset tqp stats */ 3772 hclge_reset_tqp_stats(handle); 3773 } 3774 3775 static int hclge_get_mac_vlan_cmd_status(struct hclge_vport *vport, 3776 u16 cmdq_resp, u8 resp_code, 3777 enum hclge_mac_vlan_tbl_opcode op) 3778 { 3779 struct hclge_dev *hdev = vport->back; 3780 int return_status = -EIO; 3781 3782 if (cmdq_resp) { 3783 dev_err(&hdev->pdev->dev, 3784 "cmdq execute failed for get_mac_vlan_cmd_status,status=%d.\n", 3785 cmdq_resp); 3786 return -EIO; 3787 } 3788 3789 if (op == HCLGE_MAC_VLAN_ADD) { 3790 if ((!resp_code) || (resp_code == 1)) { 3791 return_status = 0; 3792 } else if (resp_code == 2) { 3793 return_status = -EIO; 3794 dev_err(&hdev->pdev->dev, 3795 "add mac addr failed for uc_overflow.\n"); 3796 } else if (resp_code == 3) { 3797 return_status = -EIO; 3798 dev_err(&hdev->pdev->dev, 3799 "add mac addr failed for mc_overflow.\n"); 3800 } else { 3801 dev_err(&hdev->pdev->dev, 3802 "add mac addr failed for undefined, code=%d.\n", 3803 resp_code); 3804 } 3805 } else if (op == HCLGE_MAC_VLAN_REMOVE) { 3806 if (!resp_code) { 3807 return_status = 0; 3808 } else if (resp_code == 1) { 3809 return_status = -EIO; 3810 dev_dbg(&hdev->pdev->dev, 3811 "remove mac addr failed for miss.\n"); 3812 } else { 3813 dev_err(&hdev->pdev->dev, 3814 "remove mac addr failed for undefined, code=%d.\n", 3815 resp_code); 3816 } 3817 } else if (op == HCLGE_MAC_VLAN_LKUP) { 3818 if (!resp_code) { 3819 return_status = 0; 3820 } else if (resp_code == 1) { 3821 return_status = -EIO; 3822 dev_dbg(&hdev->pdev->dev, 3823 "lookup mac addr failed for miss.\n"); 3824 } else { 3825 dev_err(&hdev->pdev->dev, 3826 "lookup mac addr failed for undefined, code=%d.\n", 3827 resp_code); 3828 } 3829 } else { 3830 return_status = -EIO; 3831 dev_err(&hdev->pdev->dev, 3832 "unknown opcode for get_mac_vlan_cmd_status,opcode=%d.\n", 3833 op); 3834 } 3835 3836 return return_status; 3837 } 3838 3839 static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr) 3840 { 3841 int word_num; 3842 int bit_num; 3843 3844 if (vfid > 255 || vfid < 0) 3845 return -EIO; 3846 3847 if (vfid >= 0 && vfid <= 191) { 3848 word_num = vfid / 32; 3849 bit_num = vfid % 32; 3850 if (clr) 3851 desc[1].data[word_num] &= cpu_to_le32(~(1 << bit_num)); 3852 else 3853 desc[1].data[word_num] |= cpu_to_le32(1 << bit_num); 3854 } else { 3855 word_num = (vfid - 192) / 32; 3856 bit_num = vfid % 32; 3857 if (clr) 3858 desc[2].data[word_num] &= cpu_to_le32(~(1 << bit_num)); 3859 else 3860 desc[2].data[word_num] |= cpu_to_le32(1 << bit_num); 3861 } 3862 3863 return 0; 3864 } 3865 3866 static bool hclge_is_all_function_id_zero(struct hclge_desc *desc) 3867 { 3868 #define HCLGE_DESC_NUMBER 3 3869 #define HCLGE_FUNC_NUMBER_PER_DESC 6 3870 int i, j; 3871 3872 for (i = 0; i < HCLGE_DESC_NUMBER; i++) 3873 for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++) 3874 if (desc[i].data[j]) 3875 return false; 3876 3877 return true; 3878 } 3879 3880 static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd *new_req, 3881 const u8 *addr) 3882 { 3883 const unsigned char *mac_addr = addr; 3884 u32 high_val = mac_addr[2] << 16 | (mac_addr[3] << 24) | 3885 (mac_addr[0]) | (mac_addr[1] << 8); 3886 u32 low_val = mac_addr[4] | (mac_addr[5] << 8); 3887 3888 new_req->mac_addr_hi32 = cpu_to_le32(high_val); 3889 new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff); 3890 } 3891 3892 static u16 hclge_get_mac_addr_to_mta_index(struct hclge_vport *vport, 3893 const u8 *addr) 3894 { 3895 u16 high_val = addr[1] | (addr[0] << 8); 3896 struct hclge_dev *hdev = vport->back; 3897 u32 rsh = 4 - hdev->mta_mac_sel_type; 3898 u16 ret_val = (high_val >> rsh) & 0xfff; 3899 3900 return ret_val; 3901 } 3902 3903 static int hclge_set_mta_filter_mode(struct hclge_dev *hdev, 3904 enum hclge_mta_dmac_sel_type mta_mac_sel, 3905 bool enable) 3906 { 3907 struct hclge_mta_filter_mode_cmd *req; 3908 struct hclge_desc desc; 3909 int ret; 3910 3911 req = (struct hclge_mta_filter_mode_cmd *)desc.data; 3912 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_MODE_CFG, false); 3913 3914 hnae_set_bit(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_EN_B, 3915 enable); 3916 hnae_set_field(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_SEL_M, 3917 HCLGE_CFG_MTA_MAC_SEL_S, mta_mac_sel); 3918 3919 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3920 if (ret) { 3921 dev_err(&hdev->pdev->dev, 3922 "Config mat filter mode failed for cmd_send, ret =%d.\n", 3923 ret); 3924 return ret; 3925 } 3926 3927 return 0; 3928 } 3929 3930 int hclge_cfg_func_mta_filter(struct hclge_dev *hdev, 3931 u8 func_id, 3932 bool enable) 3933 { 3934 struct hclge_cfg_func_mta_filter_cmd *req; 3935 struct hclge_desc desc; 3936 int ret; 3937 3938 req = (struct hclge_cfg_func_mta_filter_cmd *)desc.data; 3939 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_FUNC_CFG, false); 3940 3941 hnae_set_bit(req->accept, HCLGE_CFG_FUNC_MTA_ACCEPT_B, 3942 enable); 3943 req->function_id = func_id; 3944 3945 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3946 if (ret) { 3947 dev_err(&hdev->pdev->dev, 3948 "Config func_id enable failed for cmd_send, ret =%d.\n", 3949 ret); 3950 return ret; 3951 } 3952 3953 return 0; 3954 } 3955 3956 static int hclge_set_mta_table_item(struct hclge_vport *vport, 3957 u16 idx, 3958 bool enable) 3959 { 3960 struct hclge_dev *hdev = vport->back; 3961 struct hclge_cfg_func_mta_item_cmd *req; 3962 struct hclge_desc desc; 3963 u16 item_idx = 0; 3964 int ret; 3965 3966 req = (struct hclge_cfg_func_mta_item_cmd *)desc.data; 3967 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_TBL_ITEM_CFG, false); 3968 hnae_set_bit(req->accept, HCLGE_CFG_MTA_ITEM_ACCEPT_B, enable); 3969 3970 hnae_set_field(item_idx, HCLGE_CFG_MTA_ITEM_IDX_M, 3971 HCLGE_CFG_MTA_ITEM_IDX_S, idx); 3972 req->item_idx = cpu_to_le16(item_idx); 3973 3974 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3975 if (ret) { 3976 dev_err(&hdev->pdev->dev, 3977 "Config mta table item failed for cmd_send, ret =%d.\n", 3978 ret); 3979 return ret; 3980 } 3981 3982 return 0; 3983 } 3984 3985 static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport, 3986 struct hclge_mac_vlan_tbl_entry_cmd *req) 3987 { 3988 struct hclge_dev *hdev = vport->back; 3989 struct hclge_desc desc; 3990 u8 resp_code; 3991 u16 retval; 3992 int ret; 3993 3994 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_REMOVE, false); 3995 3996 memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 3997 3998 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3999 if (ret) { 4000 dev_err(&hdev->pdev->dev, 4001 "del mac addr failed for cmd_send, ret =%d.\n", 4002 ret); 4003 return ret; 4004 } 4005 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; 4006 retval = le16_to_cpu(desc.retval); 4007 4008 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code, 4009 HCLGE_MAC_VLAN_REMOVE); 4010 } 4011 4012 static int hclge_lookup_mac_vlan_tbl(struct hclge_vport *vport, 4013 struct hclge_mac_vlan_tbl_entry_cmd *req, 4014 struct hclge_desc *desc, 4015 bool is_mc) 4016 { 4017 struct hclge_dev *hdev = vport->back; 4018 u8 resp_code; 4019 u16 retval; 4020 int ret; 4021 4022 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_MAC_VLAN_ADD, true); 4023 if (is_mc) { 4024 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 4025 memcpy(desc[0].data, 4026 req, 4027 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 4028 hclge_cmd_setup_basic_desc(&desc[1], 4029 HCLGE_OPC_MAC_VLAN_ADD, 4030 true); 4031 desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 4032 hclge_cmd_setup_basic_desc(&desc[2], 4033 HCLGE_OPC_MAC_VLAN_ADD, 4034 true); 4035 ret = hclge_cmd_send(&hdev->hw, desc, 3); 4036 } else { 4037 memcpy(desc[0].data, 4038 req, 4039 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 4040 ret = hclge_cmd_send(&hdev->hw, desc, 1); 4041 } 4042 if (ret) { 4043 dev_err(&hdev->pdev->dev, 4044 "lookup mac addr failed for cmd_send, ret =%d.\n", 4045 ret); 4046 return ret; 4047 } 4048 resp_code = (le32_to_cpu(desc[0].data[0]) >> 8) & 0xff; 4049 retval = le16_to_cpu(desc[0].retval); 4050 4051 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code, 4052 HCLGE_MAC_VLAN_LKUP); 4053 } 4054 4055 static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport, 4056 struct hclge_mac_vlan_tbl_entry_cmd *req, 4057 struct hclge_desc *mc_desc) 4058 { 4059 struct hclge_dev *hdev = vport->back; 4060 int cfg_status; 4061 u8 resp_code; 4062 u16 retval; 4063 int ret; 4064 4065 if (!mc_desc) { 4066 struct hclge_desc desc; 4067 4068 hclge_cmd_setup_basic_desc(&desc, 4069 HCLGE_OPC_MAC_VLAN_ADD, 4070 false); 4071 memcpy(desc.data, req, 4072 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 4073 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 4074 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; 4075 retval = le16_to_cpu(desc.retval); 4076 4077 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval, 4078 resp_code, 4079 HCLGE_MAC_VLAN_ADD); 4080 } else { 4081 hclge_cmd_reuse_desc(&mc_desc[0], false); 4082 mc_desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 4083 hclge_cmd_reuse_desc(&mc_desc[1], false); 4084 mc_desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 4085 hclge_cmd_reuse_desc(&mc_desc[2], false); 4086 mc_desc[2].flag &= cpu_to_le16(~HCLGE_CMD_FLAG_NEXT); 4087 memcpy(mc_desc[0].data, req, 4088 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 4089 ret = hclge_cmd_send(&hdev->hw, mc_desc, 3); 4090 resp_code = (le32_to_cpu(mc_desc[0].data[0]) >> 8) & 0xff; 4091 retval = le16_to_cpu(mc_desc[0].retval); 4092 4093 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval, 4094 resp_code, 4095 HCLGE_MAC_VLAN_ADD); 4096 } 4097 4098 if (ret) { 4099 dev_err(&hdev->pdev->dev, 4100 "add mac addr failed for cmd_send, ret =%d.\n", 4101 ret); 4102 return ret; 4103 } 4104 4105 return cfg_status; 4106 } 4107 4108 static int hclge_add_uc_addr(struct hnae3_handle *handle, 4109 const unsigned char *addr) 4110 { 4111 struct hclge_vport *vport = hclge_get_vport(handle); 4112 4113 return hclge_add_uc_addr_common(vport, addr); 4114 } 4115 4116 int hclge_add_uc_addr_common(struct hclge_vport *vport, 4117 const unsigned char *addr) 4118 { 4119 struct hclge_dev *hdev = vport->back; 4120 struct hclge_mac_vlan_tbl_entry_cmd req; 4121 enum hclge_cmd_status status; 4122 u16 egress_port = 0; 4123 4124 /* mac addr check */ 4125 if (is_zero_ether_addr(addr) || 4126 is_broadcast_ether_addr(addr) || 4127 is_multicast_ether_addr(addr)) { 4128 dev_err(&hdev->pdev->dev, 4129 "Set_uc mac err! invalid mac:%pM. is_zero:%d,is_br=%d,is_mul=%d\n", 4130 addr, 4131 is_zero_ether_addr(addr), 4132 is_broadcast_ether_addr(addr), 4133 is_multicast_ether_addr(addr)); 4134 return -EINVAL; 4135 } 4136 4137 memset(&req, 0, sizeof(req)); 4138 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1); 4139 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0); 4140 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 0); 4141 hnae_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0); 4142 4143 hnae_set_bit(egress_port, HCLGE_MAC_EPORT_SW_EN_B, 0); 4144 hnae_set_bit(egress_port, HCLGE_MAC_EPORT_TYPE_B, 0); 4145 hnae_set_field(egress_port, HCLGE_MAC_EPORT_VFID_M, 4146 HCLGE_MAC_EPORT_VFID_S, vport->vport_id); 4147 hnae_set_field(egress_port, HCLGE_MAC_EPORT_PFID_M, 4148 HCLGE_MAC_EPORT_PFID_S, 0); 4149 4150 req.egress_port = cpu_to_le16(egress_port); 4151 4152 hclge_prepare_mac_addr(&req, addr); 4153 4154 status = hclge_add_mac_vlan_tbl(vport, &req, NULL); 4155 4156 return status; 4157 } 4158 4159 static int hclge_rm_uc_addr(struct hnae3_handle *handle, 4160 const unsigned char *addr) 4161 { 4162 struct hclge_vport *vport = hclge_get_vport(handle); 4163 4164 return hclge_rm_uc_addr_common(vport, addr); 4165 } 4166 4167 int hclge_rm_uc_addr_common(struct hclge_vport *vport, 4168 const unsigned char *addr) 4169 { 4170 struct hclge_dev *hdev = vport->back; 4171 struct hclge_mac_vlan_tbl_entry_cmd req; 4172 enum hclge_cmd_status status; 4173 4174 /* mac addr check */ 4175 if (is_zero_ether_addr(addr) || 4176 is_broadcast_ether_addr(addr) || 4177 is_multicast_ether_addr(addr)) { 4178 dev_dbg(&hdev->pdev->dev, 4179 "Remove mac err! invalid mac:%pM.\n", 4180 addr); 4181 return -EINVAL; 4182 } 4183 4184 memset(&req, 0, sizeof(req)); 4185 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1); 4186 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0); 4187 hclge_prepare_mac_addr(&req, addr); 4188 status = hclge_remove_mac_vlan_tbl(vport, &req); 4189 4190 return status; 4191 } 4192 4193 static int hclge_add_mc_addr(struct hnae3_handle *handle, 4194 const unsigned char *addr) 4195 { 4196 struct hclge_vport *vport = hclge_get_vport(handle); 4197 4198 return hclge_add_mc_addr_common(vport, addr); 4199 } 4200 4201 int hclge_add_mc_addr_common(struct hclge_vport *vport, 4202 const unsigned char *addr) 4203 { 4204 struct hclge_dev *hdev = vport->back; 4205 struct hclge_mac_vlan_tbl_entry_cmd req; 4206 struct hclge_desc desc[3]; 4207 u16 tbl_idx; 4208 int status; 4209 4210 /* mac addr check */ 4211 if (!is_multicast_ether_addr(addr)) { 4212 dev_err(&hdev->pdev->dev, 4213 "Add mc mac err! invalid mac:%pM.\n", 4214 addr); 4215 return -EINVAL; 4216 } 4217 memset(&req, 0, sizeof(req)); 4218 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1); 4219 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0); 4220 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1); 4221 hnae_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0); 4222 hclge_prepare_mac_addr(&req, addr); 4223 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true); 4224 if (!status) { 4225 /* This mac addr exist, update VFID for it */ 4226 hclge_update_desc_vfid(desc, vport->vport_id, false); 4227 status = hclge_add_mac_vlan_tbl(vport, &req, desc); 4228 } else { 4229 /* This mac addr do not exist, add new entry for it */ 4230 memset(desc[0].data, 0, sizeof(desc[0].data)); 4231 memset(desc[1].data, 0, sizeof(desc[0].data)); 4232 memset(desc[2].data, 0, sizeof(desc[0].data)); 4233 hclge_update_desc_vfid(desc, vport->vport_id, false); 4234 status = hclge_add_mac_vlan_tbl(vport, &req, desc); 4235 } 4236 4237 /* Set MTA table for this MAC address */ 4238 tbl_idx = hclge_get_mac_addr_to_mta_index(vport, addr); 4239 status = hclge_set_mta_table_item(vport, tbl_idx, true); 4240 4241 return status; 4242 } 4243 4244 static int hclge_rm_mc_addr(struct hnae3_handle *handle, 4245 const unsigned char *addr) 4246 { 4247 struct hclge_vport *vport = hclge_get_vport(handle); 4248 4249 return hclge_rm_mc_addr_common(vport, addr); 4250 } 4251 4252 int hclge_rm_mc_addr_common(struct hclge_vport *vport, 4253 const unsigned char *addr) 4254 { 4255 struct hclge_dev *hdev = vport->back; 4256 struct hclge_mac_vlan_tbl_entry_cmd req; 4257 enum hclge_cmd_status status; 4258 struct hclge_desc desc[3]; 4259 u16 tbl_idx; 4260 4261 /* mac addr check */ 4262 if (!is_multicast_ether_addr(addr)) { 4263 dev_dbg(&hdev->pdev->dev, 4264 "Remove mc mac err! invalid mac:%pM.\n", 4265 addr); 4266 return -EINVAL; 4267 } 4268 4269 memset(&req, 0, sizeof(req)); 4270 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1); 4271 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0); 4272 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1); 4273 hnae_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0); 4274 hclge_prepare_mac_addr(&req, addr); 4275 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true); 4276 if (!status) { 4277 /* This mac addr exist, remove this handle's VFID for it */ 4278 hclge_update_desc_vfid(desc, vport->vport_id, true); 4279 4280 if (hclge_is_all_function_id_zero(desc)) 4281 /* All the vfid is zero, so need to delete this entry */ 4282 status = hclge_remove_mac_vlan_tbl(vport, &req); 4283 else 4284 /* Not all the vfid is zero, update the vfid */ 4285 status = hclge_add_mac_vlan_tbl(vport, &req, desc); 4286 4287 } else { 4288 /* This mac addr do not exist, can't delete it */ 4289 dev_err(&hdev->pdev->dev, 4290 "Rm multicast mac addr failed, ret = %d.\n", 4291 status); 4292 return -EIO; 4293 } 4294 4295 /* Set MTB table for this MAC address */ 4296 tbl_idx = hclge_get_mac_addr_to_mta_index(vport, addr); 4297 status = hclge_set_mta_table_item(vport, tbl_idx, false); 4298 4299 return status; 4300 } 4301 4302 static int hclge_get_mac_ethertype_cmd_status(struct hclge_dev *hdev, 4303 u16 cmdq_resp, u8 resp_code) 4304 { 4305 #define HCLGE_ETHERTYPE_SUCCESS_ADD 0 4306 #define HCLGE_ETHERTYPE_ALREADY_ADD 1 4307 #define HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW 2 4308 #define HCLGE_ETHERTYPE_KEY_CONFLICT 3 4309 4310 int return_status; 4311 4312 if (cmdq_resp) { 4313 dev_err(&hdev->pdev->dev, 4314 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n", 4315 cmdq_resp); 4316 return -EIO; 4317 } 4318 4319 switch (resp_code) { 4320 case HCLGE_ETHERTYPE_SUCCESS_ADD: 4321 case HCLGE_ETHERTYPE_ALREADY_ADD: 4322 return_status = 0; 4323 break; 4324 case HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW: 4325 dev_err(&hdev->pdev->dev, 4326 "add mac ethertype failed for manager table overflow.\n"); 4327 return_status = -EIO; 4328 break; 4329 case HCLGE_ETHERTYPE_KEY_CONFLICT: 4330 dev_err(&hdev->pdev->dev, 4331 "add mac ethertype failed for key conflict.\n"); 4332 return_status = -EIO; 4333 break; 4334 default: 4335 dev_err(&hdev->pdev->dev, 4336 "add mac ethertype failed for undefined, code=%d.\n", 4337 resp_code); 4338 return_status = -EIO; 4339 } 4340 4341 return return_status; 4342 } 4343 4344 static int hclge_add_mgr_tbl(struct hclge_dev *hdev, 4345 const struct hclge_mac_mgr_tbl_entry_cmd *req) 4346 { 4347 struct hclge_desc desc; 4348 u8 resp_code; 4349 u16 retval; 4350 int ret; 4351 4352 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_ETHTYPE_ADD, false); 4353 memcpy(desc.data, req, sizeof(struct hclge_mac_mgr_tbl_entry_cmd)); 4354 4355 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 4356 if (ret) { 4357 dev_err(&hdev->pdev->dev, 4358 "add mac ethertype failed for cmd_send, ret =%d.\n", 4359 ret); 4360 return ret; 4361 } 4362 4363 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; 4364 retval = le16_to_cpu(desc.retval); 4365 4366 return hclge_get_mac_ethertype_cmd_status(hdev, retval, resp_code); 4367 } 4368 4369 static int init_mgr_tbl(struct hclge_dev *hdev) 4370 { 4371 int ret; 4372 int i; 4373 4374 for (i = 0; i < ARRAY_SIZE(hclge_mgr_table); i++) { 4375 ret = hclge_add_mgr_tbl(hdev, &hclge_mgr_table[i]); 4376 if (ret) { 4377 dev_err(&hdev->pdev->dev, 4378 "add mac ethertype failed, ret =%d.\n", 4379 ret); 4380 return ret; 4381 } 4382 } 4383 4384 return 0; 4385 } 4386 4387 static void hclge_get_mac_addr(struct hnae3_handle *handle, u8 *p) 4388 { 4389 struct hclge_vport *vport = hclge_get_vport(handle); 4390 struct hclge_dev *hdev = vport->back; 4391 4392 ether_addr_copy(p, hdev->hw.mac.mac_addr); 4393 } 4394 4395 static int hclge_set_mac_addr(struct hnae3_handle *handle, void *p) 4396 { 4397 const unsigned char *new_addr = (const unsigned char *)p; 4398 struct hclge_vport *vport = hclge_get_vport(handle); 4399 struct hclge_dev *hdev = vport->back; 4400 int ret; 4401 4402 /* mac addr check */ 4403 if (is_zero_ether_addr(new_addr) || 4404 is_broadcast_ether_addr(new_addr) || 4405 is_multicast_ether_addr(new_addr)) { 4406 dev_err(&hdev->pdev->dev, 4407 "Change uc mac err! invalid mac:%p.\n", 4408 new_addr); 4409 return -EINVAL; 4410 } 4411 4412 ret = hclge_rm_uc_addr(handle, hdev->hw.mac.mac_addr); 4413 if (ret) 4414 dev_warn(&hdev->pdev->dev, 4415 "remove old uc mac address fail, ret =%d.\n", 4416 ret); 4417 4418 ret = hclge_add_uc_addr(handle, new_addr); 4419 if (ret) { 4420 dev_err(&hdev->pdev->dev, 4421 "add uc mac address fail, ret =%d.\n", 4422 ret); 4423 4424 ret = hclge_add_uc_addr(handle, hdev->hw.mac.mac_addr); 4425 if (ret) { 4426 dev_err(&hdev->pdev->dev, 4427 "restore uc mac address fail, ret =%d.\n", 4428 ret); 4429 } 4430 4431 return -EIO; 4432 } 4433 4434 ret = hclge_mac_pause_addr_cfg(hdev, new_addr); 4435 if (ret) { 4436 dev_err(&hdev->pdev->dev, 4437 "configure mac pause address fail, ret =%d.\n", 4438 ret); 4439 return -EIO; 4440 } 4441 4442 ether_addr_copy(hdev->hw.mac.mac_addr, new_addr); 4443 4444 return 0; 4445 } 4446 4447 static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type, 4448 bool filter_en) 4449 { 4450 struct hclge_vlan_filter_ctrl_cmd *req; 4451 struct hclge_desc desc; 4452 int ret; 4453 4454 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, false); 4455 4456 req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data; 4457 req->vlan_type = vlan_type; 4458 req->vlan_fe = filter_en; 4459 4460 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 4461 if (ret) { 4462 dev_err(&hdev->pdev->dev, "set vlan filter fail, ret =%d.\n", 4463 ret); 4464 return ret; 4465 } 4466 4467 return 0; 4468 } 4469 4470 #define HCLGE_FILTER_TYPE_VF 0 4471 #define HCLGE_FILTER_TYPE_PORT 1 4472 4473 static void hclge_enable_vlan_filter(struct hnae3_handle *handle, bool enable) 4474 { 4475 struct hclge_vport *vport = hclge_get_vport(handle); 4476 struct hclge_dev *hdev = vport->back; 4477 4478 hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, enable); 4479 } 4480 4481 int hclge_set_vf_vlan_common(struct hclge_dev *hdev, int vfid, 4482 bool is_kill, u16 vlan, u8 qos, __be16 proto) 4483 { 4484 #define HCLGE_MAX_VF_BYTES 16 4485 struct hclge_vlan_filter_vf_cfg_cmd *req0; 4486 struct hclge_vlan_filter_vf_cfg_cmd *req1; 4487 struct hclge_desc desc[2]; 4488 u8 vf_byte_val; 4489 u8 vf_byte_off; 4490 int ret; 4491 4492 hclge_cmd_setup_basic_desc(&desc[0], 4493 HCLGE_OPC_VLAN_FILTER_VF_CFG, false); 4494 hclge_cmd_setup_basic_desc(&desc[1], 4495 HCLGE_OPC_VLAN_FILTER_VF_CFG, false); 4496 4497 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 4498 4499 vf_byte_off = vfid / 8; 4500 vf_byte_val = 1 << (vfid % 8); 4501 4502 req0 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data; 4503 req1 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[1].data; 4504 4505 req0->vlan_id = cpu_to_le16(vlan); 4506 req0->vlan_cfg = is_kill; 4507 4508 if (vf_byte_off < HCLGE_MAX_VF_BYTES) 4509 req0->vf_bitmap[vf_byte_off] = vf_byte_val; 4510 else 4511 req1->vf_bitmap[vf_byte_off - HCLGE_MAX_VF_BYTES] = vf_byte_val; 4512 4513 ret = hclge_cmd_send(&hdev->hw, desc, 2); 4514 if (ret) { 4515 dev_err(&hdev->pdev->dev, 4516 "Send vf vlan command fail, ret =%d.\n", 4517 ret); 4518 return ret; 4519 } 4520 4521 if (!is_kill) { 4522 if (!req0->resp_code || req0->resp_code == 1) 4523 return 0; 4524 4525 dev_err(&hdev->pdev->dev, 4526 "Add vf vlan filter fail, ret =%d.\n", 4527 req0->resp_code); 4528 } else { 4529 if (!req0->resp_code) 4530 return 0; 4531 4532 dev_err(&hdev->pdev->dev, 4533 "Kill vf vlan filter fail, ret =%d.\n", 4534 req0->resp_code); 4535 } 4536 4537 return -EIO; 4538 } 4539 4540 static int hclge_set_port_vlan_filter(struct hnae3_handle *handle, 4541 __be16 proto, u16 vlan_id, 4542 bool is_kill) 4543 { 4544 struct hclge_vport *vport = hclge_get_vport(handle); 4545 struct hclge_dev *hdev = vport->back; 4546 struct hclge_vlan_filter_pf_cfg_cmd *req; 4547 struct hclge_desc desc; 4548 u8 vlan_offset_byte_val; 4549 u8 vlan_offset_byte; 4550 u8 vlan_offset_160; 4551 int ret; 4552 4553 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_PF_CFG, false); 4554 4555 vlan_offset_160 = vlan_id / 160; 4556 vlan_offset_byte = (vlan_id % 160) / 8; 4557 vlan_offset_byte_val = 1 << (vlan_id % 8); 4558 4559 req = (struct hclge_vlan_filter_pf_cfg_cmd *)desc.data; 4560 req->vlan_offset = vlan_offset_160; 4561 req->vlan_cfg = is_kill; 4562 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val; 4563 4564 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 4565 if (ret) { 4566 dev_err(&hdev->pdev->dev, 4567 "port vlan command, send fail, ret =%d.\n", 4568 ret); 4569 return ret; 4570 } 4571 4572 ret = hclge_set_vf_vlan_common(hdev, 0, is_kill, vlan_id, 0, proto); 4573 if (ret) { 4574 dev_err(&hdev->pdev->dev, 4575 "Set pf vlan filter config fail, ret =%d.\n", 4576 ret); 4577 return -EIO; 4578 } 4579 4580 return 0; 4581 } 4582 4583 static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid, 4584 u16 vlan, u8 qos, __be16 proto) 4585 { 4586 struct hclge_vport *vport = hclge_get_vport(handle); 4587 struct hclge_dev *hdev = vport->back; 4588 4589 if ((vfid >= hdev->num_alloc_vfs) || (vlan > 4095) || (qos > 7)) 4590 return -EINVAL; 4591 if (proto != htons(ETH_P_8021Q)) 4592 return -EPROTONOSUPPORT; 4593 4594 return hclge_set_vf_vlan_common(hdev, vfid, false, vlan, qos, proto); 4595 } 4596 4597 static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport *vport) 4598 { 4599 struct hclge_tx_vtag_cfg *vcfg = &vport->txvlan_cfg; 4600 struct hclge_vport_vtag_tx_cfg_cmd *req; 4601 struct hclge_dev *hdev = vport->back; 4602 struct hclge_desc desc; 4603 int status; 4604 4605 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_TX_CFG, false); 4606 4607 req = (struct hclge_vport_vtag_tx_cfg_cmd *)desc.data; 4608 req->def_vlan_tag1 = cpu_to_le16(vcfg->default_tag1); 4609 req->def_vlan_tag2 = cpu_to_le16(vcfg->default_tag2); 4610 hnae_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG_B, 4611 vcfg->accept_tag ? 1 : 0); 4612 hnae_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG_B, 4613 vcfg->accept_untag ? 1 : 0); 4614 hnae_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG1_EN_B, 4615 vcfg->insert_tag1_en ? 1 : 0); 4616 hnae_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG2_EN_B, 4617 vcfg->insert_tag2_en ? 1 : 0); 4618 hnae_set_bit(req->vport_vlan_cfg, HCLGE_CFG_NIC_ROCE_SEL_B, 0); 4619 4620 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD; 4621 req->vf_bitmap[req->vf_offset] = 4622 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE); 4623 4624 status = hclge_cmd_send(&hdev->hw, &desc, 1); 4625 if (status) 4626 dev_err(&hdev->pdev->dev, 4627 "Send port txvlan cfg command fail, ret =%d\n", 4628 status); 4629 4630 return status; 4631 } 4632 4633 static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport *vport) 4634 { 4635 struct hclge_rx_vtag_cfg *vcfg = &vport->rxvlan_cfg; 4636 struct hclge_vport_vtag_rx_cfg_cmd *req; 4637 struct hclge_dev *hdev = vport->back; 4638 struct hclge_desc desc; 4639 int status; 4640 4641 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_RX_CFG, false); 4642 4643 req = (struct hclge_vport_vtag_rx_cfg_cmd *)desc.data; 4644 hnae_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG1_EN_B, 4645 vcfg->strip_tag1_en ? 1 : 0); 4646 hnae_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG2_EN_B, 4647 vcfg->strip_tag2_en ? 1 : 0); 4648 hnae_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG1_EN_B, 4649 vcfg->vlan1_vlan_prionly ? 1 : 0); 4650 hnae_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG2_EN_B, 4651 vcfg->vlan2_vlan_prionly ? 1 : 0); 4652 4653 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD; 4654 req->vf_bitmap[req->vf_offset] = 4655 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE); 4656 4657 status = hclge_cmd_send(&hdev->hw, &desc, 1); 4658 if (status) 4659 dev_err(&hdev->pdev->dev, 4660 "Send port rxvlan cfg command fail, ret =%d\n", 4661 status); 4662 4663 return status; 4664 } 4665 4666 static int hclge_set_vlan_protocol_type(struct hclge_dev *hdev) 4667 { 4668 struct hclge_rx_vlan_type_cfg_cmd *rx_req; 4669 struct hclge_tx_vlan_type_cfg_cmd *tx_req; 4670 struct hclge_desc desc; 4671 int status; 4672 4673 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_TYPE_ID, false); 4674 rx_req = (struct hclge_rx_vlan_type_cfg_cmd *)desc.data; 4675 rx_req->ot_fst_vlan_type = 4676 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_fst_vlan_type); 4677 rx_req->ot_sec_vlan_type = 4678 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_sec_vlan_type); 4679 rx_req->in_fst_vlan_type = 4680 cpu_to_le16(hdev->vlan_type_cfg.rx_in_fst_vlan_type); 4681 rx_req->in_sec_vlan_type = 4682 cpu_to_le16(hdev->vlan_type_cfg.rx_in_sec_vlan_type); 4683 4684 status = hclge_cmd_send(&hdev->hw, &desc, 1); 4685 if (status) { 4686 dev_err(&hdev->pdev->dev, 4687 "Send rxvlan protocol type command fail, ret =%d\n", 4688 status); 4689 return status; 4690 } 4691 4692 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_INSERT, false); 4693 4694 tx_req = (struct hclge_tx_vlan_type_cfg_cmd *)&desc.data; 4695 tx_req->ot_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_ot_vlan_type); 4696 tx_req->in_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_in_vlan_type); 4697 4698 status = hclge_cmd_send(&hdev->hw, &desc, 1); 4699 if (status) 4700 dev_err(&hdev->pdev->dev, 4701 "Send txvlan protocol type command fail, ret =%d\n", 4702 status); 4703 4704 return status; 4705 } 4706 4707 static int hclge_init_vlan_config(struct hclge_dev *hdev) 4708 { 4709 #define HCLGE_DEF_VLAN_TYPE 0x8100 4710 4711 struct hnae3_handle *handle; 4712 struct hclge_vport *vport; 4713 int ret; 4714 int i; 4715 4716 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, true); 4717 if (ret) 4718 return ret; 4719 4720 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT, true); 4721 if (ret) 4722 return ret; 4723 4724 hdev->vlan_type_cfg.rx_in_fst_vlan_type = HCLGE_DEF_VLAN_TYPE; 4725 hdev->vlan_type_cfg.rx_in_sec_vlan_type = HCLGE_DEF_VLAN_TYPE; 4726 hdev->vlan_type_cfg.rx_ot_fst_vlan_type = HCLGE_DEF_VLAN_TYPE; 4727 hdev->vlan_type_cfg.rx_ot_sec_vlan_type = HCLGE_DEF_VLAN_TYPE; 4728 hdev->vlan_type_cfg.tx_ot_vlan_type = HCLGE_DEF_VLAN_TYPE; 4729 hdev->vlan_type_cfg.tx_in_vlan_type = HCLGE_DEF_VLAN_TYPE; 4730 4731 ret = hclge_set_vlan_protocol_type(hdev); 4732 if (ret) 4733 return ret; 4734 4735 for (i = 0; i < hdev->num_alloc_vport; i++) { 4736 vport = &hdev->vport[i]; 4737 vport->txvlan_cfg.accept_tag = true; 4738 vport->txvlan_cfg.accept_untag = true; 4739 vport->txvlan_cfg.insert_tag1_en = false; 4740 vport->txvlan_cfg.insert_tag2_en = false; 4741 vport->txvlan_cfg.default_tag1 = 0; 4742 vport->txvlan_cfg.default_tag2 = 0; 4743 4744 ret = hclge_set_vlan_tx_offload_cfg(vport); 4745 if (ret) 4746 return ret; 4747 4748 vport->rxvlan_cfg.strip_tag1_en = false; 4749 vport->rxvlan_cfg.strip_tag2_en = true; 4750 vport->rxvlan_cfg.vlan1_vlan_prionly = false; 4751 vport->rxvlan_cfg.vlan2_vlan_prionly = false; 4752 4753 ret = hclge_set_vlan_rx_offload_cfg(vport); 4754 if (ret) 4755 return ret; 4756 } 4757 4758 handle = &hdev->vport[0].nic; 4759 return hclge_set_port_vlan_filter(handle, htons(ETH_P_8021Q), 0, false); 4760 } 4761 4762 static int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 4763 { 4764 struct hclge_vport *vport = hclge_get_vport(handle); 4765 4766 vport->rxvlan_cfg.strip_tag1_en = false; 4767 vport->rxvlan_cfg.strip_tag2_en = enable; 4768 vport->rxvlan_cfg.vlan1_vlan_prionly = false; 4769 vport->rxvlan_cfg.vlan2_vlan_prionly = false; 4770 4771 return hclge_set_vlan_rx_offload_cfg(vport); 4772 } 4773 4774 static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu) 4775 { 4776 struct hclge_vport *vport = hclge_get_vport(handle); 4777 struct hclge_config_max_frm_size_cmd *req; 4778 struct hclge_dev *hdev = vport->back; 4779 struct hclge_desc desc; 4780 int max_frm_size; 4781 int ret; 4782 4783 max_frm_size = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 4784 4785 if (max_frm_size < HCLGE_MAC_MIN_FRAME || 4786 max_frm_size > HCLGE_MAC_MAX_FRAME) 4787 return -EINVAL; 4788 4789 max_frm_size = max(max_frm_size, HCLGE_MAC_DEFAULT_FRAME); 4790 4791 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, false); 4792 4793 req = (struct hclge_config_max_frm_size_cmd *)desc.data; 4794 req->max_frm_size = cpu_to_le16(max_frm_size); 4795 4796 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 4797 if (ret) { 4798 dev_err(&hdev->pdev->dev, "set mtu fail, ret =%d.\n", ret); 4799 return ret; 4800 } 4801 4802 hdev->mps = max_frm_size; 4803 4804 return 0; 4805 } 4806 4807 static int hclge_send_reset_tqp_cmd(struct hclge_dev *hdev, u16 queue_id, 4808 bool enable) 4809 { 4810 struct hclge_reset_tqp_queue_cmd *req; 4811 struct hclge_desc desc; 4812 int ret; 4813 4814 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, false); 4815 4816 req = (struct hclge_reset_tqp_queue_cmd *)desc.data; 4817 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK); 4818 hnae_set_bit(req->reset_req, HCLGE_TQP_RESET_B, enable); 4819 4820 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 4821 if (ret) { 4822 dev_err(&hdev->pdev->dev, 4823 "Send tqp reset cmd error, status =%d\n", ret); 4824 return ret; 4825 } 4826 4827 return 0; 4828 } 4829 4830 static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id) 4831 { 4832 struct hclge_reset_tqp_queue_cmd *req; 4833 struct hclge_desc desc; 4834 int ret; 4835 4836 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, true); 4837 4838 req = (struct hclge_reset_tqp_queue_cmd *)desc.data; 4839 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK); 4840 4841 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 4842 if (ret) { 4843 dev_err(&hdev->pdev->dev, 4844 "Get reset status error, status =%d\n", ret); 4845 return ret; 4846 } 4847 4848 return hnae_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B); 4849 } 4850 4851 void hclge_reset_tqp(struct hnae3_handle *handle, u16 queue_id) 4852 { 4853 struct hclge_vport *vport = hclge_get_vport(handle); 4854 struct hclge_dev *hdev = vport->back; 4855 int reset_try_times = 0; 4856 int reset_status; 4857 int ret; 4858 4859 ret = hclge_tqp_enable(hdev, queue_id, 0, false); 4860 if (ret) { 4861 dev_warn(&hdev->pdev->dev, "Disable tqp fail, ret = %d\n", ret); 4862 return; 4863 } 4864 4865 ret = hclge_send_reset_tqp_cmd(hdev, queue_id, true); 4866 if (ret) { 4867 dev_warn(&hdev->pdev->dev, 4868 "Send reset tqp cmd fail, ret = %d\n", ret); 4869 return; 4870 } 4871 4872 reset_try_times = 0; 4873 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) { 4874 /* Wait for tqp hw reset */ 4875 msleep(20); 4876 reset_status = hclge_get_reset_status(hdev, queue_id); 4877 if (reset_status) 4878 break; 4879 } 4880 4881 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) { 4882 dev_warn(&hdev->pdev->dev, "Reset TQP fail\n"); 4883 return; 4884 } 4885 4886 ret = hclge_send_reset_tqp_cmd(hdev, queue_id, false); 4887 if (ret) { 4888 dev_warn(&hdev->pdev->dev, 4889 "Deassert the soft reset fail, ret = %d\n", ret); 4890 return; 4891 } 4892 } 4893 4894 static u32 hclge_get_fw_version(struct hnae3_handle *handle) 4895 { 4896 struct hclge_vport *vport = hclge_get_vport(handle); 4897 struct hclge_dev *hdev = vport->back; 4898 4899 return hdev->fw_version; 4900 } 4901 4902 static void hclge_get_flowctrl_adv(struct hnae3_handle *handle, 4903 u32 *flowctrl_adv) 4904 { 4905 struct hclge_vport *vport = hclge_get_vport(handle); 4906 struct hclge_dev *hdev = vport->back; 4907 struct phy_device *phydev = hdev->hw.mac.phydev; 4908 4909 if (!phydev) 4910 return; 4911 4912 *flowctrl_adv |= (phydev->advertising & ADVERTISED_Pause) | 4913 (phydev->advertising & ADVERTISED_Asym_Pause); 4914 } 4915 4916 static void hclge_set_flowctrl_adv(struct hclge_dev *hdev, u32 rx_en, u32 tx_en) 4917 { 4918 struct phy_device *phydev = hdev->hw.mac.phydev; 4919 4920 if (!phydev) 4921 return; 4922 4923 phydev->advertising &= ~(ADVERTISED_Pause | ADVERTISED_Asym_Pause); 4924 4925 if (rx_en) 4926 phydev->advertising |= ADVERTISED_Pause | ADVERTISED_Asym_Pause; 4927 4928 if (tx_en) 4929 phydev->advertising ^= ADVERTISED_Asym_Pause; 4930 } 4931 4932 static int hclge_cfg_pauseparam(struct hclge_dev *hdev, u32 rx_en, u32 tx_en) 4933 { 4934 int ret; 4935 4936 if (rx_en && tx_en) 4937 hdev->fc_mode_last_time = HCLGE_FC_FULL; 4938 else if (rx_en && !tx_en) 4939 hdev->fc_mode_last_time = HCLGE_FC_RX_PAUSE; 4940 else if (!rx_en && tx_en) 4941 hdev->fc_mode_last_time = HCLGE_FC_TX_PAUSE; 4942 else 4943 hdev->fc_mode_last_time = HCLGE_FC_NONE; 4944 4945 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) 4946 return 0; 4947 4948 ret = hclge_mac_pause_en_cfg(hdev, tx_en, rx_en); 4949 if (ret) { 4950 dev_err(&hdev->pdev->dev, "configure pauseparam error, ret = %d.\n", 4951 ret); 4952 return ret; 4953 } 4954 4955 hdev->tm_info.fc_mode = hdev->fc_mode_last_time; 4956 4957 return 0; 4958 } 4959 4960 int hclge_cfg_flowctrl(struct hclge_dev *hdev) 4961 { 4962 struct phy_device *phydev = hdev->hw.mac.phydev; 4963 u16 remote_advertising = 0; 4964 u16 local_advertising = 0; 4965 u32 rx_pause, tx_pause; 4966 u8 flowctl; 4967 4968 if (!phydev->link || !phydev->autoneg) 4969 return 0; 4970 4971 if (phydev->advertising & ADVERTISED_Pause) 4972 local_advertising = ADVERTISE_PAUSE_CAP; 4973 4974 if (phydev->advertising & ADVERTISED_Asym_Pause) 4975 local_advertising |= ADVERTISE_PAUSE_ASYM; 4976 4977 if (phydev->pause) 4978 remote_advertising = LPA_PAUSE_CAP; 4979 4980 if (phydev->asym_pause) 4981 remote_advertising |= LPA_PAUSE_ASYM; 4982 4983 flowctl = mii_resolve_flowctrl_fdx(local_advertising, 4984 remote_advertising); 4985 tx_pause = flowctl & FLOW_CTRL_TX; 4986 rx_pause = flowctl & FLOW_CTRL_RX; 4987 4988 if (phydev->duplex == HCLGE_MAC_HALF) { 4989 tx_pause = 0; 4990 rx_pause = 0; 4991 } 4992 4993 return hclge_cfg_pauseparam(hdev, rx_pause, tx_pause); 4994 } 4995 4996 static void hclge_get_pauseparam(struct hnae3_handle *handle, u32 *auto_neg, 4997 u32 *rx_en, u32 *tx_en) 4998 { 4999 struct hclge_vport *vport = hclge_get_vport(handle); 5000 struct hclge_dev *hdev = vport->back; 5001 5002 *auto_neg = hclge_get_autoneg(handle); 5003 5004 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) { 5005 *rx_en = 0; 5006 *tx_en = 0; 5007 return; 5008 } 5009 5010 if (hdev->tm_info.fc_mode == HCLGE_FC_RX_PAUSE) { 5011 *rx_en = 1; 5012 *tx_en = 0; 5013 } else if (hdev->tm_info.fc_mode == HCLGE_FC_TX_PAUSE) { 5014 *tx_en = 1; 5015 *rx_en = 0; 5016 } else if (hdev->tm_info.fc_mode == HCLGE_FC_FULL) { 5017 *rx_en = 1; 5018 *tx_en = 1; 5019 } else { 5020 *rx_en = 0; 5021 *tx_en = 0; 5022 } 5023 } 5024 5025 static int hclge_set_pauseparam(struct hnae3_handle *handle, u32 auto_neg, 5026 u32 rx_en, u32 tx_en) 5027 { 5028 struct hclge_vport *vport = hclge_get_vport(handle); 5029 struct hclge_dev *hdev = vport->back; 5030 struct phy_device *phydev = hdev->hw.mac.phydev; 5031 u32 fc_autoneg; 5032 5033 /* Only support flow control negotiation for netdev with 5034 * phy attached for now. 5035 */ 5036 if (!phydev) 5037 return -EOPNOTSUPP; 5038 5039 fc_autoneg = hclge_get_autoneg(handle); 5040 if (auto_neg != fc_autoneg) { 5041 dev_info(&hdev->pdev->dev, 5042 "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n"); 5043 return -EOPNOTSUPP; 5044 } 5045 5046 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) { 5047 dev_info(&hdev->pdev->dev, 5048 "Priority flow control enabled. Cannot set link flow control.\n"); 5049 return -EOPNOTSUPP; 5050 } 5051 5052 hclge_set_flowctrl_adv(hdev, rx_en, tx_en); 5053 5054 if (!fc_autoneg) 5055 return hclge_cfg_pauseparam(hdev, rx_en, tx_en); 5056 5057 return phy_start_aneg(phydev); 5058 } 5059 5060 static void hclge_get_ksettings_an_result(struct hnae3_handle *handle, 5061 u8 *auto_neg, u32 *speed, u8 *duplex) 5062 { 5063 struct hclge_vport *vport = hclge_get_vport(handle); 5064 struct hclge_dev *hdev = vport->back; 5065 5066 if (speed) 5067 *speed = hdev->hw.mac.speed; 5068 if (duplex) 5069 *duplex = hdev->hw.mac.duplex; 5070 if (auto_neg) 5071 *auto_neg = hdev->hw.mac.autoneg; 5072 } 5073 5074 static void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type) 5075 { 5076 struct hclge_vport *vport = hclge_get_vport(handle); 5077 struct hclge_dev *hdev = vport->back; 5078 5079 if (media_type) 5080 *media_type = hdev->hw.mac.media_type; 5081 } 5082 5083 static void hclge_get_mdix_mode(struct hnae3_handle *handle, 5084 u8 *tp_mdix_ctrl, u8 *tp_mdix) 5085 { 5086 struct hclge_vport *vport = hclge_get_vport(handle); 5087 struct hclge_dev *hdev = vport->back; 5088 struct phy_device *phydev = hdev->hw.mac.phydev; 5089 int mdix_ctrl, mdix, retval, is_resolved; 5090 5091 if (!phydev) { 5092 *tp_mdix_ctrl = ETH_TP_MDI_INVALID; 5093 *tp_mdix = ETH_TP_MDI_INVALID; 5094 return; 5095 } 5096 5097 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX); 5098 5099 retval = phy_read(phydev, HCLGE_PHY_CSC_REG); 5100 mdix_ctrl = hnae_get_field(retval, HCLGE_PHY_MDIX_CTRL_M, 5101 HCLGE_PHY_MDIX_CTRL_S); 5102 5103 retval = phy_read(phydev, HCLGE_PHY_CSS_REG); 5104 mdix = hnae_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B); 5105 is_resolved = hnae_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B); 5106 5107 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER); 5108 5109 switch (mdix_ctrl) { 5110 case 0x0: 5111 *tp_mdix_ctrl = ETH_TP_MDI; 5112 break; 5113 case 0x1: 5114 *tp_mdix_ctrl = ETH_TP_MDI_X; 5115 break; 5116 case 0x3: 5117 *tp_mdix_ctrl = ETH_TP_MDI_AUTO; 5118 break; 5119 default: 5120 *tp_mdix_ctrl = ETH_TP_MDI_INVALID; 5121 break; 5122 } 5123 5124 if (!is_resolved) 5125 *tp_mdix = ETH_TP_MDI_INVALID; 5126 else if (mdix) 5127 *tp_mdix = ETH_TP_MDI_X; 5128 else 5129 *tp_mdix = ETH_TP_MDI; 5130 } 5131 5132 static int hclge_init_client_instance(struct hnae3_client *client, 5133 struct hnae3_ae_dev *ae_dev) 5134 { 5135 struct hclge_dev *hdev = ae_dev->priv; 5136 struct hclge_vport *vport; 5137 int i, ret; 5138 5139 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) { 5140 vport = &hdev->vport[i]; 5141 5142 switch (client->type) { 5143 case HNAE3_CLIENT_KNIC: 5144 5145 hdev->nic_client = client; 5146 vport->nic.client = client; 5147 ret = client->ops->init_instance(&vport->nic); 5148 if (ret) 5149 goto err; 5150 5151 if (hdev->roce_client && 5152 hnae3_dev_roce_supported(hdev)) { 5153 struct hnae3_client *rc = hdev->roce_client; 5154 5155 ret = hclge_init_roce_base_info(vport); 5156 if (ret) 5157 goto err; 5158 5159 ret = rc->ops->init_instance(&vport->roce); 5160 if (ret) 5161 goto err; 5162 } 5163 5164 break; 5165 case HNAE3_CLIENT_UNIC: 5166 hdev->nic_client = client; 5167 vport->nic.client = client; 5168 5169 ret = client->ops->init_instance(&vport->nic); 5170 if (ret) 5171 goto err; 5172 5173 break; 5174 case HNAE3_CLIENT_ROCE: 5175 if (hnae3_dev_roce_supported(hdev)) { 5176 hdev->roce_client = client; 5177 vport->roce.client = client; 5178 } 5179 5180 if (hdev->roce_client && hdev->nic_client) { 5181 ret = hclge_init_roce_base_info(vport); 5182 if (ret) 5183 goto err; 5184 5185 ret = client->ops->init_instance(&vport->roce); 5186 if (ret) 5187 goto err; 5188 } 5189 } 5190 } 5191 5192 return 0; 5193 err: 5194 return ret; 5195 } 5196 5197 static void hclge_uninit_client_instance(struct hnae3_client *client, 5198 struct hnae3_ae_dev *ae_dev) 5199 { 5200 struct hclge_dev *hdev = ae_dev->priv; 5201 struct hclge_vport *vport; 5202 int i; 5203 5204 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) { 5205 vport = &hdev->vport[i]; 5206 if (hdev->roce_client) { 5207 hdev->roce_client->ops->uninit_instance(&vport->roce, 5208 0); 5209 hdev->roce_client = NULL; 5210 vport->roce.client = NULL; 5211 } 5212 if (client->type == HNAE3_CLIENT_ROCE) 5213 return; 5214 if (client->ops->uninit_instance) { 5215 client->ops->uninit_instance(&vport->nic, 0); 5216 hdev->nic_client = NULL; 5217 vport->nic.client = NULL; 5218 } 5219 } 5220 } 5221 5222 static int hclge_pci_init(struct hclge_dev *hdev) 5223 { 5224 struct pci_dev *pdev = hdev->pdev; 5225 struct hclge_hw *hw; 5226 int ret; 5227 5228 ret = pci_enable_device(pdev); 5229 if (ret) { 5230 dev_err(&pdev->dev, "failed to enable PCI device\n"); 5231 goto err_no_drvdata; 5232 } 5233 5234 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 5235 if (ret) { 5236 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 5237 if (ret) { 5238 dev_err(&pdev->dev, 5239 "can't set consistent PCI DMA"); 5240 goto err_disable_device; 5241 } 5242 dev_warn(&pdev->dev, "set DMA mask to 32 bits\n"); 5243 } 5244 5245 ret = pci_request_regions(pdev, HCLGE_DRIVER_NAME); 5246 if (ret) { 5247 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 5248 goto err_disable_device; 5249 } 5250 5251 pci_set_master(pdev); 5252 hw = &hdev->hw; 5253 hw->back = hdev; 5254 hw->io_base = pcim_iomap(pdev, 2, 0); 5255 if (!hw->io_base) { 5256 dev_err(&pdev->dev, "Can't map configuration register space\n"); 5257 ret = -ENOMEM; 5258 goto err_clr_master; 5259 } 5260 5261 hdev->num_req_vfs = pci_sriov_get_totalvfs(pdev); 5262 5263 return 0; 5264 err_clr_master: 5265 pci_clear_master(pdev); 5266 pci_release_regions(pdev); 5267 err_disable_device: 5268 pci_disable_device(pdev); 5269 err_no_drvdata: 5270 pci_set_drvdata(pdev, NULL); 5271 5272 return ret; 5273 } 5274 5275 static void hclge_pci_uninit(struct hclge_dev *hdev) 5276 { 5277 struct pci_dev *pdev = hdev->pdev; 5278 5279 pci_free_irq_vectors(pdev); 5280 pci_clear_master(pdev); 5281 pci_release_mem_regions(pdev); 5282 pci_disable_device(pdev); 5283 } 5284 5285 static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev) 5286 { 5287 struct pci_dev *pdev = ae_dev->pdev; 5288 struct hclge_dev *hdev; 5289 int ret; 5290 5291 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 5292 if (!hdev) { 5293 ret = -ENOMEM; 5294 goto err_hclge_dev; 5295 } 5296 5297 hdev->pdev = pdev; 5298 hdev->ae_dev = ae_dev; 5299 hdev->reset_type = HNAE3_NONE_RESET; 5300 hdev->reset_request = 0; 5301 hdev->reset_pending = 0; 5302 ae_dev->priv = hdev; 5303 5304 ret = hclge_pci_init(hdev); 5305 if (ret) { 5306 dev_err(&pdev->dev, "PCI init failed\n"); 5307 goto err_pci_init; 5308 } 5309 5310 /* Firmware command queue initialize */ 5311 ret = hclge_cmd_queue_init(hdev); 5312 if (ret) { 5313 dev_err(&pdev->dev, "Cmd queue init failed, ret = %d.\n", ret); 5314 return ret; 5315 } 5316 5317 /* Firmware command initialize */ 5318 ret = hclge_cmd_init(hdev); 5319 if (ret) 5320 goto err_cmd_init; 5321 5322 ret = hclge_get_cap(hdev); 5323 if (ret) { 5324 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n", 5325 ret); 5326 return ret; 5327 } 5328 5329 ret = hclge_configure(hdev); 5330 if (ret) { 5331 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret); 5332 return ret; 5333 } 5334 5335 ret = hclge_init_msi(hdev); 5336 if (ret) { 5337 dev_err(&pdev->dev, "Init MSI/MSI-X error, ret = %d.\n", ret); 5338 return ret; 5339 } 5340 5341 ret = hclge_misc_irq_init(hdev); 5342 if (ret) { 5343 dev_err(&pdev->dev, 5344 "Misc IRQ(vector0) init error, ret = %d.\n", 5345 ret); 5346 return ret; 5347 } 5348 5349 ret = hclge_alloc_tqps(hdev); 5350 if (ret) { 5351 dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret); 5352 return ret; 5353 } 5354 5355 ret = hclge_alloc_vport(hdev); 5356 if (ret) { 5357 dev_err(&pdev->dev, "Allocate vport error, ret = %d.\n", ret); 5358 return ret; 5359 } 5360 5361 ret = hclge_map_tqp(hdev); 5362 if (ret) { 5363 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret); 5364 return ret; 5365 } 5366 5367 ret = hclge_mac_mdio_config(hdev); 5368 if (ret) { 5369 dev_warn(&hdev->pdev->dev, 5370 "mdio config fail ret=%d\n", ret); 5371 return ret; 5372 } 5373 5374 ret = hclge_mac_init(hdev); 5375 if (ret) { 5376 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret); 5377 return ret; 5378 } 5379 ret = hclge_buffer_alloc(hdev); 5380 if (ret) { 5381 dev_err(&pdev->dev, "Buffer allocate fail, ret =%d\n", ret); 5382 return ret; 5383 } 5384 5385 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX); 5386 if (ret) { 5387 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret); 5388 return ret; 5389 } 5390 5391 ret = hclge_init_vlan_config(hdev); 5392 if (ret) { 5393 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret); 5394 return ret; 5395 } 5396 5397 ret = hclge_tm_schd_init(hdev); 5398 if (ret) { 5399 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret); 5400 return ret; 5401 } 5402 5403 ret = hclge_rss_init_hw(hdev); 5404 if (ret) { 5405 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret); 5406 return ret; 5407 } 5408 5409 ret = init_mgr_tbl(hdev); 5410 if (ret) { 5411 dev_err(&pdev->dev, "manager table init fail, ret =%d\n", ret); 5412 return ret; 5413 } 5414 5415 hclge_dcb_ops_set(hdev); 5416 5417 timer_setup(&hdev->service_timer, hclge_service_timer, 0); 5418 INIT_WORK(&hdev->service_task, hclge_service_task); 5419 INIT_WORK(&hdev->rst_service_task, hclge_reset_service_task); 5420 INIT_WORK(&hdev->mbx_service_task, hclge_mailbox_service_task); 5421 5422 /* Enable MISC vector(vector0) */ 5423 hclge_enable_vector(&hdev->misc_vector, true); 5424 5425 set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state); 5426 set_bit(HCLGE_STATE_DOWN, &hdev->state); 5427 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state); 5428 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 5429 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state); 5430 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state); 5431 5432 pr_info("%s driver initialization finished.\n", HCLGE_DRIVER_NAME); 5433 return 0; 5434 5435 err_cmd_init: 5436 pci_release_regions(pdev); 5437 err_pci_init: 5438 pci_set_drvdata(pdev, NULL); 5439 err_hclge_dev: 5440 return ret; 5441 } 5442 5443 static void hclge_stats_clear(struct hclge_dev *hdev) 5444 { 5445 memset(&hdev->hw_stats, 0, sizeof(hdev->hw_stats)); 5446 } 5447 5448 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev) 5449 { 5450 struct hclge_dev *hdev = ae_dev->priv; 5451 struct pci_dev *pdev = ae_dev->pdev; 5452 int ret; 5453 5454 set_bit(HCLGE_STATE_DOWN, &hdev->state); 5455 5456 hclge_stats_clear(hdev); 5457 5458 ret = hclge_cmd_init(hdev); 5459 if (ret) { 5460 dev_err(&pdev->dev, "Cmd queue init failed\n"); 5461 return ret; 5462 } 5463 5464 ret = hclge_get_cap(hdev); 5465 if (ret) { 5466 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n", 5467 ret); 5468 return ret; 5469 } 5470 5471 ret = hclge_configure(hdev); 5472 if (ret) { 5473 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret); 5474 return ret; 5475 } 5476 5477 ret = hclge_map_tqp(hdev); 5478 if (ret) { 5479 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret); 5480 return ret; 5481 } 5482 5483 ret = hclge_mac_init(hdev); 5484 if (ret) { 5485 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret); 5486 return ret; 5487 } 5488 5489 ret = hclge_buffer_alloc(hdev); 5490 if (ret) { 5491 dev_err(&pdev->dev, "Buffer allocate fail, ret =%d\n", ret); 5492 return ret; 5493 } 5494 5495 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX); 5496 if (ret) { 5497 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret); 5498 return ret; 5499 } 5500 5501 ret = hclge_init_vlan_config(hdev); 5502 if (ret) { 5503 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret); 5504 return ret; 5505 } 5506 5507 ret = hclge_tm_schd_init(hdev); 5508 if (ret) { 5509 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret); 5510 return ret; 5511 } 5512 5513 ret = hclge_rss_init_hw(hdev); 5514 if (ret) { 5515 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret); 5516 return ret; 5517 } 5518 5519 /* Enable MISC vector(vector0) */ 5520 hclge_enable_vector(&hdev->misc_vector, true); 5521 5522 dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n", 5523 HCLGE_DRIVER_NAME); 5524 5525 return 0; 5526 } 5527 5528 static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 5529 { 5530 struct hclge_dev *hdev = ae_dev->priv; 5531 struct hclge_mac *mac = &hdev->hw.mac; 5532 5533 set_bit(HCLGE_STATE_DOWN, &hdev->state); 5534 5535 if (IS_ENABLED(CONFIG_PCI_IOV)) 5536 hclge_disable_sriov(hdev); 5537 5538 if (hdev->service_timer.function) 5539 del_timer_sync(&hdev->service_timer); 5540 if (hdev->service_task.func) 5541 cancel_work_sync(&hdev->service_task); 5542 if (hdev->rst_service_task.func) 5543 cancel_work_sync(&hdev->rst_service_task); 5544 if (hdev->mbx_service_task.func) 5545 cancel_work_sync(&hdev->mbx_service_task); 5546 5547 if (mac->phydev) 5548 mdiobus_unregister(mac->mdio_bus); 5549 5550 /* Disable MISC vector(vector0) */ 5551 hclge_enable_vector(&hdev->misc_vector, false); 5552 hclge_destroy_cmd_queue(&hdev->hw); 5553 hclge_misc_irq_uninit(hdev); 5554 hclge_pci_uninit(hdev); 5555 ae_dev->priv = NULL; 5556 } 5557 5558 static u32 hclge_get_max_channels(struct hnae3_handle *handle) 5559 { 5560 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 5561 struct hclge_vport *vport = hclge_get_vport(handle); 5562 struct hclge_dev *hdev = vport->back; 5563 5564 return min_t(u32, hdev->rss_size_max * kinfo->num_tc, hdev->num_tqps); 5565 } 5566 5567 static void hclge_get_channels(struct hnae3_handle *handle, 5568 struct ethtool_channels *ch) 5569 { 5570 struct hclge_vport *vport = hclge_get_vport(handle); 5571 5572 ch->max_combined = hclge_get_max_channels(handle); 5573 ch->other_count = 1; 5574 ch->max_other = 1; 5575 ch->combined_count = vport->alloc_tqps; 5576 } 5577 5578 static void hclge_get_tqps_and_rss_info(struct hnae3_handle *handle, 5579 u16 *free_tqps, u16 *max_rss_size) 5580 { 5581 struct hclge_vport *vport = hclge_get_vport(handle); 5582 struct hclge_dev *hdev = vport->back; 5583 u16 temp_tqps = 0; 5584 int i; 5585 5586 for (i = 0; i < hdev->num_tqps; i++) { 5587 if (!hdev->htqp[i].alloced) 5588 temp_tqps++; 5589 } 5590 *free_tqps = temp_tqps; 5591 *max_rss_size = hdev->rss_size_max; 5592 } 5593 5594 static void hclge_release_tqp(struct hclge_vport *vport) 5595 { 5596 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 5597 struct hclge_dev *hdev = vport->back; 5598 int i; 5599 5600 for (i = 0; i < kinfo->num_tqps; i++) { 5601 struct hclge_tqp *tqp = 5602 container_of(kinfo->tqp[i], struct hclge_tqp, q); 5603 5604 tqp->q.handle = NULL; 5605 tqp->q.tqp_index = 0; 5606 tqp->alloced = false; 5607 } 5608 5609 devm_kfree(&hdev->pdev->dev, kinfo->tqp); 5610 kinfo->tqp = NULL; 5611 } 5612 5613 static int hclge_set_channels(struct hnae3_handle *handle, u32 new_tqps_num) 5614 { 5615 struct hclge_vport *vport = hclge_get_vport(handle); 5616 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 5617 struct hclge_dev *hdev = vport->back; 5618 int cur_rss_size = kinfo->rss_size; 5619 int cur_tqps = kinfo->num_tqps; 5620 u16 tc_offset[HCLGE_MAX_TC_NUM]; 5621 u16 tc_valid[HCLGE_MAX_TC_NUM]; 5622 u16 tc_size[HCLGE_MAX_TC_NUM]; 5623 u16 roundup_size; 5624 u32 *rss_indir; 5625 int ret, i; 5626 5627 hclge_release_tqp(vport); 5628 5629 ret = hclge_knic_setup(vport, new_tqps_num); 5630 if (ret) { 5631 dev_err(&hdev->pdev->dev, "setup nic fail, ret =%d\n", ret); 5632 return ret; 5633 } 5634 5635 ret = hclge_map_tqp_to_vport(hdev, vport); 5636 if (ret) { 5637 dev_err(&hdev->pdev->dev, "map vport tqp fail, ret =%d\n", ret); 5638 return ret; 5639 } 5640 5641 ret = hclge_tm_schd_init(hdev); 5642 if (ret) { 5643 dev_err(&hdev->pdev->dev, "tm schd init fail, ret =%d\n", ret); 5644 return ret; 5645 } 5646 5647 roundup_size = roundup_pow_of_two(kinfo->rss_size); 5648 roundup_size = ilog2(roundup_size); 5649 /* Set the RSS TC mode according to the new RSS size */ 5650 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 5651 tc_valid[i] = 0; 5652 5653 if (!(hdev->hw_tc_map & BIT(i))) 5654 continue; 5655 5656 tc_valid[i] = 1; 5657 tc_size[i] = roundup_size; 5658 tc_offset[i] = kinfo->rss_size * i; 5659 } 5660 ret = hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset); 5661 if (ret) 5662 return ret; 5663 5664 /* Reinitializes the rss indirect table according to the new RSS size */ 5665 rss_indir = kcalloc(HCLGE_RSS_IND_TBL_SIZE, sizeof(u32), GFP_KERNEL); 5666 if (!rss_indir) 5667 return -ENOMEM; 5668 5669 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++) 5670 rss_indir[i] = i % kinfo->rss_size; 5671 5672 ret = hclge_set_rss(handle, rss_indir, NULL, 0); 5673 if (ret) 5674 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n", 5675 ret); 5676 5677 kfree(rss_indir); 5678 5679 if (!ret) 5680 dev_info(&hdev->pdev->dev, 5681 "Channels changed, rss_size from %d to %d, tqps from %d to %d", 5682 cur_rss_size, kinfo->rss_size, 5683 cur_tqps, kinfo->rss_size * kinfo->num_tc); 5684 5685 return ret; 5686 } 5687 5688 static int hclge_get_regs_num(struct hclge_dev *hdev, u32 *regs_num_32_bit, 5689 u32 *regs_num_64_bit) 5690 { 5691 struct hclge_desc desc; 5692 u32 total_num; 5693 int ret; 5694 5695 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_REG_NUM, true); 5696 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5697 if (ret) { 5698 dev_err(&hdev->pdev->dev, 5699 "Query register number cmd failed, ret = %d.\n", ret); 5700 return ret; 5701 } 5702 5703 *regs_num_32_bit = le32_to_cpu(desc.data[0]); 5704 *regs_num_64_bit = le32_to_cpu(desc.data[1]); 5705 5706 total_num = *regs_num_32_bit + *regs_num_64_bit; 5707 if (!total_num) 5708 return -EINVAL; 5709 5710 return 0; 5711 } 5712 5713 static int hclge_get_32_bit_regs(struct hclge_dev *hdev, u32 regs_num, 5714 void *data) 5715 { 5716 #define HCLGE_32_BIT_REG_RTN_DATANUM 8 5717 5718 struct hclge_desc *desc; 5719 u32 *reg_val = data; 5720 __le32 *desc_data; 5721 int cmd_num; 5722 int i, k, n; 5723 int ret; 5724 5725 if (regs_num == 0) 5726 return 0; 5727 5728 cmd_num = DIV_ROUND_UP(regs_num + 2, HCLGE_32_BIT_REG_RTN_DATANUM); 5729 desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL); 5730 if (!desc) 5731 return -ENOMEM; 5732 5733 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_32_BIT_REG, true); 5734 ret = hclge_cmd_send(&hdev->hw, desc, cmd_num); 5735 if (ret) { 5736 dev_err(&hdev->pdev->dev, 5737 "Query 32 bit register cmd failed, ret = %d.\n", ret); 5738 kfree(desc); 5739 return ret; 5740 } 5741 5742 for (i = 0; i < cmd_num; i++) { 5743 if (i == 0) { 5744 desc_data = (__le32 *)(&desc[i].data[0]); 5745 n = HCLGE_32_BIT_REG_RTN_DATANUM - 2; 5746 } else { 5747 desc_data = (__le32 *)(&desc[i]); 5748 n = HCLGE_32_BIT_REG_RTN_DATANUM; 5749 } 5750 for (k = 0; k < n; k++) { 5751 *reg_val++ = le32_to_cpu(*desc_data++); 5752 5753 regs_num--; 5754 if (!regs_num) 5755 break; 5756 } 5757 } 5758 5759 kfree(desc); 5760 return 0; 5761 } 5762 5763 static int hclge_get_64_bit_regs(struct hclge_dev *hdev, u32 regs_num, 5764 void *data) 5765 { 5766 #define HCLGE_64_BIT_REG_RTN_DATANUM 4 5767 5768 struct hclge_desc *desc; 5769 u64 *reg_val = data; 5770 __le64 *desc_data; 5771 int cmd_num; 5772 int i, k, n; 5773 int ret; 5774 5775 if (regs_num == 0) 5776 return 0; 5777 5778 cmd_num = DIV_ROUND_UP(regs_num + 1, HCLGE_64_BIT_REG_RTN_DATANUM); 5779 desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL); 5780 if (!desc) 5781 return -ENOMEM; 5782 5783 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_64_BIT_REG, true); 5784 ret = hclge_cmd_send(&hdev->hw, desc, cmd_num); 5785 if (ret) { 5786 dev_err(&hdev->pdev->dev, 5787 "Query 64 bit register cmd failed, ret = %d.\n", ret); 5788 kfree(desc); 5789 return ret; 5790 } 5791 5792 for (i = 0; i < cmd_num; i++) { 5793 if (i == 0) { 5794 desc_data = (__le64 *)(&desc[i].data[0]); 5795 n = HCLGE_64_BIT_REG_RTN_DATANUM - 1; 5796 } else { 5797 desc_data = (__le64 *)(&desc[i]); 5798 n = HCLGE_64_BIT_REG_RTN_DATANUM; 5799 } 5800 for (k = 0; k < n; k++) { 5801 *reg_val++ = le64_to_cpu(*desc_data++); 5802 5803 regs_num--; 5804 if (!regs_num) 5805 break; 5806 } 5807 } 5808 5809 kfree(desc); 5810 return 0; 5811 } 5812 5813 static int hclge_get_regs_len(struct hnae3_handle *handle) 5814 { 5815 struct hclge_vport *vport = hclge_get_vport(handle); 5816 struct hclge_dev *hdev = vport->back; 5817 u32 regs_num_32_bit, regs_num_64_bit; 5818 int ret; 5819 5820 ret = hclge_get_regs_num(hdev, ®s_num_32_bit, ®s_num_64_bit); 5821 if (ret) { 5822 dev_err(&hdev->pdev->dev, 5823 "Get register number failed, ret = %d.\n", ret); 5824 return -EOPNOTSUPP; 5825 } 5826 5827 return regs_num_32_bit * sizeof(u32) + regs_num_64_bit * sizeof(u64); 5828 } 5829 5830 static void hclge_get_regs(struct hnae3_handle *handle, u32 *version, 5831 void *data) 5832 { 5833 struct hclge_vport *vport = hclge_get_vport(handle); 5834 struct hclge_dev *hdev = vport->back; 5835 u32 regs_num_32_bit, regs_num_64_bit; 5836 int ret; 5837 5838 *version = hdev->fw_version; 5839 5840 ret = hclge_get_regs_num(hdev, ®s_num_32_bit, ®s_num_64_bit); 5841 if (ret) { 5842 dev_err(&hdev->pdev->dev, 5843 "Get register number failed, ret = %d.\n", ret); 5844 return; 5845 } 5846 5847 ret = hclge_get_32_bit_regs(hdev, regs_num_32_bit, data); 5848 if (ret) { 5849 dev_err(&hdev->pdev->dev, 5850 "Get 32 bit register failed, ret = %d.\n", ret); 5851 return; 5852 } 5853 5854 data = (u32 *)data + regs_num_32_bit; 5855 ret = hclge_get_64_bit_regs(hdev, regs_num_64_bit, 5856 data); 5857 if (ret) 5858 dev_err(&hdev->pdev->dev, 5859 "Get 64 bit register failed, ret = %d.\n", ret); 5860 } 5861 5862 static int hclge_set_led_status_sfp(struct hclge_dev *hdev, u8 speed_led_status, 5863 u8 act_led_status, u8 link_led_status, 5864 u8 locate_led_status) 5865 { 5866 struct hclge_set_led_state_cmd *req; 5867 struct hclge_desc desc; 5868 int ret; 5869 5870 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_LED_STATUS_CFG, false); 5871 5872 req = (struct hclge_set_led_state_cmd *)desc.data; 5873 hnae_set_field(req->port_speed_led_config, HCLGE_LED_PORT_SPEED_STATE_M, 5874 HCLGE_LED_PORT_SPEED_STATE_S, speed_led_status); 5875 hnae_set_field(req->link_led_config, HCLGE_LED_ACTIVITY_STATE_M, 5876 HCLGE_LED_ACTIVITY_STATE_S, act_led_status); 5877 hnae_set_field(req->activity_led_config, HCLGE_LED_LINK_STATE_M, 5878 HCLGE_LED_LINK_STATE_S, link_led_status); 5879 hnae_set_field(req->locate_led_config, HCLGE_LED_LOCATE_STATE_M, 5880 HCLGE_LED_LOCATE_STATE_S, locate_led_status); 5881 5882 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5883 if (ret) 5884 dev_err(&hdev->pdev->dev, 5885 "Send set led state cmd error, ret =%d\n", ret); 5886 5887 return ret; 5888 } 5889 5890 enum hclge_led_status { 5891 HCLGE_LED_OFF, 5892 HCLGE_LED_ON, 5893 HCLGE_LED_NO_CHANGE = 0xFF, 5894 }; 5895 5896 static int hclge_set_led_id(struct hnae3_handle *handle, 5897 enum ethtool_phys_id_state status) 5898 { 5899 #define BLINK_FREQUENCY 2 5900 struct hclge_vport *vport = hclge_get_vport(handle); 5901 struct hclge_dev *hdev = vport->back; 5902 struct phy_device *phydev = hdev->hw.mac.phydev; 5903 int ret = 0; 5904 5905 if (phydev || hdev->hw.mac.media_type != HNAE3_MEDIA_TYPE_FIBER) 5906 return -EOPNOTSUPP; 5907 5908 switch (status) { 5909 case ETHTOOL_ID_ACTIVE: 5910 ret = hclge_set_led_status_sfp(hdev, 5911 HCLGE_LED_NO_CHANGE, 5912 HCLGE_LED_NO_CHANGE, 5913 HCLGE_LED_NO_CHANGE, 5914 HCLGE_LED_ON); 5915 break; 5916 case ETHTOOL_ID_INACTIVE: 5917 ret = hclge_set_led_status_sfp(hdev, 5918 HCLGE_LED_NO_CHANGE, 5919 HCLGE_LED_NO_CHANGE, 5920 HCLGE_LED_NO_CHANGE, 5921 HCLGE_LED_OFF); 5922 break; 5923 default: 5924 ret = -EINVAL; 5925 break; 5926 } 5927 5928 return ret; 5929 } 5930 5931 enum hclge_led_port_speed { 5932 HCLGE_SPEED_LED_FOR_1G, 5933 HCLGE_SPEED_LED_FOR_10G, 5934 HCLGE_SPEED_LED_FOR_25G, 5935 HCLGE_SPEED_LED_FOR_40G, 5936 HCLGE_SPEED_LED_FOR_50G, 5937 HCLGE_SPEED_LED_FOR_100G, 5938 }; 5939 5940 static u8 hclge_led_get_speed_status(u32 speed) 5941 { 5942 u8 speed_led; 5943 5944 switch (speed) { 5945 case HCLGE_MAC_SPEED_1G: 5946 speed_led = HCLGE_SPEED_LED_FOR_1G; 5947 break; 5948 case HCLGE_MAC_SPEED_10G: 5949 speed_led = HCLGE_SPEED_LED_FOR_10G; 5950 break; 5951 case HCLGE_MAC_SPEED_25G: 5952 speed_led = HCLGE_SPEED_LED_FOR_25G; 5953 break; 5954 case HCLGE_MAC_SPEED_40G: 5955 speed_led = HCLGE_SPEED_LED_FOR_40G; 5956 break; 5957 case HCLGE_MAC_SPEED_50G: 5958 speed_led = HCLGE_SPEED_LED_FOR_50G; 5959 break; 5960 case HCLGE_MAC_SPEED_100G: 5961 speed_led = HCLGE_SPEED_LED_FOR_100G; 5962 break; 5963 default: 5964 speed_led = HCLGE_LED_NO_CHANGE; 5965 } 5966 5967 return speed_led; 5968 } 5969 5970 static int hclge_update_led_status(struct hclge_dev *hdev) 5971 { 5972 u8 port_speed_status, link_status, activity_status; 5973 u64 rx_pkts, tx_pkts; 5974 5975 if (hdev->hw.mac.media_type != HNAE3_MEDIA_TYPE_FIBER) 5976 return 0; 5977 5978 port_speed_status = hclge_led_get_speed_status(hdev->hw.mac.speed); 5979 5980 rx_pkts = hdev->hw_stats.mac_stats.mac_rx_total_pkt_num; 5981 tx_pkts = hdev->hw_stats.mac_stats.mac_tx_total_pkt_num; 5982 if (rx_pkts != hdev->rx_pkts_for_led || 5983 tx_pkts != hdev->tx_pkts_for_led) 5984 activity_status = HCLGE_LED_ON; 5985 else 5986 activity_status = HCLGE_LED_OFF; 5987 hdev->rx_pkts_for_led = rx_pkts; 5988 hdev->tx_pkts_for_led = tx_pkts; 5989 5990 if (hdev->hw.mac.link) 5991 link_status = HCLGE_LED_ON; 5992 else 5993 link_status = HCLGE_LED_OFF; 5994 5995 return hclge_set_led_status_sfp(hdev, port_speed_status, 5996 activity_status, link_status, 5997 HCLGE_LED_NO_CHANGE); 5998 } 5999 6000 static const struct hnae3_ae_ops hclge_ops = { 6001 .init_ae_dev = hclge_init_ae_dev, 6002 .uninit_ae_dev = hclge_uninit_ae_dev, 6003 .init_client_instance = hclge_init_client_instance, 6004 .uninit_client_instance = hclge_uninit_client_instance, 6005 .map_ring_to_vector = hclge_map_ring_to_vector, 6006 .unmap_ring_from_vector = hclge_unmap_ring_frm_vector, 6007 .get_vector = hclge_get_vector, 6008 .set_promisc_mode = hclge_set_promisc_mode, 6009 .set_loopback = hclge_set_loopback, 6010 .start = hclge_ae_start, 6011 .stop = hclge_ae_stop, 6012 .get_status = hclge_get_status, 6013 .get_ksettings_an_result = hclge_get_ksettings_an_result, 6014 .update_speed_duplex_h = hclge_update_speed_duplex_h, 6015 .cfg_mac_speed_dup_h = hclge_cfg_mac_speed_dup_h, 6016 .get_media_type = hclge_get_media_type, 6017 .get_rss_key_size = hclge_get_rss_key_size, 6018 .get_rss_indir_size = hclge_get_rss_indir_size, 6019 .get_rss = hclge_get_rss, 6020 .set_rss = hclge_set_rss, 6021 .set_rss_tuple = hclge_set_rss_tuple, 6022 .get_rss_tuple = hclge_get_rss_tuple, 6023 .get_tc_size = hclge_get_tc_size, 6024 .get_mac_addr = hclge_get_mac_addr, 6025 .set_mac_addr = hclge_set_mac_addr, 6026 .add_uc_addr = hclge_add_uc_addr, 6027 .rm_uc_addr = hclge_rm_uc_addr, 6028 .add_mc_addr = hclge_add_mc_addr, 6029 .rm_mc_addr = hclge_rm_mc_addr, 6030 .set_autoneg = hclge_set_autoneg, 6031 .get_autoneg = hclge_get_autoneg, 6032 .get_pauseparam = hclge_get_pauseparam, 6033 .set_pauseparam = hclge_set_pauseparam, 6034 .set_mtu = hclge_set_mtu, 6035 .reset_queue = hclge_reset_tqp, 6036 .get_stats = hclge_get_stats, 6037 .update_stats = hclge_update_stats, 6038 .get_strings = hclge_get_strings, 6039 .get_sset_count = hclge_get_sset_count, 6040 .get_fw_version = hclge_get_fw_version, 6041 .get_mdix_mode = hclge_get_mdix_mode, 6042 .enable_vlan_filter = hclge_enable_vlan_filter, 6043 .set_vlan_filter = hclge_set_port_vlan_filter, 6044 .set_vf_vlan_filter = hclge_set_vf_vlan_filter, 6045 .enable_hw_strip_rxvtag = hclge_en_hw_strip_rxvtag, 6046 .reset_event = hclge_reset_event, 6047 .get_tqps_and_rss_info = hclge_get_tqps_and_rss_info, 6048 .set_channels = hclge_set_channels, 6049 .get_channels = hclge_get_channels, 6050 .get_flowctrl_adv = hclge_get_flowctrl_adv, 6051 .get_regs_len = hclge_get_regs_len, 6052 .get_regs = hclge_get_regs, 6053 .set_led_id = hclge_set_led_id, 6054 }; 6055 6056 static struct hnae3_ae_algo ae_algo = { 6057 .ops = &hclge_ops, 6058 .name = HCLGE_NAME, 6059 .pdev_id_table = ae_algo_pci_tbl, 6060 }; 6061 6062 static int hclge_init(void) 6063 { 6064 pr_info("%s is initializing\n", HCLGE_NAME); 6065 6066 return hnae3_register_ae_algo(&ae_algo); 6067 } 6068 6069 static void hclge_exit(void) 6070 { 6071 hnae3_unregister_ae_algo(&ae_algo); 6072 } 6073 module_init(hclge_init); 6074 module_exit(hclge_exit); 6075 6076 MODULE_LICENSE("GPL"); 6077 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 6078 MODULE_DESCRIPTION("HCLGE Driver"); 6079 MODULE_VERSION(HCLGE_MOD_VERSION); 6080