1/* 2 * Samsung's Exynos5433 SoC device tree source 3 * 4 * Copyright (c) 2016 Samsung Electronics Co., Ltd. 5 * 6 * Samsung's Exynos5433 SoC device nodes are listed in this file. 7 * Exynos5433 based board files can include this file and provide 8 * values for board specific bindings. 9 * 10 * Note: This file does not include device nodes for all the controllers in 11 * Exynos5433 SoC. As device tree coverage for Exynos5433 increases, 12 * additional nodes can be added to this file. 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License version 2 as 16 * published by the Free Software Foundation. 17 */ 18 19#include <dt-bindings/clock/exynos5433.h> 20#include <dt-bindings/interrupt-controller/arm-gic.h> 21 22/ { 23 compatible = "samsung,exynos5433"; 24 #address-cells = <2>; 25 #size-cells = <2>; 26 27 interrupt-parent = <&gic>; 28 29 cpus { 30 #address-cells = <1>; 31 #size-cells = <0>; 32 33 cpu0: cpu@100 { 34 device_type = "cpu"; 35 compatible = "arm,cortex-a53", "arm,armv8"; 36 enable-method = "psci"; 37 reg = <0x100>; 38 clock-frequency = <1300000000>; 39 clocks = <&cmu_apollo CLK_SCLK_APOLLO>; 40 clock-names = "apolloclk"; 41 operating-points-v2 = <&cluster_a53_opp_table>; 42 #cooling-cells = <2>; 43 }; 44 45 cpu1: cpu@101 { 46 device_type = "cpu"; 47 compatible = "arm,cortex-a53", "arm,armv8"; 48 enable-method = "psci"; 49 reg = <0x101>; 50 clock-frequency = <1300000000>; 51 operating-points-v2 = <&cluster_a53_opp_table>; 52 #cooling-cells = <2>; 53 }; 54 55 cpu2: cpu@102 { 56 device_type = "cpu"; 57 compatible = "arm,cortex-a53", "arm,armv8"; 58 enable-method = "psci"; 59 reg = <0x102>; 60 clock-frequency = <1300000000>; 61 operating-points-v2 = <&cluster_a53_opp_table>; 62 #cooling-cells = <2>; 63 }; 64 65 cpu3: cpu@103 { 66 device_type = "cpu"; 67 compatible = "arm,cortex-a53", "arm,armv8"; 68 enable-method = "psci"; 69 reg = <0x103>; 70 clock-frequency = <1300000000>; 71 operating-points-v2 = <&cluster_a53_opp_table>; 72 #cooling-cells = <2>; 73 }; 74 75 cpu4: cpu@0 { 76 device_type = "cpu"; 77 compatible = "arm,cortex-a57", "arm,armv8"; 78 enable-method = "psci"; 79 reg = <0x0>; 80 clock-frequency = <1900000000>; 81 clocks = <&cmu_atlas CLK_SCLK_ATLAS>; 82 clock-names = "atlasclk"; 83 operating-points-v2 = <&cluster_a57_opp_table>; 84 #cooling-cells = <2>; 85 }; 86 87 cpu5: cpu@1 { 88 device_type = "cpu"; 89 compatible = "arm,cortex-a57", "arm,armv8"; 90 enable-method = "psci"; 91 reg = <0x1>; 92 clock-frequency = <1900000000>; 93 operating-points-v2 = <&cluster_a57_opp_table>; 94 #cooling-cells = <2>; 95 }; 96 97 cpu6: cpu@2 { 98 device_type = "cpu"; 99 compatible = "arm,cortex-a57", "arm,armv8"; 100 enable-method = "psci"; 101 reg = <0x2>; 102 clock-frequency = <1900000000>; 103 operating-points-v2 = <&cluster_a57_opp_table>; 104 #cooling-cells = <2>; 105 }; 106 107 cpu7: cpu@3 { 108 device_type = "cpu"; 109 compatible = "arm,cortex-a57", "arm,armv8"; 110 enable-method = "psci"; 111 reg = <0x3>; 112 clock-frequency = <1900000000>; 113 operating-points-v2 = <&cluster_a57_opp_table>; 114 #cooling-cells = <2>; 115 }; 116 }; 117 118 cluster_a53_opp_table: opp_table0 { 119 compatible = "operating-points-v2"; 120 opp-shared; 121 122 opp-400000000 { 123 opp-hz = /bits/ 64 <400000000>; 124 opp-microvolt = <900000>; 125 }; 126 opp-500000000 { 127 opp-hz = /bits/ 64 <500000000>; 128 opp-microvolt = <925000>; 129 }; 130 opp-600000000 { 131 opp-hz = /bits/ 64 <600000000>; 132 opp-microvolt = <950000>; 133 }; 134 opp-700000000 { 135 opp-hz = /bits/ 64 <700000000>; 136 opp-microvolt = <975000>; 137 }; 138 opp-800000000 { 139 opp-hz = /bits/ 64 <800000000>; 140 opp-microvolt = <1000000>; 141 }; 142 opp-900000000 { 143 opp-hz = /bits/ 64 <900000000>; 144 opp-microvolt = <1050000>; 145 }; 146 opp-1000000000 { 147 opp-hz = /bits/ 64 <1000000000>; 148 opp-microvolt = <1075000>; 149 }; 150 opp-1100000000 { 151 opp-hz = /bits/ 64 <1100000000>; 152 opp-microvolt = <1112500>; 153 }; 154 opp-1200000000 { 155 opp-hz = /bits/ 64 <1200000000>; 156 opp-microvolt = <1112500>; 157 }; 158 opp-1300000000 { 159 opp-hz = /bits/ 64 <1300000000>; 160 opp-microvolt = <1150000>; 161 }; 162 }; 163 164 cluster_a57_opp_table: opp_table1 { 165 compatible = "operating-points-v2"; 166 opp-shared; 167 168 opp-500000000 { 169 opp-hz = /bits/ 64 <500000000>; 170 opp-microvolt = <900000>; 171 }; 172 opp-600000000 { 173 opp-hz = /bits/ 64 <600000000>; 174 opp-microvolt = <900000>; 175 }; 176 opp-700000000 { 177 opp-hz = /bits/ 64 <700000000>; 178 opp-microvolt = <912500>; 179 }; 180 opp-800000000 { 181 opp-hz = /bits/ 64 <800000000>; 182 opp-microvolt = <912500>; 183 }; 184 opp-900000000 { 185 opp-hz = /bits/ 64 <900000000>; 186 opp-microvolt = <937500>; 187 }; 188 opp-1000000000 { 189 opp-hz = /bits/ 64 <1000000000>; 190 opp-microvolt = <975000>; 191 }; 192 opp-1100000000 { 193 opp-hz = /bits/ 64 <1100000000>; 194 opp-microvolt = <1012500>; 195 }; 196 opp-1200000000 { 197 opp-hz = /bits/ 64 <1200000000>; 198 opp-microvolt = <1037500>; 199 }; 200 opp-1300000000 { 201 opp-hz = /bits/ 64 <1300000000>; 202 opp-microvolt = <1062500>; 203 }; 204 opp-1400000000 { 205 opp-hz = /bits/ 64 <1400000000>; 206 opp-microvolt = <1087500>; 207 }; 208 opp-1500000000 { 209 opp-hz = /bits/ 64 <1500000000>; 210 opp-microvolt = <1125000>; 211 }; 212 opp-1600000000 { 213 opp-hz = /bits/ 64 <1600000000>; 214 opp-microvolt = <1137500>; 215 }; 216 opp-1700000000 { 217 opp-hz = /bits/ 64 <1700000000>; 218 opp-microvolt = <1175000>; 219 }; 220 opp-1800000000 { 221 opp-hz = /bits/ 64 <1800000000>; 222 opp-microvolt = <1212500>; 223 }; 224 opp-1900000000 { 225 opp-hz = /bits/ 64 <1900000000>; 226 opp-microvolt = <1262500>; 227 }; 228 }; 229 230 psci { 231 compatible = "arm,psci"; 232 method = "smc"; 233 cpu_off = <0x84000002>; 234 cpu_on = <0xC4000003>; 235 }; 236 237 reboot: syscon-reboot { 238 compatible = "syscon-reboot"; 239 regmap = <&pmu_system_controller>; 240 offset = <0x400>; /* SWRESET */ 241 mask = <0x1>; 242 }; 243 244 soc: soc { 245 compatible = "simple-bus"; 246 #address-cells = <1>; 247 #size-cells = <1>; 248 ranges = <0x0 0x0 0x0 0x18000000>; 249 250 arm_a53_pmu { 251 compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3"; 252 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 253 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 254 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 255 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 256 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 257 }; 258 259 arm_a57_pmu { 260 compatible = "arm,cortex-a57-pmu", "arm,armv8-pmuv3"; 261 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 262 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 263 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 264 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 265 interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; 266 }; 267 268 chipid@10000000 { 269 compatible = "samsung,exynos4210-chipid"; 270 reg = <0x10000000 0x100>; 271 }; 272 273 xxti: xxti { 274 compatible = "fixed-clock"; 275 clock-output-names = "oscclk"; 276 #clock-cells = <0>; 277 }; 278 279 cmu_top: clock-controller@10030000 { 280 compatible = "samsung,exynos5433-cmu-top"; 281 reg = <0x10030000 0x1000>; 282 #clock-cells = <1>; 283 284 clock-names = "oscclk", 285 "sclk_mphy_pll", 286 "sclk_mfc_pll", 287 "sclk_bus_pll"; 288 clocks = <&xxti>, 289 <&cmu_cpif CLK_SCLK_MPHY_PLL>, 290 <&cmu_mif CLK_SCLK_MFC_PLL>, 291 <&cmu_mif CLK_SCLK_BUS_PLL>; 292 }; 293 294 cmu_cpif: clock-controller@10fc0000 { 295 compatible = "samsung,exynos5433-cmu-cpif"; 296 reg = <0x10fc0000 0x1000>; 297 #clock-cells = <1>; 298 299 clock-names = "oscclk"; 300 clocks = <&xxti>; 301 }; 302 303 cmu_mif: clock-controller@105b0000 { 304 compatible = "samsung,exynos5433-cmu-mif"; 305 reg = <0x105b0000 0x2000>; 306 #clock-cells = <1>; 307 308 clock-names = "oscclk", 309 "sclk_mphy_pll"; 310 clocks = <&xxti>, 311 <&cmu_cpif CLK_SCLK_MPHY_PLL>; 312 }; 313 314 cmu_peric: clock-controller@14c80000 { 315 compatible = "samsung,exynos5433-cmu-peric"; 316 reg = <0x14c80000 0x1000>; 317 #clock-cells = <1>; 318 }; 319 320 cmu_peris: clock-controller@10040000 { 321 compatible = "samsung,exynos5433-cmu-peris"; 322 reg = <0x10040000 0x1000>; 323 #clock-cells = <1>; 324 }; 325 326 cmu_fsys: clock-controller@156e0000 { 327 compatible = "samsung,exynos5433-cmu-fsys"; 328 reg = <0x156e0000 0x1000>; 329 #clock-cells = <1>; 330 331 clock-names = "oscclk", 332 "sclk_ufs_mphy", 333 "aclk_fsys_200", 334 "sclk_pcie_100_fsys", 335 "sclk_ufsunipro_fsys", 336 "sclk_mmc2_fsys", 337 "sclk_mmc1_fsys", 338 "sclk_mmc0_fsys", 339 "sclk_usbhost30_fsys", 340 "sclk_usbdrd30_fsys"; 341 clocks = <&xxti>, 342 <&cmu_cpif CLK_SCLK_UFS_MPHY>, 343 <&cmu_top CLK_ACLK_FSYS_200>, 344 <&cmu_top CLK_SCLK_PCIE_100_FSYS>, 345 <&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>, 346 <&cmu_top CLK_SCLK_MMC2_FSYS>, 347 <&cmu_top CLK_SCLK_MMC1_FSYS>, 348 <&cmu_top CLK_SCLK_MMC0_FSYS>, 349 <&cmu_top CLK_SCLK_USBHOST30_FSYS>, 350 <&cmu_top CLK_SCLK_USBDRD30_FSYS>; 351 }; 352 353 cmu_g2d: clock-controller@12460000 { 354 compatible = "samsung,exynos5433-cmu-g2d"; 355 reg = <0x12460000 0x1000>; 356 #clock-cells = <1>; 357 358 clock-names = "oscclk", 359 "aclk_g2d_266", 360 "aclk_g2d_400"; 361 clocks = <&xxti>, 362 <&cmu_top CLK_ACLK_G2D_266>, 363 <&cmu_top CLK_ACLK_G2D_400>; 364 power-domains = <&pd_g2d>; 365 }; 366 367 cmu_disp: clock-controller@13b90000 { 368 compatible = "samsung,exynos5433-cmu-disp"; 369 reg = <0x13b90000 0x1000>; 370 #clock-cells = <1>; 371 372 clock-names = "oscclk", 373 "sclk_dsim1_disp", 374 "sclk_dsim0_disp", 375 "sclk_dsd_disp", 376 "sclk_decon_tv_eclk_disp", 377 "sclk_decon_vclk_disp", 378 "sclk_decon_eclk_disp", 379 "sclk_decon_tv_vclk_disp", 380 "aclk_disp_333"; 381 clocks = <&xxti>, 382 <&cmu_mif CLK_SCLK_DSIM1_DISP>, 383 <&cmu_mif CLK_SCLK_DSIM0_DISP>, 384 <&cmu_mif CLK_SCLK_DSD_DISP>, 385 <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>, 386 <&cmu_mif CLK_SCLK_DECON_VCLK_DISP>, 387 <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>, 388 <&cmu_mif CLK_SCLK_DECON_TV_VCLK_DISP>, 389 <&cmu_mif CLK_ACLK_DISP_333>; 390 power-domains = <&pd_disp>; 391 }; 392 393 cmu_aud: clock-controller@114c0000 { 394 compatible = "samsung,exynos5433-cmu-aud"; 395 reg = <0x114c0000 0x1000>; 396 #clock-cells = <1>; 397 clock-names = "oscclk", "fout_aud_pll"; 398 clocks = <&xxti>, <&cmu_top CLK_FOUT_AUD_PLL>; 399 power-domains = <&pd_aud>; 400 }; 401 402 cmu_bus0: clock-controller@13600000 { 403 compatible = "samsung,exynos5433-cmu-bus0"; 404 reg = <0x13600000 0x1000>; 405 #clock-cells = <1>; 406 407 clock-names = "aclk_bus0_400"; 408 clocks = <&cmu_top CLK_ACLK_BUS0_400>; 409 }; 410 411 cmu_bus1: clock-controller@14800000 { 412 compatible = "samsung,exynos5433-cmu-bus1"; 413 reg = <0x14800000 0x1000>; 414 #clock-cells = <1>; 415 416 clock-names = "aclk_bus1_400"; 417 clocks = <&cmu_top CLK_ACLK_BUS1_400>; 418 }; 419 420 cmu_bus2: clock-controller@13400000 { 421 compatible = "samsung,exynos5433-cmu-bus2"; 422 reg = <0x13400000 0x1000>; 423 #clock-cells = <1>; 424 425 clock-names = "oscclk", "aclk_bus2_400"; 426 clocks = <&xxti>, <&cmu_mif CLK_ACLK_BUS2_400>; 427 }; 428 429 cmu_g3d: clock-controller@14aa0000 { 430 compatible = "samsung,exynos5433-cmu-g3d"; 431 reg = <0x14aa0000 0x2000>; 432 #clock-cells = <1>; 433 434 clock-names = "oscclk", "aclk_g3d_400"; 435 clocks = <&xxti>, <&cmu_top CLK_ACLK_G3D_400>; 436 power-domains = <&pd_g3d>; 437 }; 438 439 cmu_gscl: clock-controller@13cf0000 { 440 compatible = "samsung,exynos5433-cmu-gscl"; 441 reg = <0x13cf0000 0x1000>; 442 #clock-cells = <1>; 443 444 clock-names = "oscclk", 445 "aclk_gscl_111", 446 "aclk_gscl_333"; 447 clocks = <&xxti>, 448 <&cmu_top CLK_ACLK_GSCL_111>, 449 <&cmu_top CLK_ACLK_GSCL_333>; 450 power-domains = <&pd_gscl>; 451 }; 452 453 cmu_apollo: clock-controller@11900000 { 454 compatible = "samsung,exynos5433-cmu-apollo"; 455 reg = <0x11900000 0x2000>; 456 #clock-cells = <1>; 457 458 clock-names = "oscclk", "sclk_bus_pll_apollo"; 459 clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_APOLLO>; 460 }; 461 462 cmu_atlas: clock-controller@11800000 { 463 compatible = "samsung,exynos5433-cmu-atlas"; 464 reg = <0x11800000 0x2000>; 465 #clock-cells = <1>; 466 467 clock-names = "oscclk", "sclk_bus_pll_atlas"; 468 clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_ATLAS>; 469 }; 470 471 cmu_mscl: clock-controller@105d0000 { 472 compatible = "samsung,exynos5433-cmu-mscl"; 473 reg = <0x150d0000 0x1000>; 474 #clock-cells = <1>; 475 476 clock-names = "oscclk", 477 "sclk_jpeg_mscl", 478 "aclk_mscl_400"; 479 clocks = <&xxti>, 480 <&cmu_top CLK_SCLK_JPEG_MSCL>, 481 <&cmu_top CLK_ACLK_MSCL_400>; 482 power-domains = <&pd_mscl>; 483 }; 484 485 cmu_mfc: clock-controller@15280000 { 486 compatible = "samsung,exynos5433-cmu-mfc"; 487 reg = <0x15280000 0x1000>; 488 #clock-cells = <1>; 489 490 clock-names = "oscclk", "aclk_mfc_400"; 491 clocks = <&xxti>, <&cmu_top CLK_ACLK_MFC_400>; 492 power-domains = <&pd_mfc>; 493 }; 494 495 cmu_hevc: clock-controller@14f80000 { 496 compatible = "samsung,exynos5433-cmu-hevc"; 497 reg = <0x14f80000 0x1000>; 498 #clock-cells = <1>; 499 500 clock-names = "oscclk", "aclk_hevc_400"; 501 clocks = <&xxti>, <&cmu_top CLK_ACLK_HEVC_400>; 502 power-domains = <&pd_hevc>; 503 }; 504 505 cmu_isp: clock-controller@146d0000 { 506 compatible = "samsung,exynos5433-cmu-isp"; 507 reg = <0x146d0000 0x1000>; 508 #clock-cells = <1>; 509 510 clock-names = "oscclk", 511 "aclk_isp_dis_400", 512 "aclk_isp_400"; 513 clocks = <&xxti>, 514 <&cmu_top CLK_ACLK_ISP_DIS_400>, 515 <&cmu_top CLK_ACLK_ISP_400>; 516 power-domains = <&pd_isp>; 517 }; 518 519 cmu_cam0: clock-controller@120d0000 { 520 compatible = "samsung,exynos5433-cmu-cam0"; 521 reg = <0x120d0000 0x1000>; 522 #clock-cells = <1>; 523 524 clock-names = "oscclk", 525 "aclk_cam0_333", 526 "aclk_cam0_400", 527 "aclk_cam0_552"; 528 clocks = <&xxti>, 529 <&cmu_top CLK_ACLK_CAM0_333>, 530 <&cmu_top CLK_ACLK_CAM0_400>, 531 <&cmu_top CLK_ACLK_CAM0_552>; 532 power-domains = <&pd_cam0>; 533 }; 534 535 cmu_cam1: clock-controller@145d0000 { 536 compatible = "samsung,exynos5433-cmu-cam1"; 537 reg = <0x145d0000 0x1000>; 538 #clock-cells = <1>; 539 540 clock-names = "oscclk", 541 "sclk_isp_uart_cam1", 542 "sclk_isp_spi1_cam1", 543 "sclk_isp_spi0_cam1", 544 "aclk_cam1_333", 545 "aclk_cam1_400", 546 "aclk_cam1_552"; 547 clocks = <&xxti>, 548 <&cmu_top CLK_SCLK_ISP_UART_CAM1>, 549 <&cmu_top CLK_SCLK_ISP_SPI1_CAM1>, 550 <&cmu_top CLK_SCLK_ISP_SPI0_CAM1>, 551 <&cmu_top CLK_ACLK_CAM1_333>, 552 <&cmu_top CLK_ACLK_CAM1_400>, 553 <&cmu_top CLK_ACLK_CAM1_552>; 554 power-domains = <&pd_cam1>; 555 }; 556 557 pd_gscl: power-domain@105c4000 { 558 compatible = "samsung,exynos5433-pd"; 559 reg = <0x105c4000 0x20>; 560 #power-domain-cells = <0>; 561 label = "GSCL"; 562 }; 563 564 pd_cam0: power-domain@105c4020 { 565 compatible = "samsung,exynos5433-pd"; 566 reg = <0x105c4020 0x20>; 567 #power-domain-cells = <0>; 568 power-domains = <&pd_cam1>; 569 label = "CAM0"; 570 }; 571 572 pd_mscl: power-domain@105c4040 { 573 compatible = "samsung,exynos5433-pd"; 574 reg = <0x105c4040 0x20>; 575 #power-domain-cells = <0>; 576 label = "MSCL"; 577 }; 578 579 pd_g3d: power-domain@105c4060 { 580 compatible = "samsung,exynos5433-pd"; 581 reg = <0x105c4060 0x20>; 582 #power-domain-cells = <0>; 583 label = "G3D"; 584 }; 585 586 pd_disp: power-domain@105c4080 { 587 compatible = "samsung,exynos5433-pd"; 588 reg = <0x105c4080 0x20>; 589 #power-domain-cells = <0>; 590 label = "DISP"; 591 }; 592 593 pd_cam1: power-domain@105c40a0 { 594 compatible = "samsung,exynos5433-pd"; 595 reg = <0x105c40a0 0x20>; 596 #power-domain-cells = <0>; 597 label = "CAM1"; 598 }; 599 600 pd_aud: power-domain@105c40c0 { 601 compatible = "samsung,exynos5433-pd"; 602 reg = <0x105c40c0 0x20>; 603 #power-domain-cells = <0>; 604 label = "AUD"; 605 }; 606 607 pd_g2d: power-domain@105c4120 { 608 compatible = "samsung,exynos5433-pd"; 609 reg = <0x105c4120 0x20>; 610 #power-domain-cells = <0>; 611 label = "G2D"; 612 }; 613 614 pd_isp: power-domain@105c4140 { 615 compatible = "samsung,exynos5433-pd"; 616 reg = <0x105c4140 0x20>; 617 #power-domain-cells = <0>; 618 power-domains = <&pd_cam0>; 619 label = "ISP"; 620 }; 621 622 pd_mfc: power-domain@105c4180 { 623 compatible = "samsung,exynos5433-pd"; 624 reg = <0x105c4180 0x20>; 625 #power-domain-cells = <0>; 626 label = "MFC"; 627 }; 628 629 pd_hevc: power-domain@105c41c0 { 630 compatible = "samsung,exynos5433-pd"; 631 reg = <0x105c41c0 0x20>; 632 #power-domain-cells = <0>; 633 label = "HEVC"; 634 }; 635 636 tmu_atlas0: tmu@10060000 { 637 compatible = "samsung,exynos5433-tmu"; 638 reg = <0x10060000 0x200>; 639 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 640 clocks = <&cmu_peris CLK_PCLK_TMU0_APBIF>, 641 <&cmu_peris CLK_SCLK_TMU0>; 642 clock-names = "tmu_apbif", "tmu_sclk"; 643 #include "exynos5433-tmu-sensor-conf.dtsi" 644 status = "disabled"; 645 }; 646 647 tmu_atlas1: tmu@10068000 { 648 compatible = "samsung,exynos5433-tmu"; 649 reg = <0x10068000 0x200>; 650 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 651 clocks = <&cmu_peris CLK_PCLK_TMU0_APBIF>, 652 <&cmu_peris CLK_SCLK_TMU0>; 653 clock-names = "tmu_apbif", "tmu_sclk"; 654 #include "exynos5433-tmu-sensor-conf.dtsi" 655 status = "disabled"; 656 }; 657 658 tmu_g3d: tmu@10070000 { 659 compatible = "samsung,exynos5433-tmu"; 660 reg = <0x10070000 0x200>; 661 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 662 clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>, 663 <&cmu_peris CLK_SCLK_TMU1>; 664 clock-names = "tmu_apbif", "tmu_sclk"; 665 #include "exynos5433-tmu-g3d-sensor-conf.dtsi" 666 status = "disabled"; 667 }; 668 669 tmu_apollo: tmu@10078000 { 670 compatible = "samsung,exynos5433-tmu"; 671 reg = <0x10078000 0x200>; 672 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 673 clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>, 674 <&cmu_peris CLK_SCLK_TMU1>; 675 clock-names = "tmu_apbif", "tmu_sclk"; 676 #include "exynos5433-tmu-sensor-conf.dtsi" 677 status = "disabled"; 678 }; 679 680 tmu_isp: tmu@1007c000 { 681 compatible = "samsung,exynos5433-tmu"; 682 reg = <0x1007c000 0x200>; 683 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 684 clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>, 685 <&cmu_peris CLK_SCLK_TMU1>; 686 clock-names = "tmu_apbif", "tmu_sclk"; 687 #include "exynos5433-tmu-sensor-conf.dtsi" 688 status = "disabled"; 689 }; 690 691 mct@101c0000 { 692 compatible = "samsung,exynos4210-mct"; 693 reg = <0x101c0000 0x800>; 694 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 695 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 696 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 697 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 698 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 699 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 700 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 701 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 702 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 703 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 704 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 705 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 706 clocks = <&xxti>, <&cmu_peris CLK_PCLK_MCT>; 707 clock-names = "fin_pll", "mct"; 708 }; 709 710 ppmu_d0_cpu: ppmu@10480000 { 711 compatible = "samsung,exynos-ppmu-v2"; 712 reg = <0x10480000 0x2000>; 713 status = "disabled"; 714 }; 715 716 ppmu_d0_general: ppmu@10490000 { 717 compatible = "samsung,exynos-ppmu-v2"; 718 reg = <0x10490000 0x2000>; 719 status = "disabled"; 720 }; 721 722 ppmu_d1_cpu: ppmu@104b0000 { 723 compatible = "samsung,exynos-ppmu-v2"; 724 reg = <0x104b0000 0x2000>; 725 status = "disabled"; 726 }; 727 728 ppmu_d1_general: ppmu@104c0000 { 729 compatible = "samsung,exynos-ppmu-v2"; 730 reg = <0x104c0000 0x2000>; 731 status = "disabled"; 732 }; 733 734 pinctrl_alive: pinctrl@10580000 { 735 compatible = "samsung,exynos5433-pinctrl"; 736 reg = <0x10580000 0x1a20>, <0x11090000 0x100>; 737 738 wakeup-interrupt-controller { 739 compatible = "samsung,exynos7-wakeup-eint"; 740 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 741 }; 742 }; 743 744 pinctrl_aud: pinctrl@114b0000 { 745 compatible = "samsung,exynos5433-pinctrl"; 746 reg = <0x114b0000 0x1000>; 747 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 748 power-domains = <&pd_aud>; 749 }; 750 751 pinctrl_cpif: pinctrl@10fe0000 { 752 compatible = "samsung,exynos5433-pinctrl"; 753 reg = <0x10fe0000 0x1000>; 754 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 755 }; 756 757 pinctrl_ese: pinctrl@14ca0000 { 758 compatible = "samsung,exynos5433-pinctrl"; 759 reg = <0x14ca0000 0x1000>; 760 interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>; 761 }; 762 763 pinctrl_finger: pinctrl@14cb0000 { 764 compatible = "samsung,exynos5433-pinctrl"; 765 reg = <0x14cb0000 0x1000>; 766 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>; 767 }; 768 769 pinctrl_fsys: pinctrl@15690000 { 770 compatible = "samsung,exynos5433-pinctrl"; 771 reg = <0x15690000 0x1000>; 772 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 773 }; 774 775 pinctrl_imem: pinctrl@11090000 { 776 compatible = "samsung,exynos5433-pinctrl"; 777 reg = <0x11090000 0x1000>; 778 interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>; 779 }; 780 781 pinctrl_nfc: pinctrl@14cd0000 { 782 compatible = "samsung,exynos5433-pinctrl"; 783 reg = <0x14cd0000 0x1000>; 784 interrupts = <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>; 785 }; 786 787 pinctrl_peric: pinctrl@14cc0000 { 788 compatible = "samsung,exynos5433-pinctrl"; 789 reg = <0x14cc0000 0x1100>; 790 interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>; 791 }; 792 793 pinctrl_touch: pinctrl@14ce0000 { 794 compatible = "samsung,exynos5433-pinctrl"; 795 reg = <0x14ce0000 0x1100>; 796 interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>; 797 }; 798 799 pmu_system_controller: system-controller@105c0000 { 800 compatible = "samsung,exynos5433-pmu", "syscon"; 801 reg = <0x105c0000 0x5008>; 802 #clock-cells = <1>; 803 clock-names = "clkout16"; 804 clocks = <&xxti>; 805 }; 806 807 gic: interrupt-controller@11001000 { 808 compatible = "arm,gic-400"; 809 #interrupt-cells = <3>; 810 interrupt-controller; 811 reg = <0x11001000 0x1000>, 812 <0x11002000 0x2000>, 813 <0x11004000 0x2000>, 814 <0x11006000 0x2000>; 815 interrupts = <GIC_PPI 9 0xf04>; 816 }; 817 818 mipi_phy: video-phy { 819 compatible = "samsung,exynos5433-mipi-video-phy"; 820 #phy-cells = <1>; 821 samsung,pmu-syscon = <&pmu_system_controller>; 822 samsung,cam0-sysreg = <&syscon_cam0>; 823 samsung,cam1-sysreg = <&syscon_cam1>; 824 samsung,disp-sysreg = <&syscon_disp>; 825 }; 826 827 decon: decon@13800000 { 828 compatible = "samsung,exynos5433-decon"; 829 reg = <0x13800000 0x2104>; 830 clocks = <&cmu_disp CLK_PCLK_DECON>, 831 <&cmu_disp CLK_ACLK_DECON>, 832 <&cmu_disp CLK_ACLK_SMMU_DECON0X>, 833 <&cmu_disp CLK_ACLK_XIU_DECON0X>, 834 <&cmu_disp CLK_PCLK_SMMU_DECON0X>, 835 <&cmu_disp CLK_SCLK_DECON_VCLK>, 836 <&cmu_disp CLK_SCLK_DECON_ECLK>; 837 clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x", 838 "aclk_xiu_decon0x", "pclk_smmu_decon0x", 839 "sclk_decon_vclk", "sclk_decon_eclk"; 840 power-domains = <&pd_disp>; 841 interrupt-names = "fifo", "vsync", "lcd_sys"; 842 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 843 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 844 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 845 samsung,disp-sysreg = <&syscon_disp>; 846 status = "disabled"; 847 iommus = <&sysmmu_decon0x>, <&sysmmu_decon1x>; 848 iommu-names = "m0", "m1"; 849 850 ports { 851 #address-cells = <1>; 852 #size-cells = <0>; 853 854 port@0 { 855 reg = <0>; 856 decon_to_mic: endpoint { 857 remote-endpoint = 858 <&mic_to_decon>; 859 }; 860 }; 861 }; 862 }; 863 864 decon_tv: decon@13880000 { 865 compatible = "samsung,exynos5433-decon-tv"; 866 reg = <0x13880000 0x20b8>; 867 clocks = <&cmu_disp CLK_PCLK_DECON_TV>, 868 <&cmu_disp CLK_ACLK_DECON_TV>, 869 <&cmu_disp CLK_ACLK_SMMU_TV0X>, 870 <&cmu_disp CLK_ACLK_XIU_TV0X>, 871 <&cmu_disp CLK_PCLK_SMMU_TV0X>, 872 <&cmu_disp CLK_SCLK_DECON_TV_VCLK>, 873 <&cmu_disp CLK_SCLK_DECON_TV_ECLK>; 874 clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x", 875 "aclk_xiu_decon0x", "pclk_smmu_decon0x", 876 "sclk_decon_vclk", "sclk_decon_eclk"; 877 samsung,disp-sysreg = <&syscon_disp>; 878 power-domains = <&pd_disp>; 879 interrupt-names = "fifo", "vsync", "lcd_sys"; 880 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 881 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 882 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; 883 status = "disabled"; 884 iommus = <&sysmmu_tv0x>, <&sysmmu_tv1x>; 885 iommu-names = "m0", "m1"; 886 }; 887 888 dsi: dsi@13900000 { 889 compatible = "samsung,exynos5433-mipi-dsi"; 890 reg = <0x13900000 0xC0>; 891 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 892 phys = <&mipi_phy 1>; 893 phy-names = "dsim"; 894 clocks = <&cmu_disp CLK_PCLK_DSIM0>, 895 <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8>, 896 <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0>, 897 <&cmu_disp CLK_SCLK_RGB_VCLK_TO_DSIM0>, 898 <&cmu_disp CLK_SCLK_DSIM0>; 899 clock-names = "bus_clk", 900 "phyclk_mipidphy0_bitclkdiv8", 901 "phyclk_mipidphy0_rxclkesc0", 902 "sclk_rgb_vclk_to_dsim0", 903 "sclk_mipi"; 904 power-domains = <&pd_disp>; 905 status = "disabled"; 906 #address-cells = <1>; 907 #size-cells = <0>; 908 909 ports { 910 #address-cells = <1>; 911 #size-cells = <0>; 912 913 port@0 { 914 reg = <0>; 915 dsi_to_mic: endpoint { 916 remote-endpoint = <&mic_to_dsi>; 917 }; 918 }; 919 }; 920 }; 921 922 mic: mic@13930000 { 923 compatible = "samsung,exynos5433-mic"; 924 reg = <0x13930000 0x48>; 925 clocks = <&cmu_disp CLK_PCLK_MIC0>, 926 <&cmu_disp CLK_SCLK_RGB_VCLK_TO_MIC0>; 927 clock-names = "pclk_mic0", "sclk_rgb_vclk_to_mic0"; 928 power-domains = <&pd_disp>; 929 samsung,disp-syscon = <&syscon_disp>; 930 status = "disabled"; 931 932 ports { 933 #address-cells = <1>; 934 #size-cells = <0>; 935 936 port@0 { 937 reg = <0>; 938 mic_to_decon: endpoint { 939 remote-endpoint = 940 <&decon_to_mic>; 941 }; 942 }; 943 944 port@1 { 945 reg = <1>; 946 mic_to_dsi: endpoint { 947 remote-endpoint = <&dsi_to_mic>; 948 }; 949 }; 950 }; 951 }; 952 953 hdmi: hdmi@13970000 { 954 compatible = "samsung,exynos5433-hdmi"; 955 reg = <0x13970000 0x70000>; 956 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 957 clocks = <&cmu_disp CLK_PCLK_HDMI>, 958 <&cmu_disp CLK_PCLK_HDMIPHY>, 959 <&cmu_disp CLK_PHYCLK_HDMIPHY_TMDS_CLKO>, 960 <&cmu_disp CLK_PHYCLK_HDMI_PIXEL>, 961 <&cmu_disp CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY>, 962 <&cmu_disp CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER>, 963 <&cmu_disp CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY>, 964 <&cmu_disp CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER>, 965 <&xxti>, <&cmu_disp CLK_SCLK_HDMI_SPDIF>; 966 clock-names = "hdmi_pclk", "hdmi_i_pclk", 967 "i_tmds_clk", "i_pixel_clk", 968 "tmds_clko", "tmds_clko_user", 969 "pixel_clko", "pixel_clko_user", 970 "oscclk", "i_spdif_clk"; 971 phy = <&hdmiphy>; 972 ddc = <&hsi2c_11>; 973 samsung,syscon-phandle = <&pmu_system_controller>; 974 samsung,sysreg-phandle = <&syscon_disp>; 975 status = "disabled"; 976 }; 977 978 hdmiphy: hdmiphy@13af0000 { 979 reg = <0x13af0000 0x80>; 980 }; 981 982 syscon_disp: syscon@13b80000 { 983 compatible = "syscon"; 984 reg = <0x13b80000 0x1010>; 985 }; 986 987 syscon_cam0: syscon@120f0000 { 988 compatible = "syscon"; 989 reg = <0x120f0000 0x1020>; 990 }; 991 992 syscon_cam1: syscon@145f0000 { 993 compatible = "syscon"; 994 reg = <0x145f0000 0x1038>; 995 }; 996 997 gsc_0: video-scaler@13C00000 { 998 compatible = "samsung,exynos5433-gsc"; 999 reg = <0x13c00000 0x1000>; 1000 interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>; 1001 clock-names = "pclk", "aclk", "aclk_xiu", 1002 "aclk_gsclbend"; 1003 clocks = <&cmu_gscl CLK_PCLK_GSCL0>, 1004 <&cmu_gscl CLK_ACLK_GSCL0>, 1005 <&cmu_gscl CLK_ACLK_XIU_GSCLX>, 1006 <&cmu_gscl CLK_ACLK_GSCLBEND_333>; 1007 iommus = <&sysmmu_gscl0>; 1008 power-domains = <&pd_gscl>; 1009 }; 1010 1011 gsc_1: video-scaler@13C10000 { 1012 compatible = "samsung,exynos5433-gsc"; 1013 reg = <0x13c10000 0x1000>; 1014 interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1015 clock-names = "pclk", "aclk", "aclk_xiu", 1016 "aclk_gsclbend"; 1017 clocks = <&cmu_gscl CLK_PCLK_GSCL1>, 1018 <&cmu_gscl CLK_ACLK_GSCL1>, 1019 <&cmu_gscl CLK_ACLK_XIU_GSCLX>, 1020 <&cmu_gscl CLK_ACLK_GSCLBEND_333>; 1021 iommus = <&sysmmu_gscl1>; 1022 power-domains = <&pd_gscl>; 1023 }; 1024 1025 gsc_2: video-scaler@13C20000 { 1026 compatible = "samsung,exynos5433-gsc"; 1027 reg = <0x13c20000 0x1000>; 1028 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 1029 clock-names = "pclk", "aclk", "aclk_xiu", 1030 "aclk_gsclbend"; 1031 clocks = <&cmu_gscl CLK_PCLK_GSCL2>, 1032 <&cmu_gscl CLK_ACLK_GSCL2>, 1033 <&cmu_gscl CLK_ACLK_XIU_GSCLX>, 1034 <&cmu_gscl CLK_ACLK_GSCLBEND_333>; 1035 iommus = <&sysmmu_gscl2>; 1036 power-domains = <&pd_gscl>; 1037 }; 1038 1039 jpeg: codec@15020000 { 1040 compatible = "samsung,exynos5433-jpeg"; 1041 reg = <0x15020000 0x10000>; 1042 interrupts = <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>; 1043 clock-names = "pclk", "aclk", "aclk_xiu", "sclk"; 1044 clocks = <&cmu_mscl CLK_PCLK_JPEG>, 1045 <&cmu_mscl CLK_ACLK_JPEG>, 1046 <&cmu_mscl CLK_ACLK_XIU_MSCLX>, 1047 <&cmu_mscl CLK_SCLK_JPEG>; 1048 iommus = <&sysmmu_jpeg>; 1049 power-domains = <&pd_mscl>; 1050 }; 1051 1052 mfc: codec@152E0000 { 1053 compatible = "samsung,exynos5433-mfc"; 1054 reg = <0x152E0000 0x10000>; 1055 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1056 clock-names = "pclk", "aclk", "aclk_xiu"; 1057 clocks = <&cmu_mfc CLK_PCLK_MFC>, 1058 <&cmu_mfc CLK_ACLK_MFC>, 1059 <&cmu_mfc CLK_ACLK_XIU_MFCX>; 1060 iommus = <&sysmmu_mfc_0>, <&sysmmu_mfc_1>; 1061 iommu-names = "left", "right"; 1062 power-domains = <&pd_mfc>; 1063 }; 1064 1065 sysmmu_decon0x: sysmmu@13a00000 { 1066 compatible = "samsung,exynos-sysmmu"; 1067 reg = <0x13a00000 0x1000>; 1068 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 1069 clock-names = "pclk", "aclk"; 1070 clocks = <&cmu_disp CLK_PCLK_SMMU_DECON0X>, 1071 <&cmu_disp CLK_ACLK_SMMU_DECON0X>; 1072 power-domains = <&pd_disp>; 1073 #iommu-cells = <0>; 1074 }; 1075 1076 sysmmu_decon1x: sysmmu@13a10000 { 1077 compatible = "samsung,exynos-sysmmu"; 1078 reg = <0x13a10000 0x1000>; 1079 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 1080 clock-names = "pclk", "aclk"; 1081 clocks = <&cmu_disp CLK_PCLK_SMMU_DECON1X>, 1082 <&cmu_disp CLK_ACLK_SMMU_DECON1X>; 1083 #iommu-cells = <0>; 1084 power-domains = <&pd_disp>; 1085 }; 1086 1087 sysmmu_tv0x: sysmmu@13a20000 { 1088 compatible = "samsung,exynos-sysmmu"; 1089 reg = <0x13a20000 0x1000>; 1090 interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; 1091 clock-names = "pclk", "aclk"; 1092 clocks = <&cmu_disp CLK_PCLK_SMMU_TV0X>, 1093 <&cmu_disp CLK_ACLK_SMMU_TV0X>; 1094 #iommu-cells = <0>; 1095 power-domains = <&pd_disp>; 1096 }; 1097 1098 sysmmu_tv1x: sysmmu@13a30000 { 1099 compatible = "samsung,exynos-sysmmu"; 1100 reg = <0x13a30000 0x1000>; 1101 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; 1102 clock-names = "pclk", "aclk"; 1103 clocks = <&cmu_disp CLK_PCLK_SMMU_TV1X>, 1104 <&cmu_disp CLK_ACLK_SMMU_TV1X>; 1105 #iommu-cells = <0>; 1106 power-domains = <&pd_disp>; 1107 }; 1108 1109 sysmmu_gscl0: sysmmu@13c80000 { 1110 compatible = "samsung,exynos-sysmmu"; 1111 reg = <0x13C80000 0x1000>; 1112 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 1113 clock-names = "aclk", "pclk"; 1114 clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL0>, 1115 <&cmu_gscl CLK_PCLK_SMMU_GSCL0>; 1116 #iommu-cells = <0>; 1117 power-domains = <&pd_gscl>; 1118 }; 1119 1120 sysmmu_gscl1: sysmmu@13c90000 { 1121 compatible = "samsung,exynos-sysmmu"; 1122 reg = <0x13C90000 0x1000>; 1123 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 1124 clock-names = "aclk", "pclk"; 1125 clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL1>, 1126 <&cmu_gscl CLK_PCLK_SMMU_GSCL1>; 1127 #iommu-cells = <0>; 1128 power-domains = <&pd_gscl>; 1129 }; 1130 1131 sysmmu_gscl2: sysmmu@13ca0000 { 1132 compatible = "samsung,exynos-sysmmu"; 1133 reg = <0x13CA0000 0x1000>; 1134 interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>; 1135 clock-names = "aclk", "pclk"; 1136 clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL2>, 1137 <&cmu_gscl CLK_PCLK_SMMU_GSCL2>; 1138 #iommu-cells = <0>; 1139 power-domains = <&pd_gscl>; 1140 }; 1141 1142 sysmmu_jpeg: sysmmu@15060000 { 1143 compatible = "samsung,exynos-sysmmu"; 1144 reg = <0x15060000 0x1000>; 1145 interrupts = <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 1146 clock-names = "pclk", "aclk"; 1147 clocks = <&cmu_mscl CLK_PCLK_SMMU_JPEG>, 1148 <&cmu_mscl CLK_ACLK_SMMU_JPEG>; 1149 #iommu-cells = <0>; 1150 power-domains = <&pd_mscl>; 1151 }; 1152 1153 sysmmu_mfc_0: sysmmu@15200000 { 1154 compatible = "samsung,exynos-sysmmu"; 1155 reg = <0x15200000 0x1000>; 1156 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 1157 clock-names = "pclk", "aclk"; 1158 clocks = <&cmu_mfc CLK_PCLK_SMMU_MFC_0>, 1159 <&cmu_mfc CLK_ACLK_SMMU_MFC_0>; 1160 #iommu-cells = <0>; 1161 power-domains = <&pd_mfc>; 1162 }; 1163 1164 sysmmu_mfc_1: sysmmu@15210000 { 1165 compatible = "samsung,exynos-sysmmu"; 1166 reg = <0x15210000 0x1000>; 1167 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1168 clock-names = "pclk", "aclk"; 1169 clocks = <&cmu_mfc CLK_PCLK_SMMU_MFC_1>, 1170 <&cmu_mfc CLK_ACLK_SMMU_MFC_1>; 1171 #iommu-cells = <0>; 1172 power-domains = <&pd_mfc>; 1173 }; 1174 1175 serial_0: serial@14c10000 { 1176 compatible = "samsung,exynos5433-uart"; 1177 reg = <0x14c10000 0x100>; 1178 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>; 1179 clocks = <&cmu_peric CLK_PCLK_UART0>, 1180 <&cmu_peric CLK_SCLK_UART0>; 1181 clock-names = "uart", "clk_uart_baud0"; 1182 pinctrl-names = "default"; 1183 pinctrl-0 = <&uart0_bus>; 1184 status = "disabled"; 1185 }; 1186 1187 serial_1: serial@14c20000 { 1188 compatible = "samsung,exynos5433-uart"; 1189 reg = <0x14c20000 0x100>; 1190 interrupts = <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>; 1191 clocks = <&cmu_peric CLK_PCLK_UART1>, 1192 <&cmu_peric CLK_SCLK_UART1>; 1193 clock-names = "uart", "clk_uart_baud0"; 1194 pinctrl-names = "default"; 1195 pinctrl-0 = <&uart1_bus>; 1196 status = "disabled"; 1197 }; 1198 1199 serial_2: serial@14c30000 { 1200 compatible = "samsung,exynos5433-uart"; 1201 reg = <0x14c30000 0x100>; 1202 interrupts = <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>; 1203 clocks = <&cmu_peric CLK_PCLK_UART2>, 1204 <&cmu_peric CLK_SCLK_UART2>; 1205 clock-names = "uart", "clk_uart_baud0"; 1206 pinctrl-names = "default"; 1207 pinctrl-0 = <&uart2_bus>; 1208 status = "disabled"; 1209 }; 1210 1211 spi_0: spi@14d20000 { 1212 compatible = "samsung,exynos5433-spi"; 1213 reg = <0x14d20000 0x100>; 1214 interrupts = <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>; 1215 dmas = <&pdma0 9>, <&pdma0 8>; 1216 dma-names = "tx", "rx"; 1217 #address-cells = <1>; 1218 #size-cells = <0>; 1219 clocks = <&cmu_peric CLK_PCLK_SPI0>, 1220 <&cmu_peric CLK_SCLK_SPI0>, 1221 <&cmu_peric CLK_SCLK_IOCLK_SPI0>; 1222 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 1223 samsung,spi-src-clk = <0>; 1224 pinctrl-names = "default"; 1225 pinctrl-0 = <&spi0_bus>; 1226 num-cs = <1>; 1227 status = "disabled"; 1228 }; 1229 1230 spi_1: spi@14d30000 { 1231 compatible = "samsung,exynos5433-spi"; 1232 reg = <0x14d30000 0x100>; 1233 interrupts = <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>; 1234 dmas = <&pdma0 11>, <&pdma0 10>; 1235 dma-names = "tx", "rx"; 1236 #address-cells = <1>; 1237 #size-cells = <0>; 1238 clocks = <&cmu_peric CLK_PCLK_SPI1>, 1239 <&cmu_peric CLK_SCLK_SPI1>, 1240 <&cmu_peric CLK_SCLK_IOCLK_SPI1>; 1241 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 1242 samsung,spi-src-clk = <0>; 1243 pinctrl-names = "default"; 1244 pinctrl-0 = <&spi1_bus>; 1245 num-cs = <1>; 1246 status = "disabled"; 1247 }; 1248 1249 spi_2: spi@14d40000 { 1250 compatible = "samsung,exynos5433-spi"; 1251 reg = <0x14d40000 0x100>; 1252 interrupts = <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>; 1253 dmas = <&pdma0 13>, <&pdma0 12>; 1254 dma-names = "tx", "rx"; 1255 #address-cells = <1>; 1256 #size-cells = <0>; 1257 clocks = <&cmu_peric CLK_PCLK_SPI2>, 1258 <&cmu_peric CLK_SCLK_SPI2>, 1259 <&cmu_peric CLK_SCLK_IOCLK_SPI2>; 1260 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 1261 samsung,spi-src-clk = <0>; 1262 pinctrl-names = "default"; 1263 pinctrl-0 = <&spi2_bus>; 1264 num-cs = <1>; 1265 status = "disabled"; 1266 }; 1267 1268 spi_3: spi@14d50000 { 1269 compatible = "samsung,exynos5433-spi"; 1270 reg = <0x14d50000 0x100>; 1271 interrupts = <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>; 1272 dmas = <&pdma0 23>, <&pdma0 22>; 1273 dma-names = "tx", "rx"; 1274 #address-cells = <1>; 1275 #size-cells = <0>; 1276 clocks = <&cmu_peric CLK_PCLK_SPI3>, 1277 <&cmu_peric CLK_SCLK_SPI3>, 1278 <&cmu_peric CLK_SCLK_IOCLK_SPI3>; 1279 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 1280 samsung,spi-src-clk = <0>; 1281 pinctrl-names = "default"; 1282 pinctrl-0 = <&spi3_bus>; 1283 num-cs = <1>; 1284 status = "disabled"; 1285 }; 1286 1287 spi_4: spi@14d00000 { 1288 compatible = "samsung,exynos5433-spi"; 1289 reg = <0x14d00000 0x100>; 1290 interrupts = <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>; 1291 dmas = <&pdma0 25>, <&pdma0 24>; 1292 dma-names = "tx", "rx"; 1293 #address-cells = <1>; 1294 #size-cells = <0>; 1295 clocks = <&cmu_peric CLK_PCLK_SPI4>, 1296 <&cmu_peric CLK_SCLK_SPI4>, 1297 <&cmu_peric CLK_SCLK_IOCLK_SPI4>; 1298 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 1299 samsung,spi-src-clk = <0>; 1300 pinctrl-names = "default"; 1301 pinctrl-0 = <&spi4_bus>; 1302 num-cs = <1>; 1303 status = "disabled"; 1304 }; 1305 1306 adc: adc@14d10000 { 1307 compatible = "samsung,exynos7-adc"; 1308 reg = <0x14d10000 0x100>; 1309 interrupts = <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>; 1310 clock-names = "adc"; 1311 clocks = <&cmu_peric CLK_PCLK_ADCIF>; 1312 #io-channel-cells = <1>; 1313 io-channel-ranges; 1314 status = "disabled"; 1315 }; 1316 1317 pwm: pwm@14dd0000 { 1318 compatible = "samsung,exynos4210-pwm"; 1319 reg = <0x14dd0000 0x100>; 1320 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 1321 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 1322 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 1323 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 1324 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>; 1325 samsung,pwm-outputs = <0>, <1>, <2>, <3>; 1326 clocks = <&cmu_peric CLK_PCLK_PWM>; 1327 clock-names = "timers"; 1328 #pwm-cells = <3>; 1329 status = "disabled"; 1330 }; 1331 1332 hsi2c_0: hsi2c@14e40000 { 1333 compatible = "samsung,exynos7-hsi2c"; 1334 reg = <0x14e40000 0x1000>; 1335 interrupts = <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>; 1336 #address-cells = <1>; 1337 #size-cells = <0>; 1338 pinctrl-names = "default"; 1339 pinctrl-0 = <&hs_i2c0_bus>; 1340 clocks = <&cmu_peric CLK_PCLK_HSI2C0>; 1341 clock-names = "hsi2c"; 1342 status = "disabled"; 1343 }; 1344 1345 hsi2c_1: hsi2c@14e50000 { 1346 compatible = "samsung,exynos7-hsi2c"; 1347 reg = <0x14e50000 0x1000>; 1348 interrupts = <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>; 1349 #address-cells = <1>; 1350 #size-cells = <0>; 1351 pinctrl-names = "default"; 1352 pinctrl-0 = <&hs_i2c1_bus>; 1353 clocks = <&cmu_peric CLK_PCLK_HSI2C1>; 1354 clock-names = "hsi2c"; 1355 status = "disabled"; 1356 }; 1357 1358 hsi2c_2: hsi2c@14e60000 { 1359 compatible = "samsung,exynos7-hsi2c"; 1360 reg = <0x14e60000 0x1000>; 1361 interrupts = <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>; 1362 #address-cells = <1>; 1363 #size-cells = <0>; 1364 pinctrl-names = "default"; 1365 pinctrl-0 = <&hs_i2c2_bus>; 1366 clocks = <&cmu_peric CLK_PCLK_HSI2C2>; 1367 clock-names = "hsi2c"; 1368 status = "disabled"; 1369 }; 1370 1371 hsi2c_3: hsi2c@14e70000 { 1372 compatible = "samsung,exynos7-hsi2c"; 1373 reg = <0x14e70000 0x1000>; 1374 interrupts = <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>; 1375 #address-cells = <1>; 1376 #size-cells = <0>; 1377 pinctrl-names = "default"; 1378 pinctrl-0 = <&hs_i2c3_bus>; 1379 clocks = <&cmu_peric CLK_PCLK_HSI2C3>; 1380 clock-names = "hsi2c"; 1381 status = "disabled"; 1382 }; 1383 1384 hsi2c_4: hsi2c@14ec0000 { 1385 compatible = "samsung,exynos7-hsi2c"; 1386 reg = <0x14ec0000 0x1000>; 1387 interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>; 1388 #address-cells = <1>; 1389 #size-cells = <0>; 1390 pinctrl-names = "default"; 1391 pinctrl-0 = <&hs_i2c4_bus>; 1392 clocks = <&cmu_peric CLK_PCLK_HSI2C4>; 1393 clock-names = "hsi2c"; 1394 status = "disabled"; 1395 }; 1396 1397 hsi2c_5: hsi2c@14ed0000 { 1398 compatible = "samsung,exynos7-hsi2c"; 1399 reg = <0x14ed0000 0x1000>; 1400 interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 1401 #address-cells = <1>; 1402 #size-cells = <0>; 1403 pinctrl-names = "default"; 1404 pinctrl-0 = <&hs_i2c5_bus>; 1405 clocks = <&cmu_peric CLK_PCLK_HSI2C5>; 1406 clock-names = "hsi2c"; 1407 status = "disabled"; 1408 }; 1409 1410 hsi2c_6: hsi2c@14ee0000 { 1411 compatible = "samsung,exynos7-hsi2c"; 1412 reg = <0x14ee0000 0x1000>; 1413 interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>; 1414 #address-cells = <1>; 1415 #size-cells = <0>; 1416 pinctrl-names = "default"; 1417 pinctrl-0 = <&hs_i2c6_bus>; 1418 clocks = <&cmu_peric CLK_PCLK_HSI2C6>; 1419 clock-names = "hsi2c"; 1420 status = "disabled"; 1421 }; 1422 1423 hsi2c_7: hsi2c@14ef0000 { 1424 compatible = "samsung,exynos7-hsi2c"; 1425 reg = <0x14ef0000 0x1000>; 1426 interrupts = <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>; 1427 #address-cells = <1>; 1428 #size-cells = <0>; 1429 pinctrl-names = "default"; 1430 pinctrl-0 = <&hs_i2c7_bus>; 1431 clocks = <&cmu_peric CLK_PCLK_HSI2C7>; 1432 clock-names = "hsi2c"; 1433 status = "disabled"; 1434 }; 1435 1436 hsi2c_8: hsi2c@14d90000 { 1437 compatible = "samsung,exynos7-hsi2c"; 1438 reg = <0x14d90000 0x1000>; 1439 interrupts = <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>; 1440 #address-cells = <1>; 1441 #size-cells = <0>; 1442 pinctrl-names = "default"; 1443 pinctrl-0 = <&hs_i2c8_bus>; 1444 clocks = <&cmu_peric CLK_PCLK_HSI2C8>; 1445 clock-names = "hsi2c"; 1446 status = "disabled"; 1447 }; 1448 1449 hsi2c_9: hsi2c@14da0000 { 1450 compatible = "samsung,exynos7-hsi2c"; 1451 reg = <0x14da0000 0x1000>; 1452 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>; 1453 #address-cells = <1>; 1454 #size-cells = <0>; 1455 pinctrl-names = "default"; 1456 pinctrl-0 = <&hs_i2c9_bus>; 1457 clocks = <&cmu_peric CLK_PCLK_HSI2C9>; 1458 clock-names = "hsi2c"; 1459 status = "disabled"; 1460 }; 1461 1462 hsi2c_10: hsi2c@14de0000 { 1463 compatible = "samsung,exynos7-hsi2c"; 1464 reg = <0x14de0000 0x1000>; 1465 interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>; 1466 #address-cells = <1>; 1467 #size-cells = <0>; 1468 pinctrl-names = "default"; 1469 pinctrl-0 = <&hs_i2c10_bus>; 1470 clocks = <&cmu_peric CLK_PCLK_HSI2C10>; 1471 clock-names = "hsi2c"; 1472 status = "disabled"; 1473 }; 1474 1475 hsi2c_11: hsi2c@14df0000 { 1476 compatible = "samsung,exynos7-hsi2c"; 1477 reg = <0x14df0000 0x1000>; 1478 interrupts = <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>; 1479 #address-cells = <1>; 1480 #size-cells = <0>; 1481 pinctrl-names = "default"; 1482 pinctrl-0 = <&hs_i2c11_bus>; 1483 clocks = <&cmu_peric CLK_PCLK_HSI2C11>; 1484 clock-names = "hsi2c"; 1485 status = "disabled"; 1486 }; 1487 1488 usbdrd30: usbdrd { 1489 compatible = "samsung,exynos5250-dwusb3"; 1490 clocks = <&cmu_fsys CLK_ACLK_USBDRD30>, 1491 <&cmu_fsys CLK_SCLK_USBDRD30>; 1492 clock-names = "usbdrd30", "usbdrd30_susp_clk"; 1493 #address-cells = <1>; 1494 #size-cells = <1>; 1495 ranges; 1496 status = "disabled"; 1497 1498 usbdrd_dwc3: dwc3@15400000 { 1499 compatible = "snps,dwc3"; 1500 reg = <0x15400000 0x10000>; 1501 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 1502 phys = <&usbdrd30_phy 0>, <&usbdrd30_phy 1>; 1503 phy-names = "usb2-phy", "usb3-phy"; 1504 }; 1505 }; 1506 1507 usbdrd30_phy: phy@15500000 { 1508 compatible = "samsung,exynos5433-usbdrd-phy"; 1509 reg = <0x15500000 0x100>; 1510 clocks = <&cmu_fsys CLK_ACLK_USBDRD30>, <&xxti>, 1511 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK>, 1512 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK>, 1513 <&cmu_fsys CLK_SCLK_USBDRD30>; 1514 clock-names = "phy", "ref", "phy_utmi", "phy_pipe", 1515 "itp"; 1516 #phy-cells = <1>; 1517 samsung,pmu-syscon = <&pmu_system_controller>; 1518 status = "disabled"; 1519 }; 1520 1521 usbhost30_phy: phy@15580000 { 1522 compatible = "samsung,exynos5433-usbdrd-phy"; 1523 reg = <0x15580000 0x100>; 1524 clocks = <&cmu_fsys CLK_ACLK_USBHOST30>, <&xxti>, 1525 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK>, 1526 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK>, 1527 <&cmu_fsys CLK_SCLK_USBHOST30>; 1528 clock-names = "phy", "ref", "phy_utmi", "phy_pipe", 1529 "itp"; 1530 #phy-cells = <1>; 1531 samsung,pmu-syscon = <&pmu_system_controller>; 1532 status = "disabled"; 1533 }; 1534 1535 usbhost30: usbhost { 1536 compatible = "samsung,exynos5250-dwusb3"; 1537 clocks = <&cmu_fsys CLK_ACLK_USBHOST30>, 1538 <&cmu_fsys CLK_SCLK_USBHOST30>; 1539 clock-names = "usbdrd30", "usbdrd30_susp_clk"; 1540 #address-cells = <1>; 1541 #size-cells = <1>; 1542 ranges; 1543 status = "disabled"; 1544 1545 usbhost_dwc3: dwc3@15a00000 { 1546 compatible = "snps,dwc3"; 1547 reg = <0x15a00000 0x10000>; 1548 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 1549 phys = <&usbhost30_phy 0>, <&usbhost30_phy 1>; 1550 phy-names = "usb2-phy", "usb3-phy"; 1551 }; 1552 }; 1553 1554 mshc_0: mshc@15540000 { 1555 compatible = "samsung,exynos7-dw-mshc-smu"; 1556 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 1557 #address-cells = <1>; 1558 #size-cells = <0>; 1559 reg = <0x15540000 0x2000>; 1560 clocks = <&cmu_fsys CLK_ACLK_MMC0>, 1561 <&cmu_fsys CLK_SCLK_MMC0>; 1562 clock-names = "biu", "ciu"; 1563 fifo-depth = <0x40>; 1564 status = "disabled"; 1565 }; 1566 1567 mshc_1: mshc@15550000 { 1568 compatible = "samsung,exynos7-dw-mshc-smu"; 1569 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 1570 #address-cells = <1>; 1571 #size-cells = <0>; 1572 reg = <0x15550000 0x2000>; 1573 clocks = <&cmu_fsys CLK_ACLK_MMC1>, 1574 <&cmu_fsys CLK_SCLK_MMC1>; 1575 clock-names = "biu", "ciu"; 1576 fifo-depth = <0x40>; 1577 status = "disabled"; 1578 }; 1579 1580 mshc_2: mshc@15560000 { 1581 compatible = "samsung,exynos7-dw-mshc-smu"; 1582 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 1583 #address-cells = <1>; 1584 #size-cells = <0>; 1585 reg = <0x15560000 0x2000>; 1586 clocks = <&cmu_fsys CLK_ACLK_MMC2>, 1587 <&cmu_fsys CLK_SCLK_MMC2>; 1588 clock-names = "biu", "ciu"; 1589 fifo-depth = <0x40>; 1590 status = "disabled"; 1591 }; 1592 1593 amba { 1594 compatible = "simple-bus"; 1595 #address-cells = <1>; 1596 #size-cells = <1>; 1597 ranges; 1598 1599 pdma0: pdma@15610000 { 1600 compatible = "arm,pl330", "arm,primecell"; 1601 reg = <0x15610000 0x1000>; 1602 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 1603 clocks = <&cmu_fsys CLK_PDMA0>; 1604 clock-names = "apb_pclk"; 1605 #dma-cells = <1>; 1606 #dma-channels = <8>; 1607 #dma-requests = <32>; 1608 }; 1609 1610 pdma1: pdma@15600000 { 1611 compatible = "arm,pl330", "arm,primecell"; 1612 reg = <0x15600000 0x1000>; 1613 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 1614 clocks = <&cmu_fsys CLK_PDMA1>; 1615 clock-names = "apb_pclk"; 1616 #dma-cells = <1>; 1617 #dma-channels = <8>; 1618 #dma-requests = <32>; 1619 }; 1620 }; 1621 1622 audio-subsystem@11400000 { 1623 compatible = "samsung,exynos5433-lpass"; 1624 reg = <0x11400000 0x100>, <0x11500000 0x08>; 1625 clocks = <&cmu_aud CLK_PCLK_SFR0_CTRL>; 1626 clock-names = "sfr0_ctrl"; 1627 samsung,pmu-syscon = <&pmu_system_controller>; 1628 power-domains = <&pd_aud>; 1629 #address-cells = <1>; 1630 #size-cells = <1>; 1631 ranges; 1632 1633 adma: adma@11420000 { 1634 compatible = "arm,pl330", "arm,primecell"; 1635 reg = <0x11420000 0x1000>; 1636 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 1637 clocks = <&cmu_aud CLK_ACLK_DMAC>; 1638 clock-names = "apb_pclk"; 1639 #dma-cells = <1>; 1640 #dma-channels = <8>; 1641 #dma-requests = <32>; 1642 power-domains = <&pd_aud>; 1643 }; 1644 1645 i2s0: i2s0@11440000 { 1646 compatible = "samsung,exynos7-i2s"; 1647 reg = <0x11440000 0x100>; 1648 dmas = <&adma 0 &adma 2>; 1649 dma-names = "tx", "rx"; 1650 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1651 #address-cells = <1>; 1652 #size-cells = <0>; 1653 clocks = <&cmu_aud CLK_PCLK_AUD_I2S>, 1654 <&cmu_aud CLK_SCLK_AUD_I2S>, 1655 <&cmu_aud CLK_SCLK_I2S_BCLK>; 1656 clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; 1657 pinctrl-names = "default"; 1658 pinctrl-0 = <&i2s0_bus>; 1659 power-domains = <&pd_aud>; 1660 status = "disabled"; 1661 }; 1662 1663 serial_3: serial@11460000 { 1664 compatible = "samsung,exynos5433-uart"; 1665 reg = <0x11460000 0x100>; 1666 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 1667 clocks = <&cmu_aud CLK_PCLK_AUD_UART>, 1668 <&cmu_aud CLK_SCLK_AUD_UART>; 1669 clock-names = "uart", "clk_uart_baud0"; 1670 pinctrl-names = "default"; 1671 pinctrl-0 = <&uart_aud_bus>; 1672 power-domains = <&pd_aud>; 1673 status = "disabled"; 1674 }; 1675 }; 1676 }; 1677 1678 timer: timer { 1679 compatible = "arm,armv8-timer"; 1680 interrupts = <GIC_PPI 13 1681 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>, 1682 <GIC_PPI 14 1683 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>, 1684 <GIC_PPI 11 1685 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>, 1686 <GIC_PPI 10 1687 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 1688 }; 1689}; 1690 1691#include "exynos5433-bus.dtsi" 1692#include "exynos5433-pinctrl.dtsi" 1693#include "exynos5433-tmu.dtsi" 1694