1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * linux/arch/x86_64/entry.S 4 * 5 * Copyright (C) 1991, 1992 Linus Torvalds 6 * Copyright (C) 2000, 2001, 2002 Andi Kleen SuSE Labs 7 * Copyright (C) 2000 Pavel Machek <pavel@suse.cz> 8 * 9 * entry.S contains the system-call and fault low-level handling routines. 10 * 11 * Some of this is documented in Documentation/x86/entry_64.txt 12 * 13 * A note on terminology: 14 * - iret frame: Architecture defined interrupt frame from SS to RIP 15 * at the top of the kernel process stack. 16 * 17 * Some macro usage: 18 * - ENTRY/END: Define functions in the symbol table. 19 * - TRACE_IRQ_*: Trace hardirq state for lock debugging. 20 * - idtentry: Define exception entry points. 21 */ 22#include <linux/linkage.h> 23#include <asm/segment.h> 24#include <asm/cache.h> 25#include <asm/errno.h> 26#include <asm/asm-offsets.h> 27#include <asm/msr.h> 28#include <asm/unistd.h> 29#include <asm/thread_info.h> 30#include <asm/hw_irq.h> 31#include <asm/page_types.h> 32#include <asm/irqflags.h> 33#include <asm/paravirt.h> 34#include <asm/percpu.h> 35#include <asm/asm.h> 36#include <asm/smap.h> 37#include <asm/pgtable_types.h> 38#include <asm/export.h> 39#include <asm/frame.h> 40#include <asm/nospec-branch.h> 41#include <linux/err.h> 42 43#include "calling.h" 44 45.code64 46.section .entry.text, "ax" 47 48#ifdef CONFIG_PARAVIRT 49ENTRY(native_usergs_sysret64) 50 UNWIND_HINT_EMPTY 51 swapgs 52 sysretq 53END(native_usergs_sysret64) 54#endif /* CONFIG_PARAVIRT */ 55 56.macro TRACE_IRQS_FLAGS flags:req 57#ifdef CONFIG_TRACE_IRQFLAGS 58 btl $9, \flags /* interrupts off? */ 59 jnc 1f 60 TRACE_IRQS_ON 611: 62#endif 63.endm 64 65.macro TRACE_IRQS_IRETQ 66 TRACE_IRQS_FLAGS EFLAGS(%rsp) 67.endm 68 69/* 70 * When dynamic function tracer is enabled it will add a breakpoint 71 * to all locations that it is about to modify, sync CPUs, update 72 * all the code, sync CPUs, then remove the breakpoints. In this time 73 * if lockdep is enabled, it might jump back into the debug handler 74 * outside the updating of the IST protection. (TRACE_IRQS_ON/OFF). 75 * 76 * We need to change the IDT table before calling TRACE_IRQS_ON/OFF to 77 * make sure the stack pointer does not get reset back to the top 78 * of the debug stack, and instead just reuses the current stack. 79 */ 80#if defined(CONFIG_DYNAMIC_FTRACE) && defined(CONFIG_TRACE_IRQFLAGS) 81 82.macro TRACE_IRQS_OFF_DEBUG 83 call debug_stack_set_zero 84 TRACE_IRQS_OFF 85 call debug_stack_reset 86.endm 87 88.macro TRACE_IRQS_ON_DEBUG 89 call debug_stack_set_zero 90 TRACE_IRQS_ON 91 call debug_stack_reset 92.endm 93 94.macro TRACE_IRQS_IRETQ_DEBUG 95 bt $9, EFLAGS(%rsp) /* interrupts off? */ 96 jnc 1f 97 TRACE_IRQS_ON_DEBUG 981: 99.endm 100 101#else 102# define TRACE_IRQS_OFF_DEBUG TRACE_IRQS_OFF 103# define TRACE_IRQS_ON_DEBUG TRACE_IRQS_ON 104# define TRACE_IRQS_IRETQ_DEBUG TRACE_IRQS_IRETQ 105#endif 106 107/* 108 * 64-bit SYSCALL instruction entry. Up to 6 arguments in registers. 109 * 110 * This is the only entry point used for 64-bit system calls. The 111 * hardware interface is reasonably well designed and the register to 112 * argument mapping Linux uses fits well with the registers that are 113 * available when SYSCALL is used. 114 * 115 * SYSCALL instructions can be found inlined in libc implementations as 116 * well as some other programs and libraries. There are also a handful 117 * of SYSCALL instructions in the vDSO used, for example, as a 118 * clock_gettimeofday fallback. 119 * 120 * 64-bit SYSCALL saves rip to rcx, clears rflags.RF, then saves rflags to r11, 121 * then loads new ss, cs, and rip from previously programmed MSRs. 122 * rflags gets masked by a value from another MSR (so CLD and CLAC 123 * are not needed). SYSCALL does not save anything on the stack 124 * and does not change rsp. 125 * 126 * Registers on entry: 127 * rax system call number 128 * rcx return address 129 * r11 saved rflags (note: r11 is callee-clobbered register in C ABI) 130 * rdi arg0 131 * rsi arg1 132 * rdx arg2 133 * r10 arg3 (needs to be moved to rcx to conform to C ABI) 134 * r8 arg4 135 * r9 arg5 136 * (note: r12-r15, rbp, rbx are callee-preserved in C ABI) 137 * 138 * Only called from user space. 139 * 140 * When user can change pt_regs->foo always force IRET. That is because 141 * it deals with uncanonical addresses better. SYSRET has trouble 142 * with them due to bugs in both AMD and Intel CPUs. 143 */ 144 145 .pushsection .entry_trampoline, "ax" 146 147/* 148 * The code in here gets remapped into cpu_entry_area's trampoline. This means 149 * that the assembler and linker have the wrong idea as to where this code 150 * lives (and, in fact, it's mapped more than once, so it's not even at a 151 * fixed address). So we can't reference any symbols outside the entry 152 * trampoline and expect it to work. 153 * 154 * Instead, we carefully abuse %rip-relative addressing. 155 * _entry_trampoline(%rip) refers to the start of the remapped) entry 156 * trampoline. We can thus find cpu_entry_area with this macro: 157 */ 158 159#define CPU_ENTRY_AREA \ 160 _entry_trampoline - CPU_ENTRY_AREA_entry_trampoline(%rip) 161 162/* The top word of the SYSENTER stack is hot and is usable as scratch space. */ 163#define RSP_SCRATCH CPU_ENTRY_AREA_entry_stack + \ 164 SIZEOF_entry_stack - 8 + CPU_ENTRY_AREA 165 166ENTRY(entry_SYSCALL_64_trampoline) 167 UNWIND_HINT_EMPTY 168 swapgs 169 170 /* Stash the user RSP. */ 171 movq %rsp, RSP_SCRATCH 172 173 /* Note: using %rsp as a scratch reg. */ 174 SWITCH_TO_KERNEL_CR3 scratch_reg=%rsp 175 176 /* Load the top of the task stack into RSP */ 177 movq CPU_ENTRY_AREA_tss + TSS_sp1 + CPU_ENTRY_AREA, %rsp 178 179 /* Start building the simulated IRET frame. */ 180 pushq $__USER_DS /* pt_regs->ss */ 181 pushq RSP_SCRATCH /* pt_regs->sp */ 182 pushq %r11 /* pt_regs->flags */ 183 pushq $__USER_CS /* pt_regs->cs */ 184 pushq %rcx /* pt_regs->ip */ 185 186 /* 187 * x86 lacks a near absolute jump, and we can't jump to the real 188 * entry text with a relative jump. We could push the target 189 * address and then use retq, but this destroys the pipeline on 190 * many CPUs (wasting over 20 cycles on Sandy Bridge). Instead, 191 * spill RDI and restore it in a second-stage trampoline. 192 */ 193 pushq %rdi 194 movq $entry_SYSCALL_64_stage2, %rdi 195 JMP_NOSPEC %rdi 196END(entry_SYSCALL_64_trampoline) 197 198 .popsection 199 200ENTRY(entry_SYSCALL_64_stage2) 201 UNWIND_HINT_EMPTY 202 popq %rdi 203 jmp entry_SYSCALL_64_after_hwframe 204END(entry_SYSCALL_64_stage2) 205 206ENTRY(entry_SYSCALL_64) 207 UNWIND_HINT_EMPTY 208 /* 209 * Interrupts are off on entry. 210 * We do not frame this tiny irq-off block with TRACE_IRQS_OFF/ON, 211 * it is too small to ever cause noticeable irq latency. 212 */ 213 214 swapgs 215 /* 216 * This path is only taken when PAGE_TABLE_ISOLATION is disabled so it 217 * is not required to switch CR3. 218 */ 219 movq %rsp, PER_CPU_VAR(rsp_scratch) 220 movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp 221 222 /* Construct struct pt_regs on stack */ 223 pushq $__USER_DS /* pt_regs->ss */ 224 pushq PER_CPU_VAR(rsp_scratch) /* pt_regs->sp */ 225 pushq %r11 /* pt_regs->flags */ 226 pushq $__USER_CS /* pt_regs->cs */ 227 pushq %rcx /* pt_regs->ip */ 228GLOBAL(entry_SYSCALL_64_after_hwframe) 229 pushq %rax /* pt_regs->orig_ax */ 230 231 PUSH_AND_CLEAR_REGS rax=$-ENOSYS 232 233 TRACE_IRQS_OFF 234 235 /* IRQs are off. */ 236 movq %rsp, %rdi 237 call do_syscall_64 /* returns with IRQs disabled */ 238 239 TRACE_IRQS_IRETQ /* we're about to change IF */ 240 241 /* 242 * Try to use SYSRET instead of IRET if we're returning to 243 * a completely clean 64-bit userspace context. If we're not, 244 * go to the slow exit path. 245 */ 246 movq RCX(%rsp), %rcx 247 movq RIP(%rsp), %r11 248 249 cmpq %rcx, %r11 /* SYSRET requires RCX == RIP */ 250 jne swapgs_restore_regs_and_return_to_usermode 251 252 /* 253 * On Intel CPUs, SYSRET with non-canonical RCX/RIP will #GP 254 * in kernel space. This essentially lets the user take over 255 * the kernel, since userspace controls RSP. 256 * 257 * If width of "canonical tail" ever becomes variable, this will need 258 * to be updated to remain correct on both old and new CPUs. 259 * 260 * Change top bits to match most significant bit (47th or 56th bit 261 * depending on paging mode) in the address. 262 */ 263#ifdef CONFIG_X86_5LEVEL 264 ALTERNATIVE "shl $(64 - 48), %rcx; sar $(64 - 48), %rcx", \ 265 "shl $(64 - 57), %rcx; sar $(64 - 57), %rcx", X86_FEATURE_LA57 266#else 267 shl $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx 268 sar $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx 269#endif 270 271 /* If this changed %rcx, it was not canonical */ 272 cmpq %rcx, %r11 273 jne swapgs_restore_regs_and_return_to_usermode 274 275 cmpq $__USER_CS, CS(%rsp) /* CS must match SYSRET */ 276 jne swapgs_restore_regs_and_return_to_usermode 277 278 movq R11(%rsp), %r11 279 cmpq %r11, EFLAGS(%rsp) /* R11 == RFLAGS */ 280 jne swapgs_restore_regs_and_return_to_usermode 281 282 /* 283 * SYSCALL clears RF when it saves RFLAGS in R11 and SYSRET cannot 284 * restore RF properly. If the slowpath sets it for whatever reason, we 285 * need to restore it correctly. 286 * 287 * SYSRET can restore TF, but unlike IRET, restoring TF results in a 288 * trap from userspace immediately after SYSRET. This would cause an 289 * infinite loop whenever #DB happens with register state that satisfies 290 * the opportunistic SYSRET conditions. For example, single-stepping 291 * this user code: 292 * 293 * movq $stuck_here, %rcx 294 * pushfq 295 * popq %r11 296 * stuck_here: 297 * 298 * would never get past 'stuck_here'. 299 */ 300 testq $(X86_EFLAGS_RF|X86_EFLAGS_TF), %r11 301 jnz swapgs_restore_regs_and_return_to_usermode 302 303 /* nothing to check for RSP */ 304 305 cmpq $__USER_DS, SS(%rsp) /* SS must match SYSRET */ 306 jne swapgs_restore_regs_and_return_to_usermode 307 308 /* 309 * We win! This label is here just for ease of understanding 310 * perf profiles. Nothing jumps here. 311 */ 312syscall_return_via_sysret: 313 /* rcx and r11 are already restored (see code above) */ 314 UNWIND_HINT_EMPTY 315 POP_REGS pop_rdi=0 skip_r11rcx=1 316 317 /* 318 * Now all regs are restored except RSP and RDI. 319 * Save old stack pointer and switch to trampoline stack. 320 */ 321 movq %rsp, %rdi 322 movq PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %rsp 323 324 pushq RSP-RDI(%rdi) /* RSP */ 325 pushq (%rdi) /* RDI */ 326 327 /* 328 * We are on the trampoline stack. All regs except RDI are live. 329 * We can do future final exit work right here. 330 */ 331 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi 332 333 popq %rdi 334 popq %rsp 335 USERGS_SYSRET64 336END(entry_SYSCALL_64) 337 338/* 339 * %rdi: prev task 340 * %rsi: next task 341 */ 342ENTRY(__switch_to_asm) 343 UNWIND_HINT_FUNC 344 /* 345 * Save callee-saved registers 346 * This must match the order in inactive_task_frame 347 */ 348 pushq %rbp 349 pushq %rbx 350 pushq %r12 351 pushq %r13 352 pushq %r14 353 pushq %r15 354 355 /* switch stack */ 356 movq %rsp, TASK_threadsp(%rdi) 357 movq TASK_threadsp(%rsi), %rsp 358 359#ifdef CONFIG_CC_STACKPROTECTOR 360 movq TASK_stack_canary(%rsi), %rbx 361 movq %rbx, PER_CPU_VAR(irq_stack_union)+stack_canary_offset 362#endif 363 364#ifdef CONFIG_RETPOLINE 365 /* 366 * When switching from a shallower to a deeper call stack 367 * the RSB may either underflow or use entries populated 368 * with userspace addresses. On CPUs where those concerns 369 * exist, overwrite the RSB with entries which capture 370 * speculative execution to prevent attack. 371 */ 372 FILL_RETURN_BUFFER %r12, RSB_CLEAR_LOOPS, X86_FEATURE_RSB_CTXSW 373#endif 374 375 /* restore callee-saved registers */ 376 popq %r15 377 popq %r14 378 popq %r13 379 popq %r12 380 popq %rbx 381 popq %rbp 382 383 jmp __switch_to 384END(__switch_to_asm) 385 386/* 387 * A newly forked process directly context switches into this address. 388 * 389 * rax: prev task we switched from 390 * rbx: kernel thread func (NULL for user thread) 391 * r12: kernel thread arg 392 */ 393ENTRY(ret_from_fork) 394 UNWIND_HINT_EMPTY 395 movq %rax, %rdi 396 call schedule_tail /* rdi: 'prev' task parameter */ 397 398 testq %rbx, %rbx /* from kernel_thread? */ 399 jnz 1f /* kernel threads are uncommon */ 400 4012: 402 UNWIND_HINT_REGS 403 movq %rsp, %rdi 404 call syscall_return_slowpath /* returns with IRQs disabled */ 405 TRACE_IRQS_ON /* user mode is traced as IRQS on */ 406 jmp swapgs_restore_regs_and_return_to_usermode 407 4081: 409 /* kernel thread */ 410 movq %r12, %rdi 411 CALL_NOSPEC %rbx 412 /* 413 * A kernel thread is allowed to return here after successfully 414 * calling do_execve(). Exit to userspace to complete the execve() 415 * syscall. 416 */ 417 movq $0, RAX(%rsp) 418 jmp 2b 419END(ret_from_fork) 420 421/* 422 * Build the entry stubs with some assembler magic. 423 * We pack 1 stub into every 8-byte block. 424 */ 425 .align 8 426ENTRY(irq_entries_start) 427 vector=FIRST_EXTERNAL_VECTOR 428 .rept (FIRST_SYSTEM_VECTOR - FIRST_EXTERNAL_VECTOR) 429 UNWIND_HINT_IRET_REGS 430 pushq $(~vector+0x80) /* Note: always in signed byte range */ 431 jmp common_interrupt 432 .align 8 433 vector=vector+1 434 .endr 435END(irq_entries_start) 436 437.macro DEBUG_ENTRY_ASSERT_IRQS_OFF 438#ifdef CONFIG_DEBUG_ENTRY 439 pushq %rax 440 SAVE_FLAGS(CLBR_RAX) 441 testl $X86_EFLAGS_IF, %eax 442 jz .Lokay_\@ 443 ud2 444.Lokay_\@: 445 popq %rax 446#endif 447.endm 448 449/* 450 * Enters the IRQ stack if we're not already using it. NMI-safe. Clobbers 451 * flags and puts old RSP into old_rsp, and leaves all other GPRs alone. 452 * Requires kernel GSBASE. 453 * 454 * The invariant is that, if irq_count != -1, then the IRQ stack is in use. 455 */ 456.macro ENTER_IRQ_STACK regs=1 old_rsp save_ret=0 457 DEBUG_ENTRY_ASSERT_IRQS_OFF 458 459 .if \save_ret 460 /* 461 * If save_ret is set, the original stack contains one additional 462 * entry -- the return address. Therefore, move the address one 463 * entry below %rsp to \old_rsp. 464 */ 465 leaq 8(%rsp), \old_rsp 466 .else 467 movq %rsp, \old_rsp 468 .endif 469 470 .if \regs 471 UNWIND_HINT_REGS base=\old_rsp 472 .endif 473 474 incl PER_CPU_VAR(irq_count) 475 jnz .Lirq_stack_push_old_rsp_\@ 476 477 /* 478 * Right now, if we just incremented irq_count to zero, we've 479 * claimed the IRQ stack but we haven't switched to it yet. 480 * 481 * If anything is added that can interrupt us here without using IST, 482 * it must be *extremely* careful to limit its stack usage. This 483 * could include kprobes and a hypothetical future IST-less #DB 484 * handler. 485 * 486 * The OOPS unwinder relies on the word at the top of the IRQ 487 * stack linking back to the previous RSP for the entire time we're 488 * on the IRQ stack. For this to work reliably, we need to write 489 * it before we actually move ourselves to the IRQ stack. 490 */ 491 492 movq \old_rsp, PER_CPU_VAR(irq_stack_union + IRQ_STACK_SIZE - 8) 493 movq PER_CPU_VAR(irq_stack_ptr), %rsp 494 495#ifdef CONFIG_DEBUG_ENTRY 496 /* 497 * If the first movq above becomes wrong due to IRQ stack layout 498 * changes, the only way we'll notice is if we try to unwind right 499 * here. Assert that we set up the stack right to catch this type 500 * of bug quickly. 501 */ 502 cmpq -8(%rsp), \old_rsp 503 je .Lirq_stack_okay\@ 504 ud2 505 .Lirq_stack_okay\@: 506#endif 507 508.Lirq_stack_push_old_rsp_\@: 509 pushq \old_rsp 510 511 .if \regs 512 UNWIND_HINT_REGS indirect=1 513 .endif 514 515 .if \save_ret 516 /* 517 * Push the return address to the stack. This return address can 518 * be found at the "real" original RSP, which was offset by 8 at 519 * the beginning of this macro. 520 */ 521 pushq -8(\old_rsp) 522 .endif 523.endm 524 525/* 526 * Undoes ENTER_IRQ_STACK. 527 */ 528.macro LEAVE_IRQ_STACK regs=1 529 DEBUG_ENTRY_ASSERT_IRQS_OFF 530 /* We need to be off the IRQ stack before decrementing irq_count. */ 531 popq %rsp 532 533 .if \regs 534 UNWIND_HINT_REGS 535 .endif 536 537 /* 538 * As in ENTER_IRQ_STACK, irq_count == 0, we are still claiming 539 * the irq stack but we're not on it. 540 */ 541 542 decl PER_CPU_VAR(irq_count) 543.endm 544 545/* 546 * Interrupt entry helper function. 547 * 548 * Entry runs with interrupts off. Stack layout at entry: 549 * +----------------------------------------------------+ 550 * | regs->ss | 551 * | regs->rsp | 552 * | regs->eflags | 553 * | regs->cs | 554 * | regs->ip | 555 * +----------------------------------------------------+ 556 * | regs->orig_ax = ~(interrupt number) | 557 * +----------------------------------------------------+ 558 * | return address | 559 * +----------------------------------------------------+ 560 */ 561ENTRY(interrupt_entry) 562 UNWIND_HINT_FUNC 563 ASM_CLAC 564 cld 565 566 testb $3, CS-ORIG_RAX+8(%rsp) 567 jz 1f 568 SWAPGS 569 570 /* 571 * Switch to the thread stack. The IRET frame and orig_ax are 572 * on the stack, as well as the return address. RDI..R12 are 573 * not (yet) on the stack and space has not (yet) been 574 * allocated for them. 575 */ 576 pushq %rdi 577 578 /* Need to switch before accessing the thread stack. */ 579 SWITCH_TO_KERNEL_CR3 scratch_reg=%rdi 580 movq %rsp, %rdi 581 movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp 582 583 /* 584 * We have RDI, return address, and orig_ax on the stack on 585 * top of the IRET frame. That means offset=24 586 */ 587 UNWIND_HINT_IRET_REGS base=%rdi offset=24 588 589 pushq 7*8(%rdi) /* regs->ss */ 590 pushq 6*8(%rdi) /* regs->rsp */ 591 pushq 5*8(%rdi) /* regs->eflags */ 592 pushq 4*8(%rdi) /* regs->cs */ 593 pushq 3*8(%rdi) /* regs->ip */ 594 pushq 2*8(%rdi) /* regs->orig_ax */ 595 pushq 8(%rdi) /* return address */ 596 UNWIND_HINT_FUNC 597 598 movq (%rdi), %rdi 5991: 600 601 PUSH_AND_CLEAR_REGS save_ret=1 602 ENCODE_FRAME_POINTER 8 603 604 testb $3, CS+8(%rsp) 605 jz 1f 606 607 /* 608 * IRQ from user mode. 609 * 610 * We need to tell lockdep that IRQs are off. We can't do this until 611 * we fix gsbase, and we should do it before enter_from_user_mode 612 * (which can take locks). Since TRACE_IRQS_OFF is idempotent, 613 * the simplest way to handle it is to just call it twice if 614 * we enter from user mode. There's no reason to optimize this since 615 * TRACE_IRQS_OFF is a no-op if lockdep is off. 616 */ 617 TRACE_IRQS_OFF 618 619 CALL_enter_from_user_mode 620 6211: 622 ENTER_IRQ_STACK old_rsp=%rdi save_ret=1 623 /* We entered an interrupt context - irqs are off: */ 624 TRACE_IRQS_OFF 625 626 ret 627END(interrupt_entry) 628 629 630/* Interrupt entry/exit. */ 631 632 /* 633 * The interrupt stubs push (~vector+0x80) onto the stack and 634 * then jump to common_interrupt. 635 */ 636 .p2align CONFIG_X86_L1_CACHE_SHIFT 637common_interrupt: 638 addq $-0x80, (%rsp) /* Adjust vector to [-256, -1] range */ 639 call interrupt_entry 640 UNWIND_HINT_REGS indirect=1 641 call do_IRQ /* rdi points to pt_regs */ 642 /* 0(%rsp): old RSP */ 643ret_from_intr: 644 DISABLE_INTERRUPTS(CLBR_ANY) 645 TRACE_IRQS_OFF 646 647 LEAVE_IRQ_STACK 648 649 testb $3, CS(%rsp) 650 jz retint_kernel 651 652 /* Interrupt came from user space */ 653GLOBAL(retint_user) 654 mov %rsp,%rdi 655 call prepare_exit_to_usermode 656 TRACE_IRQS_IRETQ 657 658GLOBAL(swapgs_restore_regs_and_return_to_usermode) 659#ifdef CONFIG_DEBUG_ENTRY 660 /* Assert that pt_regs indicates user mode. */ 661 testb $3, CS(%rsp) 662 jnz 1f 663 ud2 6641: 665#endif 666 POP_REGS pop_rdi=0 667 668 /* 669 * The stack is now user RDI, orig_ax, RIP, CS, EFLAGS, RSP, SS. 670 * Save old stack pointer and switch to trampoline stack. 671 */ 672 movq %rsp, %rdi 673 movq PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %rsp 674 675 /* Copy the IRET frame to the trampoline stack. */ 676 pushq 6*8(%rdi) /* SS */ 677 pushq 5*8(%rdi) /* RSP */ 678 pushq 4*8(%rdi) /* EFLAGS */ 679 pushq 3*8(%rdi) /* CS */ 680 pushq 2*8(%rdi) /* RIP */ 681 682 /* Push user RDI on the trampoline stack. */ 683 pushq (%rdi) 684 685 /* 686 * We are on the trampoline stack. All regs except RDI are live. 687 * We can do future final exit work right here. 688 */ 689 690 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi 691 692 /* Restore RDI. */ 693 popq %rdi 694 SWAPGS 695 INTERRUPT_RETURN 696 697 698/* Returning to kernel space */ 699retint_kernel: 700#ifdef CONFIG_PREEMPT 701 /* Interrupts are off */ 702 /* Check if we need preemption */ 703 bt $9, EFLAGS(%rsp) /* were interrupts off? */ 704 jnc 1f 7050: cmpl $0, PER_CPU_VAR(__preempt_count) 706 jnz 1f 707 call preempt_schedule_irq 708 jmp 0b 7091: 710#endif 711 /* 712 * The iretq could re-enable interrupts: 713 */ 714 TRACE_IRQS_IRETQ 715 716GLOBAL(restore_regs_and_return_to_kernel) 717#ifdef CONFIG_DEBUG_ENTRY 718 /* Assert that pt_regs indicates kernel mode. */ 719 testb $3, CS(%rsp) 720 jz 1f 721 ud2 7221: 723#endif 724 POP_REGS 725 addq $8, %rsp /* skip regs->orig_ax */ 726 /* 727 * ARCH_HAS_MEMBARRIER_SYNC_CORE rely on IRET core serialization 728 * when returning from IPI handler. 729 */ 730 INTERRUPT_RETURN 731 732ENTRY(native_iret) 733 UNWIND_HINT_IRET_REGS 734 /* 735 * Are we returning to a stack segment from the LDT? Note: in 736 * 64-bit mode SS:RSP on the exception stack is always valid. 737 */ 738#ifdef CONFIG_X86_ESPFIX64 739 testb $4, (SS-RIP)(%rsp) 740 jnz native_irq_return_ldt 741#endif 742 743.global native_irq_return_iret 744native_irq_return_iret: 745 /* 746 * This may fault. Non-paranoid faults on return to userspace are 747 * handled by fixup_bad_iret. These include #SS, #GP, and #NP. 748 * Double-faults due to espfix64 are handled in do_double_fault. 749 * Other faults here are fatal. 750 */ 751 iretq 752 753#ifdef CONFIG_X86_ESPFIX64 754native_irq_return_ldt: 755 /* 756 * We are running with user GSBASE. All GPRs contain their user 757 * values. We have a percpu ESPFIX stack that is eight slots 758 * long (see ESPFIX_STACK_SIZE). espfix_waddr points to the bottom 759 * of the ESPFIX stack. 760 * 761 * We clobber RAX and RDI in this code. We stash RDI on the 762 * normal stack and RAX on the ESPFIX stack. 763 * 764 * The ESPFIX stack layout we set up looks like this: 765 * 766 * --- top of ESPFIX stack --- 767 * SS 768 * RSP 769 * RFLAGS 770 * CS 771 * RIP <-- RSP points here when we're done 772 * RAX <-- espfix_waddr points here 773 * --- bottom of ESPFIX stack --- 774 */ 775 776 pushq %rdi /* Stash user RDI */ 777 SWAPGS /* to kernel GS */ 778 SWITCH_TO_KERNEL_CR3 scratch_reg=%rdi /* to kernel CR3 */ 779 780 movq PER_CPU_VAR(espfix_waddr), %rdi 781 movq %rax, (0*8)(%rdi) /* user RAX */ 782 movq (1*8)(%rsp), %rax /* user RIP */ 783 movq %rax, (1*8)(%rdi) 784 movq (2*8)(%rsp), %rax /* user CS */ 785 movq %rax, (2*8)(%rdi) 786 movq (3*8)(%rsp), %rax /* user RFLAGS */ 787 movq %rax, (3*8)(%rdi) 788 movq (5*8)(%rsp), %rax /* user SS */ 789 movq %rax, (5*8)(%rdi) 790 movq (4*8)(%rsp), %rax /* user RSP */ 791 movq %rax, (4*8)(%rdi) 792 /* Now RAX == RSP. */ 793 794 andl $0xffff0000, %eax /* RAX = (RSP & 0xffff0000) */ 795 796 /* 797 * espfix_stack[31:16] == 0. The page tables are set up such that 798 * (espfix_stack | (X & 0xffff0000)) points to a read-only alias of 799 * espfix_waddr for any X. That is, there are 65536 RO aliases of 800 * the same page. Set up RSP so that RSP[31:16] contains the 801 * respective 16 bits of the /userspace/ RSP and RSP nonetheless 802 * still points to an RO alias of the ESPFIX stack. 803 */ 804 orq PER_CPU_VAR(espfix_stack), %rax 805 806 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi 807 SWAPGS /* to user GS */ 808 popq %rdi /* Restore user RDI */ 809 810 movq %rax, %rsp 811 UNWIND_HINT_IRET_REGS offset=8 812 813 /* 814 * At this point, we cannot write to the stack any more, but we can 815 * still read. 816 */ 817 popq %rax /* Restore user RAX */ 818 819 /* 820 * RSP now points to an ordinary IRET frame, except that the page 821 * is read-only and RSP[31:16] are preloaded with the userspace 822 * values. We can now IRET back to userspace. 823 */ 824 jmp native_irq_return_iret 825#endif 826END(common_interrupt) 827 828/* 829 * APIC interrupts. 830 */ 831.macro apicinterrupt3 num sym do_sym 832ENTRY(\sym) 833 UNWIND_HINT_IRET_REGS 834 pushq $~(\num) 835.Lcommon_\sym: 836 call interrupt_entry 837 UNWIND_HINT_REGS indirect=1 838 call \do_sym /* rdi points to pt_regs */ 839 jmp ret_from_intr 840END(\sym) 841.endm 842 843/* Make sure APIC interrupt handlers end up in the irqentry section: */ 844#define PUSH_SECTION_IRQENTRY .pushsection .irqentry.text, "ax" 845#define POP_SECTION_IRQENTRY .popsection 846 847.macro apicinterrupt num sym do_sym 848PUSH_SECTION_IRQENTRY 849apicinterrupt3 \num \sym \do_sym 850POP_SECTION_IRQENTRY 851.endm 852 853#ifdef CONFIG_SMP 854apicinterrupt3 IRQ_MOVE_CLEANUP_VECTOR irq_move_cleanup_interrupt smp_irq_move_cleanup_interrupt 855apicinterrupt3 REBOOT_VECTOR reboot_interrupt smp_reboot_interrupt 856#endif 857 858#ifdef CONFIG_X86_UV 859apicinterrupt3 UV_BAU_MESSAGE uv_bau_message_intr1 uv_bau_message_interrupt 860#endif 861 862apicinterrupt LOCAL_TIMER_VECTOR apic_timer_interrupt smp_apic_timer_interrupt 863apicinterrupt X86_PLATFORM_IPI_VECTOR x86_platform_ipi smp_x86_platform_ipi 864 865#ifdef CONFIG_HAVE_KVM 866apicinterrupt3 POSTED_INTR_VECTOR kvm_posted_intr_ipi smp_kvm_posted_intr_ipi 867apicinterrupt3 POSTED_INTR_WAKEUP_VECTOR kvm_posted_intr_wakeup_ipi smp_kvm_posted_intr_wakeup_ipi 868apicinterrupt3 POSTED_INTR_NESTED_VECTOR kvm_posted_intr_nested_ipi smp_kvm_posted_intr_nested_ipi 869#endif 870 871#ifdef CONFIG_X86_MCE_THRESHOLD 872apicinterrupt THRESHOLD_APIC_VECTOR threshold_interrupt smp_threshold_interrupt 873#endif 874 875#ifdef CONFIG_X86_MCE_AMD 876apicinterrupt DEFERRED_ERROR_VECTOR deferred_error_interrupt smp_deferred_error_interrupt 877#endif 878 879#ifdef CONFIG_X86_THERMAL_VECTOR 880apicinterrupt THERMAL_APIC_VECTOR thermal_interrupt smp_thermal_interrupt 881#endif 882 883#ifdef CONFIG_SMP 884apicinterrupt CALL_FUNCTION_SINGLE_VECTOR call_function_single_interrupt smp_call_function_single_interrupt 885apicinterrupt CALL_FUNCTION_VECTOR call_function_interrupt smp_call_function_interrupt 886apicinterrupt RESCHEDULE_VECTOR reschedule_interrupt smp_reschedule_interrupt 887#endif 888 889apicinterrupt ERROR_APIC_VECTOR error_interrupt smp_error_interrupt 890apicinterrupt SPURIOUS_APIC_VECTOR spurious_interrupt smp_spurious_interrupt 891 892#ifdef CONFIG_IRQ_WORK 893apicinterrupt IRQ_WORK_VECTOR irq_work_interrupt smp_irq_work_interrupt 894#endif 895 896/* 897 * Exception entry points. 898 */ 899#define CPU_TSS_IST(x) PER_CPU_VAR(cpu_tss_rw) + (TSS_ist + ((x) - 1) * 8) 900 901.macro idtentry sym do_sym has_error_code:req paranoid=0 shift_ist=-1 902ENTRY(\sym) 903 UNWIND_HINT_IRET_REGS offset=\has_error_code*8 904 905 /* Sanity check */ 906 .if \shift_ist != -1 && \paranoid == 0 907 .error "using shift_ist requires paranoid=1" 908 .endif 909 910 ASM_CLAC 911 912 .if \has_error_code == 0 913 pushq $-1 /* ORIG_RAX: no syscall to restart */ 914 .endif 915 916 .if \paranoid < 2 917 testb $3, CS-ORIG_RAX(%rsp) /* If coming from userspace, switch stacks */ 918 jnz .Lfrom_usermode_switch_stack_\@ 919 .endif 920 921 .if \paranoid 922 call paranoid_entry 923 .else 924 call error_entry 925 .endif 926 UNWIND_HINT_REGS 927 /* returned flag: ebx=0: need swapgs on exit, ebx=1: don't need it */ 928 929 .if \paranoid 930 .if \shift_ist != -1 931 TRACE_IRQS_OFF_DEBUG /* reload IDT in case of recursion */ 932 .else 933 TRACE_IRQS_OFF 934 .endif 935 .endif 936 937 movq %rsp, %rdi /* pt_regs pointer */ 938 939 .if \has_error_code 940 movq ORIG_RAX(%rsp), %rsi /* get error code */ 941 movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */ 942 .else 943 xorl %esi, %esi /* no error code */ 944 .endif 945 946 .if \shift_ist != -1 947 subq $EXCEPTION_STKSZ, CPU_TSS_IST(\shift_ist) 948 .endif 949 950 call \do_sym 951 952 .if \shift_ist != -1 953 addq $EXCEPTION_STKSZ, CPU_TSS_IST(\shift_ist) 954 .endif 955 956 /* these procedures expect "no swapgs" flag in ebx */ 957 .if \paranoid 958 jmp paranoid_exit 959 .else 960 jmp error_exit 961 .endif 962 963 .if \paranoid < 2 964 /* 965 * Entry from userspace. Switch stacks and treat it 966 * as a normal entry. This means that paranoid handlers 967 * run in real process context if user_mode(regs). 968 */ 969.Lfrom_usermode_switch_stack_\@: 970 call error_entry 971 972 movq %rsp, %rdi /* pt_regs pointer */ 973 974 .if \has_error_code 975 movq ORIG_RAX(%rsp), %rsi /* get error code */ 976 movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */ 977 .else 978 xorl %esi, %esi /* no error code */ 979 .endif 980 981 call \do_sym 982 983 jmp error_exit /* %ebx: no swapgs flag */ 984 .endif 985END(\sym) 986.endm 987 988idtentry divide_error do_divide_error has_error_code=0 989idtentry overflow do_overflow has_error_code=0 990idtentry bounds do_bounds has_error_code=0 991idtentry invalid_op do_invalid_op has_error_code=0 992idtentry device_not_available do_device_not_available has_error_code=0 993idtentry double_fault do_double_fault has_error_code=1 paranoid=2 994idtentry coprocessor_segment_overrun do_coprocessor_segment_overrun has_error_code=0 995idtentry invalid_TSS do_invalid_TSS has_error_code=1 996idtentry segment_not_present do_segment_not_present has_error_code=1 997idtentry spurious_interrupt_bug do_spurious_interrupt_bug has_error_code=0 998idtentry coprocessor_error do_coprocessor_error has_error_code=0 999idtentry alignment_check do_alignment_check has_error_code=1 1000idtentry simd_coprocessor_error do_simd_coprocessor_error has_error_code=0 1001 1002 1003 /* 1004 * Reload gs selector with exception handling 1005 * edi: new selector 1006 */ 1007ENTRY(native_load_gs_index) 1008 FRAME_BEGIN 1009 pushfq 1010 DISABLE_INTERRUPTS(CLBR_ANY & ~CLBR_RDI) 1011 TRACE_IRQS_OFF 1012 SWAPGS 1013.Lgs_change: 1014 movl %edi, %gs 10152: ALTERNATIVE "", "mfence", X86_BUG_SWAPGS_FENCE 1016 SWAPGS 1017 TRACE_IRQS_FLAGS (%rsp) 1018 popfq 1019 FRAME_END 1020 ret 1021ENDPROC(native_load_gs_index) 1022EXPORT_SYMBOL(native_load_gs_index) 1023 1024 _ASM_EXTABLE(.Lgs_change, bad_gs) 1025 .section .fixup, "ax" 1026 /* running with kernelgs */ 1027bad_gs: 1028 SWAPGS /* switch back to user gs */ 1029.macro ZAP_GS 1030 /* This can't be a string because the preprocessor needs to see it. */ 1031 movl $__USER_DS, %eax 1032 movl %eax, %gs 1033.endm 1034 ALTERNATIVE "", "ZAP_GS", X86_BUG_NULL_SEG 1035 xorl %eax, %eax 1036 movl %eax, %gs 1037 jmp 2b 1038 .previous 1039 1040/* Call softirq on interrupt stack. Interrupts are off. */ 1041ENTRY(do_softirq_own_stack) 1042 pushq %rbp 1043 mov %rsp, %rbp 1044 ENTER_IRQ_STACK regs=0 old_rsp=%r11 1045 call __do_softirq 1046 LEAVE_IRQ_STACK regs=0 1047 leaveq 1048 ret 1049ENDPROC(do_softirq_own_stack) 1050 1051#ifdef CONFIG_XEN 1052idtentry hypervisor_callback xen_do_hypervisor_callback has_error_code=0 1053 1054/* 1055 * A note on the "critical region" in our callback handler. 1056 * We want to avoid stacking callback handlers due to events occurring 1057 * during handling of the last event. To do this, we keep events disabled 1058 * until we've done all processing. HOWEVER, we must enable events before 1059 * popping the stack frame (can't be done atomically) and so it would still 1060 * be possible to get enough handler activations to overflow the stack. 1061 * Although unlikely, bugs of that kind are hard to track down, so we'd 1062 * like to avoid the possibility. 1063 * So, on entry to the handler we detect whether we interrupted an 1064 * existing activation in its critical region -- if so, we pop the current 1065 * activation and restart the handler using the previous one. 1066 */ 1067ENTRY(xen_do_hypervisor_callback) /* do_hypervisor_callback(struct *pt_regs) */ 1068 1069/* 1070 * Since we don't modify %rdi, evtchn_do_upall(struct *pt_regs) will 1071 * see the correct pointer to the pt_regs 1072 */ 1073 UNWIND_HINT_FUNC 1074 movq %rdi, %rsp /* we don't return, adjust the stack frame */ 1075 UNWIND_HINT_REGS 1076 1077 ENTER_IRQ_STACK old_rsp=%r10 1078 call xen_evtchn_do_upcall 1079 LEAVE_IRQ_STACK 1080 1081#ifndef CONFIG_PREEMPT 1082 call xen_maybe_preempt_hcall 1083#endif 1084 jmp error_exit 1085END(xen_do_hypervisor_callback) 1086 1087/* 1088 * Hypervisor uses this for application faults while it executes. 1089 * We get here for two reasons: 1090 * 1. Fault while reloading DS, ES, FS or GS 1091 * 2. Fault while executing IRET 1092 * Category 1 we do not need to fix up as Xen has already reloaded all segment 1093 * registers that could be reloaded and zeroed the others. 1094 * Category 2 we fix up by killing the current process. We cannot use the 1095 * normal Linux return path in this case because if we use the IRET hypercall 1096 * to pop the stack frame we end up in an infinite loop of failsafe callbacks. 1097 * We distinguish between categories by comparing each saved segment register 1098 * with its current contents: any discrepancy means we in category 1. 1099 */ 1100ENTRY(xen_failsafe_callback) 1101 UNWIND_HINT_EMPTY 1102 movl %ds, %ecx 1103 cmpw %cx, 0x10(%rsp) 1104 jne 1f 1105 movl %es, %ecx 1106 cmpw %cx, 0x18(%rsp) 1107 jne 1f 1108 movl %fs, %ecx 1109 cmpw %cx, 0x20(%rsp) 1110 jne 1f 1111 movl %gs, %ecx 1112 cmpw %cx, 0x28(%rsp) 1113 jne 1f 1114 /* All segments match their saved values => Category 2 (Bad IRET). */ 1115 movq (%rsp), %rcx 1116 movq 8(%rsp), %r11 1117 addq $0x30, %rsp 1118 pushq $0 /* RIP */ 1119 UNWIND_HINT_IRET_REGS offset=8 1120 jmp general_protection 11211: /* Segment mismatch => Category 1 (Bad segment). Retry the IRET. */ 1122 movq (%rsp), %rcx 1123 movq 8(%rsp), %r11 1124 addq $0x30, %rsp 1125 UNWIND_HINT_IRET_REGS 1126 pushq $-1 /* orig_ax = -1 => not a system call */ 1127 PUSH_AND_CLEAR_REGS 1128 ENCODE_FRAME_POINTER 1129 jmp error_exit 1130END(xen_failsafe_callback) 1131 1132apicinterrupt3 HYPERVISOR_CALLBACK_VECTOR \ 1133 xen_hvm_callback_vector xen_evtchn_do_upcall 1134 1135#endif /* CONFIG_XEN */ 1136 1137#if IS_ENABLED(CONFIG_HYPERV) 1138apicinterrupt3 HYPERVISOR_CALLBACK_VECTOR \ 1139 hyperv_callback_vector hyperv_vector_handler 1140 1141apicinterrupt3 HYPERV_REENLIGHTENMENT_VECTOR \ 1142 hyperv_reenlightenment_vector hyperv_reenlightenment_intr 1143 1144apicinterrupt3 HYPERV_STIMER0_VECTOR \ 1145 hv_stimer0_callback_vector hv_stimer0_vector_handler 1146#endif /* CONFIG_HYPERV */ 1147 1148idtentry debug do_debug has_error_code=0 paranoid=1 shift_ist=DEBUG_STACK 1149idtentry int3 do_int3 has_error_code=0 1150idtentry stack_segment do_stack_segment has_error_code=1 1151 1152#ifdef CONFIG_XEN 1153idtentry xennmi do_nmi has_error_code=0 1154idtentry xendebug do_debug has_error_code=0 1155idtentry xenint3 do_int3 has_error_code=0 1156#endif 1157 1158idtentry general_protection do_general_protection has_error_code=1 1159idtentry page_fault do_page_fault has_error_code=1 1160 1161#ifdef CONFIG_KVM_GUEST 1162idtentry async_page_fault do_async_page_fault has_error_code=1 1163#endif 1164 1165#ifdef CONFIG_X86_MCE 1166idtentry machine_check do_mce has_error_code=0 paranoid=1 1167#endif 1168 1169/* 1170 * Save all registers in pt_regs, and switch gs if needed. 1171 * Use slow, but surefire "are we in kernel?" check. 1172 * Return: ebx=0: need swapgs on exit, ebx=1: otherwise 1173 */ 1174ENTRY(paranoid_entry) 1175 UNWIND_HINT_FUNC 1176 cld 1177 PUSH_AND_CLEAR_REGS save_ret=1 1178 ENCODE_FRAME_POINTER 8 1179 movl $1, %ebx 1180 movl $MSR_GS_BASE, %ecx 1181 rdmsr 1182 testl %edx, %edx 1183 js 1f /* negative -> in kernel */ 1184 SWAPGS 1185 xorl %ebx, %ebx 1186 11871: 1188 SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg=%rax save_reg=%r14 1189 1190 ret 1191END(paranoid_entry) 1192 1193/* 1194 * "Paranoid" exit path from exception stack. This is invoked 1195 * only on return from non-NMI IST interrupts that came 1196 * from kernel space. 1197 * 1198 * We may be returning to very strange contexts (e.g. very early 1199 * in syscall entry), so checking for preemption here would 1200 * be complicated. Fortunately, we there's no good reason 1201 * to try to handle preemption here. 1202 * 1203 * On entry, ebx is "no swapgs" flag (1: don't need swapgs, 0: need it) 1204 */ 1205ENTRY(paranoid_exit) 1206 UNWIND_HINT_REGS 1207 DISABLE_INTERRUPTS(CLBR_ANY) 1208 TRACE_IRQS_OFF_DEBUG 1209 testl %ebx, %ebx /* swapgs needed? */ 1210 jnz .Lparanoid_exit_no_swapgs 1211 TRACE_IRQS_IRETQ 1212 RESTORE_CR3 scratch_reg=%rbx save_reg=%r14 1213 SWAPGS_UNSAFE_STACK 1214 jmp .Lparanoid_exit_restore 1215.Lparanoid_exit_no_swapgs: 1216 TRACE_IRQS_IRETQ_DEBUG 1217 RESTORE_CR3 scratch_reg=%rbx save_reg=%r14 1218.Lparanoid_exit_restore: 1219 jmp restore_regs_and_return_to_kernel 1220END(paranoid_exit) 1221 1222/* 1223 * Save all registers in pt_regs, and switch GS if needed. 1224 * Return: EBX=0: came from user mode; EBX=1: otherwise 1225 */ 1226ENTRY(error_entry) 1227 UNWIND_HINT_FUNC 1228 cld 1229 PUSH_AND_CLEAR_REGS save_ret=1 1230 ENCODE_FRAME_POINTER 8 1231 testb $3, CS+8(%rsp) 1232 jz .Lerror_kernelspace 1233 1234 /* 1235 * We entered from user mode or we're pretending to have entered 1236 * from user mode due to an IRET fault. 1237 */ 1238 SWAPGS 1239 /* We have user CR3. Change to kernel CR3. */ 1240 SWITCH_TO_KERNEL_CR3 scratch_reg=%rax 1241 1242.Lerror_entry_from_usermode_after_swapgs: 1243 /* Put us onto the real thread stack. */ 1244 popq %r12 /* save return addr in %12 */ 1245 movq %rsp, %rdi /* arg0 = pt_regs pointer */ 1246 call sync_regs 1247 movq %rax, %rsp /* switch stack */ 1248 ENCODE_FRAME_POINTER 1249 pushq %r12 1250 1251 /* 1252 * We need to tell lockdep that IRQs are off. We can't do this until 1253 * we fix gsbase, and we should do it before enter_from_user_mode 1254 * (which can take locks). 1255 */ 1256 TRACE_IRQS_OFF 1257 CALL_enter_from_user_mode 1258 ret 1259 1260.Lerror_entry_done: 1261 TRACE_IRQS_OFF 1262 ret 1263 1264 /* 1265 * There are two places in the kernel that can potentially fault with 1266 * usergs. Handle them here. B stepping K8s sometimes report a 1267 * truncated RIP for IRET exceptions returning to compat mode. Check 1268 * for these here too. 1269 */ 1270.Lerror_kernelspace: 1271 incl %ebx 1272 leaq native_irq_return_iret(%rip), %rcx 1273 cmpq %rcx, RIP+8(%rsp) 1274 je .Lerror_bad_iret 1275 movl %ecx, %eax /* zero extend */ 1276 cmpq %rax, RIP+8(%rsp) 1277 je .Lbstep_iret 1278 cmpq $.Lgs_change, RIP+8(%rsp) 1279 jne .Lerror_entry_done 1280 1281 /* 1282 * hack: .Lgs_change can fail with user gsbase. If this happens, fix up 1283 * gsbase and proceed. We'll fix up the exception and land in 1284 * .Lgs_change's error handler with kernel gsbase. 1285 */ 1286 SWAPGS 1287 SWITCH_TO_KERNEL_CR3 scratch_reg=%rax 1288 jmp .Lerror_entry_done 1289 1290.Lbstep_iret: 1291 /* Fix truncated RIP */ 1292 movq %rcx, RIP+8(%rsp) 1293 /* fall through */ 1294 1295.Lerror_bad_iret: 1296 /* 1297 * We came from an IRET to user mode, so we have user 1298 * gsbase and CR3. Switch to kernel gsbase and CR3: 1299 */ 1300 SWAPGS 1301 SWITCH_TO_KERNEL_CR3 scratch_reg=%rax 1302 1303 /* 1304 * Pretend that the exception came from user mode: set up pt_regs 1305 * as if we faulted immediately after IRET and clear EBX so that 1306 * error_exit knows that we will be returning to user mode. 1307 */ 1308 mov %rsp, %rdi 1309 call fixup_bad_iret 1310 mov %rax, %rsp 1311 decl %ebx 1312 jmp .Lerror_entry_from_usermode_after_swapgs 1313END(error_entry) 1314 1315 1316/* 1317 * On entry, EBX is a "return to kernel mode" flag: 1318 * 1: already in kernel mode, don't need SWAPGS 1319 * 0: user gsbase is loaded, we need SWAPGS and standard preparation for return to usermode 1320 */ 1321ENTRY(error_exit) 1322 UNWIND_HINT_REGS 1323 DISABLE_INTERRUPTS(CLBR_ANY) 1324 TRACE_IRQS_OFF 1325 testl %ebx, %ebx 1326 jnz retint_kernel 1327 jmp retint_user 1328END(error_exit) 1329 1330/* 1331 * Runs on exception stack. Xen PV does not go through this path at all, 1332 * so we can use real assembly here. 1333 * 1334 * Registers: 1335 * %r14: Used to save/restore the CR3 of the interrupted context 1336 * when PAGE_TABLE_ISOLATION is in use. Do not clobber. 1337 */ 1338ENTRY(nmi) 1339 UNWIND_HINT_IRET_REGS 1340 1341 /* 1342 * We allow breakpoints in NMIs. If a breakpoint occurs, then 1343 * the iretq it performs will take us out of NMI context. 1344 * This means that we can have nested NMIs where the next 1345 * NMI is using the top of the stack of the previous NMI. We 1346 * can't let it execute because the nested NMI will corrupt the 1347 * stack of the previous NMI. NMI handlers are not re-entrant 1348 * anyway. 1349 * 1350 * To handle this case we do the following: 1351 * Check the a special location on the stack that contains 1352 * a variable that is set when NMIs are executing. 1353 * The interrupted task's stack is also checked to see if it 1354 * is an NMI stack. 1355 * If the variable is not set and the stack is not the NMI 1356 * stack then: 1357 * o Set the special variable on the stack 1358 * o Copy the interrupt frame into an "outermost" location on the 1359 * stack 1360 * o Copy the interrupt frame into an "iret" location on the stack 1361 * o Continue processing the NMI 1362 * If the variable is set or the previous stack is the NMI stack: 1363 * o Modify the "iret" location to jump to the repeat_nmi 1364 * o return back to the first NMI 1365 * 1366 * Now on exit of the first NMI, we first clear the stack variable 1367 * The NMI stack will tell any nested NMIs at that point that it is 1368 * nested. Then we pop the stack normally with iret, and if there was 1369 * a nested NMI that updated the copy interrupt stack frame, a 1370 * jump will be made to the repeat_nmi code that will handle the second 1371 * NMI. 1372 * 1373 * However, espfix prevents us from directly returning to userspace 1374 * with a single IRET instruction. Similarly, IRET to user mode 1375 * can fault. We therefore handle NMIs from user space like 1376 * other IST entries. 1377 */ 1378 1379 ASM_CLAC 1380 1381 /* Use %rdx as our temp variable throughout */ 1382 pushq %rdx 1383 1384 testb $3, CS-RIP+8(%rsp) 1385 jz .Lnmi_from_kernel 1386 1387 /* 1388 * NMI from user mode. We need to run on the thread stack, but we 1389 * can't go through the normal entry paths: NMIs are masked, and 1390 * we don't want to enable interrupts, because then we'll end 1391 * up in an awkward situation in which IRQs are on but NMIs 1392 * are off. 1393 * 1394 * We also must not push anything to the stack before switching 1395 * stacks lest we corrupt the "NMI executing" variable. 1396 */ 1397 1398 swapgs 1399 cld 1400 SWITCH_TO_KERNEL_CR3 scratch_reg=%rdx 1401 movq %rsp, %rdx 1402 movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp 1403 UNWIND_HINT_IRET_REGS base=%rdx offset=8 1404 pushq 5*8(%rdx) /* pt_regs->ss */ 1405 pushq 4*8(%rdx) /* pt_regs->rsp */ 1406 pushq 3*8(%rdx) /* pt_regs->flags */ 1407 pushq 2*8(%rdx) /* pt_regs->cs */ 1408 pushq 1*8(%rdx) /* pt_regs->rip */ 1409 UNWIND_HINT_IRET_REGS 1410 pushq $-1 /* pt_regs->orig_ax */ 1411 PUSH_AND_CLEAR_REGS rdx=(%rdx) 1412 ENCODE_FRAME_POINTER 1413 1414 /* 1415 * At this point we no longer need to worry about stack damage 1416 * due to nesting -- we're on the normal thread stack and we're 1417 * done with the NMI stack. 1418 */ 1419 1420 movq %rsp, %rdi 1421 movq $-1, %rsi 1422 call do_nmi 1423 1424 /* 1425 * Return back to user mode. We must *not* do the normal exit 1426 * work, because we don't want to enable interrupts. 1427 */ 1428 jmp swapgs_restore_regs_and_return_to_usermode 1429 1430.Lnmi_from_kernel: 1431 /* 1432 * Here's what our stack frame will look like: 1433 * +---------------------------------------------------------+ 1434 * | original SS | 1435 * | original Return RSP | 1436 * | original RFLAGS | 1437 * | original CS | 1438 * | original RIP | 1439 * +---------------------------------------------------------+ 1440 * | temp storage for rdx | 1441 * +---------------------------------------------------------+ 1442 * | "NMI executing" variable | 1443 * +---------------------------------------------------------+ 1444 * | iret SS } Copied from "outermost" frame | 1445 * | iret Return RSP } on each loop iteration; overwritten | 1446 * | iret RFLAGS } by a nested NMI to force another | 1447 * | iret CS } iteration if needed. | 1448 * | iret RIP } | 1449 * +---------------------------------------------------------+ 1450 * | outermost SS } initialized in first_nmi; | 1451 * | outermost Return RSP } will not be changed before | 1452 * | outermost RFLAGS } NMI processing is done. | 1453 * | outermost CS } Copied to "iret" frame on each | 1454 * | outermost RIP } iteration. | 1455 * +---------------------------------------------------------+ 1456 * | pt_regs | 1457 * +---------------------------------------------------------+ 1458 * 1459 * The "original" frame is used by hardware. Before re-enabling 1460 * NMIs, we need to be done with it, and we need to leave enough 1461 * space for the asm code here. 1462 * 1463 * We return by executing IRET while RSP points to the "iret" frame. 1464 * That will either return for real or it will loop back into NMI 1465 * processing. 1466 * 1467 * The "outermost" frame is copied to the "iret" frame on each 1468 * iteration of the loop, so each iteration starts with the "iret" 1469 * frame pointing to the final return target. 1470 */ 1471 1472 /* 1473 * Determine whether we're a nested NMI. 1474 * 1475 * If we interrupted kernel code between repeat_nmi and 1476 * end_repeat_nmi, then we are a nested NMI. We must not 1477 * modify the "iret" frame because it's being written by 1478 * the outer NMI. That's okay; the outer NMI handler is 1479 * about to about to call do_nmi anyway, so we can just 1480 * resume the outer NMI. 1481 */ 1482 1483 movq $repeat_nmi, %rdx 1484 cmpq 8(%rsp), %rdx 1485 ja 1f 1486 movq $end_repeat_nmi, %rdx 1487 cmpq 8(%rsp), %rdx 1488 ja nested_nmi_out 14891: 1490 1491 /* 1492 * Now check "NMI executing". If it's set, then we're nested. 1493 * This will not detect if we interrupted an outer NMI just 1494 * before IRET. 1495 */ 1496 cmpl $1, -8(%rsp) 1497 je nested_nmi 1498 1499 /* 1500 * Now test if the previous stack was an NMI stack. This covers 1501 * the case where we interrupt an outer NMI after it clears 1502 * "NMI executing" but before IRET. We need to be careful, though: 1503 * there is one case in which RSP could point to the NMI stack 1504 * despite there being no NMI active: naughty userspace controls 1505 * RSP at the very beginning of the SYSCALL targets. We can 1506 * pull a fast one on naughty userspace, though: we program 1507 * SYSCALL to mask DF, so userspace cannot cause DF to be set 1508 * if it controls the kernel's RSP. We set DF before we clear 1509 * "NMI executing". 1510 */ 1511 lea 6*8(%rsp), %rdx 1512 /* Compare the NMI stack (rdx) with the stack we came from (4*8(%rsp)) */ 1513 cmpq %rdx, 4*8(%rsp) 1514 /* If the stack pointer is above the NMI stack, this is a normal NMI */ 1515 ja first_nmi 1516 1517 subq $EXCEPTION_STKSZ, %rdx 1518 cmpq %rdx, 4*8(%rsp) 1519 /* If it is below the NMI stack, it is a normal NMI */ 1520 jb first_nmi 1521 1522 /* Ah, it is within the NMI stack. */ 1523 1524 testb $(X86_EFLAGS_DF >> 8), (3*8 + 1)(%rsp) 1525 jz first_nmi /* RSP was user controlled. */ 1526 1527 /* This is a nested NMI. */ 1528 1529nested_nmi: 1530 /* 1531 * Modify the "iret" frame to point to repeat_nmi, forcing another 1532 * iteration of NMI handling. 1533 */ 1534 subq $8, %rsp 1535 leaq -10*8(%rsp), %rdx 1536 pushq $__KERNEL_DS 1537 pushq %rdx 1538 pushfq 1539 pushq $__KERNEL_CS 1540 pushq $repeat_nmi 1541 1542 /* Put stack back */ 1543 addq $(6*8), %rsp 1544 1545nested_nmi_out: 1546 popq %rdx 1547 1548 /* We are returning to kernel mode, so this cannot result in a fault. */ 1549 iretq 1550 1551first_nmi: 1552 /* Restore rdx. */ 1553 movq (%rsp), %rdx 1554 1555 /* Make room for "NMI executing". */ 1556 pushq $0 1557 1558 /* Leave room for the "iret" frame */ 1559 subq $(5*8), %rsp 1560 1561 /* Copy the "original" frame to the "outermost" frame */ 1562 .rept 5 1563 pushq 11*8(%rsp) 1564 .endr 1565 UNWIND_HINT_IRET_REGS 1566 1567 /* Everything up to here is safe from nested NMIs */ 1568 1569#ifdef CONFIG_DEBUG_ENTRY 1570 /* 1571 * For ease of testing, unmask NMIs right away. Disabled by 1572 * default because IRET is very expensive. 1573 */ 1574 pushq $0 /* SS */ 1575 pushq %rsp /* RSP (minus 8 because of the previous push) */ 1576 addq $8, (%rsp) /* Fix up RSP */ 1577 pushfq /* RFLAGS */ 1578 pushq $__KERNEL_CS /* CS */ 1579 pushq $1f /* RIP */ 1580 iretq /* continues at repeat_nmi below */ 1581 UNWIND_HINT_IRET_REGS 15821: 1583#endif 1584 1585repeat_nmi: 1586 /* 1587 * If there was a nested NMI, the first NMI's iret will return 1588 * here. But NMIs are still enabled and we can take another 1589 * nested NMI. The nested NMI checks the interrupted RIP to see 1590 * if it is between repeat_nmi and end_repeat_nmi, and if so 1591 * it will just return, as we are about to repeat an NMI anyway. 1592 * This makes it safe to copy to the stack frame that a nested 1593 * NMI will update. 1594 * 1595 * RSP is pointing to "outermost RIP". gsbase is unknown, but, if 1596 * we're repeating an NMI, gsbase has the same value that it had on 1597 * the first iteration. paranoid_entry will load the kernel 1598 * gsbase if needed before we call do_nmi. "NMI executing" 1599 * is zero. 1600 */ 1601 movq $1, 10*8(%rsp) /* Set "NMI executing". */ 1602 1603 /* 1604 * Copy the "outermost" frame to the "iret" frame. NMIs that nest 1605 * here must not modify the "iret" frame while we're writing to 1606 * it or it will end up containing garbage. 1607 */ 1608 addq $(10*8), %rsp 1609 .rept 5 1610 pushq -6*8(%rsp) 1611 .endr 1612 subq $(5*8), %rsp 1613end_repeat_nmi: 1614 1615 /* 1616 * Everything below this point can be preempted by a nested NMI. 1617 * If this happens, then the inner NMI will change the "iret" 1618 * frame to point back to repeat_nmi. 1619 */ 1620 pushq $-1 /* ORIG_RAX: no syscall to restart */ 1621 1622 /* 1623 * Use paranoid_entry to handle SWAPGS, but no need to use paranoid_exit 1624 * as we should not be calling schedule in NMI context. 1625 * Even with normal interrupts enabled. An NMI should not be 1626 * setting NEED_RESCHED or anything that normal interrupts and 1627 * exceptions might do. 1628 */ 1629 call paranoid_entry 1630 UNWIND_HINT_REGS 1631 1632 /* paranoidentry do_nmi, 0; without TRACE_IRQS_OFF */ 1633 movq %rsp, %rdi 1634 movq $-1, %rsi 1635 call do_nmi 1636 1637 RESTORE_CR3 scratch_reg=%r15 save_reg=%r14 1638 1639 testl %ebx, %ebx /* swapgs needed? */ 1640 jnz nmi_restore 1641nmi_swapgs: 1642 SWAPGS_UNSAFE_STACK 1643nmi_restore: 1644 POP_REGS 1645 1646 /* 1647 * Skip orig_ax and the "outermost" frame to point RSP at the "iret" 1648 * at the "iret" frame. 1649 */ 1650 addq $6*8, %rsp 1651 1652 /* 1653 * Clear "NMI executing". Set DF first so that we can easily 1654 * distinguish the remaining code between here and IRET from 1655 * the SYSCALL entry and exit paths. 1656 * 1657 * We arguably should just inspect RIP instead, but I (Andy) wrote 1658 * this code when I had the misapprehension that Xen PV supported 1659 * NMIs, and Xen PV would break that approach. 1660 */ 1661 std 1662 movq $0, 5*8(%rsp) /* clear "NMI executing" */ 1663 1664 /* 1665 * iretq reads the "iret" frame and exits the NMI stack in a 1666 * single instruction. We are returning to kernel mode, so this 1667 * cannot result in a fault. Similarly, we don't need to worry 1668 * about espfix64 on the way back to kernel mode. 1669 */ 1670 iretq 1671END(nmi) 1672 1673ENTRY(ignore_sysret) 1674 UNWIND_HINT_EMPTY 1675 mov $-ENOSYS, %eax 1676 sysret 1677END(ignore_sysret) 1678 1679ENTRY(rewind_stack_do_exit) 1680 UNWIND_HINT_FUNC 1681 /* Prevent any naive code from trying to unwind to our caller. */ 1682 xorl %ebp, %ebp 1683 1684 movq PER_CPU_VAR(cpu_current_top_of_stack), %rax 1685 leaq -PTREGS_SIZE(%rax), %rsp 1686 UNWIND_HINT_FUNC sp_offset=PTREGS_SIZE 1687 1688 call do_exit 1689END(rewind_stack_do_exit) 1690