1 /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) */ 2 /* 3 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34 #ifndef MLX5_ABI_USER_H 35 #define MLX5_ABI_USER_H 36 37 #include <linux/types.h> 38 #include <linux/if_ether.h> /* For ETH_ALEN. */ 39 40 enum { 41 MLX5_QP_FLAG_SIGNATURE = 1 << 0, 42 MLX5_QP_FLAG_SCATTER_CQE = 1 << 1, 43 MLX5_QP_FLAG_TUNNEL_OFFLOADS = 1 << 2, 44 MLX5_QP_FLAG_BFREG_INDEX = 1 << 3, 45 MLX5_QP_FLAG_TYPE_DCT = 1 << 4, 46 MLX5_QP_FLAG_TYPE_DCI = 1 << 5, 47 }; 48 49 enum { 50 MLX5_SRQ_FLAG_SIGNATURE = 1 << 0, 51 }; 52 53 enum { 54 MLX5_WQ_FLAG_SIGNATURE = 1 << 0, 55 }; 56 57 /* Increment this value if any changes that break userspace ABI 58 * compatibility are made. 59 */ 60 #define MLX5_IB_UVERBS_ABI_VERSION 1 61 62 /* Make sure that all structs defined in this file remain laid out so 63 * that they pack the same way on 32-bit and 64-bit architectures (to 64 * avoid incompatibility between 32-bit userspace and 64-bit kernels). 65 * In particular do not use pointer types -- pass pointers in __u64 66 * instead. 67 */ 68 69 struct mlx5_ib_alloc_ucontext_req { 70 __u32 total_num_bfregs; 71 __u32 num_low_latency_bfregs; 72 }; 73 74 enum mlx5_lib_caps { 75 MLX5_LIB_CAP_4K_UAR = (__u64)1 << 0, 76 }; 77 78 struct mlx5_ib_alloc_ucontext_req_v2 { 79 __u32 total_num_bfregs; 80 __u32 num_low_latency_bfregs; 81 __u32 flags; 82 __u32 comp_mask; 83 __u8 max_cqe_version; 84 __u8 reserved0; 85 __u16 reserved1; 86 __u32 reserved2; 87 __aligned_u64 lib_caps; 88 }; 89 90 enum mlx5_ib_alloc_ucontext_resp_mask { 91 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET = 1UL << 0, 92 }; 93 94 enum mlx5_user_cmds_supp_uhw { 95 MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE = 1 << 0, 96 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH = 1 << 1, 97 }; 98 99 /* The eth_min_inline response value is set to off-by-one vs the FW 100 * returned value to allow user-space to deal with older kernels. 101 */ 102 enum mlx5_user_inline_mode { 103 MLX5_USER_INLINE_MODE_NA, 104 MLX5_USER_INLINE_MODE_NONE, 105 MLX5_USER_INLINE_MODE_L2, 106 MLX5_USER_INLINE_MODE_IP, 107 MLX5_USER_INLINE_MODE_TCP_UDP, 108 }; 109 110 enum { 111 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM = 1 << 0, 112 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA = 1 << 1, 113 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING = 1 << 2, 114 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD = 1 << 3, 115 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN = 1 << 4, 116 }; 117 118 struct mlx5_ib_alloc_ucontext_resp { 119 __u32 qp_tab_size; 120 __u32 bf_reg_size; 121 __u32 tot_bfregs; 122 __u32 cache_line_size; 123 __u16 max_sq_desc_sz; 124 __u16 max_rq_desc_sz; 125 __u32 max_send_wqebb; 126 __u32 max_recv_wr; 127 __u32 max_srq_recv_wr; 128 __u16 num_ports; 129 __u16 flow_action_flags; 130 __u32 comp_mask; 131 __u32 response_length; 132 __u8 cqe_version; 133 __u8 cmds_supp_uhw; 134 __u8 eth_min_inline; 135 __u8 clock_info_versions; 136 __aligned_u64 hca_core_clock_offset; 137 __u32 log_uar_size; 138 __u32 num_uars_per_page; 139 __u32 num_dyn_bfregs; 140 __u32 reserved3; 141 }; 142 143 struct mlx5_ib_alloc_pd_resp { 144 __u32 pdn; 145 }; 146 147 struct mlx5_ib_tso_caps { 148 __u32 max_tso; /* Maximum tso payload size in bytes */ 149 150 /* Corresponding bit will be set if qp type from 151 * 'enum ib_qp_type' is supported, e.g. 152 * supported_qpts |= 1 << IB_QPT_UD 153 */ 154 __u32 supported_qpts; 155 }; 156 157 struct mlx5_ib_rss_caps { 158 __aligned_u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */ 159 __u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */ 160 __u8 reserved[7]; 161 }; 162 163 enum mlx5_ib_cqe_comp_res_format { 164 MLX5_IB_CQE_RES_FORMAT_HASH = 1 << 0, 165 MLX5_IB_CQE_RES_FORMAT_CSUM = 1 << 1, 166 MLX5_IB_CQE_RES_RESERVED = 1 << 2, 167 }; 168 169 struct mlx5_ib_cqe_comp_caps { 170 __u32 max_num; 171 __u32 supported_format; /* enum mlx5_ib_cqe_comp_res_format */ 172 }; 173 174 enum mlx5_ib_packet_pacing_cap_flags { 175 MLX5_IB_PP_SUPPORT_BURST = 1 << 0, 176 }; 177 178 struct mlx5_packet_pacing_caps { 179 __u32 qp_rate_limit_min; 180 __u32 qp_rate_limit_max; /* In kpbs */ 181 182 /* Corresponding bit will be set if qp type from 183 * 'enum ib_qp_type' is supported, e.g. 184 * supported_qpts |= 1 << IB_QPT_RAW_PACKET 185 */ 186 __u32 supported_qpts; 187 __u8 cap_flags; /* enum mlx5_ib_packet_pacing_cap_flags */ 188 __u8 reserved[3]; 189 }; 190 191 enum mlx5_ib_mpw_caps { 192 MPW_RESERVED = 1 << 0, 193 MLX5_IB_ALLOW_MPW = 1 << 1, 194 MLX5_IB_SUPPORT_EMPW = 1 << 2, 195 }; 196 197 enum mlx5_ib_sw_parsing_offloads { 198 MLX5_IB_SW_PARSING = 1 << 0, 199 MLX5_IB_SW_PARSING_CSUM = 1 << 1, 200 MLX5_IB_SW_PARSING_LSO = 1 << 2, 201 }; 202 203 struct mlx5_ib_sw_parsing_caps { 204 __u32 sw_parsing_offloads; /* enum mlx5_ib_sw_parsing_offloads */ 205 206 /* Corresponding bit will be set if qp type from 207 * 'enum ib_qp_type' is supported, e.g. 208 * supported_qpts |= 1 << IB_QPT_RAW_PACKET 209 */ 210 __u32 supported_qpts; 211 }; 212 213 struct mlx5_ib_striding_rq_caps { 214 __u32 min_single_stride_log_num_of_bytes; 215 __u32 max_single_stride_log_num_of_bytes; 216 __u32 min_single_wqe_log_num_of_strides; 217 __u32 max_single_wqe_log_num_of_strides; 218 219 /* Corresponding bit will be set if qp type from 220 * 'enum ib_qp_type' is supported, e.g. 221 * supported_qpts |= 1 << IB_QPT_RAW_PACKET 222 */ 223 __u32 supported_qpts; 224 __u32 reserved; 225 }; 226 227 enum mlx5_ib_query_dev_resp_flags { 228 /* Support 128B CQE compression */ 229 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP = 1 << 0, 230 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD = 1 << 1, 231 }; 232 233 enum mlx5_ib_tunnel_offloads { 234 MLX5_IB_TUNNELED_OFFLOADS_VXLAN = 1 << 0, 235 MLX5_IB_TUNNELED_OFFLOADS_GRE = 1 << 1, 236 MLX5_IB_TUNNELED_OFFLOADS_GENEVE = 1 << 2 237 }; 238 239 struct mlx5_ib_query_device_resp { 240 __u32 comp_mask; 241 __u32 response_length; 242 struct mlx5_ib_tso_caps tso_caps; 243 struct mlx5_ib_rss_caps rss_caps; 244 struct mlx5_ib_cqe_comp_caps cqe_comp_caps; 245 struct mlx5_packet_pacing_caps packet_pacing_caps; 246 __u32 mlx5_ib_support_multi_pkt_send_wqes; 247 __u32 flags; /* Use enum mlx5_ib_query_dev_resp_flags */ 248 struct mlx5_ib_sw_parsing_caps sw_parsing_caps; 249 struct mlx5_ib_striding_rq_caps striding_rq_caps; 250 __u32 tunnel_offloads_caps; /* enum mlx5_ib_tunnel_offloads */ 251 __u32 reserved; 252 }; 253 254 enum mlx5_ib_create_cq_flags { 255 MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD = 1 << 0, 256 }; 257 258 struct mlx5_ib_create_cq { 259 __aligned_u64 buf_addr; 260 __aligned_u64 db_addr; 261 __u32 cqe_size; 262 __u8 cqe_comp_en; 263 __u8 cqe_comp_res_format; 264 __u16 flags; 265 }; 266 267 struct mlx5_ib_create_cq_resp { 268 __u32 cqn; 269 __u32 reserved; 270 }; 271 272 struct mlx5_ib_resize_cq { 273 __aligned_u64 buf_addr; 274 __u16 cqe_size; 275 __u16 reserved0; 276 __u32 reserved1; 277 }; 278 279 struct mlx5_ib_create_srq { 280 __aligned_u64 buf_addr; 281 __aligned_u64 db_addr; 282 __u32 flags; 283 __u32 reserved0; /* explicit padding (optional on i386) */ 284 __u32 uidx; 285 __u32 reserved1; 286 }; 287 288 struct mlx5_ib_create_srq_resp { 289 __u32 srqn; 290 __u32 reserved; 291 }; 292 293 struct mlx5_ib_create_qp { 294 __aligned_u64 buf_addr; 295 __aligned_u64 db_addr; 296 __u32 sq_wqe_count; 297 __u32 rq_wqe_count; 298 __u32 rq_wqe_shift; 299 __u32 flags; 300 __u32 uidx; 301 __u32 bfreg_index; 302 union { 303 __aligned_u64 sq_buf_addr; 304 __aligned_u64 access_key; 305 }; 306 }; 307 308 /* RX Hash function flags */ 309 enum mlx5_rx_hash_function_flags { 310 MLX5_RX_HASH_FUNC_TOEPLITZ = 1 << 0, 311 }; 312 313 /* 314 * RX Hash flags, these flags allows to set which incoming packet's field should 315 * participates in RX Hash. Each flag represent certain packet's field, 316 * when the flag is set the field that is represented by the flag will 317 * participate in RX Hash calculation. 318 * Note: *IPV4 and *IPV6 flags can't be enabled together on the same QP 319 * and *TCP and *UDP flags can't be enabled together on the same QP. 320 */ 321 enum mlx5_rx_hash_fields { 322 MLX5_RX_HASH_SRC_IPV4 = 1 << 0, 323 MLX5_RX_HASH_DST_IPV4 = 1 << 1, 324 MLX5_RX_HASH_SRC_IPV6 = 1 << 2, 325 MLX5_RX_HASH_DST_IPV6 = 1 << 3, 326 MLX5_RX_HASH_SRC_PORT_TCP = 1 << 4, 327 MLX5_RX_HASH_DST_PORT_TCP = 1 << 5, 328 MLX5_RX_HASH_SRC_PORT_UDP = 1 << 6, 329 MLX5_RX_HASH_DST_PORT_UDP = 1 << 7, 330 MLX5_RX_HASH_IPSEC_SPI = 1 << 8, 331 /* Save bits for future fields */ 332 MLX5_RX_HASH_INNER = (1UL << 31), 333 }; 334 335 struct mlx5_ib_create_qp_rss { 336 __aligned_u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */ 337 __u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */ 338 __u8 rx_key_len; /* valid only for Toeplitz */ 339 __u8 reserved[6]; 340 __u8 rx_hash_key[128]; /* valid only for Toeplitz */ 341 __u32 comp_mask; 342 __u32 flags; 343 }; 344 345 struct mlx5_ib_create_qp_resp { 346 __u32 bfreg_index; 347 __u32 reserved; 348 }; 349 350 struct mlx5_ib_alloc_mw { 351 __u32 comp_mask; 352 __u8 num_klms; 353 __u8 reserved1; 354 __u16 reserved2; 355 }; 356 357 enum mlx5_ib_create_wq_mask { 358 MLX5_IB_CREATE_WQ_STRIDING_RQ = (1 << 0), 359 }; 360 361 struct mlx5_ib_create_wq { 362 __aligned_u64 buf_addr; 363 __aligned_u64 db_addr; 364 __u32 rq_wqe_count; 365 __u32 rq_wqe_shift; 366 __u32 user_index; 367 __u32 flags; 368 __u32 comp_mask; 369 __u32 single_stride_log_num_of_bytes; 370 __u32 single_wqe_log_num_of_strides; 371 __u32 two_byte_shift_en; 372 }; 373 374 struct mlx5_ib_create_ah_resp { 375 __u32 response_length; 376 __u8 dmac[ETH_ALEN]; 377 __u8 reserved[6]; 378 }; 379 380 struct mlx5_ib_burst_info { 381 __u32 max_burst_sz; 382 __u16 typical_pkt_sz; 383 __u16 reserved; 384 }; 385 386 struct mlx5_ib_modify_qp { 387 __u32 comp_mask; 388 struct mlx5_ib_burst_info burst_info; 389 __u32 reserved; 390 }; 391 392 struct mlx5_ib_modify_qp_resp { 393 __u32 response_length; 394 __u32 dctn; 395 }; 396 397 struct mlx5_ib_create_wq_resp { 398 __u32 response_length; 399 __u32 reserved; 400 }; 401 402 struct mlx5_ib_create_rwq_ind_tbl_resp { 403 __u32 response_length; 404 __u32 reserved; 405 }; 406 407 struct mlx5_ib_modify_wq { 408 __u32 comp_mask; 409 __u32 reserved; 410 }; 411 412 struct mlx5_ib_clock_info { 413 __u32 sign; 414 __u32 resv; 415 __aligned_u64 nsec; 416 __aligned_u64 cycles; 417 __aligned_u64 frac; 418 __u32 mult; 419 __u32 shift; 420 __aligned_u64 mask; 421 __aligned_u64 overflow_period; 422 }; 423 424 enum mlx5_ib_mmap_cmd { 425 MLX5_IB_MMAP_REGULAR_PAGE = 0, 426 MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES = 1, 427 MLX5_IB_MMAP_WC_PAGE = 2, 428 MLX5_IB_MMAP_NC_PAGE = 3, 429 /* 5 is chosen in order to be compatible with old versions of libmlx5 */ 430 MLX5_IB_MMAP_CORE_CLOCK = 5, 431 MLX5_IB_MMAP_ALLOC_WC = 6, 432 MLX5_IB_MMAP_CLOCK_INFO = 7, 433 MLX5_IB_MMAP_DEVICE_MEM = 8, 434 }; 435 436 enum { 437 MLX5_IB_CLOCK_INFO_KERNEL_UPDATING = 1, 438 }; 439 440 /* Bit indexes for the mlx5_alloc_ucontext_resp.clock_info_versions bitmap */ 441 enum { 442 MLX5_IB_CLOCK_INFO_V1 = 0, 443 }; 444 #endif /* MLX5_ABI_USER_H */ 445