1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include "amdgpu.h" 28 #include "amdgpu_psp.h" 29 #include "amdgpu_ucode.h" 30 #include "soc15_common.h" 31 #include "psp_v10_0.h" 32 33 #include "mp/mp_10_0_offset.h" 34 #include "gc/gc_9_1_offset.h" 35 #include "sdma0/sdma0_4_1_offset.h" 36 37 MODULE_FIRMWARE("amdgpu/raven_asd.bin"); 38 39 static int 40 psp_v10_0_get_fw_type(struct amdgpu_firmware_info *ucode, enum psp_gfx_fw_type *type) 41 { 42 switch(ucode->ucode_id) { 43 case AMDGPU_UCODE_ID_SDMA0: 44 *type = GFX_FW_TYPE_SDMA0; 45 break; 46 case AMDGPU_UCODE_ID_SDMA1: 47 *type = GFX_FW_TYPE_SDMA1; 48 break; 49 case AMDGPU_UCODE_ID_CP_CE: 50 *type = GFX_FW_TYPE_CP_CE; 51 break; 52 case AMDGPU_UCODE_ID_CP_PFP: 53 *type = GFX_FW_TYPE_CP_PFP; 54 break; 55 case AMDGPU_UCODE_ID_CP_ME: 56 *type = GFX_FW_TYPE_CP_ME; 57 break; 58 case AMDGPU_UCODE_ID_CP_MEC1: 59 *type = GFX_FW_TYPE_CP_MEC; 60 break; 61 case AMDGPU_UCODE_ID_CP_MEC1_JT: 62 *type = GFX_FW_TYPE_CP_MEC_ME1; 63 break; 64 case AMDGPU_UCODE_ID_CP_MEC2: 65 *type = GFX_FW_TYPE_CP_MEC; 66 break; 67 case AMDGPU_UCODE_ID_CP_MEC2_JT: 68 *type = GFX_FW_TYPE_CP_MEC_ME2; 69 break; 70 case AMDGPU_UCODE_ID_RLC_G: 71 *type = GFX_FW_TYPE_RLC_G; 72 break; 73 case AMDGPU_UCODE_ID_SMC: 74 *type = GFX_FW_TYPE_SMU; 75 break; 76 case AMDGPU_UCODE_ID_UVD: 77 *type = GFX_FW_TYPE_UVD; 78 break; 79 case AMDGPU_UCODE_ID_VCE: 80 *type = GFX_FW_TYPE_VCE; 81 break; 82 case AMDGPU_UCODE_ID_MAXIMUM: 83 default: 84 return -EINVAL; 85 } 86 87 return 0; 88 } 89 90 static int psp_v10_0_init_microcode(struct psp_context *psp) 91 { 92 struct amdgpu_device *adev = psp->adev; 93 const char *chip_name; 94 char fw_name[30]; 95 int err = 0; 96 const struct psp_firmware_header_v1_0 *hdr; 97 98 DRM_DEBUG("\n"); 99 100 switch (adev->asic_type) { 101 case CHIP_RAVEN: 102 chip_name = "raven"; 103 break; 104 default: BUG(); 105 } 106 107 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 108 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev); 109 if (err) 110 goto out; 111 112 err = amdgpu_ucode_validate(adev->psp.asd_fw); 113 if (err) 114 goto out; 115 116 hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 117 adev->psp.asd_fw_version = le32_to_cpu(hdr->header.ucode_version); 118 adev->psp.asd_feature_version = le32_to_cpu(hdr->ucode_feature_version); 119 adev->psp.asd_ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes); 120 adev->psp.asd_start_addr = (uint8_t *)hdr + 121 le32_to_cpu(hdr->header.ucode_array_offset_bytes); 122 123 return 0; 124 out: 125 if (err) { 126 dev_err(adev->dev, 127 "psp v10.0: Failed to load firmware \"%s\"\n", 128 fw_name); 129 release_firmware(adev->psp.asd_fw); 130 adev->psp.asd_fw = NULL; 131 } 132 133 return err; 134 } 135 136 static int psp_v10_0_prep_cmd_buf(struct amdgpu_firmware_info *ucode, 137 struct psp_gfx_cmd_resp *cmd) 138 { 139 int ret; 140 uint64_t fw_mem_mc_addr = ucode->mc_addr; 141 142 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 143 144 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 145 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 146 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 147 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 148 149 ret = psp_v10_0_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 150 if (ret) 151 DRM_ERROR("Unknown firmware type\n"); 152 153 return ret; 154 } 155 156 static int psp_v10_0_ring_init(struct psp_context *psp, 157 enum psp_ring_type ring_type) 158 { 159 int ret = 0; 160 struct psp_ring *ring; 161 struct amdgpu_device *adev = psp->adev; 162 163 ring = &psp->km_ring; 164 165 ring->ring_type = ring_type; 166 167 /* allocate 4k Page of Local Frame Buffer memory for ring */ 168 ring->ring_size = 0x1000; 169 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 170 AMDGPU_GEM_DOMAIN_VRAM, 171 &adev->firmware.rbuf, 172 &ring->ring_mem_mc_addr, 173 (void **)&ring->ring_mem); 174 if (ret) { 175 ring->ring_size = 0; 176 return ret; 177 } 178 179 return 0; 180 } 181 182 static int psp_v10_0_ring_create(struct psp_context *psp, 183 enum psp_ring_type ring_type) 184 { 185 int ret = 0; 186 unsigned int psp_ring_reg = 0; 187 struct psp_ring *ring = &psp->km_ring; 188 struct amdgpu_device *adev = psp->adev; 189 190 /* Write low address of the ring to C2PMSG_69 */ 191 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 192 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg); 193 /* Write high address of the ring to C2PMSG_70 */ 194 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 195 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg); 196 /* Write size of ring to C2PMSG_71 */ 197 psp_ring_reg = ring->ring_size; 198 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg); 199 /* Write the ring initialization command to C2PMSG_64 */ 200 psp_ring_reg = ring_type; 201 psp_ring_reg = psp_ring_reg << 16; 202 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); 203 204 /* There might be handshake issue with hardware which needs delay */ 205 mdelay(20); 206 207 /* Wait for response flag (bit 31) in C2PMSG_64 */ 208 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 209 0x80000000, 0x8000FFFF, false); 210 211 return ret; 212 } 213 214 static int psp_v10_0_ring_stop(struct psp_context *psp, 215 enum psp_ring_type ring_type) 216 { 217 int ret = 0; 218 struct psp_ring *ring; 219 unsigned int psp_ring_reg = 0; 220 struct amdgpu_device *adev = psp->adev; 221 222 ring = &psp->km_ring; 223 224 /* Write the ring destroy command to C2PMSG_64 */ 225 psp_ring_reg = 3 << 16; 226 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); 227 228 /* There might be handshake issue with hardware which needs delay */ 229 mdelay(20); 230 231 /* Wait for response flag (bit 31) in C2PMSG_64 */ 232 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 233 0x80000000, 0x80000000, false); 234 235 return ret; 236 } 237 238 static int psp_v10_0_ring_destroy(struct psp_context *psp, 239 enum psp_ring_type ring_type) 240 { 241 int ret = 0; 242 struct psp_ring *ring = &psp->km_ring; 243 struct amdgpu_device *adev = psp->adev; 244 245 ret = psp_v10_0_ring_stop(psp, ring_type); 246 if (ret) 247 DRM_ERROR("Fail to stop psp ring\n"); 248 249 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 250 &ring->ring_mem_mc_addr, 251 (void **)&ring->ring_mem); 252 253 return ret; 254 } 255 256 static int psp_v10_0_cmd_submit(struct psp_context *psp, 257 struct amdgpu_firmware_info *ucode, 258 uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr, 259 int index) 260 { 261 unsigned int psp_write_ptr_reg = 0; 262 struct psp_gfx_rb_frame * write_frame = psp->km_ring.ring_mem; 263 struct psp_ring *ring = &psp->km_ring; 264 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 265 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 266 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 267 struct amdgpu_device *adev = psp->adev; 268 uint32_t ring_size_dw = ring->ring_size / 4; 269 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 270 271 /* KM (GPCOM) prepare write pointer */ 272 psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67); 273 274 /* Update KM RB frame pointer to new frame */ 275 if ((psp_write_ptr_reg % ring_size_dw) == 0) 276 write_frame = ring_buffer_start; 277 else 278 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 279 /* Check invalid write_frame ptr address */ 280 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 281 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 282 ring_buffer_start, ring_buffer_end, write_frame); 283 DRM_ERROR("write_frame is pointing to address out of bounds\n"); 284 return -EINVAL; 285 } 286 287 /* Initialize KM RB frame */ 288 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 289 290 /* Update KM RB frame */ 291 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 292 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 293 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 294 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 295 write_frame->fence_value = index; 296 297 /* Update the write Pointer in DWORDs */ 298 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 299 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg); 300 301 return 0; 302 } 303 304 static int 305 psp_v10_0_sram_map(struct amdgpu_device *adev, 306 unsigned int *sram_offset, unsigned int *sram_addr_reg_offset, 307 unsigned int *sram_data_reg_offset, 308 enum AMDGPU_UCODE_ID ucode_id) 309 { 310 int ret = 0; 311 312 switch(ucode_id) { 313 /* TODO: needs to confirm */ 314 #if 0 315 case AMDGPU_UCODE_ID_SMC: 316 *sram_offset = 0; 317 *sram_addr_reg_offset = 0; 318 *sram_data_reg_offset = 0; 319 break; 320 #endif 321 322 case AMDGPU_UCODE_ID_CP_CE: 323 *sram_offset = 0x0; 324 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR); 325 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA); 326 break; 327 328 case AMDGPU_UCODE_ID_CP_PFP: 329 *sram_offset = 0x0; 330 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR); 331 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA); 332 break; 333 334 case AMDGPU_UCODE_ID_CP_ME: 335 *sram_offset = 0x0; 336 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR); 337 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA); 338 break; 339 340 case AMDGPU_UCODE_ID_CP_MEC1: 341 *sram_offset = 0x10000; 342 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR); 343 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA); 344 break; 345 346 case AMDGPU_UCODE_ID_CP_MEC2: 347 *sram_offset = 0x10000; 348 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR); 349 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA); 350 break; 351 352 case AMDGPU_UCODE_ID_RLC_G: 353 *sram_offset = 0x2000; 354 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR); 355 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA); 356 break; 357 358 case AMDGPU_UCODE_ID_SDMA0: 359 *sram_offset = 0x0; 360 *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR); 361 *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA); 362 break; 363 364 /* TODO: needs to confirm */ 365 #if 0 366 case AMDGPU_UCODE_ID_SDMA1: 367 *sram_offset = ; 368 *sram_addr_reg_offset = ; 369 break; 370 371 case AMDGPU_UCODE_ID_UVD: 372 *sram_offset = ; 373 *sram_addr_reg_offset = ; 374 break; 375 376 case AMDGPU_UCODE_ID_VCE: 377 *sram_offset = ; 378 *sram_addr_reg_offset = ; 379 break; 380 #endif 381 382 case AMDGPU_UCODE_ID_MAXIMUM: 383 default: 384 ret = -EINVAL; 385 break; 386 } 387 388 return ret; 389 } 390 391 static bool psp_v10_0_compare_sram_data(struct psp_context *psp, 392 struct amdgpu_firmware_info *ucode, 393 enum AMDGPU_UCODE_ID ucode_type) 394 { 395 int err = 0; 396 unsigned int fw_sram_reg_val = 0; 397 unsigned int fw_sram_addr_reg_offset = 0; 398 unsigned int fw_sram_data_reg_offset = 0; 399 unsigned int ucode_size; 400 uint32_t *ucode_mem = NULL; 401 struct amdgpu_device *adev = psp->adev; 402 403 err = psp_v10_0_sram_map(adev, &fw_sram_reg_val, &fw_sram_addr_reg_offset, 404 &fw_sram_data_reg_offset, ucode_type); 405 if (err) 406 return false; 407 408 WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val); 409 410 ucode_size = ucode->ucode_size; 411 ucode_mem = (uint32_t *)ucode->kaddr; 412 while (!ucode_size) { 413 fw_sram_reg_val = RREG32(fw_sram_data_reg_offset); 414 415 if (*ucode_mem != fw_sram_reg_val) 416 return false; 417 418 ucode_mem++; 419 /* 4 bytes */ 420 ucode_size -= 4; 421 } 422 423 return true; 424 } 425 426 427 static int psp_v10_0_mode1_reset(struct psp_context *psp) 428 { 429 DRM_INFO("psp mode 1 reset not supported now! \n"); 430 return -EINVAL; 431 } 432 433 static const struct psp_funcs psp_v10_0_funcs = { 434 .init_microcode = psp_v10_0_init_microcode, 435 .prep_cmd_buf = psp_v10_0_prep_cmd_buf, 436 .ring_init = psp_v10_0_ring_init, 437 .ring_create = psp_v10_0_ring_create, 438 .ring_stop = psp_v10_0_ring_stop, 439 .ring_destroy = psp_v10_0_ring_destroy, 440 .cmd_submit = psp_v10_0_cmd_submit, 441 .compare_sram_data = psp_v10_0_compare_sram_data, 442 .mode1_reset = psp_v10_0_mode1_reset, 443 }; 444 445 void psp_v10_0_set_psp_funcs(struct psp_context *psp) 446 { 447 psp->funcs = &psp_v10_0_funcs; 448 } 449