1 // SPDX-License-Identifier: GPL-2.0 2 /******************************************************************************* 3 4 Intel 10 Gigabit PCI Express Linux driver 5 Copyright(c) 1999 - 2013 Intel Corporation. 6 7 This program is free software; you can redistribute it and/or modify it 8 under the terms and conditions of the GNU General Public License, 9 version 2, as published by the Free Software Foundation. 10 11 This program is distributed in the hope it will be useful, but WITHOUT 12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 more details. 15 16 You should have received a copy of the GNU General Public License along with 17 this program; if not, write to the Free Software Foundation, Inc., 18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 19 20 The full GNU General Public License is included in this distribution in 21 the file called "COPYING". 22 23 Contact Information: 24 Linux NICS <linux.nics@intel.com> 25 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 26 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 27 28 *******************************************************************************/ 29 30 #include "ixgbe.h" 31 #include "ixgbe_type.h" 32 #include "ixgbe_dcb.h" 33 #include "ixgbe_dcb_82598.h" 34 35 /** 36 * ixgbe_dcb_config_rx_arbiter_82598 - Config Rx data arbiter 37 * @hw: pointer to hardware structure 38 * @refill: refill credits index by traffic class 39 * @max: max credits index by traffic class 40 * @prio_type: priority type indexed by traffic class 41 * 42 * Configure Rx Data Arbiter and credits for each traffic class. 43 */ 44 s32 ixgbe_dcb_config_rx_arbiter_82598(struct ixgbe_hw *hw, 45 u16 *refill, 46 u16 *max, 47 u8 *prio_type) 48 { 49 u32 reg = 0; 50 u32 credit_refill = 0; 51 u32 credit_max = 0; 52 u8 i = 0; 53 54 reg = IXGBE_READ_REG(hw, IXGBE_RUPPBMR) | IXGBE_RUPPBMR_MQA; 55 IXGBE_WRITE_REG(hw, IXGBE_RUPPBMR, reg); 56 57 reg = IXGBE_READ_REG(hw, IXGBE_RMCS); 58 /* Enable Arbiter */ 59 reg &= ~IXGBE_RMCS_ARBDIS; 60 /* Enable Receive Recycle within the BWG */ 61 reg |= IXGBE_RMCS_RRM; 62 /* Enable Deficit Fixed Priority arbitration*/ 63 reg |= IXGBE_RMCS_DFP; 64 65 IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg); 66 67 /* Configure traffic class credits and priority */ 68 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 69 credit_refill = refill[i]; 70 credit_max = max[i]; 71 72 reg = credit_refill | (credit_max << IXGBE_RT2CR_MCL_SHIFT); 73 74 if (prio_type[i] == prio_link) 75 reg |= IXGBE_RT2CR_LSP; 76 77 IXGBE_WRITE_REG(hw, IXGBE_RT2CR(i), reg); 78 } 79 80 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 81 reg |= IXGBE_RDRXCTL_RDMTS_1_2; 82 reg |= IXGBE_RDRXCTL_MPBEN; 83 reg |= IXGBE_RDRXCTL_MCEN; 84 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg); 85 86 reg = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 87 /* Make sure there is enough descriptors before arbitration */ 88 reg &= ~IXGBE_RXCTRL_DMBYPS; 89 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg); 90 91 return 0; 92 } 93 94 /** 95 * ixgbe_dcb_config_tx_desc_arbiter_82598 - Config Tx Desc. arbiter 96 * @hw: pointer to hardware structure 97 * @refill: refill credits index by traffic class 98 * @max: max credits index by traffic class 99 * @bwg_id: bandwidth grouping indexed by traffic class 100 * @prio_type: priority type indexed by traffic class 101 * 102 * Configure Tx Descriptor Arbiter and credits for each traffic class. 103 */ 104 s32 ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw *hw, 105 u16 *refill, 106 u16 *max, 107 u8 *bwg_id, 108 u8 *prio_type) 109 { 110 u32 reg, max_credits; 111 u8 i; 112 113 reg = IXGBE_READ_REG(hw, IXGBE_DPMCS); 114 115 /* Enable arbiter */ 116 reg &= ~IXGBE_DPMCS_ARBDIS; 117 reg |= IXGBE_DPMCS_TSOEF; 118 119 /* Configure Max TSO packet size 34KB including payload and headers */ 120 reg |= (0x4 << IXGBE_DPMCS_MTSOS_SHIFT); 121 122 IXGBE_WRITE_REG(hw, IXGBE_DPMCS, reg); 123 124 /* Configure traffic class credits and priority */ 125 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 126 max_credits = max[i]; 127 reg = max_credits << IXGBE_TDTQ2TCCR_MCL_SHIFT; 128 reg |= refill[i]; 129 reg |= (u32)(bwg_id[i]) << IXGBE_TDTQ2TCCR_BWG_SHIFT; 130 131 if (prio_type[i] == prio_group) 132 reg |= IXGBE_TDTQ2TCCR_GSP; 133 134 if (prio_type[i] == prio_link) 135 reg |= IXGBE_TDTQ2TCCR_LSP; 136 137 IXGBE_WRITE_REG(hw, IXGBE_TDTQ2TCCR(i), reg); 138 } 139 140 return 0; 141 } 142 143 /** 144 * ixgbe_dcb_config_tx_data_arbiter_82598 - Config Tx data arbiter 145 * @hw: pointer to hardware structure 146 * @refill: refill credits index by traffic class 147 * @max: max credits index by traffic class 148 * @bwg_id: bandwidth grouping indexed by traffic class 149 * @prio_type: priority type indexed by traffic class 150 * 151 * Configure Tx Data Arbiter and credits for each traffic class. 152 */ 153 s32 ixgbe_dcb_config_tx_data_arbiter_82598(struct ixgbe_hw *hw, 154 u16 *refill, 155 u16 *max, 156 u8 *bwg_id, 157 u8 *prio_type) 158 { 159 u32 reg; 160 u8 i; 161 162 reg = IXGBE_READ_REG(hw, IXGBE_PDPMCS); 163 /* Enable Data Plane Arbiter */ 164 reg &= ~IXGBE_PDPMCS_ARBDIS; 165 /* Enable DFP and Transmit Recycle Mode */ 166 reg |= (IXGBE_PDPMCS_TPPAC | IXGBE_PDPMCS_TRM); 167 168 IXGBE_WRITE_REG(hw, IXGBE_PDPMCS, reg); 169 170 /* Configure traffic class credits and priority */ 171 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 172 reg = refill[i]; 173 reg |= (u32)(max[i]) << IXGBE_TDPT2TCCR_MCL_SHIFT; 174 reg |= (u32)(bwg_id[i]) << IXGBE_TDPT2TCCR_BWG_SHIFT; 175 176 if (prio_type[i] == prio_group) 177 reg |= IXGBE_TDPT2TCCR_GSP; 178 179 if (prio_type[i] == prio_link) 180 reg |= IXGBE_TDPT2TCCR_LSP; 181 182 IXGBE_WRITE_REG(hw, IXGBE_TDPT2TCCR(i), reg); 183 } 184 185 /* Enable Tx packet buffer division */ 186 reg = IXGBE_READ_REG(hw, IXGBE_DTXCTL); 187 reg |= IXGBE_DTXCTL_ENDBUBD; 188 IXGBE_WRITE_REG(hw, IXGBE_DTXCTL, reg); 189 190 return 0; 191 } 192 193 /** 194 * ixgbe_dcb_config_pfc_82598 - Config priority flow control 195 * @hw: pointer to hardware structure 196 * @pfc_en: enabled pfc bitmask 197 * 198 * Configure Priority Flow Control for each traffic class. 199 */ 200 s32 ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *hw, u8 pfc_en) 201 { 202 u32 fcrtl, reg; 203 u8 i; 204 205 /* Enable Transmit Priority Flow Control */ 206 reg = IXGBE_READ_REG(hw, IXGBE_RMCS); 207 reg &= ~IXGBE_RMCS_TFCE_802_3X; 208 reg |= IXGBE_RMCS_TFCE_PRIORITY; 209 IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg); 210 211 /* Enable Receive Priority Flow Control */ 212 reg = IXGBE_READ_REG(hw, IXGBE_FCTRL); 213 reg &= ~(IXGBE_FCTRL_RPFCE | IXGBE_FCTRL_RFCE); 214 215 if (pfc_en) 216 reg |= IXGBE_FCTRL_RPFCE; 217 218 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg); 219 220 /* Configure PFC Tx thresholds per TC */ 221 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 222 if (!(pfc_en & BIT(i))) { 223 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), 0); 224 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), 0); 225 continue; 226 } 227 228 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE; 229 reg = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN; 230 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), fcrtl); 231 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), reg); 232 } 233 234 /* Configure pause time */ 235 reg = hw->fc.pause_time * 0x00010001; 236 for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++) 237 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); 238 239 /* Configure flow control refresh threshold value */ 240 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); 241 242 243 return 0; 244 } 245 246 /** 247 * ixgbe_dcb_config_tc_stats_82598 - Configure traffic class statistics 248 * @hw: pointer to hardware structure 249 * 250 * Configure queue statistics registers, all queues belonging to same traffic 251 * class uses a single set of queue statistics counters. 252 */ 253 static s32 ixgbe_dcb_config_tc_stats_82598(struct ixgbe_hw *hw) 254 { 255 u32 reg = 0; 256 u8 i = 0; 257 u8 j = 0; 258 259 /* Receive Queues stats setting - 8 queues per statistics reg */ 260 for (i = 0, j = 0; i < 15 && j < 8; i = i + 2, j++) { 261 reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i)); 262 reg |= ((0x1010101) * j); 263 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg); 264 reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i + 1)); 265 reg |= ((0x1010101) * j); 266 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i + 1), reg); 267 } 268 /* Transmit Queues stats setting - 4 queues per statistics reg */ 269 for (i = 0; i < 8; i++) { 270 reg = IXGBE_READ_REG(hw, IXGBE_TQSMR(i)); 271 reg |= ((0x1010101) * i); 272 IXGBE_WRITE_REG(hw, IXGBE_TQSMR(i), reg); 273 } 274 275 return 0; 276 } 277 278 /** 279 * ixgbe_dcb_hw_config_82598 - Config and enable DCB 280 * @hw: pointer to hardware structure 281 * @pfc_en: enabled pfc bitmask 282 * @refill: refill credits index by traffic class 283 * @max: max credits index by traffic class 284 * @bwg_id: bandwidth grouping indexed by traffic class 285 * @prio_type: priority type indexed by traffic class 286 * 287 * Configure dcb settings and enable dcb mode. 288 */ 289 s32 ixgbe_dcb_hw_config_82598(struct ixgbe_hw *hw, u8 pfc_en, u16 *refill, 290 u16 *max, u8 *bwg_id, u8 *prio_type) 291 { 292 ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, prio_type); 293 ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, 294 bwg_id, prio_type); 295 ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, 296 bwg_id, prio_type); 297 ixgbe_dcb_config_pfc_82598(hw, pfc_en); 298 ixgbe_dcb_config_tc_stats_82598(hw); 299 300 return 0; 301 } 302