1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * This file is part of STM32 ADC driver 4 * 5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved 6 * Author: Fabrice Gasnier <fabrice.gasnier@st.com>. 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/dmaengine.h> 13 #include <linux/iio/iio.h> 14 #include <linux/iio/buffer.h> 15 #include <linux/iio/timer/stm32-lptim-trigger.h> 16 #include <linux/iio/timer/stm32-timer-trigger.h> 17 #include <linux/iio/trigger.h> 18 #include <linux/iio/trigger_consumer.h> 19 #include <linux/iio/triggered_buffer.h> 20 #include <linux/interrupt.h> 21 #include <linux/io.h> 22 #include <linux/iopoll.h> 23 #include <linux/module.h> 24 #include <linux/platform_device.h> 25 #include <linux/of.h> 26 #include <linux/of_device.h> 27 28 #include "stm32-adc-core.h" 29 30 /* STM32F4 - Registers for each ADC instance */ 31 #define STM32F4_ADC_SR 0x00 32 #define STM32F4_ADC_CR1 0x04 33 #define STM32F4_ADC_CR2 0x08 34 #define STM32F4_ADC_SMPR1 0x0C 35 #define STM32F4_ADC_SMPR2 0x10 36 #define STM32F4_ADC_HTR 0x24 37 #define STM32F4_ADC_LTR 0x28 38 #define STM32F4_ADC_SQR1 0x2C 39 #define STM32F4_ADC_SQR2 0x30 40 #define STM32F4_ADC_SQR3 0x34 41 #define STM32F4_ADC_JSQR 0x38 42 #define STM32F4_ADC_JDR1 0x3C 43 #define STM32F4_ADC_JDR2 0x40 44 #define STM32F4_ADC_JDR3 0x44 45 #define STM32F4_ADC_JDR4 0x48 46 #define STM32F4_ADC_DR 0x4C 47 48 /* STM32F4_ADC_SR - bit fields */ 49 #define STM32F4_STRT BIT(4) 50 #define STM32F4_EOC BIT(1) 51 52 /* STM32F4_ADC_CR1 - bit fields */ 53 #define STM32F4_RES_SHIFT 24 54 #define STM32F4_RES_MASK GENMASK(25, 24) 55 #define STM32F4_SCAN BIT(8) 56 #define STM32F4_EOCIE BIT(5) 57 58 /* STM32F4_ADC_CR2 - bit fields */ 59 #define STM32F4_SWSTART BIT(30) 60 #define STM32F4_EXTEN_SHIFT 28 61 #define STM32F4_EXTEN_MASK GENMASK(29, 28) 62 #define STM32F4_EXTSEL_SHIFT 24 63 #define STM32F4_EXTSEL_MASK GENMASK(27, 24) 64 #define STM32F4_EOCS BIT(10) 65 #define STM32F4_DDS BIT(9) 66 #define STM32F4_DMA BIT(8) 67 #define STM32F4_ADON BIT(0) 68 69 /* STM32H7 - Registers for each ADC instance */ 70 #define STM32H7_ADC_ISR 0x00 71 #define STM32H7_ADC_IER 0x04 72 #define STM32H7_ADC_CR 0x08 73 #define STM32H7_ADC_CFGR 0x0C 74 #define STM32H7_ADC_SMPR1 0x14 75 #define STM32H7_ADC_SMPR2 0x18 76 #define STM32H7_ADC_PCSEL 0x1C 77 #define STM32H7_ADC_SQR1 0x30 78 #define STM32H7_ADC_SQR2 0x34 79 #define STM32H7_ADC_SQR3 0x38 80 #define STM32H7_ADC_SQR4 0x3C 81 #define STM32H7_ADC_DR 0x40 82 #define STM32H7_ADC_DIFSEL 0xC0 83 #define STM32H7_ADC_CALFACT 0xC4 84 #define STM32H7_ADC_CALFACT2 0xC8 85 86 /* STM32H7_ADC_ISR - bit fields */ 87 #define STM32H7_EOC BIT(2) 88 #define STM32H7_ADRDY BIT(0) 89 90 /* STM32H7_ADC_IER - bit fields */ 91 #define STM32H7_EOCIE STM32H7_EOC 92 93 /* STM32H7_ADC_CR - bit fields */ 94 #define STM32H7_ADCAL BIT(31) 95 #define STM32H7_ADCALDIF BIT(30) 96 #define STM32H7_DEEPPWD BIT(29) 97 #define STM32H7_ADVREGEN BIT(28) 98 #define STM32H7_LINCALRDYW6 BIT(27) 99 #define STM32H7_LINCALRDYW5 BIT(26) 100 #define STM32H7_LINCALRDYW4 BIT(25) 101 #define STM32H7_LINCALRDYW3 BIT(24) 102 #define STM32H7_LINCALRDYW2 BIT(23) 103 #define STM32H7_LINCALRDYW1 BIT(22) 104 #define STM32H7_ADCALLIN BIT(16) 105 #define STM32H7_BOOST BIT(8) 106 #define STM32H7_ADSTP BIT(4) 107 #define STM32H7_ADSTART BIT(2) 108 #define STM32H7_ADDIS BIT(1) 109 #define STM32H7_ADEN BIT(0) 110 111 /* STM32H7_ADC_CFGR bit fields */ 112 #define STM32H7_EXTEN_SHIFT 10 113 #define STM32H7_EXTEN_MASK GENMASK(11, 10) 114 #define STM32H7_EXTSEL_SHIFT 5 115 #define STM32H7_EXTSEL_MASK GENMASK(9, 5) 116 #define STM32H7_RES_SHIFT 2 117 #define STM32H7_RES_MASK GENMASK(4, 2) 118 #define STM32H7_DMNGT_SHIFT 0 119 #define STM32H7_DMNGT_MASK GENMASK(1, 0) 120 121 enum stm32h7_adc_dmngt { 122 STM32H7_DMNGT_DR_ONLY, /* Regular data in DR only */ 123 STM32H7_DMNGT_DMA_ONESHOT, /* DMA one shot mode */ 124 STM32H7_DMNGT_DFSDM, /* DFSDM mode */ 125 STM32H7_DMNGT_DMA_CIRC, /* DMA circular mode */ 126 }; 127 128 /* STM32H7_ADC_CALFACT - bit fields */ 129 #define STM32H7_CALFACT_D_SHIFT 16 130 #define STM32H7_CALFACT_D_MASK GENMASK(26, 16) 131 #define STM32H7_CALFACT_S_SHIFT 0 132 #define STM32H7_CALFACT_S_MASK GENMASK(10, 0) 133 134 /* STM32H7_ADC_CALFACT2 - bit fields */ 135 #define STM32H7_LINCALFACT_SHIFT 0 136 #define STM32H7_LINCALFACT_MASK GENMASK(29, 0) 137 138 /* Number of linear calibration shadow registers / LINCALRDYW control bits */ 139 #define STM32H7_LINCALFACT_NUM 6 140 141 /* BOOST bit must be set on STM32H7 when ADC clock is above 20MHz */ 142 #define STM32H7_BOOST_CLKRATE 20000000UL 143 144 #define STM32_ADC_CH_MAX 20 /* max number of channels */ 145 #define STM32_ADC_CH_SZ 10 /* max channel name size */ 146 #define STM32_ADC_MAX_SQ 16 /* SQ1..SQ16 */ 147 #define STM32_ADC_MAX_SMP 7 /* SMPx range is [0..7] */ 148 #define STM32_ADC_TIMEOUT_US 100000 149 #define STM32_ADC_TIMEOUT (msecs_to_jiffies(STM32_ADC_TIMEOUT_US / 1000)) 150 151 #define STM32_DMA_BUFFER_SIZE PAGE_SIZE 152 153 /* External trigger enable */ 154 enum stm32_adc_exten { 155 STM32_EXTEN_SWTRIG, 156 STM32_EXTEN_HWTRIG_RISING_EDGE, 157 STM32_EXTEN_HWTRIG_FALLING_EDGE, 158 STM32_EXTEN_HWTRIG_BOTH_EDGES, 159 }; 160 161 /* extsel - trigger mux selection value */ 162 enum stm32_adc_extsel { 163 STM32_EXT0, 164 STM32_EXT1, 165 STM32_EXT2, 166 STM32_EXT3, 167 STM32_EXT4, 168 STM32_EXT5, 169 STM32_EXT6, 170 STM32_EXT7, 171 STM32_EXT8, 172 STM32_EXT9, 173 STM32_EXT10, 174 STM32_EXT11, 175 STM32_EXT12, 176 STM32_EXT13, 177 STM32_EXT14, 178 STM32_EXT15, 179 STM32_EXT16, 180 STM32_EXT17, 181 STM32_EXT18, 182 STM32_EXT19, 183 STM32_EXT20, 184 }; 185 186 /** 187 * struct stm32_adc_trig_info - ADC trigger info 188 * @name: name of the trigger, corresponding to its source 189 * @extsel: trigger selection 190 */ 191 struct stm32_adc_trig_info { 192 const char *name; 193 enum stm32_adc_extsel extsel; 194 }; 195 196 /** 197 * struct stm32_adc_calib - optional adc calibration data 198 * @calfact_s: Calibration offset for single ended channels 199 * @calfact_d: Calibration offset in differential 200 * @lincalfact: Linearity calibration factor 201 */ 202 struct stm32_adc_calib { 203 u32 calfact_s; 204 u32 calfact_d; 205 u32 lincalfact[STM32H7_LINCALFACT_NUM]; 206 }; 207 208 /** 209 * stm32_adc_regs - stm32 ADC misc registers & bitfield desc 210 * @reg: register offset 211 * @mask: bitfield mask 212 * @shift: left shift 213 */ 214 struct stm32_adc_regs { 215 int reg; 216 int mask; 217 int shift; 218 }; 219 220 /** 221 * stm32_adc_regspec - stm32 registers definition, compatible dependent data 222 * @dr: data register offset 223 * @ier_eoc: interrupt enable register & eocie bitfield 224 * @isr_eoc: interrupt status register & eoc bitfield 225 * @sqr: reference to sequence registers array 226 * @exten: trigger control register & bitfield 227 * @extsel: trigger selection register & bitfield 228 * @res: resolution selection register & bitfield 229 * @smpr: smpr1 & smpr2 registers offset array 230 * @smp_bits: smpr1 & smpr2 index and bitfields 231 */ 232 struct stm32_adc_regspec { 233 const u32 dr; 234 const struct stm32_adc_regs ier_eoc; 235 const struct stm32_adc_regs isr_eoc; 236 const struct stm32_adc_regs *sqr; 237 const struct stm32_adc_regs exten; 238 const struct stm32_adc_regs extsel; 239 const struct stm32_adc_regs res; 240 const u32 smpr[2]; 241 const struct stm32_adc_regs *smp_bits; 242 }; 243 244 struct stm32_adc; 245 246 /** 247 * stm32_adc_cfg - stm32 compatible configuration data 248 * @regs: registers descriptions 249 * @adc_info: per instance input channels definitions 250 * @trigs: external trigger sources 251 * @clk_required: clock is required 252 * @selfcalib: optional routine for self-calibration 253 * @prepare: optional prepare routine (power-up, enable) 254 * @start_conv: routine to start conversions 255 * @stop_conv: routine to stop conversions 256 * @unprepare: optional unprepare routine (disable, power-down) 257 * @smp_cycles: programmable sampling time (ADC clock cycles) 258 */ 259 struct stm32_adc_cfg { 260 const struct stm32_adc_regspec *regs; 261 const struct stm32_adc_info *adc_info; 262 struct stm32_adc_trig_info *trigs; 263 bool clk_required; 264 int (*selfcalib)(struct stm32_adc *); 265 int (*prepare)(struct stm32_adc *); 266 void (*start_conv)(struct stm32_adc *, bool dma); 267 void (*stop_conv)(struct stm32_adc *); 268 void (*unprepare)(struct stm32_adc *); 269 const unsigned int *smp_cycles; 270 }; 271 272 /** 273 * struct stm32_adc - private data of each ADC IIO instance 274 * @common: reference to ADC block common data 275 * @offset: ADC instance register offset in ADC block 276 * @cfg: compatible configuration data 277 * @completion: end of single conversion completion 278 * @buffer: data buffer 279 * @clk: clock for this adc instance 280 * @irq: interrupt for this adc instance 281 * @lock: spinlock 282 * @bufi: data buffer index 283 * @num_conv: expected number of scan conversions 284 * @res: data resolution (e.g. RES bitfield value) 285 * @trigger_polarity: external trigger polarity (e.g. exten) 286 * @dma_chan: dma channel 287 * @rx_buf: dma rx buffer cpu address 288 * @rx_dma_buf: dma rx buffer bus address 289 * @rx_buf_sz: dma rx buffer size 290 * @difsel bitmask to set single-ended/differential channel 291 * @pcsel bitmask to preselect channels on some devices 292 * @smpr_val: sampling time settings (e.g. smpr1 / smpr2) 293 * @cal: optional calibration data on some devices 294 * @chan_name: channel name array 295 */ 296 struct stm32_adc { 297 struct stm32_adc_common *common; 298 u32 offset; 299 const struct stm32_adc_cfg *cfg; 300 struct completion completion; 301 u16 buffer[STM32_ADC_MAX_SQ]; 302 struct clk *clk; 303 int irq; 304 spinlock_t lock; /* interrupt lock */ 305 unsigned int bufi; 306 unsigned int num_conv; 307 u32 res; 308 u32 trigger_polarity; 309 struct dma_chan *dma_chan; 310 u8 *rx_buf; 311 dma_addr_t rx_dma_buf; 312 unsigned int rx_buf_sz; 313 u32 difsel; 314 u32 pcsel; 315 u32 smpr_val[2]; 316 struct stm32_adc_calib cal; 317 char chan_name[STM32_ADC_CH_MAX][STM32_ADC_CH_SZ]; 318 }; 319 320 struct stm32_adc_diff_channel { 321 u32 vinp; 322 u32 vinn; 323 }; 324 325 /** 326 * struct stm32_adc_info - stm32 ADC, per instance config data 327 * @max_channels: Number of channels 328 * @resolutions: available resolutions 329 * @num_res: number of available resolutions 330 */ 331 struct stm32_adc_info { 332 int max_channels; 333 const unsigned int *resolutions; 334 const unsigned int num_res; 335 }; 336 337 static const unsigned int stm32f4_adc_resolutions[] = { 338 /* sorted values so the index matches RES[1:0] in STM32F4_ADC_CR1 */ 339 12, 10, 8, 6, 340 }; 341 342 /* stm32f4 can have up to 16 channels */ 343 static const struct stm32_adc_info stm32f4_adc_info = { 344 .max_channels = 16, 345 .resolutions = stm32f4_adc_resolutions, 346 .num_res = ARRAY_SIZE(stm32f4_adc_resolutions), 347 }; 348 349 static const unsigned int stm32h7_adc_resolutions[] = { 350 /* sorted values so the index matches RES[2:0] in STM32H7_ADC_CFGR */ 351 16, 14, 12, 10, 8, 352 }; 353 354 /* stm32h7 can have up to 20 channels */ 355 static const struct stm32_adc_info stm32h7_adc_info = { 356 .max_channels = STM32_ADC_CH_MAX, 357 .resolutions = stm32h7_adc_resolutions, 358 .num_res = ARRAY_SIZE(stm32h7_adc_resolutions), 359 }; 360 361 /** 362 * stm32f4_sq - describe regular sequence registers 363 * - L: sequence len (register & bit field) 364 * - SQ1..SQ16: sequence entries (register & bit field) 365 */ 366 static const struct stm32_adc_regs stm32f4_sq[STM32_ADC_MAX_SQ + 1] = { 367 /* L: len bit field description to be kept as first element */ 368 { STM32F4_ADC_SQR1, GENMASK(23, 20), 20 }, 369 /* SQ1..SQ16 registers & bit fields (reg, mask, shift) */ 370 { STM32F4_ADC_SQR3, GENMASK(4, 0), 0 }, 371 { STM32F4_ADC_SQR3, GENMASK(9, 5), 5 }, 372 { STM32F4_ADC_SQR3, GENMASK(14, 10), 10 }, 373 { STM32F4_ADC_SQR3, GENMASK(19, 15), 15 }, 374 { STM32F4_ADC_SQR3, GENMASK(24, 20), 20 }, 375 { STM32F4_ADC_SQR3, GENMASK(29, 25), 25 }, 376 { STM32F4_ADC_SQR2, GENMASK(4, 0), 0 }, 377 { STM32F4_ADC_SQR2, GENMASK(9, 5), 5 }, 378 { STM32F4_ADC_SQR2, GENMASK(14, 10), 10 }, 379 { STM32F4_ADC_SQR2, GENMASK(19, 15), 15 }, 380 { STM32F4_ADC_SQR2, GENMASK(24, 20), 20 }, 381 { STM32F4_ADC_SQR2, GENMASK(29, 25), 25 }, 382 { STM32F4_ADC_SQR1, GENMASK(4, 0), 0 }, 383 { STM32F4_ADC_SQR1, GENMASK(9, 5), 5 }, 384 { STM32F4_ADC_SQR1, GENMASK(14, 10), 10 }, 385 { STM32F4_ADC_SQR1, GENMASK(19, 15), 15 }, 386 }; 387 388 /* STM32F4 external trigger sources for all instances */ 389 static struct stm32_adc_trig_info stm32f4_adc_trigs[] = { 390 { TIM1_CH1, STM32_EXT0 }, 391 { TIM1_CH2, STM32_EXT1 }, 392 { TIM1_CH3, STM32_EXT2 }, 393 { TIM2_CH2, STM32_EXT3 }, 394 { TIM2_CH3, STM32_EXT4 }, 395 { TIM2_CH4, STM32_EXT5 }, 396 { TIM2_TRGO, STM32_EXT6 }, 397 { TIM3_CH1, STM32_EXT7 }, 398 { TIM3_TRGO, STM32_EXT8 }, 399 { TIM4_CH4, STM32_EXT9 }, 400 { TIM5_CH1, STM32_EXT10 }, 401 { TIM5_CH2, STM32_EXT11 }, 402 { TIM5_CH3, STM32_EXT12 }, 403 { TIM8_CH1, STM32_EXT13 }, 404 { TIM8_TRGO, STM32_EXT14 }, 405 {}, /* sentinel */ 406 }; 407 408 /** 409 * stm32f4_smp_bits[] - describe sampling time register index & bit fields 410 * Sorted so it can be indexed by channel number. 411 */ 412 static const struct stm32_adc_regs stm32f4_smp_bits[] = { 413 /* STM32F4_ADC_SMPR2: smpr[] index, mask, shift for SMP0 to SMP9 */ 414 { 1, GENMASK(2, 0), 0 }, 415 { 1, GENMASK(5, 3), 3 }, 416 { 1, GENMASK(8, 6), 6 }, 417 { 1, GENMASK(11, 9), 9 }, 418 { 1, GENMASK(14, 12), 12 }, 419 { 1, GENMASK(17, 15), 15 }, 420 { 1, GENMASK(20, 18), 18 }, 421 { 1, GENMASK(23, 21), 21 }, 422 { 1, GENMASK(26, 24), 24 }, 423 { 1, GENMASK(29, 27), 27 }, 424 /* STM32F4_ADC_SMPR1, smpr[] index, mask, shift for SMP10 to SMP18 */ 425 { 0, GENMASK(2, 0), 0 }, 426 { 0, GENMASK(5, 3), 3 }, 427 { 0, GENMASK(8, 6), 6 }, 428 { 0, GENMASK(11, 9), 9 }, 429 { 0, GENMASK(14, 12), 12 }, 430 { 0, GENMASK(17, 15), 15 }, 431 { 0, GENMASK(20, 18), 18 }, 432 { 0, GENMASK(23, 21), 21 }, 433 { 0, GENMASK(26, 24), 24 }, 434 }; 435 436 /* STM32F4 programmable sampling time (ADC clock cycles) */ 437 static const unsigned int stm32f4_adc_smp_cycles[STM32_ADC_MAX_SMP + 1] = { 438 3, 15, 28, 56, 84, 112, 144, 480, 439 }; 440 441 static const struct stm32_adc_regspec stm32f4_adc_regspec = { 442 .dr = STM32F4_ADC_DR, 443 .ier_eoc = { STM32F4_ADC_CR1, STM32F4_EOCIE }, 444 .isr_eoc = { STM32F4_ADC_SR, STM32F4_EOC }, 445 .sqr = stm32f4_sq, 446 .exten = { STM32F4_ADC_CR2, STM32F4_EXTEN_MASK, STM32F4_EXTEN_SHIFT }, 447 .extsel = { STM32F4_ADC_CR2, STM32F4_EXTSEL_MASK, 448 STM32F4_EXTSEL_SHIFT }, 449 .res = { STM32F4_ADC_CR1, STM32F4_RES_MASK, STM32F4_RES_SHIFT }, 450 .smpr = { STM32F4_ADC_SMPR1, STM32F4_ADC_SMPR2 }, 451 .smp_bits = stm32f4_smp_bits, 452 }; 453 454 static const struct stm32_adc_regs stm32h7_sq[STM32_ADC_MAX_SQ + 1] = { 455 /* L: len bit field description to be kept as first element */ 456 { STM32H7_ADC_SQR1, GENMASK(3, 0), 0 }, 457 /* SQ1..SQ16 registers & bit fields (reg, mask, shift) */ 458 { STM32H7_ADC_SQR1, GENMASK(10, 6), 6 }, 459 { STM32H7_ADC_SQR1, GENMASK(16, 12), 12 }, 460 { STM32H7_ADC_SQR1, GENMASK(22, 18), 18 }, 461 { STM32H7_ADC_SQR1, GENMASK(28, 24), 24 }, 462 { STM32H7_ADC_SQR2, GENMASK(4, 0), 0 }, 463 { STM32H7_ADC_SQR2, GENMASK(10, 6), 6 }, 464 { STM32H7_ADC_SQR2, GENMASK(16, 12), 12 }, 465 { STM32H7_ADC_SQR2, GENMASK(22, 18), 18 }, 466 { STM32H7_ADC_SQR2, GENMASK(28, 24), 24 }, 467 { STM32H7_ADC_SQR3, GENMASK(4, 0), 0 }, 468 { STM32H7_ADC_SQR3, GENMASK(10, 6), 6 }, 469 { STM32H7_ADC_SQR3, GENMASK(16, 12), 12 }, 470 { STM32H7_ADC_SQR3, GENMASK(22, 18), 18 }, 471 { STM32H7_ADC_SQR3, GENMASK(28, 24), 24 }, 472 { STM32H7_ADC_SQR4, GENMASK(4, 0), 0 }, 473 { STM32H7_ADC_SQR4, GENMASK(10, 6), 6 }, 474 }; 475 476 /* STM32H7 external trigger sources for all instances */ 477 static struct stm32_adc_trig_info stm32h7_adc_trigs[] = { 478 { TIM1_CH1, STM32_EXT0 }, 479 { TIM1_CH2, STM32_EXT1 }, 480 { TIM1_CH3, STM32_EXT2 }, 481 { TIM2_CH2, STM32_EXT3 }, 482 { TIM3_TRGO, STM32_EXT4 }, 483 { TIM4_CH4, STM32_EXT5 }, 484 { TIM8_TRGO, STM32_EXT7 }, 485 { TIM8_TRGO2, STM32_EXT8 }, 486 { TIM1_TRGO, STM32_EXT9 }, 487 { TIM1_TRGO2, STM32_EXT10 }, 488 { TIM2_TRGO, STM32_EXT11 }, 489 { TIM4_TRGO, STM32_EXT12 }, 490 { TIM6_TRGO, STM32_EXT13 }, 491 { TIM15_TRGO, STM32_EXT14 }, 492 { TIM3_CH4, STM32_EXT15 }, 493 { LPTIM1_OUT, STM32_EXT18 }, 494 { LPTIM2_OUT, STM32_EXT19 }, 495 { LPTIM3_OUT, STM32_EXT20 }, 496 {}, 497 }; 498 499 /** 500 * stm32h7_smp_bits - describe sampling time register index & bit fields 501 * Sorted so it can be indexed by channel number. 502 */ 503 static const struct stm32_adc_regs stm32h7_smp_bits[] = { 504 /* STM32H7_ADC_SMPR1, smpr[] index, mask, shift for SMP0 to SMP9 */ 505 { 0, GENMASK(2, 0), 0 }, 506 { 0, GENMASK(5, 3), 3 }, 507 { 0, GENMASK(8, 6), 6 }, 508 { 0, GENMASK(11, 9), 9 }, 509 { 0, GENMASK(14, 12), 12 }, 510 { 0, GENMASK(17, 15), 15 }, 511 { 0, GENMASK(20, 18), 18 }, 512 { 0, GENMASK(23, 21), 21 }, 513 { 0, GENMASK(26, 24), 24 }, 514 { 0, GENMASK(29, 27), 27 }, 515 /* STM32H7_ADC_SMPR2, smpr[] index, mask, shift for SMP10 to SMP19 */ 516 { 1, GENMASK(2, 0), 0 }, 517 { 1, GENMASK(5, 3), 3 }, 518 { 1, GENMASK(8, 6), 6 }, 519 { 1, GENMASK(11, 9), 9 }, 520 { 1, GENMASK(14, 12), 12 }, 521 { 1, GENMASK(17, 15), 15 }, 522 { 1, GENMASK(20, 18), 18 }, 523 { 1, GENMASK(23, 21), 21 }, 524 { 1, GENMASK(26, 24), 24 }, 525 { 1, GENMASK(29, 27), 27 }, 526 }; 527 528 /* STM32H7 programmable sampling time (ADC clock cycles, rounded down) */ 529 static const unsigned int stm32h7_adc_smp_cycles[STM32_ADC_MAX_SMP + 1] = { 530 1, 2, 8, 16, 32, 64, 387, 810, 531 }; 532 533 static const struct stm32_adc_regspec stm32h7_adc_regspec = { 534 .dr = STM32H7_ADC_DR, 535 .ier_eoc = { STM32H7_ADC_IER, STM32H7_EOCIE }, 536 .isr_eoc = { STM32H7_ADC_ISR, STM32H7_EOC }, 537 .sqr = stm32h7_sq, 538 .exten = { STM32H7_ADC_CFGR, STM32H7_EXTEN_MASK, STM32H7_EXTEN_SHIFT }, 539 .extsel = { STM32H7_ADC_CFGR, STM32H7_EXTSEL_MASK, 540 STM32H7_EXTSEL_SHIFT }, 541 .res = { STM32H7_ADC_CFGR, STM32H7_RES_MASK, STM32H7_RES_SHIFT }, 542 .smpr = { STM32H7_ADC_SMPR1, STM32H7_ADC_SMPR2 }, 543 .smp_bits = stm32h7_smp_bits, 544 }; 545 546 /** 547 * STM32 ADC registers access routines 548 * @adc: stm32 adc instance 549 * @reg: reg offset in adc instance 550 * 551 * Note: All instances share same base, with 0x0, 0x100 or 0x200 offset resp. 552 * for adc1, adc2 and adc3. 553 */ 554 static u32 stm32_adc_readl(struct stm32_adc *adc, u32 reg) 555 { 556 return readl_relaxed(adc->common->base + adc->offset + reg); 557 } 558 559 #define stm32_adc_readl_addr(addr) stm32_adc_readl(adc, addr) 560 561 #define stm32_adc_readl_poll_timeout(reg, val, cond, sleep_us, timeout_us) \ 562 readx_poll_timeout(stm32_adc_readl_addr, reg, val, \ 563 cond, sleep_us, timeout_us) 564 565 static u16 stm32_adc_readw(struct stm32_adc *adc, u32 reg) 566 { 567 return readw_relaxed(adc->common->base + adc->offset + reg); 568 } 569 570 static void stm32_adc_writel(struct stm32_adc *adc, u32 reg, u32 val) 571 { 572 writel_relaxed(val, adc->common->base + adc->offset + reg); 573 } 574 575 static void stm32_adc_set_bits(struct stm32_adc *adc, u32 reg, u32 bits) 576 { 577 unsigned long flags; 578 579 spin_lock_irqsave(&adc->lock, flags); 580 stm32_adc_writel(adc, reg, stm32_adc_readl(adc, reg) | bits); 581 spin_unlock_irqrestore(&adc->lock, flags); 582 } 583 584 static void stm32_adc_clr_bits(struct stm32_adc *adc, u32 reg, u32 bits) 585 { 586 unsigned long flags; 587 588 spin_lock_irqsave(&adc->lock, flags); 589 stm32_adc_writel(adc, reg, stm32_adc_readl(adc, reg) & ~bits); 590 spin_unlock_irqrestore(&adc->lock, flags); 591 } 592 593 /** 594 * stm32_adc_conv_irq_enable() - Enable end of conversion interrupt 595 * @adc: stm32 adc instance 596 */ 597 static void stm32_adc_conv_irq_enable(struct stm32_adc *adc) 598 { 599 stm32_adc_set_bits(adc, adc->cfg->regs->ier_eoc.reg, 600 adc->cfg->regs->ier_eoc.mask); 601 }; 602 603 /** 604 * stm32_adc_conv_irq_disable() - Disable end of conversion interrupt 605 * @adc: stm32 adc instance 606 */ 607 static void stm32_adc_conv_irq_disable(struct stm32_adc *adc) 608 { 609 stm32_adc_clr_bits(adc, adc->cfg->regs->ier_eoc.reg, 610 adc->cfg->regs->ier_eoc.mask); 611 } 612 613 static void stm32_adc_set_res(struct stm32_adc *adc) 614 { 615 const struct stm32_adc_regs *res = &adc->cfg->regs->res; 616 u32 val; 617 618 val = stm32_adc_readl(adc, res->reg); 619 val = (val & ~res->mask) | (adc->res << res->shift); 620 stm32_adc_writel(adc, res->reg, val); 621 } 622 623 /** 624 * stm32f4_adc_start_conv() - Start conversions for regular channels. 625 * @adc: stm32 adc instance 626 * @dma: use dma to transfer conversion result 627 * 628 * Start conversions for regular channels. 629 * Also take care of normal or DMA mode. Circular DMA may be used for regular 630 * conversions, in IIO buffer modes. Otherwise, use ADC interrupt with direct 631 * DR read instead (e.g. read_raw, or triggered buffer mode without DMA). 632 */ 633 static void stm32f4_adc_start_conv(struct stm32_adc *adc, bool dma) 634 { 635 stm32_adc_set_bits(adc, STM32F4_ADC_CR1, STM32F4_SCAN); 636 637 if (dma) 638 stm32_adc_set_bits(adc, STM32F4_ADC_CR2, 639 STM32F4_DMA | STM32F4_DDS); 640 641 stm32_adc_set_bits(adc, STM32F4_ADC_CR2, STM32F4_EOCS | STM32F4_ADON); 642 643 /* Wait for Power-up time (tSTAB from datasheet) */ 644 usleep_range(2, 3); 645 646 /* Software start ? (e.g. trigger detection disabled ?) */ 647 if (!(stm32_adc_readl(adc, STM32F4_ADC_CR2) & STM32F4_EXTEN_MASK)) 648 stm32_adc_set_bits(adc, STM32F4_ADC_CR2, STM32F4_SWSTART); 649 } 650 651 static void stm32f4_adc_stop_conv(struct stm32_adc *adc) 652 { 653 stm32_adc_clr_bits(adc, STM32F4_ADC_CR2, STM32F4_EXTEN_MASK); 654 stm32_adc_clr_bits(adc, STM32F4_ADC_SR, STM32F4_STRT); 655 656 stm32_adc_clr_bits(adc, STM32F4_ADC_CR1, STM32F4_SCAN); 657 stm32_adc_clr_bits(adc, STM32F4_ADC_CR2, 658 STM32F4_ADON | STM32F4_DMA | STM32F4_DDS); 659 } 660 661 static void stm32h7_adc_start_conv(struct stm32_adc *adc, bool dma) 662 { 663 enum stm32h7_adc_dmngt dmngt; 664 unsigned long flags; 665 u32 val; 666 667 if (dma) 668 dmngt = STM32H7_DMNGT_DMA_CIRC; 669 else 670 dmngt = STM32H7_DMNGT_DR_ONLY; 671 672 spin_lock_irqsave(&adc->lock, flags); 673 val = stm32_adc_readl(adc, STM32H7_ADC_CFGR); 674 val = (val & ~STM32H7_DMNGT_MASK) | (dmngt << STM32H7_DMNGT_SHIFT); 675 stm32_adc_writel(adc, STM32H7_ADC_CFGR, val); 676 spin_unlock_irqrestore(&adc->lock, flags); 677 678 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADSTART); 679 } 680 681 static void stm32h7_adc_stop_conv(struct stm32_adc *adc) 682 { 683 struct iio_dev *indio_dev = iio_priv_to_dev(adc); 684 int ret; 685 u32 val; 686 687 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADSTP); 688 689 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val, 690 !(val & (STM32H7_ADSTART)), 691 100, STM32_ADC_TIMEOUT_US); 692 if (ret) 693 dev_warn(&indio_dev->dev, "stop failed\n"); 694 695 stm32_adc_clr_bits(adc, STM32H7_ADC_CFGR, STM32H7_DMNGT_MASK); 696 } 697 698 static void stm32h7_adc_exit_pwr_down(struct stm32_adc *adc) 699 { 700 /* Exit deep power down, then enable ADC voltage regulator */ 701 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_DEEPPWD); 702 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADVREGEN); 703 704 if (adc->common->rate > STM32H7_BOOST_CLKRATE) 705 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_BOOST); 706 707 /* Wait for startup time */ 708 usleep_range(10, 20); 709 } 710 711 static void stm32h7_adc_enter_pwr_down(struct stm32_adc *adc) 712 { 713 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_BOOST); 714 715 /* Setting DEEPPWD disables ADC vreg and clears ADVREGEN */ 716 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_DEEPPWD); 717 } 718 719 static int stm32h7_adc_enable(struct stm32_adc *adc) 720 { 721 struct iio_dev *indio_dev = iio_priv_to_dev(adc); 722 int ret; 723 u32 val; 724 725 /* Clear ADRDY by writing one, then enable ADC */ 726 stm32_adc_set_bits(adc, STM32H7_ADC_ISR, STM32H7_ADRDY); 727 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADEN); 728 729 /* Poll for ADRDY to be set (after adc startup time) */ 730 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_ISR, val, 731 val & STM32H7_ADRDY, 732 100, STM32_ADC_TIMEOUT_US); 733 if (ret) { 734 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_ADEN); 735 dev_err(&indio_dev->dev, "Failed to enable ADC\n"); 736 } 737 738 return ret; 739 } 740 741 static void stm32h7_adc_disable(struct stm32_adc *adc) 742 { 743 struct iio_dev *indio_dev = iio_priv_to_dev(adc); 744 int ret; 745 u32 val; 746 747 /* Disable ADC and wait until it's effectively disabled */ 748 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADDIS); 749 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val, 750 !(val & STM32H7_ADEN), 100, 751 STM32_ADC_TIMEOUT_US); 752 if (ret) 753 dev_warn(&indio_dev->dev, "Failed to disable\n"); 754 } 755 756 /** 757 * stm32h7_adc_read_selfcalib() - read calibration shadow regs, save result 758 * @adc: stm32 adc instance 759 */ 760 static int stm32h7_adc_read_selfcalib(struct stm32_adc *adc) 761 { 762 struct iio_dev *indio_dev = iio_priv_to_dev(adc); 763 int i, ret; 764 u32 lincalrdyw_mask, val; 765 766 /* Enable adc so LINCALRDYW1..6 bits are writable */ 767 ret = stm32h7_adc_enable(adc); 768 if (ret) 769 return ret; 770 771 /* Read linearity calibration */ 772 lincalrdyw_mask = STM32H7_LINCALRDYW6; 773 for (i = STM32H7_LINCALFACT_NUM - 1; i >= 0; i--) { 774 /* Clear STM32H7_LINCALRDYW[6..1]: transfer calib to CALFACT2 */ 775 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, lincalrdyw_mask); 776 777 /* Poll: wait calib data to be ready in CALFACT2 register */ 778 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val, 779 !(val & lincalrdyw_mask), 780 100, STM32_ADC_TIMEOUT_US); 781 if (ret) { 782 dev_err(&indio_dev->dev, "Failed to read calfact\n"); 783 goto disable; 784 } 785 786 val = stm32_adc_readl(adc, STM32H7_ADC_CALFACT2); 787 adc->cal.lincalfact[i] = (val & STM32H7_LINCALFACT_MASK); 788 adc->cal.lincalfact[i] >>= STM32H7_LINCALFACT_SHIFT; 789 790 lincalrdyw_mask >>= 1; 791 } 792 793 /* Read offset calibration */ 794 val = stm32_adc_readl(adc, STM32H7_ADC_CALFACT); 795 adc->cal.calfact_s = (val & STM32H7_CALFACT_S_MASK); 796 adc->cal.calfact_s >>= STM32H7_CALFACT_S_SHIFT; 797 adc->cal.calfact_d = (val & STM32H7_CALFACT_D_MASK); 798 adc->cal.calfact_d >>= STM32H7_CALFACT_D_SHIFT; 799 800 disable: 801 stm32h7_adc_disable(adc); 802 803 return ret; 804 } 805 806 /** 807 * stm32h7_adc_restore_selfcalib() - Restore saved self-calibration result 808 * @adc: stm32 adc instance 809 * Note: ADC must be enabled, with no on-going conversions. 810 */ 811 static int stm32h7_adc_restore_selfcalib(struct stm32_adc *adc) 812 { 813 struct iio_dev *indio_dev = iio_priv_to_dev(adc); 814 int i, ret; 815 u32 lincalrdyw_mask, val; 816 817 val = (adc->cal.calfact_s << STM32H7_CALFACT_S_SHIFT) | 818 (adc->cal.calfact_d << STM32H7_CALFACT_D_SHIFT); 819 stm32_adc_writel(adc, STM32H7_ADC_CALFACT, val); 820 821 lincalrdyw_mask = STM32H7_LINCALRDYW6; 822 for (i = STM32H7_LINCALFACT_NUM - 1; i >= 0; i--) { 823 /* 824 * Write saved calibration data to shadow registers: 825 * Write CALFACT2, and set LINCALRDYW[6..1] bit to trigger 826 * data write. Then poll to wait for complete transfer. 827 */ 828 val = adc->cal.lincalfact[i] << STM32H7_LINCALFACT_SHIFT; 829 stm32_adc_writel(adc, STM32H7_ADC_CALFACT2, val); 830 stm32_adc_set_bits(adc, STM32H7_ADC_CR, lincalrdyw_mask); 831 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val, 832 val & lincalrdyw_mask, 833 100, STM32_ADC_TIMEOUT_US); 834 if (ret) { 835 dev_err(&indio_dev->dev, "Failed to write calfact\n"); 836 return ret; 837 } 838 839 /* 840 * Read back calibration data, has two effects: 841 * - It ensures bits LINCALRDYW[6..1] are kept cleared 842 * for next time calibration needs to be restored. 843 * - BTW, bit clear triggers a read, then check data has been 844 * correctly written. 845 */ 846 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, lincalrdyw_mask); 847 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val, 848 !(val & lincalrdyw_mask), 849 100, STM32_ADC_TIMEOUT_US); 850 if (ret) { 851 dev_err(&indio_dev->dev, "Failed to read calfact\n"); 852 return ret; 853 } 854 val = stm32_adc_readl(adc, STM32H7_ADC_CALFACT2); 855 if (val != adc->cal.lincalfact[i] << STM32H7_LINCALFACT_SHIFT) { 856 dev_err(&indio_dev->dev, "calfact not consistent\n"); 857 return -EIO; 858 } 859 860 lincalrdyw_mask >>= 1; 861 } 862 863 return 0; 864 } 865 866 /** 867 * Fixed timeout value for ADC calibration. 868 * worst cases: 869 * - low clock frequency 870 * - maximum prescalers 871 * Calibration requires: 872 * - 131,072 ADC clock cycle for the linear calibration 873 * - 20 ADC clock cycle for the offset calibration 874 * 875 * Set to 100ms for now 876 */ 877 #define STM32H7_ADC_CALIB_TIMEOUT_US 100000 878 879 /** 880 * stm32h7_adc_selfcalib() - Procedure to calibrate ADC (from power down) 881 * @adc: stm32 adc instance 882 * Exit from power down, calibrate ADC, then return to power down. 883 */ 884 static int stm32h7_adc_selfcalib(struct stm32_adc *adc) 885 { 886 struct iio_dev *indio_dev = iio_priv_to_dev(adc); 887 int ret; 888 u32 val; 889 890 stm32h7_adc_exit_pwr_down(adc); 891 892 /* 893 * Select calibration mode: 894 * - Offset calibration for single ended inputs 895 * - No linearity calibration (do it later, before reading it) 896 */ 897 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_ADCALDIF); 898 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_ADCALLIN); 899 900 /* Start calibration, then wait for completion */ 901 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADCAL); 902 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val, 903 !(val & STM32H7_ADCAL), 100, 904 STM32H7_ADC_CALIB_TIMEOUT_US); 905 if (ret) { 906 dev_err(&indio_dev->dev, "calibration failed\n"); 907 goto pwr_dwn; 908 } 909 910 /* 911 * Select calibration mode, then start calibration: 912 * - Offset calibration for differential input 913 * - Linearity calibration (needs to be done only once for single/diff) 914 * will run simultaneously with offset calibration. 915 */ 916 stm32_adc_set_bits(adc, STM32H7_ADC_CR, 917 STM32H7_ADCALDIF | STM32H7_ADCALLIN); 918 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADCAL); 919 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val, 920 !(val & STM32H7_ADCAL), 100, 921 STM32H7_ADC_CALIB_TIMEOUT_US); 922 if (ret) { 923 dev_err(&indio_dev->dev, "calibration failed\n"); 924 goto pwr_dwn; 925 } 926 927 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, 928 STM32H7_ADCALDIF | STM32H7_ADCALLIN); 929 930 /* Read calibration result for future reference */ 931 ret = stm32h7_adc_read_selfcalib(adc); 932 933 pwr_dwn: 934 stm32h7_adc_enter_pwr_down(adc); 935 936 return ret; 937 } 938 939 /** 940 * stm32h7_adc_prepare() - Leave power down mode to enable ADC. 941 * @adc: stm32 adc instance 942 * Leave power down mode. 943 * Configure channels as single ended or differential before enabling ADC. 944 * Enable ADC. 945 * Restore calibration data. 946 * Pre-select channels that may be used in PCSEL (required by input MUX / IO): 947 * - Only one input is selected for single ended (e.g. 'vinp') 948 * - Two inputs are selected for differential channels (e.g. 'vinp' & 'vinn') 949 */ 950 static int stm32h7_adc_prepare(struct stm32_adc *adc) 951 { 952 int ret; 953 954 stm32h7_adc_exit_pwr_down(adc); 955 stm32_adc_writel(adc, STM32H7_ADC_DIFSEL, adc->difsel); 956 957 ret = stm32h7_adc_enable(adc); 958 if (ret) 959 goto pwr_dwn; 960 961 ret = stm32h7_adc_restore_selfcalib(adc); 962 if (ret) 963 goto disable; 964 965 stm32_adc_writel(adc, STM32H7_ADC_PCSEL, adc->pcsel); 966 967 return 0; 968 969 disable: 970 stm32h7_adc_disable(adc); 971 pwr_dwn: 972 stm32h7_adc_enter_pwr_down(adc); 973 974 return ret; 975 } 976 977 static void stm32h7_adc_unprepare(struct stm32_adc *adc) 978 { 979 stm32h7_adc_disable(adc); 980 stm32h7_adc_enter_pwr_down(adc); 981 } 982 983 /** 984 * stm32_adc_conf_scan_seq() - Build regular channels scan sequence 985 * @indio_dev: IIO device 986 * @scan_mask: channels to be converted 987 * 988 * Conversion sequence : 989 * Apply sampling time settings for all channels. 990 * Configure ADC scan sequence based on selected channels in scan_mask. 991 * Add channels to SQR registers, from scan_mask LSB to MSB, then 992 * program sequence len. 993 */ 994 static int stm32_adc_conf_scan_seq(struct iio_dev *indio_dev, 995 const unsigned long *scan_mask) 996 { 997 struct stm32_adc *adc = iio_priv(indio_dev); 998 const struct stm32_adc_regs *sqr = adc->cfg->regs->sqr; 999 const struct iio_chan_spec *chan; 1000 u32 val, bit; 1001 int i = 0; 1002 1003 /* Apply sampling time settings */ 1004 stm32_adc_writel(adc, adc->cfg->regs->smpr[0], adc->smpr_val[0]); 1005 stm32_adc_writel(adc, adc->cfg->regs->smpr[1], adc->smpr_val[1]); 1006 1007 for_each_set_bit(bit, scan_mask, indio_dev->masklength) { 1008 chan = indio_dev->channels + bit; 1009 /* 1010 * Assign one channel per SQ entry in regular 1011 * sequence, starting with SQ1. 1012 */ 1013 i++; 1014 if (i > STM32_ADC_MAX_SQ) 1015 return -EINVAL; 1016 1017 dev_dbg(&indio_dev->dev, "%s chan %d to SQ%d\n", 1018 __func__, chan->channel, i); 1019 1020 val = stm32_adc_readl(adc, sqr[i].reg); 1021 val &= ~sqr[i].mask; 1022 val |= chan->channel << sqr[i].shift; 1023 stm32_adc_writel(adc, sqr[i].reg, val); 1024 } 1025 1026 if (!i) 1027 return -EINVAL; 1028 1029 /* Sequence len */ 1030 val = stm32_adc_readl(adc, sqr[0].reg); 1031 val &= ~sqr[0].mask; 1032 val |= ((i - 1) << sqr[0].shift); 1033 stm32_adc_writel(adc, sqr[0].reg, val); 1034 1035 return 0; 1036 } 1037 1038 /** 1039 * stm32_adc_get_trig_extsel() - Get external trigger selection 1040 * @trig: trigger 1041 * 1042 * Returns trigger extsel value, if trig matches, -EINVAL otherwise. 1043 */ 1044 static int stm32_adc_get_trig_extsel(struct iio_dev *indio_dev, 1045 struct iio_trigger *trig) 1046 { 1047 struct stm32_adc *adc = iio_priv(indio_dev); 1048 int i; 1049 1050 /* lookup triggers registered by stm32 timer trigger driver */ 1051 for (i = 0; adc->cfg->trigs[i].name; i++) { 1052 /** 1053 * Checking both stm32 timer trigger type and trig name 1054 * should be safe against arbitrary trigger names. 1055 */ 1056 if ((is_stm32_timer_trigger(trig) || 1057 is_stm32_lptim_trigger(trig)) && 1058 !strcmp(adc->cfg->trigs[i].name, trig->name)) { 1059 return adc->cfg->trigs[i].extsel; 1060 } 1061 } 1062 1063 return -EINVAL; 1064 } 1065 1066 /** 1067 * stm32_adc_set_trig() - Set a regular trigger 1068 * @indio_dev: IIO device 1069 * @trig: IIO trigger 1070 * 1071 * Set trigger source/polarity (e.g. SW, or HW with polarity) : 1072 * - if HW trigger disabled (e.g. trig == NULL, conversion launched by sw) 1073 * - if HW trigger enabled, set source & polarity 1074 */ 1075 static int stm32_adc_set_trig(struct iio_dev *indio_dev, 1076 struct iio_trigger *trig) 1077 { 1078 struct stm32_adc *adc = iio_priv(indio_dev); 1079 u32 val, extsel = 0, exten = STM32_EXTEN_SWTRIG; 1080 unsigned long flags; 1081 int ret; 1082 1083 if (trig) { 1084 ret = stm32_adc_get_trig_extsel(indio_dev, trig); 1085 if (ret < 0) 1086 return ret; 1087 1088 /* set trigger source and polarity (default to rising edge) */ 1089 extsel = ret; 1090 exten = adc->trigger_polarity + STM32_EXTEN_HWTRIG_RISING_EDGE; 1091 } 1092 1093 spin_lock_irqsave(&adc->lock, flags); 1094 val = stm32_adc_readl(adc, adc->cfg->regs->exten.reg); 1095 val &= ~(adc->cfg->regs->exten.mask | adc->cfg->regs->extsel.mask); 1096 val |= exten << adc->cfg->regs->exten.shift; 1097 val |= extsel << adc->cfg->regs->extsel.shift; 1098 stm32_adc_writel(adc, adc->cfg->regs->exten.reg, val); 1099 spin_unlock_irqrestore(&adc->lock, flags); 1100 1101 return 0; 1102 } 1103 1104 static int stm32_adc_set_trig_pol(struct iio_dev *indio_dev, 1105 const struct iio_chan_spec *chan, 1106 unsigned int type) 1107 { 1108 struct stm32_adc *adc = iio_priv(indio_dev); 1109 1110 adc->trigger_polarity = type; 1111 1112 return 0; 1113 } 1114 1115 static int stm32_adc_get_trig_pol(struct iio_dev *indio_dev, 1116 const struct iio_chan_spec *chan) 1117 { 1118 struct stm32_adc *adc = iio_priv(indio_dev); 1119 1120 return adc->trigger_polarity; 1121 } 1122 1123 static const char * const stm32_trig_pol_items[] = { 1124 "rising-edge", "falling-edge", "both-edges", 1125 }; 1126 1127 static const struct iio_enum stm32_adc_trig_pol = { 1128 .items = stm32_trig_pol_items, 1129 .num_items = ARRAY_SIZE(stm32_trig_pol_items), 1130 .get = stm32_adc_get_trig_pol, 1131 .set = stm32_adc_set_trig_pol, 1132 }; 1133 1134 /** 1135 * stm32_adc_single_conv() - Performs a single conversion 1136 * @indio_dev: IIO device 1137 * @chan: IIO channel 1138 * @res: conversion result 1139 * 1140 * The function performs a single conversion on a given channel: 1141 * - Apply sampling time settings 1142 * - Program sequencer with one channel (e.g. in SQ1 with len = 1) 1143 * - Use SW trigger 1144 * - Start conversion, then wait for interrupt completion. 1145 */ 1146 static int stm32_adc_single_conv(struct iio_dev *indio_dev, 1147 const struct iio_chan_spec *chan, 1148 int *res) 1149 { 1150 struct stm32_adc *adc = iio_priv(indio_dev); 1151 const struct stm32_adc_regspec *regs = adc->cfg->regs; 1152 long timeout; 1153 u32 val; 1154 int ret; 1155 1156 reinit_completion(&adc->completion); 1157 1158 adc->bufi = 0; 1159 1160 if (adc->cfg->prepare) { 1161 ret = adc->cfg->prepare(adc); 1162 if (ret) 1163 return ret; 1164 } 1165 1166 /* Apply sampling time settings */ 1167 stm32_adc_writel(adc, regs->smpr[0], adc->smpr_val[0]); 1168 stm32_adc_writel(adc, regs->smpr[1], adc->smpr_val[1]); 1169 1170 /* Program chan number in regular sequence (SQ1) */ 1171 val = stm32_adc_readl(adc, regs->sqr[1].reg); 1172 val &= ~regs->sqr[1].mask; 1173 val |= chan->channel << regs->sqr[1].shift; 1174 stm32_adc_writel(adc, regs->sqr[1].reg, val); 1175 1176 /* Set regular sequence len (0 for 1 conversion) */ 1177 stm32_adc_clr_bits(adc, regs->sqr[0].reg, regs->sqr[0].mask); 1178 1179 /* Trigger detection disabled (conversion can be launched in SW) */ 1180 stm32_adc_clr_bits(adc, regs->exten.reg, regs->exten.mask); 1181 1182 stm32_adc_conv_irq_enable(adc); 1183 1184 adc->cfg->start_conv(adc, false); 1185 1186 timeout = wait_for_completion_interruptible_timeout( 1187 &adc->completion, STM32_ADC_TIMEOUT); 1188 if (timeout == 0) { 1189 ret = -ETIMEDOUT; 1190 } else if (timeout < 0) { 1191 ret = timeout; 1192 } else { 1193 *res = adc->buffer[0]; 1194 ret = IIO_VAL_INT; 1195 } 1196 1197 adc->cfg->stop_conv(adc); 1198 1199 stm32_adc_conv_irq_disable(adc); 1200 1201 if (adc->cfg->unprepare) 1202 adc->cfg->unprepare(adc); 1203 1204 return ret; 1205 } 1206 1207 static int stm32_adc_read_raw(struct iio_dev *indio_dev, 1208 struct iio_chan_spec const *chan, 1209 int *val, int *val2, long mask) 1210 { 1211 struct stm32_adc *adc = iio_priv(indio_dev); 1212 int ret; 1213 1214 switch (mask) { 1215 case IIO_CHAN_INFO_RAW: 1216 ret = iio_device_claim_direct_mode(indio_dev); 1217 if (ret) 1218 return ret; 1219 if (chan->type == IIO_VOLTAGE) 1220 ret = stm32_adc_single_conv(indio_dev, chan, val); 1221 else 1222 ret = -EINVAL; 1223 iio_device_release_direct_mode(indio_dev); 1224 return ret; 1225 1226 case IIO_CHAN_INFO_SCALE: 1227 if (chan->differential) { 1228 *val = adc->common->vref_mv * 2; 1229 *val2 = chan->scan_type.realbits; 1230 } else { 1231 *val = adc->common->vref_mv; 1232 *val2 = chan->scan_type.realbits; 1233 } 1234 return IIO_VAL_FRACTIONAL_LOG2; 1235 1236 case IIO_CHAN_INFO_OFFSET: 1237 if (chan->differential) 1238 /* ADC_full_scale / 2 */ 1239 *val = -((1 << chan->scan_type.realbits) / 2); 1240 else 1241 *val = 0; 1242 return IIO_VAL_INT; 1243 1244 default: 1245 return -EINVAL; 1246 } 1247 } 1248 1249 static irqreturn_t stm32_adc_isr(int irq, void *data) 1250 { 1251 struct stm32_adc *adc = data; 1252 struct iio_dev *indio_dev = iio_priv_to_dev(adc); 1253 const struct stm32_adc_regspec *regs = adc->cfg->regs; 1254 u32 status = stm32_adc_readl(adc, regs->isr_eoc.reg); 1255 1256 if (status & regs->isr_eoc.mask) { 1257 /* Reading DR also clears EOC status flag */ 1258 adc->buffer[adc->bufi] = stm32_adc_readw(adc, regs->dr); 1259 if (iio_buffer_enabled(indio_dev)) { 1260 adc->bufi++; 1261 if (adc->bufi >= adc->num_conv) { 1262 stm32_adc_conv_irq_disable(adc); 1263 iio_trigger_poll(indio_dev->trig); 1264 } 1265 } else { 1266 complete(&adc->completion); 1267 } 1268 return IRQ_HANDLED; 1269 } 1270 1271 return IRQ_NONE; 1272 } 1273 1274 /** 1275 * stm32_adc_validate_trigger() - validate trigger for stm32 adc 1276 * @indio_dev: IIO device 1277 * @trig: new trigger 1278 * 1279 * Returns: 0 if trig matches one of the triggers registered by stm32 adc 1280 * driver, -EINVAL otherwise. 1281 */ 1282 static int stm32_adc_validate_trigger(struct iio_dev *indio_dev, 1283 struct iio_trigger *trig) 1284 { 1285 return stm32_adc_get_trig_extsel(indio_dev, trig) < 0 ? -EINVAL : 0; 1286 } 1287 1288 static int stm32_adc_set_watermark(struct iio_dev *indio_dev, unsigned int val) 1289 { 1290 struct stm32_adc *adc = iio_priv(indio_dev); 1291 unsigned int watermark = STM32_DMA_BUFFER_SIZE / 2; 1292 unsigned int rx_buf_sz = STM32_DMA_BUFFER_SIZE; 1293 1294 /* 1295 * dma cyclic transfers are used, buffer is split into two periods. 1296 * There should be : 1297 * - always one buffer (period) dma is working on 1298 * - one buffer (period) driver can push with iio_trigger_poll(). 1299 */ 1300 watermark = min(watermark, val * (unsigned)(sizeof(u16))); 1301 adc->rx_buf_sz = min(rx_buf_sz, watermark * 2 * adc->num_conv); 1302 1303 return 0; 1304 } 1305 1306 static int stm32_adc_update_scan_mode(struct iio_dev *indio_dev, 1307 const unsigned long *scan_mask) 1308 { 1309 struct stm32_adc *adc = iio_priv(indio_dev); 1310 int ret; 1311 1312 adc->num_conv = bitmap_weight(scan_mask, indio_dev->masklength); 1313 1314 ret = stm32_adc_conf_scan_seq(indio_dev, scan_mask); 1315 if (ret) 1316 return ret; 1317 1318 return 0; 1319 } 1320 1321 static int stm32_adc_of_xlate(struct iio_dev *indio_dev, 1322 const struct of_phandle_args *iiospec) 1323 { 1324 int i; 1325 1326 for (i = 0; i < indio_dev->num_channels; i++) 1327 if (indio_dev->channels[i].channel == iiospec->args[0]) 1328 return i; 1329 1330 return -EINVAL; 1331 } 1332 1333 /** 1334 * stm32_adc_debugfs_reg_access - read or write register value 1335 * 1336 * To read a value from an ADC register: 1337 * echo [ADC reg offset] > direct_reg_access 1338 * cat direct_reg_access 1339 * 1340 * To write a value in a ADC register: 1341 * echo [ADC_reg_offset] [value] > direct_reg_access 1342 */ 1343 static int stm32_adc_debugfs_reg_access(struct iio_dev *indio_dev, 1344 unsigned reg, unsigned writeval, 1345 unsigned *readval) 1346 { 1347 struct stm32_adc *adc = iio_priv(indio_dev); 1348 1349 if (!readval) 1350 stm32_adc_writel(adc, reg, writeval); 1351 else 1352 *readval = stm32_adc_readl(adc, reg); 1353 1354 return 0; 1355 } 1356 1357 static const struct iio_info stm32_adc_iio_info = { 1358 .read_raw = stm32_adc_read_raw, 1359 .validate_trigger = stm32_adc_validate_trigger, 1360 .hwfifo_set_watermark = stm32_adc_set_watermark, 1361 .update_scan_mode = stm32_adc_update_scan_mode, 1362 .debugfs_reg_access = stm32_adc_debugfs_reg_access, 1363 .of_xlate = stm32_adc_of_xlate, 1364 }; 1365 1366 static unsigned int stm32_adc_dma_residue(struct stm32_adc *adc) 1367 { 1368 struct dma_tx_state state; 1369 enum dma_status status; 1370 1371 status = dmaengine_tx_status(adc->dma_chan, 1372 adc->dma_chan->cookie, 1373 &state); 1374 if (status == DMA_IN_PROGRESS) { 1375 /* Residue is size in bytes from end of buffer */ 1376 unsigned int i = adc->rx_buf_sz - state.residue; 1377 unsigned int size; 1378 1379 /* Return available bytes */ 1380 if (i >= adc->bufi) 1381 size = i - adc->bufi; 1382 else 1383 size = adc->rx_buf_sz + i - adc->bufi; 1384 1385 return size; 1386 } 1387 1388 return 0; 1389 } 1390 1391 static void stm32_adc_dma_buffer_done(void *data) 1392 { 1393 struct iio_dev *indio_dev = data; 1394 1395 iio_trigger_poll_chained(indio_dev->trig); 1396 } 1397 1398 static int stm32_adc_dma_start(struct iio_dev *indio_dev) 1399 { 1400 struct stm32_adc *adc = iio_priv(indio_dev); 1401 struct dma_async_tx_descriptor *desc; 1402 dma_cookie_t cookie; 1403 int ret; 1404 1405 if (!adc->dma_chan) 1406 return 0; 1407 1408 dev_dbg(&indio_dev->dev, "%s size=%d watermark=%d\n", __func__, 1409 adc->rx_buf_sz, adc->rx_buf_sz / 2); 1410 1411 /* Prepare a DMA cyclic transaction */ 1412 desc = dmaengine_prep_dma_cyclic(adc->dma_chan, 1413 adc->rx_dma_buf, 1414 adc->rx_buf_sz, adc->rx_buf_sz / 2, 1415 DMA_DEV_TO_MEM, 1416 DMA_PREP_INTERRUPT); 1417 if (!desc) 1418 return -EBUSY; 1419 1420 desc->callback = stm32_adc_dma_buffer_done; 1421 desc->callback_param = indio_dev; 1422 1423 cookie = dmaengine_submit(desc); 1424 ret = dma_submit_error(cookie); 1425 if (ret) { 1426 dmaengine_terminate_all(adc->dma_chan); 1427 return ret; 1428 } 1429 1430 /* Issue pending DMA requests */ 1431 dma_async_issue_pending(adc->dma_chan); 1432 1433 return 0; 1434 } 1435 1436 static int stm32_adc_buffer_postenable(struct iio_dev *indio_dev) 1437 { 1438 struct stm32_adc *adc = iio_priv(indio_dev); 1439 int ret; 1440 1441 if (adc->cfg->prepare) { 1442 ret = adc->cfg->prepare(adc); 1443 if (ret) 1444 return ret; 1445 } 1446 1447 ret = stm32_adc_set_trig(indio_dev, indio_dev->trig); 1448 if (ret) { 1449 dev_err(&indio_dev->dev, "Can't set trigger\n"); 1450 goto err_unprepare; 1451 } 1452 1453 ret = stm32_adc_dma_start(indio_dev); 1454 if (ret) { 1455 dev_err(&indio_dev->dev, "Can't start dma\n"); 1456 goto err_clr_trig; 1457 } 1458 1459 ret = iio_triggered_buffer_postenable(indio_dev); 1460 if (ret < 0) 1461 goto err_stop_dma; 1462 1463 /* Reset adc buffer index */ 1464 adc->bufi = 0; 1465 1466 if (!adc->dma_chan) 1467 stm32_adc_conv_irq_enable(adc); 1468 1469 adc->cfg->start_conv(adc, !!adc->dma_chan); 1470 1471 return 0; 1472 1473 err_stop_dma: 1474 if (adc->dma_chan) 1475 dmaengine_terminate_all(adc->dma_chan); 1476 err_clr_trig: 1477 stm32_adc_set_trig(indio_dev, NULL); 1478 err_unprepare: 1479 if (adc->cfg->unprepare) 1480 adc->cfg->unprepare(adc); 1481 1482 return ret; 1483 } 1484 1485 static int stm32_adc_buffer_predisable(struct iio_dev *indio_dev) 1486 { 1487 struct stm32_adc *adc = iio_priv(indio_dev); 1488 int ret; 1489 1490 adc->cfg->stop_conv(adc); 1491 if (!adc->dma_chan) 1492 stm32_adc_conv_irq_disable(adc); 1493 1494 ret = iio_triggered_buffer_predisable(indio_dev); 1495 if (ret < 0) 1496 dev_err(&indio_dev->dev, "predisable failed\n"); 1497 1498 if (adc->dma_chan) 1499 dmaengine_terminate_all(adc->dma_chan); 1500 1501 if (stm32_adc_set_trig(indio_dev, NULL)) 1502 dev_err(&indio_dev->dev, "Can't clear trigger\n"); 1503 1504 if (adc->cfg->unprepare) 1505 adc->cfg->unprepare(adc); 1506 1507 return ret; 1508 } 1509 1510 static const struct iio_buffer_setup_ops stm32_adc_buffer_setup_ops = { 1511 .postenable = &stm32_adc_buffer_postenable, 1512 .predisable = &stm32_adc_buffer_predisable, 1513 }; 1514 1515 static irqreturn_t stm32_adc_trigger_handler(int irq, void *p) 1516 { 1517 struct iio_poll_func *pf = p; 1518 struct iio_dev *indio_dev = pf->indio_dev; 1519 struct stm32_adc *adc = iio_priv(indio_dev); 1520 1521 dev_dbg(&indio_dev->dev, "%s bufi=%d\n", __func__, adc->bufi); 1522 1523 if (!adc->dma_chan) { 1524 /* reset buffer index */ 1525 adc->bufi = 0; 1526 iio_push_to_buffers_with_timestamp(indio_dev, adc->buffer, 1527 pf->timestamp); 1528 } else { 1529 int residue = stm32_adc_dma_residue(adc); 1530 1531 while (residue >= indio_dev->scan_bytes) { 1532 u16 *buffer = (u16 *)&adc->rx_buf[adc->bufi]; 1533 1534 iio_push_to_buffers_with_timestamp(indio_dev, buffer, 1535 pf->timestamp); 1536 residue -= indio_dev->scan_bytes; 1537 adc->bufi += indio_dev->scan_bytes; 1538 if (adc->bufi >= adc->rx_buf_sz) 1539 adc->bufi = 0; 1540 } 1541 } 1542 1543 iio_trigger_notify_done(indio_dev->trig); 1544 1545 /* re-enable eoc irq */ 1546 if (!adc->dma_chan) 1547 stm32_adc_conv_irq_enable(adc); 1548 1549 return IRQ_HANDLED; 1550 } 1551 1552 static const struct iio_chan_spec_ext_info stm32_adc_ext_info[] = { 1553 IIO_ENUM("trigger_polarity", IIO_SHARED_BY_ALL, &stm32_adc_trig_pol), 1554 { 1555 .name = "trigger_polarity_available", 1556 .shared = IIO_SHARED_BY_ALL, 1557 .read = iio_enum_available_read, 1558 .private = (uintptr_t)&stm32_adc_trig_pol, 1559 }, 1560 {}, 1561 }; 1562 1563 static int stm32_adc_of_get_resolution(struct iio_dev *indio_dev) 1564 { 1565 struct device_node *node = indio_dev->dev.of_node; 1566 struct stm32_adc *adc = iio_priv(indio_dev); 1567 unsigned int i; 1568 u32 res; 1569 1570 if (of_property_read_u32(node, "assigned-resolution-bits", &res)) 1571 res = adc->cfg->adc_info->resolutions[0]; 1572 1573 for (i = 0; i < adc->cfg->adc_info->num_res; i++) 1574 if (res == adc->cfg->adc_info->resolutions[i]) 1575 break; 1576 if (i >= adc->cfg->adc_info->num_res) { 1577 dev_err(&indio_dev->dev, "Bad resolution: %u bits\n", res); 1578 return -EINVAL; 1579 } 1580 1581 dev_dbg(&indio_dev->dev, "Using %u bits resolution\n", res); 1582 adc->res = i; 1583 1584 return 0; 1585 } 1586 1587 static void stm32_adc_smpr_init(struct stm32_adc *adc, int channel, u32 smp_ns) 1588 { 1589 const struct stm32_adc_regs *smpr = &adc->cfg->regs->smp_bits[channel]; 1590 u32 period_ns, shift = smpr->shift, mask = smpr->mask; 1591 unsigned int smp, r = smpr->reg; 1592 1593 /* Determine sampling time (ADC clock cycles) */ 1594 period_ns = NSEC_PER_SEC / adc->common->rate; 1595 for (smp = 0; smp <= STM32_ADC_MAX_SMP; smp++) 1596 if ((period_ns * adc->cfg->smp_cycles[smp]) >= smp_ns) 1597 break; 1598 if (smp > STM32_ADC_MAX_SMP) 1599 smp = STM32_ADC_MAX_SMP; 1600 1601 /* pre-build sampling time registers (e.g. smpr1, smpr2) */ 1602 adc->smpr_val[r] = (adc->smpr_val[r] & ~mask) | (smp << shift); 1603 } 1604 1605 static void stm32_adc_chan_init_one(struct iio_dev *indio_dev, 1606 struct iio_chan_spec *chan, u32 vinp, 1607 u32 vinn, int scan_index, bool differential) 1608 { 1609 struct stm32_adc *adc = iio_priv(indio_dev); 1610 char *name = adc->chan_name[vinp]; 1611 1612 chan->type = IIO_VOLTAGE; 1613 chan->channel = vinp; 1614 if (differential) { 1615 chan->differential = 1; 1616 chan->channel2 = vinn; 1617 snprintf(name, STM32_ADC_CH_SZ, "in%d-in%d", vinp, vinn); 1618 } else { 1619 snprintf(name, STM32_ADC_CH_SZ, "in%d", vinp); 1620 } 1621 chan->datasheet_name = name; 1622 chan->scan_index = scan_index; 1623 chan->indexed = 1; 1624 chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW); 1625 chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | 1626 BIT(IIO_CHAN_INFO_OFFSET); 1627 chan->scan_type.sign = 'u'; 1628 chan->scan_type.realbits = adc->cfg->adc_info->resolutions[adc->res]; 1629 chan->scan_type.storagebits = 16; 1630 chan->ext_info = stm32_adc_ext_info; 1631 1632 /* pre-build selected channels mask */ 1633 adc->pcsel |= BIT(chan->channel); 1634 if (differential) { 1635 /* pre-build diff channels mask */ 1636 adc->difsel |= BIT(chan->channel); 1637 /* Also add negative input to pre-selected channels */ 1638 adc->pcsel |= BIT(chan->channel2); 1639 } 1640 } 1641 1642 static int stm32_adc_chan_of_init(struct iio_dev *indio_dev) 1643 { 1644 struct device_node *node = indio_dev->dev.of_node; 1645 struct stm32_adc *adc = iio_priv(indio_dev); 1646 const struct stm32_adc_info *adc_info = adc->cfg->adc_info; 1647 struct stm32_adc_diff_channel diff[STM32_ADC_CH_MAX]; 1648 struct property *prop; 1649 const __be32 *cur; 1650 struct iio_chan_spec *channels; 1651 int scan_index = 0, num_channels = 0, num_diff = 0, ret, i; 1652 u32 val, smp = 0; 1653 1654 ret = of_property_count_u32_elems(node, "st,adc-channels"); 1655 if (ret > adc_info->max_channels) { 1656 dev_err(&indio_dev->dev, "Bad st,adc-channels?\n"); 1657 return -EINVAL; 1658 } else if (ret > 0) { 1659 num_channels += ret; 1660 } 1661 1662 ret = of_property_count_elems_of_size(node, "st,adc-diff-channels", 1663 sizeof(*diff)); 1664 if (ret > adc_info->max_channels) { 1665 dev_err(&indio_dev->dev, "Bad st,adc-diff-channels?\n"); 1666 return -EINVAL; 1667 } else if (ret > 0) { 1668 int size = ret * sizeof(*diff) / sizeof(u32); 1669 1670 num_diff = ret; 1671 num_channels += ret; 1672 ret = of_property_read_u32_array(node, "st,adc-diff-channels", 1673 (u32 *)diff, size); 1674 if (ret) 1675 return ret; 1676 } 1677 1678 if (!num_channels) { 1679 dev_err(&indio_dev->dev, "No channels configured\n"); 1680 return -ENODATA; 1681 } 1682 1683 /* Optional sample time is provided either for each, or all channels */ 1684 ret = of_property_count_u32_elems(node, "st,min-sample-time-nsecs"); 1685 if (ret > 1 && ret != num_channels) { 1686 dev_err(&indio_dev->dev, "Invalid st,min-sample-time-nsecs\n"); 1687 return -EINVAL; 1688 } 1689 1690 channels = devm_kcalloc(&indio_dev->dev, num_channels, 1691 sizeof(struct iio_chan_spec), GFP_KERNEL); 1692 if (!channels) 1693 return -ENOMEM; 1694 1695 of_property_for_each_u32(node, "st,adc-channels", prop, cur, val) { 1696 if (val >= adc_info->max_channels) { 1697 dev_err(&indio_dev->dev, "Invalid channel %d\n", val); 1698 return -EINVAL; 1699 } 1700 1701 /* Channel can't be configured both as single-ended & diff */ 1702 for (i = 0; i < num_diff; i++) { 1703 if (val == diff[i].vinp) { 1704 dev_err(&indio_dev->dev, 1705 "channel %d miss-configured\n", val); 1706 return -EINVAL; 1707 } 1708 } 1709 stm32_adc_chan_init_one(indio_dev, &channels[scan_index], val, 1710 0, scan_index, false); 1711 scan_index++; 1712 } 1713 1714 for (i = 0; i < num_diff; i++) { 1715 if (diff[i].vinp >= adc_info->max_channels || 1716 diff[i].vinn >= adc_info->max_channels) { 1717 dev_err(&indio_dev->dev, "Invalid channel in%d-in%d\n", 1718 diff[i].vinp, diff[i].vinn); 1719 return -EINVAL; 1720 } 1721 stm32_adc_chan_init_one(indio_dev, &channels[scan_index], 1722 diff[i].vinp, diff[i].vinn, scan_index, 1723 true); 1724 scan_index++; 1725 } 1726 1727 for (i = 0; i < scan_index; i++) { 1728 /* 1729 * Using of_property_read_u32_index(), smp value will only be 1730 * modified if valid u32 value can be decoded. This allows to 1731 * get either no value, 1 shared value for all indexes, or one 1732 * value per channel. 1733 */ 1734 of_property_read_u32_index(node, "st,min-sample-time-nsecs", 1735 i, &smp); 1736 /* Prepare sampling time settings */ 1737 stm32_adc_smpr_init(adc, channels[i].channel, smp); 1738 } 1739 1740 indio_dev->num_channels = scan_index; 1741 indio_dev->channels = channels; 1742 1743 return 0; 1744 } 1745 1746 static int stm32_adc_dma_request(struct iio_dev *indio_dev) 1747 { 1748 struct stm32_adc *adc = iio_priv(indio_dev); 1749 struct dma_slave_config config; 1750 int ret; 1751 1752 adc->dma_chan = dma_request_slave_channel(&indio_dev->dev, "rx"); 1753 if (!adc->dma_chan) 1754 return 0; 1755 1756 adc->rx_buf = dma_alloc_coherent(adc->dma_chan->device->dev, 1757 STM32_DMA_BUFFER_SIZE, 1758 &adc->rx_dma_buf, GFP_KERNEL); 1759 if (!adc->rx_buf) { 1760 ret = -ENOMEM; 1761 goto err_release; 1762 } 1763 1764 /* Configure DMA channel to read data register */ 1765 memset(&config, 0, sizeof(config)); 1766 config.src_addr = (dma_addr_t)adc->common->phys_base; 1767 config.src_addr += adc->offset + adc->cfg->regs->dr; 1768 config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 1769 1770 ret = dmaengine_slave_config(adc->dma_chan, &config); 1771 if (ret) 1772 goto err_free; 1773 1774 return 0; 1775 1776 err_free: 1777 dma_free_coherent(adc->dma_chan->device->dev, STM32_DMA_BUFFER_SIZE, 1778 adc->rx_buf, adc->rx_dma_buf); 1779 err_release: 1780 dma_release_channel(adc->dma_chan); 1781 1782 return ret; 1783 } 1784 1785 static int stm32_adc_probe(struct platform_device *pdev) 1786 { 1787 struct iio_dev *indio_dev; 1788 struct device *dev = &pdev->dev; 1789 struct stm32_adc *adc; 1790 int ret; 1791 1792 if (!pdev->dev.of_node) 1793 return -ENODEV; 1794 1795 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc)); 1796 if (!indio_dev) 1797 return -ENOMEM; 1798 1799 adc = iio_priv(indio_dev); 1800 adc->common = dev_get_drvdata(pdev->dev.parent); 1801 spin_lock_init(&adc->lock); 1802 init_completion(&adc->completion); 1803 adc->cfg = (const struct stm32_adc_cfg *) 1804 of_match_device(dev->driver->of_match_table, dev)->data; 1805 1806 indio_dev->name = dev_name(&pdev->dev); 1807 indio_dev->dev.parent = &pdev->dev; 1808 indio_dev->dev.of_node = pdev->dev.of_node; 1809 indio_dev->info = &stm32_adc_iio_info; 1810 indio_dev->modes = INDIO_DIRECT_MODE | INDIO_HARDWARE_TRIGGERED; 1811 1812 platform_set_drvdata(pdev, adc); 1813 1814 ret = of_property_read_u32(pdev->dev.of_node, "reg", &adc->offset); 1815 if (ret != 0) { 1816 dev_err(&pdev->dev, "missing reg property\n"); 1817 return -EINVAL; 1818 } 1819 1820 adc->irq = platform_get_irq(pdev, 0); 1821 if (adc->irq < 0) { 1822 dev_err(&pdev->dev, "failed to get irq\n"); 1823 return adc->irq; 1824 } 1825 1826 ret = devm_request_irq(&pdev->dev, adc->irq, stm32_adc_isr, 1827 0, pdev->name, adc); 1828 if (ret) { 1829 dev_err(&pdev->dev, "failed to request IRQ\n"); 1830 return ret; 1831 } 1832 1833 adc->clk = devm_clk_get(&pdev->dev, NULL); 1834 if (IS_ERR(adc->clk)) { 1835 ret = PTR_ERR(adc->clk); 1836 if (ret == -ENOENT && !adc->cfg->clk_required) { 1837 adc->clk = NULL; 1838 } else { 1839 dev_err(&pdev->dev, "Can't get clock\n"); 1840 return ret; 1841 } 1842 } 1843 1844 if (adc->clk) { 1845 ret = clk_prepare_enable(adc->clk); 1846 if (ret < 0) { 1847 dev_err(&pdev->dev, "clk enable failed\n"); 1848 return ret; 1849 } 1850 } 1851 1852 ret = stm32_adc_of_get_resolution(indio_dev); 1853 if (ret < 0) 1854 goto err_clk_disable; 1855 stm32_adc_set_res(adc); 1856 1857 if (adc->cfg->selfcalib) { 1858 ret = adc->cfg->selfcalib(adc); 1859 if (ret) 1860 goto err_clk_disable; 1861 } 1862 1863 ret = stm32_adc_chan_of_init(indio_dev); 1864 if (ret < 0) 1865 goto err_clk_disable; 1866 1867 ret = stm32_adc_dma_request(indio_dev); 1868 if (ret < 0) 1869 goto err_clk_disable; 1870 1871 ret = iio_triggered_buffer_setup(indio_dev, 1872 &iio_pollfunc_store_time, 1873 &stm32_adc_trigger_handler, 1874 &stm32_adc_buffer_setup_ops); 1875 if (ret) { 1876 dev_err(&pdev->dev, "buffer setup failed\n"); 1877 goto err_dma_disable; 1878 } 1879 1880 ret = iio_device_register(indio_dev); 1881 if (ret) { 1882 dev_err(&pdev->dev, "iio dev register failed\n"); 1883 goto err_buffer_cleanup; 1884 } 1885 1886 return 0; 1887 1888 err_buffer_cleanup: 1889 iio_triggered_buffer_cleanup(indio_dev); 1890 1891 err_dma_disable: 1892 if (adc->dma_chan) { 1893 dma_free_coherent(adc->dma_chan->device->dev, 1894 STM32_DMA_BUFFER_SIZE, 1895 adc->rx_buf, adc->rx_dma_buf); 1896 dma_release_channel(adc->dma_chan); 1897 } 1898 err_clk_disable: 1899 if (adc->clk) 1900 clk_disable_unprepare(adc->clk); 1901 1902 return ret; 1903 } 1904 1905 static int stm32_adc_remove(struct platform_device *pdev) 1906 { 1907 struct stm32_adc *adc = platform_get_drvdata(pdev); 1908 struct iio_dev *indio_dev = iio_priv_to_dev(adc); 1909 1910 iio_device_unregister(indio_dev); 1911 iio_triggered_buffer_cleanup(indio_dev); 1912 if (adc->dma_chan) { 1913 dma_free_coherent(adc->dma_chan->device->dev, 1914 STM32_DMA_BUFFER_SIZE, 1915 adc->rx_buf, adc->rx_dma_buf); 1916 dma_release_channel(adc->dma_chan); 1917 } 1918 if (adc->clk) 1919 clk_disable_unprepare(adc->clk); 1920 1921 return 0; 1922 } 1923 1924 static const struct stm32_adc_cfg stm32f4_adc_cfg = { 1925 .regs = &stm32f4_adc_regspec, 1926 .adc_info = &stm32f4_adc_info, 1927 .trigs = stm32f4_adc_trigs, 1928 .clk_required = true, 1929 .start_conv = stm32f4_adc_start_conv, 1930 .stop_conv = stm32f4_adc_stop_conv, 1931 .smp_cycles = stm32f4_adc_smp_cycles, 1932 }; 1933 1934 static const struct stm32_adc_cfg stm32h7_adc_cfg = { 1935 .regs = &stm32h7_adc_regspec, 1936 .adc_info = &stm32h7_adc_info, 1937 .trigs = stm32h7_adc_trigs, 1938 .selfcalib = stm32h7_adc_selfcalib, 1939 .start_conv = stm32h7_adc_start_conv, 1940 .stop_conv = stm32h7_adc_stop_conv, 1941 .prepare = stm32h7_adc_prepare, 1942 .unprepare = stm32h7_adc_unprepare, 1943 .smp_cycles = stm32h7_adc_smp_cycles, 1944 }; 1945 1946 static const struct of_device_id stm32_adc_of_match[] = { 1947 { .compatible = "st,stm32f4-adc", .data = (void *)&stm32f4_adc_cfg }, 1948 { .compatible = "st,stm32h7-adc", .data = (void *)&stm32h7_adc_cfg }, 1949 {}, 1950 }; 1951 MODULE_DEVICE_TABLE(of, stm32_adc_of_match); 1952 1953 static struct platform_driver stm32_adc_driver = { 1954 .probe = stm32_adc_probe, 1955 .remove = stm32_adc_remove, 1956 .driver = { 1957 .name = "stm32-adc", 1958 .of_match_table = stm32_adc_of_match, 1959 }, 1960 }; 1961 module_platform_driver(stm32_adc_driver); 1962 1963 MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>"); 1964 MODULE_DESCRIPTION("STMicroelectronics STM32 ADC IIO driver"); 1965 MODULE_LICENSE("GPL v2"); 1966 MODULE_ALIAS("platform:stm32-adc"); 1967