1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX5_IB_H 34 #define MLX5_IB_H 35 36 #include <linux/kernel.h> 37 #include <linux/sched.h> 38 #include <rdma/ib_verbs.h> 39 #include <rdma/ib_smi.h> 40 #include <linux/mlx5/driver.h> 41 #include <linux/mlx5/cq.h> 42 #include <linux/mlx5/qp.h> 43 #include <linux/mlx5/srq.h> 44 #include <linux/types.h> 45 #include <linux/mlx5/transobj.h> 46 #include <rdma/ib_user_verbs.h> 47 #include <rdma/mlx5-abi.h> 48 49 #define mlx5_ib_dbg(dev, format, arg...) \ 50 pr_debug("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \ 51 __LINE__, current->pid, ##arg) 52 53 #define mlx5_ib_err(dev, format, arg...) \ 54 pr_err("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \ 55 __LINE__, current->pid, ##arg) 56 57 #define mlx5_ib_warn(dev, format, arg...) \ 58 pr_warn("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \ 59 __LINE__, current->pid, ##arg) 60 61 #define field_avail(type, fld, sz) (offsetof(type, fld) + \ 62 sizeof(((type *)0)->fld) <= (sz)) 63 #define MLX5_IB_DEFAULT_UIDX 0xffffff 64 #define MLX5_USER_ASSIGNED_UIDX_MASK __mlx5_mask(qpc, user_index) 65 66 #define MLX5_MKEY_PAGE_SHIFT_MASK __mlx5_mask(mkc, log_page_size) 67 68 enum { 69 MLX5_IB_MMAP_CMD_SHIFT = 8, 70 MLX5_IB_MMAP_CMD_MASK = 0xff, 71 }; 72 73 enum { 74 MLX5_RES_SCAT_DATA32_CQE = 0x1, 75 MLX5_RES_SCAT_DATA64_CQE = 0x2, 76 MLX5_REQ_SCAT_DATA32_CQE = 0x11, 77 MLX5_REQ_SCAT_DATA64_CQE = 0x22, 78 }; 79 80 enum mlx5_ib_latency_class { 81 MLX5_IB_LATENCY_CLASS_LOW, 82 MLX5_IB_LATENCY_CLASS_MEDIUM, 83 MLX5_IB_LATENCY_CLASS_HIGH, 84 }; 85 86 enum mlx5_ib_mad_ifc_flags { 87 MLX5_MAD_IFC_IGNORE_MKEY = 1, 88 MLX5_MAD_IFC_IGNORE_BKEY = 2, 89 MLX5_MAD_IFC_NET_VIEW = 4, 90 }; 91 92 enum { 93 MLX5_CROSS_CHANNEL_BFREG = 0, 94 }; 95 96 enum { 97 MLX5_CQE_VERSION_V0, 98 MLX5_CQE_VERSION_V1, 99 }; 100 101 enum { 102 MLX5_TM_MAX_RNDV_MSG_SIZE = 64, 103 MLX5_TM_MAX_SGE = 1, 104 }; 105 106 enum { 107 MLX5_IB_INVALID_UAR_INDEX = BIT(31), 108 MLX5_IB_INVALID_BFREG = BIT(31), 109 }; 110 111 struct mlx5_ib_vma_private_data { 112 struct list_head list; 113 struct vm_area_struct *vma; 114 /* protect vma_private_list add/del */ 115 struct mutex *vma_private_list_mutex; 116 }; 117 118 struct mlx5_ib_ucontext { 119 struct ib_ucontext ibucontext; 120 struct list_head db_page_list; 121 122 /* protect doorbell record alloc/free 123 */ 124 struct mutex db_page_mutex; 125 struct mlx5_bfreg_info bfregi; 126 u8 cqe_version; 127 /* Transport Domain number */ 128 u32 tdn; 129 struct list_head vma_private_list; 130 /* protect vma_private_list add/del */ 131 struct mutex vma_private_list_mutex; 132 133 unsigned long upd_xlt_page; 134 /* protect ODP/KSM */ 135 struct mutex upd_xlt_page_mutex; 136 u64 lib_caps; 137 }; 138 139 static inline struct mlx5_ib_ucontext *to_mucontext(struct ib_ucontext *ibucontext) 140 { 141 return container_of(ibucontext, struct mlx5_ib_ucontext, ibucontext); 142 } 143 144 struct mlx5_ib_pd { 145 struct ib_pd ibpd; 146 u32 pdn; 147 }; 148 149 #define MLX5_IB_FLOW_MCAST_PRIO (MLX5_BY_PASS_NUM_PRIOS - 1) 150 #define MLX5_IB_FLOW_LAST_PRIO (MLX5_BY_PASS_NUM_REGULAR_PRIOS - 1) 151 #if (MLX5_IB_FLOW_LAST_PRIO <= 0) 152 #error "Invalid number of bypass priorities" 153 #endif 154 #define MLX5_IB_FLOW_LEFTOVERS_PRIO (MLX5_IB_FLOW_MCAST_PRIO + 1) 155 156 #define MLX5_IB_NUM_FLOW_FT (MLX5_IB_FLOW_LEFTOVERS_PRIO + 1) 157 #define MLX5_IB_NUM_SNIFFER_FTS 2 158 struct mlx5_ib_flow_prio { 159 struct mlx5_flow_table *flow_table; 160 unsigned int refcount; 161 }; 162 163 struct mlx5_ib_flow_handler { 164 struct list_head list; 165 struct ib_flow ibflow; 166 struct mlx5_ib_flow_prio *prio; 167 struct mlx5_flow_handle *rule; 168 }; 169 170 struct mlx5_ib_flow_db { 171 struct mlx5_ib_flow_prio prios[MLX5_IB_NUM_FLOW_FT]; 172 struct mlx5_ib_flow_prio sniffer[MLX5_IB_NUM_SNIFFER_FTS]; 173 struct mlx5_flow_table *lag_demux_ft; 174 /* Protect flow steering bypass flow tables 175 * when add/del flow rules. 176 * only single add/removal of flow steering rule could be done 177 * simultaneously. 178 */ 179 struct mutex lock; 180 }; 181 182 /* Use macros here so that don't have to duplicate 183 * enum ib_send_flags and enum ib_qp_type for low-level driver 184 */ 185 186 #define MLX5_IB_SEND_UMR_ENABLE_MR (IB_SEND_RESERVED_START << 0) 187 #define MLX5_IB_SEND_UMR_DISABLE_MR (IB_SEND_RESERVED_START << 1) 188 #define MLX5_IB_SEND_UMR_FAIL_IF_FREE (IB_SEND_RESERVED_START << 2) 189 #define MLX5_IB_SEND_UMR_UPDATE_XLT (IB_SEND_RESERVED_START << 3) 190 #define MLX5_IB_SEND_UMR_UPDATE_TRANSLATION (IB_SEND_RESERVED_START << 4) 191 #define MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS IB_SEND_RESERVED_END 192 193 #define MLX5_IB_QPT_REG_UMR IB_QPT_RESERVED1 194 /* 195 * IB_QPT_GSI creates the software wrapper around GSI, and MLX5_IB_QPT_HW_GSI 196 * creates the actual hardware QP. 197 */ 198 #define MLX5_IB_QPT_HW_GSI IB_QPT_RESERVED2 199 #define MLX5_IB_QPT_DCI IB_QPT_RESERVED3 200 #define MLX5_IB_QPT_DCT IB_QPT_RESERVED4 201 #define MLX5_IB_WR_UMR IB_WR_RESERVED1 202 203 #define MLX5_IB_UMR_OCTOWORD 16 204 #define MLX5_IB_UMR_XLT_ALIGNMENT 64 205 206 #define MLX5_IB_UPD_XLT_ZAP BIT(0) 207 #define MLX5_IB_UPD_XLT_ENABLE BIT(1) 208 #define MLX5_IB_UPD_XLT_ATOMIC BIT(2) 209 #define MLX5_IB_UPD_XLT_ADDR BIT(3) 210 #define MLX5_IB_UPD_XLT_PD BIT(4) 211 #define MLX5_IB_UPD_XLT_ACCESS BIT(5) 212 #define MLX5_IB_UPD_XLT_INDIRECT BIT(6) 213 214 /* Private QP creation flags to be passed in ib_qp_init_attr.create_flags. 215 * 216 * These flags are intended for internal use by the mlx5_ib driver, and they 217 * rely on the range reserved for that use in the ib_qp_create_flags enum. 218 */ 219 220 /* Create a UD QP whose source QP number is 1 */ 221 static inline enum ib_qp_create_flags mlx5_ib_create_qp_sqpn_qp1(void) 222 { 223 return IB_QP_CREATE_RESERVED_START; 224 } 225 226 struct wr_list { 227 u16 opcode; 228 u16 next; 229 }; 230 231 enum mlx5_ib_rq_flags { 232 MLX5_IB_RQ_CVLAN_STRIPPING = 1 << 0, 233 MLX5_IB_RQ_PCI_WRITE_END_PADDING = 1 << 1, 234 }; 235 236 struct mlx5_ib_wq { 237 u64 *wrid; 238 u32 *wr_data; 239 struct wr_list *w_list; 240 unsigned *wqe_head; 241 u16 unsig_count; 242 243 /* serialize post to the work queue 244 */ 245 spinlock_t lock; 246 int wqe_cnt; 247 int max_post; 248 int max_gs; 249 int offset; 250 int wqe_shift; 251 unsigned head; 252 unsigned tail; 253 u16 cur_post; 254 u16 last_poll; 255 void *qend; 256 }; 257 258 enum mlx5_ib_wq_flags { 259 MLX5_IB_WQ_FLAGS_DELAY_DROP = 0x1, 260 MLX5_IB_WQ_FLAGS_STRIDING_RQ = 0x2, 261 }; 262 263 #define MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES 9 264 #define MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES 16 265 #define MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES 6 266 #define MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES 13 267 268 struct mlx5_ib_rwq { 269 struct ib_wq ibwq; 270 struct mlx5_core_qp core_qp; 271 u32 rq_num_pas; 272 u32 log_rq_stride; 273 u32 log_rq_size; 274 u32 rq_page_offset; 275 u32 log_page_size; 276 u32 log_num_strides; 277 u32 two_byte_shift_en; 278 u32 single_stride_log_num_of_bytes; 279 struct ib_umem *umem; 280 size_t buf_size; 281 unsigned int page_shift; 282 int create_type; 283 struct mlx5_db db; 284 u32 user_index; 285 u32 wqe_count; 286 u32 wqe_shift; 287 int wq_sig; 288 u32 create_flags; /* Use enum mlx5_ib_wq_flags */ 289 }; 290 291 enum { 292 MLX5_QP_USER, 293 MLX5_QP_KERNEL, 294 MLX5_QP_EMPTY 295 }; 296 297 enum { 298 MLX5_WQ_USER, 299 MLX5_WQ_KERNEL 300 }; 301 302 struct mlx5_ib_rwq_ind_table { 303 struct ib_rwq_ind_table ib_rwq_ind_tbl; 304 u32 rqtn; 305 }; 306 307 struct mlx5_ib_ubuffer { 308 struct ib_umem *umem; 309 int buf_size; 310 u64 buf_addr; 311 }; 312 313 struct mlx5_ib_qp_base { 314 struct mlx5_ib_qp *container_mibqp; 315 struct mlx5_core_qp mqp; 316 struct mlx5_ib_ubuffer ubuffer; 317 }; 318 319 struct mlx5_ib_qp_trans { 320 struct mlx5_ib_qp_base base; 321 u16 xrcdn; 322 u8 alt_port; 323 u8 atomic_rd_en; 324 u8 resp_depth; 325 }; 326 327 struct mlx5_ib_rss_qp { 328 u32 tirn; 329 }; 330 331 struct mlx5_ib_rq { 332 struct mlx5_ib_qp_base base; 333 struct mlx5_ib_wq *rq; 334 struct mlx5_ib_ubuffer ubuffer; 335 struct mlx5_db *doorbell; 336 u32 tirn; 337 u8 state; 338 u32 flags; 339 }; 340 341 struct mlx5_ib_sq { 342 struct mlx5_ib_qp_base base; 343 struct mlx5_ib_wq *sq; 344 struct mlx5_ib_ubuffer ubuffer; 345 struct mlx5_db *doorbell; 346 struct mlx5_flow_handle *flow_rule; 347 u32 tisn; 348 u8 state; 349 }; 350 351 struct mlx5_ib_raw_packet_qp { 352 struct mlx5_ib_sq sq; 353 struct mlx5_ib_rq rq; 354 }; 355 356 struct mlx5_bf { 357 int buf_size; 358 unsigned long offset; 359 struct mlx5_sq_bfreg *bfreg; 360 }; 361 362 struct mlx5_ib_dct { 363 struct mlx5_core_dct mdct; 364 u32 *in; 365 }; 366 367 struct mlx5_ib_qp { 368 struct ib_qp ibqp; 369 union { 370 struct mlx5_ib_qp_trans trans_qp; 371 struct mlx5_ib_raw_packet_qp raw_packet_qp; 372 struct mlx5_ib_rss_qp rss_qp; 373 struct mlx5_ib_dct dct; 374 }; 375 struct mlx5_frag_buf buf; 376 377 struct mlx5_db db; 378 struct mlx5_ib_wq rq; 379 380 u8 sq_signal_bits; 381 u8 next_fence; 382 struct mlx5_ib_wq sq; 383 384 /* serialize qp state modifications 385 */ 386 struct mutex mutex; 387 u32 flags; 388 u8 port; 389 u8 state; 390 int wq_sig; 391 int scat_cqe; 392 int max_inline_data; 393 struct mlx5_bf bf; 394 int has_rq; 395 396 /* only for user space QPs. For kernel 397 * we have it from the bf object 398 */ 399 int bfregn; 400 401 int create_type; 402 403 /* Store signature errors */ 404 bool signature_en; 405 406 struct list_head qps_list; 407 struct list_head cq_recv_list; 408 struct list_head cq_send_list; 409 u32 rate_limit; 410 u32 underlay_qpn; 411 bool tunnel_offload_en; 412 /* storage for qp sub type when core qp type is IB_QPT_DRIVER */ 413 enum ib_qp_type qp_sub_type; 414 }; 415 416 struct mlx5_ib_cq_buf { 417 struct mlx5_frag_buf_ctrl fbc; 418 struct ib_umem *umem; 419 int cqe_size; 420 int nent; 421 }; 422 423 enum mlx5_ib_qp_flags { 424 MLX5_IB_QP_LSO = IB_QP_CREATE_IPOIB_UD_LSO, 425 MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK = IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK, 426 MLX5_IB_QP_CROSS_CHANNEL = IB_QP_CREATE_CROSS_CHANNEL, 427 MLX5_IB_QP_MANAGED_SEND = IB_QP_CREATE_MANAGED_SEND, 428 MLX5_IB_QP_MANAGED_RECV = IB_QP_CREATE_MANAGED_RECV, 429 MLX5_IB_QP_SIGNATURE_HANDLING = 1 << 5, 430 /* QP uses 1 as its source QP number */ 431 MLX5_IB_QP_SQPN_QP1 = 1 << 6, 432 MLX5_IB_QP_CAP_SCATTER_FCS = 1 << 7, 433 MLX5_IB_QP_RSS = 1 << 8, 434 MLX5_IB_QP_CVLAN_STRIPPING = 1 << 9, 435 MLX5_IB_QP_UNDERLAY = 1 << 10, 436 MLX5_IB_QP_PCI_WRITE_END_PADDING = 1 << 11, 437 MLX5_IB_QP_TUNNEL_OFFLOAD = 1 << 12, 438 }; 439 440 struct mlx5_umr_wr { 441 struct ib_send_wr wr; 442 u64 virt_addr; 443 u64 offset; 444 struct ib_pd *pd; 445 unsigned int page_shift; 446 unsigned int xlt_size; 447 u64 length; 448 int access_flags; 449 u32 mkey; 450 }; 451 452 static inline struct mlx5_umr_wr *umr_wr(struct ib_send_wr *wr) 453 { 454 return container_of(wr, struct mlx5_umr_wr, wr); 455 } 456 457 struct mlx5_shared_mr_info { 458 int mr_id; 459 struct ib_umem *umem; 460 }; 461 462 enum mlx5_ib_cq_pr_flags { 463 MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD = 1 << 0, 464 }; 465 466 struct mlx5_ib_cq { 467 struct ib_cq ibcq; 468 struct mlx5_core_cq mcq; 469 struct mlx5_ib_cq_buf buf; 470 struct mlx5_db db; 471 472 /* serialize access to the CQ 473 */ 474 spinlock_t lock; 475 476 /* protect resize cq 477 */ 478 struct mutex resize_mutex; 479 struct mlx5_ib_cq_buf *resize_buf; 480 struct ib_umem *resize_umem; 481 int cqe_size; 482 struct list_head list_send_qp; 483 struct list_head list_recv_qp; 484 u32 create_flags; 485 struct list_head wc_list; 486 enum ib_cq_notify_flags notify_flags; 487 struct work_struct notify_work; 488 u16 private_flags; /* Use mlx5_ib_cq_pr_flags */ 489 }; 490 491 struct mlx5_ib_wc { 492 struct ib_wc wc; 493 struct list_head list; 494 }; 495 496 struct mlx5_ib_srq { 497 struct ib_srq ibsrq; 498 struct mlx5_core_srq msrq; 499 struct mlx5_frag_buf buf; 500 struct mlx5_db db; 501 u64 *wrid; 502 /* protect SRQ hanlding 503 */ 504 spinlock_t lock; 505 int head; 506 int tail; 507 u16 wqe_ctr; 508 struct ib_umem *umem; 509 /* serialize arming a SRQ 510 */ 511 struct mutex mutex; 512 int wq_sig; 513 }; 514 515 struct mlx5_ib_xrcd { 516 struct ib_xrcd ibxrcd; 517 u32 xrcdn; 518 }; 519 520 enum mlx5_ib_mtt_access_flags { 521 MLX5_IB_MTT_READ = (1 << 0), 522 MLX5_IB_MTT_WRITE = (1 << 1), 523 }; 524 525 #define MLX5_IB_MTT_PRESENT (MLX5_IB_MTT_READ | MLX5_IB_MTT_WRITE) 526 527 struct mlx5_ib_mr { 528 struct ib_mr ibmr; 529 void *descs; 530 dma_addr_t desc_map; 531 int ndescs; 532 int max_descs; 533 int desc_size; 534 int access_mode; 535 struct mlx5_core_mkey mmkey; 536 struct ib_umem *umem; 537 struct mlx5_shared_mr_info *smr_info; 538 struct list_head list; 539 int order; 540 bool allocated_from_cache; 541 int npages; 542 struct mlx5_ib_dev *dev; 543 u32 out[MLX5_ST_SZ_DW(create_mkey_out)]; 544 struct mlx5_core_sig_ctx *sig; 545 int live; 546 void *descs_alloc; 547 int access_flags; /* Needed for rereg MR */ 548 549 struct mlx5_ib_mr *parent; 550 atomic_t num_leaf_free; 551 wait_queue_head_t q_leaf_free; 552 }; 553 554 struct mlx5_ib_mw { 555 struct ib_mw ibmw; 556 struct mlx5_core_mkey mmkey; 557 int ndescs; 558 }; 559 560 struct mlx5_ib_umr_context { 561 struct ib_cqe cqe; 562 enum ib_wc_status status; 563 struct completion done; 564 }; 565 566 struct umr_common { 567 struct ib_pd *pd; 568 struct ib_cq *cq; 569 struct ib_qp *qp; 570 /* control access to UMR QP 571 */ 572 struct semaphore sem; 573 }; 574 575 enum { 576 MLX5_FMR_INVALID, 577 MLX5_FMR_VALID, 578 MLX5_FMR_BUSY, 579 }; 580 581 struct mlx5_cache_ent { 582 struct list_head head; 583 /* sync access to the cahce entry 584 */ 585 spinlock_t lock; 586 587 588 struct dentry *dir; 589 char name[4]; 590 u32 order; 591 u32 xlt; 592 u32 access_mode; 593 u32 page; 594 595 u32 size; 596 u32 cur; 597 u32 miss; 598 u32 limit; 599 600 struct dentry *fsize; 601 struct dentry *fcur; 602 struct dentry *fmiss; 603 struct dentry *flimit; 604 605 struct mlx5_ib_dev *dev; 606 struct work_struct work; 607 struct delayed_work dwork; 608 int pending; 609 struct completion compl; 610 }; 611 612 struct mlx5_mr_cache { 613 struct workqueue_struct *wq; 614 struct mlx5_cache_ent ent[MAX_MR_CACHE_ENTRIES]; 615 int stopped; 616 struct dentry *root; 617 unsigned long last_add; 618 }; 619 620 struct mlx5_ib_gsi_qp; 621 622 struct mlx5_ib_port_resources { 623 struct mlx5_ib_resources *devr; 624 struct mlx5_ib_gsi_qp *gsi; 625 struct work_struct pkey_change_work; 626 }; 627 628 struct mlx5_ib_resources { 629 struct ib_cq *c0; 630 struct ib_xrcd *x0; 631 struct ib_xrcd *x1; 632 struct ib_pd *p0; 633 struct ib_srq *s0; 634 struct ib_srq *s1; 635 struct mlx5_ib_port_resources ports[2]; 636 /* Protects changes to the port resources */ 637 struct mutex mutex; 638 }; 639 640 struct mlx5_ib_counters { 641 const char **names; 642 size_t *offsets; 643 u32 num_q_counters; 644 u32 num_cong_counters; 645 u16 set_id; 646 bool set_id_valid; 647 }; 648 649 struct mlx5_ib_multiport_info; 650 651 struct mlx5_ib_multiport { 652 struct mlx5_ib_multiport_info *mpi; 653 /* To be held when accessing the multiport info */ 654 spinlock_t mpi_lock; 655 }; 656 657 struct mlx5_ib_port { 658 struct mlx5_ib_counters cnts; 659 struct mlx5_ib_multiport mp; 660 struct mlx5_ib_dbg_cc_params *dbg_cc_params; 661 }; 662 663 struct mlx5_roce { 664 /* Protect mlx5_ib_get_netdev from invoking dev_hold() with a NULL 665 * netdev pointer 666 */ 667 rwlock_t netdev_lock; 668 struct net_device *netdev; 669 struct notifier_block nb; 670 atomic_t next_port; 671 enum ib_port_state last_port_state; 672 struct mlx5_ib_dev *dev; 673 u8 native_port_num; 674 }; 675 676 struct mlx5_ib_dbg_param { 677 int offset; 678 struct mlx5_ib_dev *dev; 679 struct dentry *dentry; 680 u8 port_num; 681 }; 682 683 enum mlx5_ib_dbg_cc_types { 684 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE, 685 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE_ATI, 686 MLX5_IB_DBG_CC_RP_TIME_RESET, 687 MLX5_IB_DBG_CC_RP_BYTE_RESET, 688 MLX5_IB_DBG_CC_RP_THRESHOLD, 689 MLX5_IB_DBG_CC_RP_AI_RATE, 690 MLX5_IB_DBG_CC_RP_HAI_RATE, 691 MLX5_IB_DBG_CC_RP_MIN_DEC_FAC, 692 MLX5_IB_DBG_CC_RP_MIN_RATE, 693 MLX5_IB_DBG_CC_RP_RATE_TO_SET_ON_FIRST_CNP, 694 MLX5_IB_DBG_CC_RP_DCE_TCP_G, 695 MLX5_IB_DBG_CC_RP_DCE_TCP_RTT, 696 MLX5_IB_DBG_CC_RP_RATE_REDUCE_MONITOR_PERIOD, 697 MLX5_IB_DBG_CC_RP_INITIAL_ALPHA_VALUE, 698 MLX5_IB_DBG_CC_RP_GD, 699 MLX5_IB_DBG_CC_NP_CNP_DSCP, 700 MLX5_IB_DBG_CC_NP_CNP_PRIO_MODE, 701 MLX5_IB_DBG_CC_NP_CNP_PRIO, 702 MLX5_IB_DBG_CC_MAX, 703 }; 704 705 struct mlx5_ib_dbg_cc_params { 706 struct dentry *root; 707 struct mlx5_ib_dbg_param params[MLX5_IB_DBG_CC_MAX]; 708 }; 709 710 enum { 711 MLX5_MAX_DELAY_DROP_TIMEOUT_MS = 100, 712 }; 713 714 struct mlx5_ib_dbg_delay_drop { 715 struct dentry *dir_debugfs; 716 struct dentry *rqs_cnt_debugfs; 717 struct dentry *events_cnt_debugfs; 718 struct dentry *timeout_debugfs; 719 }; 720 721 struct mlx5_ib_delay_drop { 722 struct mlx5_ib_dev *dev; 723 struct work_struct delay_drop_work; 724 /* serialize setting of delay drop */ 725 struct mutex lock; 726 u32 timeout; 727 bool activate; 728 atomic_t events_cnt; 729 atomic_t rqs_cnt; 730 struct mlx5_ib_dbg_delay_drop *dbg; 731 }; 732 733 enum mlx5_ib_stages { 734 MLX5_IB_STAGE_INIT, 735 MLX5_IB_STAGE_FLOW_DB, 736 MLX5_IB_STAGE_CAPS, 737 MLX5_IB_STAGE_NON_DEFAULT_CB, 738 MLX5_IB_STAGE_ROCE, 739 MLX5_IB_STAGE_DEVICE_RESOURCES, 740 MLX5_IB_STAGE_ODP, 741 MLX5_IB_STAGE_COUNTERS, 742 MLX5_IB_STAGE_CONG_DEBUGFS, 743 MLX5_IB_STAGE_UAR, 744 MLX5_IB_STAGE_BFREG, 745 MLX5_IB_STAGE_PRE_IB_REG_UMR, 746 MLX5_IB_STAGE_IB_REG, 747 MLX5_IB_STAGE_POST_IB_REG_UMR, 748 MLX5_IB_STAGE_DELAY_DROP, 749 MLX5_IB_STAGE_CLASS_ATTR, 750 MLX5_IB_STAGE_REP_REG, 751 MLX5_IB_STAGE_MAX, 752 }; 753 754 struct mlx5_ib_stage { 755 int (*init)(struct mlx5_ib_dev *dev); 756 void (*cleanup)(struct mlx5_ib_dev *dev); 757 }; 758 759 #define STAGE_CREATE(_stage, _init, _cleanup) \ 760 .stage[_stage] = {.init = _init, .cleanup = _cleanup} 761 762 struct mlx5_ib_profile { 763 struct mlx5_ib_stage stage[MLX5_IB_STAGE_MAX]; 764 }; 765 766 struct mlx5_ib_multiport_info { 767 struct list_head list; 768 struct mlx5_ib_dev *ibdev; 769 struct mlx5_core_dev *mdev; 770 struct completion unref_comp; 771 u64 sys_image_guid; 772 u32 mdev_refcnt; 773 bool is_master; 774 bool unaffiliate; 775 }; 776 777 struct mlx5_ib_dev { 778 struct ib_device ib_dev; 779 struct mlx5_core_dev *mdev; 780 struct mlx5_roce roce[MLX5_MAX_PORTS]; 781 int num_ports; 782 /* serialize update of capability mask 783 */ 784 struct mutex cap_mask_mutex; 785 bool ib_active; 786 struct umr_common umrc; 787 /* sync used page count stats 788 */ 789 struct mlx5_ib_resources devr; 790 struct mlx5_mr_cache cache; 791 struct timer_list delay_timer; 792 /* Prevents soft lock on massive reg MRs */ 793 struct mutex slow_path_mutex; 794 int fill_delay; 795 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 796 struct ib_odp_caps odp_caps; 797 u64 odp_max_size; 798 /* 799 * Sleepable RCU that prevents destruction of MRs while they are still 800 * being used by a page fault handler. 801 */ 802 struct srcu_struct mr_srcu; 803 u32 null_mkey; 804 #endif 805 struct mlx5_ib_flow_db *flow_db; 806 /* protect resources needed as part of reset flow */ 807 spinlock_t reset_flow_resource_lock; 808 struct list_head qp_list; 809 /* Array with num_ports elements */ 810 struct mlx5_ib_port *port; 811 struct mlx5_sq_bfreg bfreg; 812 struct mlx5_sq_bfreg fp_bfreg; 813 struct mlx5_ib_delay_drop delay_drop; 814 const struct mlx5_ib_profile *profile; 815 struct mlx5_eswitch_rep *rep; 816 817 /* protect the user_td */ 818 struct mutex lb_mutex; 819 u32 user_td; 820 u8 umr_fence; 821 struct list_head ib_dev_list; 822 u64 sys_image_guid; 823 }; 824 825 static inline struct mlx5_ib_cq *to_mibcq(struct mlx5_core_cq *mcq) 826 { 827 return container_of(mcq, struct mlx5_ib_cq, mcq); 828 } 829 830 static inline struct mlx5_ib_xrcd *to_mxrcd(struct ib_xrcd *ibxrcd) 831 { 832 return container_of(ibxrcd, struct mlx5_ib_xrcd, ibxrcd); 833 } 834 835 static inline struct mlx5_ib_dev *to_mdev(struct ib_device *ibdev) 836 { 837 return container_of(ibdev, struct mlx5_ib_dev, ib_dev); 838 } 839 840 static inline struct mlx5_ib_cq *to_mcq(struct ib_cq *ibcq) 841 { 842 return container_of(ibcq, struct mlx5_ib_cq, ibcq); 843 } 844 845 static inline struct mlx5_ib_qp *to_mibqp(struct mlx5_core_qp *mqp) 846 { 847 return container_of(mqp, struct mlx5_ib_qp_base, mqp)->container_mibqp; 848 } 849 850 static inline struct mlx5_ib_rwq *to_mibrwq(struct mlx5_core_qp *core_qp) 851 { 852 return container_of(core_qp, struct mlx5_ib_rwq, core_qp); 853 } 854 855 static inline struct mlx5_ib_mr *to_mibmr(struct mlx5_core_mkey *mmkey) 856 { 857 return container_of(mmkey, struct mlx5_ib_mr, mmkey); 858 } 859 860 static inline struct mlx5_ib_pd *to_mpd(struct ib_pd *ibpd) 861 { 862 return container_of(ibpd, struct mlx5_ib_pd, ibpd); 863 } 864 865 static inline struct mlx5_ib_srq *to_msrq(struct ib_srq *ibsrq) 866 { 867 return container_of(ibsrq, struct mlx5_ib_srq, ibsrq); 868 } 869 870 static inline struct mlx5_ib_qp *to_mqp(struct ib_qp *ibqp) 871 { 872 return container_of(ibqp, struct mlx5_ib_qp, ibqp); 873 } 874 875 static inline struct mlx5_ib_rwq *to_mrwq(struct ib_wq *ibwq) 876 { 877 return container_of(ibwq, struct mlx5_ib_rwq, ibwq); 878 } 879 880 static inline struct mlx5_ib_rwq_ind_table *to_mrwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) 881 { 882 return container_of(ib_rwq_ind_tbl, struct mlx5_ib_rwq_ind_table, ib_rwq_ind_tbl); 883 } 884 885 static inline struct mlx5_ib_srq *to_mibsrq(struct mlx5_core_srq *msrq) 886 { 887 return container_of(msrq, struct mlx5_ib_srq, msrq); 888 } 889 890 static inline struct mlx5_ib_mr *to_mmr(struct ib_mr *ibmr) 891 { 892 return container_of(ibmr, struct mlx5_ib_mr, ibmr); 893 } 894 895 static inline struct mlx5_ib_mw *to_mmw(struct ib_mw *ibmw) 896 { 897 return container_of(ibmw, struct mlx5_ib_mw, ibmw); 898 } 899 900 int mlx5_ib_db_map_user(struct mlx5_ib_ucontext *context, unsigned long virt, 901 struct mlx5_db *db); 902 void mlx5_ib_db_unmap_user(struct mlx5_ib_ucontext *context, struct mlx5_db *db); 903 void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); 904 void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); 905 void mlx5_ib_free_srq_wqe(struct mlx5_ib_srq *srq, int wqe_index); 906 int mlx5_MAD_IFC(struct mlx5_ib_dev *dev, int ignore_mkey, int ignore_bkey, 907 u8 port, const struct ib_wc *in_wc, const struct ib_grh *in_grh, 908 const void *in_mad, void *response_mad); 909 struct ib_ah *mlx5_ib_create_ah(struct ib_pd *pd, struct rdma_ah_attr *ah_attr, 910 struct ib_udata *udata); 911 int mlx5_ib_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr); 912 int mlx5_ib_destroy_ah(struct ib_ah *ah); 913 struct ib_srq *mlx5_ib_create_srq(struct ib_pd *pd, 914 struct ib_srq_init_attr *init_attr, 915 struct ib_udata *udata); 916 int mlx5_ib_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr, 917 enum ib_srq_attr_mask attr_mask, struct ib_udata *udata); 918 int mlx5_ib_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr); 919 int mlx5_ib_destroy_srq(struct ib_srq *srq); 920 int mlx5_ib_post_srq_recv(struct ib_srq *ibsrq, struct ib_recv_wr *wr, 921 struct ib_recv_wr **bad_wr); 922 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, 923 struct ib_qp_init_attr *init_attr, 924 struct ib_udata *udata); 925 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 926 int attr_mask, struct ib_udata *udata); 927 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask, 928 struct ib_qp_init_attr *qp_init_attr); 929 int mlx5_ib_destroy_qp(struct ib_qp *qp); 930 int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, 931 struct ib_send_wr **bad_wr); 932 int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr, 933 struct ib_recv_wr **bad_wr); 934 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n); 935 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index, 936 void *buffer, u32 length, 937 struct mlx5_ib_qp_base *base); 938 struct ib_cq *mlx5_ib_create_cq(struct ib_device *ibdev, 939 const struct ib_cq_init_attr *attr, 940 struct ib_ucontext *context, 941 struct ib_udata *udata); 942 int mlx5_ib_destroy_cq(struct ib_cq *cq); 943 int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc); 944 int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags); 945 int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period); 946 int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata); 947 struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc); 948 struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, 949 u64 virt_addr, int access_flags, 950 struct ib_udata *udata); 951 struct ib_mw *mlx5_ib_alloc_mw(struct ib_pd *pd, enum ib_mw_type type, 952 struct ib_udata *udata); 953 int mlx5_ib_dealloc_mw(struct ib_mw *mw); 954 int mlx5_ib_update_xlt(struct mlx5_ib_mr *mr, u64 idx, int npages, 955 int page_shift, int flags); 956 struct mlx5_ib_mr *mlx5_ib_alloc_implicit_mr(struct mlx5_ib_pd *pd, 957 int access_flags); 958 void mlx5_ib_free_implicit_mr(struct mlx5_ib_mr *mr); 959 int mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start, 960 u64 length, u64 virt_addr, int access_flags, 961 struct ib_pd *pd, struct ib_udata *udata); 962 int mlx5_ib_dereg_mr(struct ib_mr *ibmr); 963 struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd, 964 enum ib_mr_type mr_type, 965 u32 max_num_sg); 966 int mlx5_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, 967 unsigned int *sg_offset); 968 int mlx5_ib_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num, 969 const struct ib_wc *in_wc, const struct ib_grh *in_grh, 970 const struct ib_mad_hdr *in, size_t in_mad_size, 971 struct ib_mad_hdr *out, size_t *out_mad_size, 972 u16 *out_mad_pkey_index); 973 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev, 974 struct ib_ucontext *context, 975 struct ib_udata *udata); 976 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd); 977 int mlx5_ib_get_buf_offset(u64 addr, int page_shift, u32 *offset); 978 int mlx5_query_ext_port_caps(struct mlx5_ib_dev *dev, u8 port); 979 int mlx5_query_mad_ifc_smp_attr_node_info(struct ib_device *ibdev, 980 struct ib_smp *out_mad); 981 int mlx5_query_mad_ifc_system_image_guid(struct ib_device *ibdev, 982 __be64 *sys_image_guid); 983 int mlx5_query_mad_ifc_max_pkeys(struct ib_device *ibdev, 984 u16 *max_pkeys); 985 int mlx5_query_mad_ifc_vendor_id(struct ib_device *ibdev, 986 u32 *vendor_id); 987 int mlx5_query_mad_ifc_node_desc(struct mlx5_ib_dev *dev, char *node_desc); 988 int mlx5_query_mad_ifc_node_guid(struct mlx5_ib_dev *dev, __be64 *node_guid); 989 int mlx5_query_mad_ifc_pkey(struct ib_device *ibdev, u8 port, u16 index, 990 u16 *pkey); 991 int mlx5_query_mad_ifc_gids(struct ib_device *ibdev, u8 port, int index, 992 union ib_gid *gid); 993 int mlx5_query_mad_ifc_port(struct ib_device *ibdev, u8 port, 994 struct ib_port_attr *props); 995 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, 996 struct ib_port_attr *props); 997 int mlx5_ib_init_fmr(struct mlx5_ib_dev *dev); 998 void mlx5_ib_cleanup_fmr(struct mlx5_ib_dev *dev); 999 void mlx5_ib_cont_pages(struct ib_umem *umem, u64 addr, 1000 unsigned long max_page_shift, 1001 int *count, int *shift, 1002 int *ncont, int *order); 1003 void __mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem, 1004 int page_shift, size_t offset, size_t num_pages, 1005 __be64 *pas, int access_flags); 1006 void mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem, 1007 int page_shift, __be64 *pas, int access_flags); 1008 void mlx5_ib_copy_pas(u64 *old, u64 *new, int step, int num); 1009 int mlx5_ib_get_cqe_size(struct mlx5_ib_dev *dev, struct ib_cq *ibcq); 1010 int mlx5_mr_cache_init(struct mlx5_ib_dev *dev); 1011 int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev); 1012 1013 struct mlx5_ib_mr *mlx5_mr_cache_alloc(struct mlx5_ib_dev *dev, int entry); 1014 void mlx5_mr_cache_free(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr); 1015 int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask, 1016 struct ib_mr_status *mr_status); 1017 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, 1018 struct ib_wq_init_attr *init_attr, 1019 struct ib_udata *udata); 1020 int mlx5_ib_destroy_wq(struct ib_wq *wq); 1021 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, 1022 u32 wq_attr_mask, struct ib_udata *udata); 1023 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device, 1024 struct ib_rwq_ind_table_init_attr *init_attr, 1025 struct ib_udata *udata); 1026 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *wq_ind_table); 1027 bool mlx5_ib_dc_atomic_is_supported(struct mlx5_ib_dev *dev); 1028 1029 1030 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 1031 void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev); 1032 void mlx5_ib_pfault(struct mlx5_core_dev *mdev, void *context, 1033 struct mlx5_pagefault *pfault); 1034 int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev); 1035 int __init mlx5_ib_odp_init(void); 1036 void mlx5_ib_odp_cleanup(void); 1037 void mlx5_ib_invalidate_range(struct ib_umem *umem, unsigned long start, 1038 unsigned long end); 1039 void mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent *ent); 1040 void mlx5_odp_populate_klm(struct mlx5_klm *pklm, size_t offset, 1041 size_t nentries, struct mlx5_ib_mr *mr, int flags); 1042 #else /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ 1043 static inline void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev) 1044 { 1045 return; 1046 } 1047 1048 static inline int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev) { return 0; } 1049 static inline int mlx5_ib_odp_init(void) { return 0; } 1050 static inline void mlx5_ib_odp_cleanup(void) {} 1051 static inline void mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent *ent) {} 1052 static inline void mlx5_odp_populate_klm(struct mlx5_klm *pklm, size_t offset, 1053 size_t nentries, struct mlx5_ib_mr *mr, 1054 int flags) {} 1055 1056 #endif /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ 1057 1058 /* Needed for rep profile */ 1059 int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev); 1060 void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev); 1061 int mlx5_ib_stage_rep_flow_db_init(struct mlx5_ib_dev *dev); 1062 int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev); 1063 int mlx5_ib_stage_rep_non_default_cb(struct mlx5_ib_dev *dev); 1064 int mlx5_ib_stage_rep_roce_init(struct mlx5_ib_dev *dev); 1065 void mlx5_ib_stage_rep_roce_cleanup(struct mlx5_ib_dev *dev); 1066 int mlx5_ib_stage_dev_res_init(struct mlx5_ib_dev *dev); 1067 void mlx5_ib_stage_dev_res_cleanup(struct mlx5_ib_dev *dev); 1068 int mlx5_ib_stage_counters_init(struct mlx5_ib_dev *dev); 1069 void mlx5_ib_stage_counters_cleanup(struct mlx5_ib_dev *dev); 1070 int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev); 1071 void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev); 1072 void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev); 1073 int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev); 1074 void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev); 1075 int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev); 1076 int mlx5_ib_stage_class_attr_init(struct mlx5_ib_dev *dev); 1077 void __mlx5_ib_remove(struct mlx5_ib_dev *dev, 1078 const struct mlx5_ib_profile *profile, 1079 int stage); 1080 void *__mlx5_ib_add(struct mlx5_ib_dev *dev, 1081 const struct mlx5_ib_profile *profile); 1082 1083 int mlx5_ib_get_vf_config(struct ib_device *device, int vf, 1084 u8 port, struct ifla_vf_info *info); 1085 int mlx5_ib_set_vf_link_state(struct ib_device *device, int vf, 1086 u8 port, int state); 1087 int mlx5_ib_get_vf_stats(struct ib_device *device, int vf, 1088 u8 port, struct ifla_vf_stats *stats); 1089 int mlx5_ib_set_vf_guid(struct ib_device *device, int vf, u8 port, 1090 u64 guid, int type); 1091 1092 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num, 1093 int index); 1094 int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port_num, 1095 int index, enum ib_gid_type *gid_type); 1096 1097 void mlx5_ib_cleanup_cong_debugfs(struct mlx5_ib_dev *dev, u8 port_num); 1098 int mlx5_ib_init_cong_debugfs(struct mlx5_ib_dev *dev, u8 port_num); 1099 1100 /* GSI QP helper functions */ 1101 struct ib_qp *mlx5_ib_gsi_create_qp(struct ib_pd *pd, 1102 struct ib_qp_init_attr *init_attr); 1103 int mlx5_ib_gsi_destroy_qp(struct ib_qp *qp); 1104 int mlx5_ib_gsi_modify_qp(struct ib_qp *qp, struct ib_qp_attr *attr, 1105 int attr_mask); 1106 int mlx5_ib_gsi_query_qp(struct ib_qp *qp, struct ib_qp_attr *qp_attr, 1107 int qp_attr_mask, 1108 struct ib_qp_init_attr *qp_init_attr); 1109 int mlx5_ib_gsi_post_send(struct ib_qp *qp, struct ib_send_wr *wr, 1110 struct ib_send_wr **bad_wr); 1111 int mlx5_ib_gsi_post_recv(struct ib_qp *qp, struct ib_recv_wr *wr, 1112 struct ib_recv_wr **bad_wr); 1113 void mlx5_ib_gsi_pkey_change(struct mlx5_ib_gsi_qp *gsi); 1114 1115 int mlx5_ib_generate_wc(struct ib_cq *ibcq, struct ib_wc *wc); 1116 1117 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, 1118 int bfregn); 1119 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi); 1120 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *dev, 1121 u8 ib_port_num, 1122 u8 *native_port_num); 1123 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *dev, 1124 u8 port_num); 1125 1126 static inline void init_query_mad(struct ib_smp *mad) 1127 { 1128 mad->base_version = 1; 1129 mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED; 1130 mad->class_version = 1; 1131 mad->method = IB_MGMT_METHOD_GET; 1132 } 1133 1134 static inline u8 convert_access(int acc) 1135 { 1136 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) | 1137 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) | 1138 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) | 1139 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) | 1140 MLX5_PERM_LOCAL_READ; 1141 } 1142 1143 static inline int is_qp1(enum ib_qp_type qp_type) 1144 { 1145 return qp_type == MLX5_IB_QPT_HW_GSI; 1146 } 1147 1148 #define MLX5_MAX_UMR_SHIFT 16 1149 #define MLX5_MAX_UMR_PAGES (1 << MLX5_MAX_UMR_SHIFT) 1150 1151 static inline u32 check_cq_create_flags(u32 flags) 1152 { 1153 /* 1154 * It returns non-zero value for unsupported CQ 1155 * create flags, otherwise it returns zero. 1156 */ 1157 return (flags & ~(IB_UVERBS_CQ_FLAGS_IGNORE_OVERRUN | 1158 IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION)); 1159 } 1160 1161 static inline int verify_assign_uidx(u8 cqe_version, u32 cmd_uidx, 1162 u32 *user_index) 1163 { 1164 if (cqe_version) { 1165 if ((cmd_uidx == MLX5_IB_DEFAULT_UIDX) || 1166 (cmd_uidx & ~MLX5_USER_ASSIGNED_UIDX_MASK)) 1167 return -EINVAL; 1168 *user_index = cmd_uidx; 1169 } else { 1170 *user_index = MLX5_IB_DEFAULT_UIDX; 1171 } 1172 1173 return 0; 1174 } 1175 1176 static inline int get_qp_user_index(struct mlx5_ib_ucontext *ucontext, 1177 struct mlx5_ib_create_qp *ucmd, 1178 int inlen, 1179 u32 *user_index) 1180 { 1181 u8 cqe_version = ucontext->cqe_version; 1182 1183 if (field_avail(struct mlx5_ib_create_qp, uidx, inlen) && 1184 !cqe_version && (ucmd->uidx == MLX5_IB_DEFAULT_UIDX)) 1185 return 0; 1186 1187 if (!!(field_avail(struct mlx5_ib_create_qp, uidx, inlen) != 1188 !!cqe_version)) 1189 return -EINVAL; 1190 1191 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index); 1192 } 1193 1194 static inline int get_srq_user_index(struct mlx5_ib_ucontext *ucontext, 1195 struct mlx5_ib_create_srq *ucmd, 1196 int inlen, 1197 u32 *user_index) 1198 { 1199 u8 cqe_version = ucontext->cqe_version; 1200 1201 if (field_avail(struct mlx5_ib_create_srq, uidx, inlen) && 1202 !cqe_version && (ucmd->uidx == MLX5_IB_DEFAULT_UIDX)) 1203 return 0; 1204 1205 if (!!(field_avail(struct mlx5_ib_create_srq, uidx, inlen) != 1206 !!cqe_version)) 1207 return -EINVAL; 1208 1209 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index); 1210 } 1211 1212 static inline int get_uars_per_sys_page(struct mlx5_ib_dev *dev, bool lib_support) 1213 { 1214 return lib_support && MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1215 MLX5_UARS_IN_PAGE : 1; 1216 } 1217 1218 static inline int get_num_static_uars(struct mlx5_ib_dev *dev, 1219 struct mlx5_bfreg_info *bfregi) 1220 { 1221 return get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * bfregi->num_static_sys_pages; 1222 } 1223 1224 #endif /* MLX5_IB_H */ 1225