1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 }; 64 65 enum { 66 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0, 67 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1, 68 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2, 69 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3 70 }; 71 72 enum { 73 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 74 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 75 }; 76 77 enum { 78 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 79 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 80 MLX5_CMD_OP_INIT_HCA = 0x102, 81 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 82 MLX5_CMD_OP_ENABLE_HCA = 0x104, 83 MLX5_CMD_OP_DISABLE_HCA = 0x105, 84 MLX5_CMD_OP_QUERY_PAGES = 0x107, 85 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 86 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 87 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 88 MLX5_CMD_OP_SET_ISSI = 0x10b, 89 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 90 MLX5_CMD_OP_CREATE_MKEY = 0x200, 91 MLX5_CMD_OP_QUERY_MKEY = 0x201, 92 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 93 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 94 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 95 MLX5_CMD_OP_CREATE_EQ = 0x301, 96 MLX5_CMD_OP_DESTROY_EQ = 0x302, 97 MLX5_CMD_OP_QUERY_EQ = 0x303, 98 MLX5_CMD_OP_GEN_EQE = 0x304, 99 MLX5_CMD_OP_CREATE_CQ = 0x400, 100 MLX5_CMD_OP_DESTROY_CQ = 0x401, 101 MLX5_CMD_OP_QUERY_CQ = 0x402, 102 MLX5_CMD_OP_MODIFY_CQ = 0x403, 103 MLX5_CMD_OP_CREATE_QP = 0x500, 104 MLX5_CMD_OP_DESTROY_QP = 0x501, 105 MLX5_CMD_OP_RST2INIT_QP = 0x502, 106 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 107 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 108 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 109 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 110 MLX5_CMD_OP_2ERR_QP = 0x507, 111 MLX5_CMD_OP_2RST_QP = 0x50a, 112 MLX5_CMD_OP_QUERY_QP = 0x50b, 113 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 114 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 115 MLX5_CMD_OP_CREATE_PSV = 0x600, 116 MLX5_CMD_OP_DESTROY_PSV = 0x601, 117 MLX5_CMD_OP_CREATE_SRQ = 0x700, 118 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 119 MLX5_CMD_OP_QUERY_SRQ = 0x702, 120 MLX5_CMD_OP_ARM_RQ = 0x703, 121 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 122 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 123 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 124 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 125 MLX5_CMD_OP_CREATE_DCT = 0x710, 126 MLX5_CMD_OP_DESTROY_DCT = 0x711, 127 MLX5_CMD_OP_DRAIN_DCT = 0x712, 128 MLX5_CMD_OP_QUERY_DCT = 0x713, 129 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 130 MLX5_CMD_OP_CREATE_XRQ = 0x717, 131 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 132 MLX5_CMD_OP_QUERY_XRQ = 0x719, 133 MLX5_CMD_OP_ARM_XRQ = 0x71a, 134 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 135 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 136 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 137 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 138 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 139 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 140 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 141 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 142 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 143 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 144 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 145 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 146 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 147 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 148 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 149 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 150 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 151 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 152 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 153 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 154 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 155 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 156 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 157 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 158 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 159 MLX5_CMD_OP_ALLOC_PD = 0x800, 160 MLX5_CMD_OP_DEALLOC_PD = 0x801, 161 MLX5_CMD_OP_ALLOC_UAR = 0x802, 162 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 163 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 164 MLX5_CMD_OP_ACCESS_REG = 0x805, 165 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 166 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 167 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 168 MLX5_CMD_OP_MAD_IFC = 0x50d, 169 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 170 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 171 MLX5_CMD_OP_NOP = 0x80d, 172 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 173 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 174 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 175 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 176 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 177 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 178 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 179 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 180 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 181 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 182 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 183 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 184 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 185 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 186 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 187 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 188 MLX5_CMD_OP_CREATE_LAG = 0x840, 189 MLX5_CMD_OP_MODIFY_LAG = 0x841, 190 MLX5_CMD_OP_QUERY_LAG = 0x842, 191 MLX5_CMD_OP_DESTROY_LAG = 0x843, 192 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 193 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 194 MLX5_CMD_OP_CREATE_TIR = 0x900, 195 MLX5_CMD_OP_MODIFY_TIR = 0x901, 196 MLX5_CMD_OP_DESTROY_TIR = 0x902, 197 MLX5_CMD_OP_QUERY_TIR = 0x903, 198 MLX5_CMD_OP_CREATE_SQ = 0x904, 199 MLX5_CMD_OP_MODIFY_SQ = 0x905, 200 MLX5_CMD_OP_DESTROY_SQ = 0x906, 201 MLX5_CMD_OP_QUERY_SQ = 0x907, 202 MLX5_CMD_OP_CREATE_RQ = 0x908, 203 MLX5_CMD_OP_MODIFY_RQ = 0x909, 204 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 205 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 206 MLX5_CMD_OP_QUERY_RQ = 0x90b, 207 MLX5_CMD_OP_CREATE_RMP = 0x90c, 208 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 209 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 210 MLX5_CMD_OP_QUERY_RMP = 0x90f, 211 MLX5_CMD_OP_CREATE_TIS = 0x912, 212 MLX5_CMD_OP_MODIFY_TIS = 0x913, 213 MLX5_CMD_OP_DESTROY_TIS = 0x914, 214 MLX5_CMD_OP_QUERY_TIS = 0x915, 215 MLX5_CMD_OP_CREATE_RQT = 0x916, 216 MLX5_CMD_OP_MODIFY_RQT = 0x917, 217 MLX5_CMD_OP_DESTROY_RQT = 0x918, 218 MLX5_CMD_OP_QUERY_RQT = 0x919, 219 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 220 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 221 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 222 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 223 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 224 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 225 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 226 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 227 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 228 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 229 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 230 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 231 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 232 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 233 MLX5_CMD_OP_ALLOC_ENCAP_HEADER = 0x93d, 234 MLX5_CMD_OP_DEALLOC_ENCAP_HEADER = 0x93e, 235 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 236 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 237 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 238 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 239 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 240 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 241 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 242 MLX5_CMD_OP_MAX 243 }; 244 245 struct mlx5_ifc_flow_table_fields_supported_bits { 246 u8 outer_dmac[0x1]; 247 u8 outer_smac[0x1]; 248 u8 outer_ether_type[0x1]; 249 u8 outer_ip_version[0x1]; 250 u8 outer_first_prio[0x1]; 251 u8 outer_first_cfi[0x1]; 252 u8 outer_first_vid[0x1]; 253 u8 outer_ipv4_ttl[0x1]; 254 u8 outer_second_prio[0x1]; 255 u8 outer_second_cfi[0x1]; 256 u8 outer_second_vid[0x1]; 257 u8 reserved_at_b[0x1]; 258 u8 outer_sip[0x1]; 259 u8 outer_dip[0x1]; 260 u8 outer_frag[0x1]; 261 u8 outer_ip_protocol[0x1]; 262 u8 outer_ip_ecn[0x1]; 263 u8 outer_ip_dscp[0x1]; 264 u8 outer_udp_sport[0x1]; 265 u8 outer_udp_dport[0x1]; 266 u8 outer_tcp_sport[0x1]; 267 u8 outer_tcp_dport[0x1]; 268 u8 outer_tcp_flags[0x1]; 269 u8 outer_gre_protocol[0x1]; 270 u8 outer_gre_key[0x1]; 271 u8 outer_vxlan_vni[0x1]; 272 u8 reserved_at_1a[0x5]; 273 u8 source_eswitch_port[0x1]; 274 275 u8 inner_dmac[0x1]; 276 u8 inner_smac[0x1]; 277 u8 inner_ether_type[0x1]; 278 u8 inner_ip_version[0x1]; 279 u8 inner_first_prio[0x1]; 280 u8 inner_first_cfi[0x1]; 281 u8 inner_first_vid[0x1]; 282 u8 reserved_at_27[0x1]; 283 u8 inner_second_prio[0x1]; 284 u8 inner_second_cfi[0x1]; 285 u8 inner_second_vid[0x1]; 286 u8 reserved_at_2b[0x1]; 287 u8 inner_sip[0x1]; 288 u8 inner_dip[0x1]; 289 u8 inner_frag[0x1]; 290 u8 inner_ip_protocol[0x1]; 291 u8 inner_ip_ecn[0x1]; 292 u8 inner_ip_dscp[0x1]; 293 u8 inner_udp_sport[0x1]; 294 u8 inner_udp_dport[0x1]; 295 u8 inner_tcp_sport[0x1]; 296 u8 inner_tcp_dport[0x1]; 297 u8 inner_tcp_flags[0x1]; 298 u8 reserved_at_37[0x9]; 299 u8 reserved_at_40[0x17]; 300 u8 outer_esp_spi[0x1]; 301 u8 reserved_at_58[0x2]; 302 u8 bth_dst_qp[0x1]; 303 304 u8 reserved_at_5b[0x25]; 305 }; 306 307 struct mlx5_ifc_flow_table_prop_layout_bits { 308 u8 ft_support[0x1]; 309 u8 reserved_at_1[0x1]; 310 u8 flow_counter[0x1]; 311 u8 flow_modify_en[0x1]; 312 u8 modify_root[0x1]; 313 u8 identified_miss_table_mode[0x1]; 314 u8 flow_table_modify[0x1]; 315 u8 encap[0x1]; 316 u8 decap[0x1]; 317 u8 reserved_at_9[0x1]; 318 u8 pop_vlan[0x1]; 319 u8 push_vlan[0x1]; 320 u8 reserved_at_c[0x14]; 321 322 u8 reserved_at_20[0x2]; 323 u8 log_max_ft_size[0x6]; 324 u8 log_max_modify_header_context[0x8]; 325 u8 max_modify_header_actions[0x8]; 326 u8 max_ft_level[0x8]; 327 328 u8 reserved_at_40[0x20]; 329 330 u8 reserved_at_60[0x18]; 331 u8 log_max_ft_num[0x8]; 332 333 u8 reserved_at_80[0x18]; 334 u8 log_max_destination[0x8]; 335 336 u8 log_max_flow_counter[0x8]; 337 u8 reserved_at_a8[0x10]; 338 u8 log_max_flow[0x8]; 339 340 u8 reserved_at_c0[0x40]; 341 342 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 343 344 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 345 }; 346 347 struct mlx5_ifc_odp_per_transport_service_cap_bits { 348 u8 send[0x1]; 349 u8 receive[0x1]; 350 u8 write[0x1]; 351 u8 read[0x1]; 352 u8 atomic[0x1]; 353 u8 srq_receive[0x1]; 354 u8 reserved_at_6[0x1a]; 355 }; 356 357 struct mlx5_ifc_ipv4_layout_bits { 358 u8 reserved_at_0[0x60]; 359 360 u8 ipv4[0x20]; 361 }; 362 363 struct mlx5_ifc_ipv6_layout_bits { 364 u8 ipv6[16][0x8]; 365 }; 366 367 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 368 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 369 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 370 u8 reserved_at_0[0x80]; 371 }; 372 373 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 374 u8 smac_47_16[0x20]; 375 376 u8 smac_15_0[0x10]; 377 u8 ethertype[0x10]; 378 379 u8 dmac_47_16[0x20]; 380 381 u8 dmac_15_0[0x10]; 382 u8 first_prio[0x3]; 383 u8 first_cfi[0x1]; 384 u8 first_vid[0xc]; 385 386 u8 ip_protocol[0x8]; 387 u8 ip_dscp[0x6]; 388 u8 ip_ecn[0x2]; 389 u8 cvlan_tag[0x1]; 390 u8 svlan_tag[0x1]; 391 u8 frag[0x1]; 392 u8 ip_version[0x4]; 393 u8 tcp_flags[0x9]; 394 395 u8 tcp_sport[0x10]; 396 u8 tcp_dport[0x10]; 397 398 u8 reserved_at_c0[0x18]; 399 u8 ttl_hoplimit[0x8]; 400 401 u8 udp_sport[0x10]; 402 u8 udp_dport[0x10]; 403 404 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 405 406 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 407 }; 408 409 struct mlx5_ifc_fte_match_set_misc_bits { 410 u8 reserved_at_0[0x8]; 411 u8 source_sqn[0x18]; 412 413 u8 reserved_at_20[0x10]; 414 u8 source_port[0x10]; 415 416 u8 outer_second_prio[0x3]; 417 u8 outer_second_cfi[0x1]; 418 u8 outer_second_vid[0xc]; 419 u8 inner_second_prio[0x3]; 420 u8 inner_second_cfi[0x1]; 421 u8 inner_second_vid[0xc]; 422 423 u8 outer_second_cvlan_tag[0x1]; 424 u8 inner_second_cvlan_tag[0x1]; 425 u8 outer_second_svlan_tag[0x1]; 426 u8 inner_second_svlan_tag[0x1]; 427 u8 reserved_at_64[0xc]; 428 u8 gre_protocol[0x10]; 429 430 u8 gre_key_h[0x18]; 431 u8 gre_key_l[0x8]; 432 433 u8 vxlan_vni[0x18]; 434 u8 reserved_at_b8[0x8]; 435 436 u8 reserved_at_c0[0x20]; 437 438 u8 reserved_at_e0[0xc]; 439 u8 outer_ipv6_flow_label[0x14]; 440 441 u8 reserved_at_100[0xc]; 442 u8 inner_ipv6_flow_label[0x14]; 443 444 u8 reserved_at_120[0x28]; 445 u8 bth_dst_qp[0x18]; 446 u8 reserved_at_160[0x20]; 447 u8 outer_esp_spi[0x20]; 448 u8 reserved_at_1a0[0x60]; 449 }; 450 451 struct mlx5_ifc_cmd_pas_bits { 452 u8 pa_h[0x20]; 453 454 u8 pa_l[0x14]; 455 u8 reserved_at_34[0xc]; 456 }; 457 458 struct mlx5_ifc_uint64_bits { 459 u8 hi[0x20]; 460 461 u8 lo[0x20]; 462 }; 463 464 enum { 465 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 466 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 467 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 468 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 469 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 470 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 471 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 472 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 473 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 474 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 475 }; 476 477 struct mlx5_ifc_ads_bits { 478 u8 fl[0x1]; 479 u8 free_ar[0x1]; 480 u8 reserved_at_2[0xe]; 481 u8 pkey_index[0x10]; 482 483 u8 reserved_at_20[0x8]; 484 u8 grh[0x1]; 485 u8 mlid[0x7]; 486 u8 rlid[0x10]; 487 488 u8 ack_timeout[0x5]; 489 u8 reserved_at_45[0x3]; 490 u8 src_addr_index[0x8]; 491 u8 reserved_at_50[0x4]; 492 u8 stat_rate[0x4]; 493 u8 hop_limit[0x8]; 494 495 u8 reserved_at_60[0x4]; 496 u8 tclass[0x8]; 497 u8 flow_label[0x14]; 498 499 u8 rgid_rip[16][0x8]; 500 501 u8 reserved_at_100[0x4]; 502 u8 f_dscp[0x1]; 503 u8 f_ecn[0x1]; 504 u8 reserved_at_106[0x1]; 505 u8 f_eth_prio[0x1]; 506 u8 ecn[0x2]; 507 u8 dscp[0x6]; 508 u8 udp_sport[0x10]; 509 510 u8 dei_cfi[0x1]; 511 u8 eth_prio[0x3]; 512 u8 sl[0x4]; 513 u8 vhca_port_num[0x8]; 514 u8 rmac_47_32[0x10]; 515 516 u8 rmac_31_0[0x20]; 517 }; 518 519 struct mlx5_ifc_flow_table_nic_cap_bits { 520 u8 nic_rx_multi_path_tirs[0x1]; 521 u8 nic_rx_multi_path_tirs_fts[0x1]; 522 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 523 u8 reserved_at_3[0x1fd]; 524 525 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 526 527 u8 reserved_at_400[0x200]; 528 529 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 530 531 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 532 533 u8 reserved_at_a00[0x200]; 534 535 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 536 537 u8 reserved_at_e00[0x7200]; 538 }; 539 540 struct mlx5_ifc_flow_table_eswitch_cap_bits { 541 u8 reserved_at_0[0x200]; 542 543 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 544 545 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 546 547 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 548 549 u8 reserved_at_800[0x7800]; 550 }; 551 552 struct mlx5_ifc_e_switch_cap_bits { 553 u8 vport_svlan_strip[0x1]; 554 u8 vport_cvlan_strip[0x1]; 555 u8 vport_svlan_insert[0x1]; 556 u8 vport_cvlan_insert_if_not_exist[0x1]; 557 u8 vport_cvlan_insert_overwrite[0x1]; 558 u8 reserved_at_5[0x19]; 559 u8 nic_vport_node_guid_modify[0x1]; 560 u8 nic_vport_port_guid_modify[0x1]; 561 562 u8 vxlan_encap_decap[0x1]; 563 u8 nvgre_encap_decap[0x1]; 564 u8 reserved_at_22[0x9]; 565 u8 log_max_encap_headers[0x5]; 566 u8 reserved_2b[0x6]; 567 u8 max_encap_header_size[0xa]; 568 569 u8 reserved_40[0x7c0]; 570 571 }; 572 573 struct mlx5_ifc_qos_cap_bits { 574 u8 packet_pacing[0x1]; 575 u8 esw_scheduling[0x1]; 576 u8 esw_bw_share[0x1]; 577 u8 esw_rate_limit[0x1]; 578 u8 reserved_at_4[0x1c]; 579 580 u8 reserved_at_20[0x20]; 581 582 u8 packet_pacing_max_rate[0x20]; 583 584 u8 packet_pacing_min_rate[0x20]; 585 586 u8 reserved_at_80[0x10]; 587 u8 packet_pacing_rate_table_size[0x10]; 588 589 u8 esw_element_type[0x10]; 590 u8 esw_tsar_type[0x10]; 591 592 u8 reserved_at_c0[0x10]; 593 u8 max_qos_para_vport[0x10]; 594 595 u8 max_tsar_bw_share[0x20]; 596 597 u8 reserved_at_100[0x700]; 598 }; 599 600 struct mlx5_ifc_debug_cap_bits { 601 u8 reserved_at_0[0x20]; 602 603 u8 reserved_at_20[0x2]; 604 u8 stall_detect[0x1]; 605 u8 reserved_at_23[0x1d]; 606 607 u8 reserved_at_40[0x7c0]; 608 }; 609 610 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 611 u8 csum_cap[0x1]; 612 u8 vlan_cap[0x1]; 613 u8 lro_cap[0x1]; 614 u8 lro_psh_flag[0x1]; 615 u8 lro_time_stamp[0x1]; 616 u8 reserved_at_5[0x2]; 617 u8 wqe_vlan_insert[0x1]; 618 u8 self_lb_en_modifiable[0x1]; 619 u8 reserved_at_9[0x2]; 620 u8 max_lso_cap[0x5]; 621 u8 multi_pkt_send_wqe[0x2]; 622 u8 wqe_inline_mode[0x2]; 623 u8 rss_ind_tbl_cap[0x4]; 624 u8 reg_umr_sq[0x1]; 625 u8 scatter_fcs[0x1]; 626 u8 enhanced_multi_pkt_send_wqe[0x1]; 627 u8 tunnel_lso_const_out_ip_id[0x1]; 628 u8 reserved_at_1c[0x2]; 629 u8 tunnel_stateless_gre[0x1]; 630 u8 tunnel_stateless_vxlan[0x1]; 631 632 u8 swp[0x1]; 633 u8 swp_csum[0x1]; 634 u8 swp_lso[0x1]; 635 u8 reserved_at_23[0x1b]; 636 u8 max_geneve_opt_len[0x1]; 637 u8 tunnel_stateless_geneve_rx[0x1]; 638 639 u8 reserved_at_40[0x10]; 640 u8 lro_min_mss_size[0x10]; 641 642 u8 reserved_at_60[0x120]; 643 644 u8 lro_timer_supported_periods[4][0x20]; 645 646 u8 reserved_at_200[0x600]; 647 }; 648 649 struct mlx5_ifc_roce_cap_bits { 650 u8 roce_apm[0x1]; 651 u8 reserved_at_1[0x1f]; 652 653 u8 reserved_at_20[0x60]; 654 655 u8 reserved_at_80[0xc]; 656 u8 l3_type[0x4]; 657 u8 reserved_at_90[0x8]; 658 u8 roce_version[0x8]; 659 660 u8 reserved_at_a0[0x10]; 661 u8 r_roce_dest_udp_port[0x10]; 662 663 u8 r_roce_max_src_udp_port[0x10]; 664 u8 r_roce_min_src_udp_port[0x10]; 665 666 u8 reserved_at_e0[0x10]; 667 u8 roce_address_table_size[0x10]; 668 669 u8 reserved_at_100[0x700]; 670 }; 671 672 enum { 673 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 674 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 675 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 676 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 677 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 678 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 679 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 680 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 681 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 682 }; 683 684 enum { 685 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 686 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 687 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 688 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 689 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 690 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 691 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 692 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 693 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 694 }; 695 696 struct mlx5_ifc_atomic_caps_bits { 697 u8 reserved_at_0[0x40]; 698 699 u8 atomic_req_8B_endianness_mode[0x2]; 700 u8 reserved_at_42[0x4]; 701 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 702 703 u8 reserved_at_47[0x19]; 704 705 u8 reserved_at_60[0x20]; 706 707 u8 reserved_at_80[0x10]; 708 u8 atomic_operations[0x10]; 709 710 u8 reserved_at_a0[0x10]; 711 u8 atomic_size_qp[0x10]; 712 713 u8 reserved_at_c0[0x10]; 714 u8 atomic_size_dc[0x10]; 715 716 u8 reserved_at_e0[0x720]; 717 }; 718 719 struct mlx5_ifc_odp_cap_bits { 720 u8 reserved_at_0[0x40]; 721 722 u8 sig[0x1]; 723 u8 reserved_at_41[0x1f]; 724 725 u8 reserved_at_60[0x20]; 726 727 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 728 729 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 730 731 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 732 733 u8 reserved_at_e0[0x720]; 734 }; 735 736 struct mlx5_ifc_calc_op { 737 u8 reserved_at_0[0x10]; 738 u8 reserved_at_10[0x9]; 739 u8 op_swap_endianness[0x1]; 740 u8 op_min[0x1]; 741 u8 op_xor[0x1]; 742 u8 op_or[0x1]; 743 u8 op_and[0x1]; 744 u8 op_max[0x1]; 745 u8 op_add[0x1]; 746 }; 747 748 struct mlx5_ifc_vector_calc_cap_bits { 749 u8 calc_matrix[0x1]; 750 u8 reserved_at_1[0x1f]; 751 u8 reserved_at_20[0x8]; 752 u8 max_vec_count[0x8]; 753 u8 reserved_at_30[0xd]; 754 u8 max_chunk_size[0x3]; 755 struct mlx5_ifc_calc_op calc0; 756 struct mlx5_ifc_calc_op calc1; 757 struct mlx5_ifc_calc_op calc2; 758 struct mlx5_ifc_calc_op calc3; 759 760 u8 reserved_at_e0[0x720]; 761 }; 762 763 enum { 764 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 765 MLX5_WQ_TYPE_CYCLIC = 0x1, 766 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 767 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 768 }; 769 770 enum { 771 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 772 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 773 }; 774 775 enum { 776 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 777 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 778 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 779 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 780 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 781 }; 782 783 enum { 784 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 785 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 786 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 787 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 788 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 789 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 790 }; 791 792 enum { 793 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 794 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 795 }; 796 797 enum { 798 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 799 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 800 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 801 }; 802 803 enum { 804 MLX5_CAP_PORT_TYPE_IB = 0x0, 805 MLX5_CAP_PORT_TYPE_ETH = 0x1, 806 }; 807 808 enum { 809 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 810 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 811 MLX5_CAP_UMR_FENCE_NONE = 0x2, 812 }; 813 814 struct mlx5_ifc_cmd_hca_cap_bits { 815 u8 reserved_at_0[0x30]; 816 u8 vhca_id[0x10]; 817 818 u8 reserved_at_40[0x40]; 819 820 u8 log_max_srq_sz[0x8]; 821 u8 log_max_qp_sz[0x8]; 822 u8 reserved_at_90[0xb]; 823 u8 log_max_qp[0x5]; 824 825 u8 reserved_at_a0[0xb]; 826 u8 log_max_srq[0x5]; 827 u8 reserved_at_b0[0x10]; 828 829 u8 reserved_at_c0[0x8]; 830 u8 log_max_cq_sz[0x8]; 831 u8 reserved_at_d0[0xb]; 832 u8 log_max_cq[0x5]; 833 834 u8 log_max_eq_sz[0x8]; 835 u8 reserved_at_e8[0x2]; 836 u8 log_max_mkey[0x6]; 837 u8 reserved_at_f0[0xc]; 838 u8 log_max_eq[0x4]; 839 840 u8 max_indirection[0x8]; 841 u8 fixed_buffer_size[0x1]; 842 u8 log_max_mrw_sz[0x7]; 843 u8 force_teardown[0x1]; 844 u8 reserved_at_111[0x1]; 845 u8 log_max_bsf_list_size[0x6]; 846 u8 umr_extended_translation_offset[0x1]; 847 u8 null_mkey[0x1]; 848 u8 log_max_klm_list_size[0x6]; 849 850 u8 reserved_at_120[0xa]; 851 u8 log_max_ra_req_dc[0x6]; 852 u8 reserved_at_130[0xa]; 853 u8 log_max_ra_res_dc[0x6]; 854 855 u8 reserved_at_140[0xa]; 856 u8 log_max_ra_req_qp[0x6]; 857 u8 reserved_at_150[0xa]; 858 u8 log_max_ra_res_qp[0x6]; 859 860 u8 end_pad[0x1]; 861 u8 cc_query_allowed[0x1]; 862 u8 cc_modify_allowed[0x1]; 863 u8 start_pad[0x1]; 864 u8 cache_line_128byte[0x1]; 865 u8 reserved_at_165[0xa]; 866 u8 qcam_reg[0x1]; 867 u8 gid_table_size[0x10]; 868 869 u8 out_of_seq_cnt[0x1]; 870 u8 vport_counters[0x1]; 871 u8 retransmission_q_counters[0x1]; 872 u8 debug[0x1]; 873 u8 modify_rq_counter_set_id[0x1]; 874 u8 rq_delay_drop[0x1]; 875 u8 max_qp_cnt[0xa]; 876 u8 pkey_table_size[0x10]; 877 878 u8 vport_group_manager[0x1]; 879 u8 vhca_group_manager[0x1]; 880 u8 ib_virt[0x1]; 881 u8 eth_virt[0x1]; 882 u8 vnic_env_queue_counters[0x1]; 883 u8 ets[0x1]; 884 u8 nic_flow_table[0x1]; 885 u8 eswitch_flow_table[0x1]; 886 u8 early_vf_enable[0x1]; 887 u8 mcam_reg[0x1]; 888 u8 pcam_reg[0x1]; 889 u8 local_ca_ack_delay[0x5]; 890 u8 port_module_event[0x1]; 891 u8 enhanced_error_q_counters[0x1]; 892 u8 ports_check[0x1]; 893 u8 reserved_at_1b3[0x1]; 894 u8 disable_link_up[0x1]; 895 u8 beacon_led[0x1]; 896 u8 port_type[0x2]; 897 u8 num_ports[0x8]; 898 899 u8 reserved_at_1c0[0x1]; 900 u8 pps[0x1]; 901 u8 pps_modify[0x1]; 902 u8 log_max_msg[0x5]; 903 u8 reserved_at_1c8[0x4]; 904 u8 max_tc[0x4]; 905 u8 reserved_at_1d0[0x1]; 906 u8 dcbx[0x1]; 907 u8 general_notification_event[0x1]; 908 u8 reserved_at_1d3[0x2]; 909 u8 fpga[0x1]; 910 u8 rol_s[0x1]; 911 u8 rol_g[0x1]; 912 u8 reserved_at_1d8[0x1]; 913 u8 wol_s[0x1]; 914 u8 wol_g[0x1]; 915 u8 wol_a[0x1]; 916 u8 wol_b[0x1]; 917 u8 wol_m[0x1]; 918 u8 wol_u[0x1]; 919 u8 wol_p[0x1]; 920 921 u8 stat_rate_support[0x10]; 922 u8 reserved_at_1f0[0xc]; 923 u8 cqe_version[0x4]; 924 925 u8 compact_address_vector[0x1]; 926 u8 striding_rq[0x1]; 927 u8 reserved_at_202[0x1]; 928 u8 ipoib_enhanced_offloads[0x1]; 929 u8 ipoib_basic_offloads[0x1]; 930 u8 reserved_at_205[0x5]; 931 u8 umr_fence[0x2]; 932 u8 reserved_at_20c[0x3]; 933 u8 drain_sigerr[0x1]; 934 u8 cmdif_checksum[0x2]; 935 u8 sigerr_cqe[0x1]; 936 u8 reserved_at_213[0x1]; 937 u8 wq_signature[0x1]; 938 u8 sctr_data_cqe[0x1]; 939 u8 reserved_at_216[0x1]; 940 u8 sho[0x1]; 941 u8 tph[0x1]; 942 u8 rf[0x1]; 943 u8 dct[0x1]; 944 u8 qos[0x1]; 945 u8 eth_net_offloads[0x1]; 946 u8 roce[0x1]; 947 u8 atomic[0x1]; 948 u8 reserved_at_21f[0x1]; 949 950 u8 cq_oi[0x1]; 951 u8 cq_resize[0x1]; 952 u8 cq_moderation[0x1]; 953 u8 reserved_at_223[0x3]; 954 u8 cq_eq_remap[0x1]; 955 u8 pg[0x1]; 956 u8 block_lb_mc[0x1]; 957 u8 reserved_at_229[0x1]; 958 u8 scqe_break_moderation[0x1]; 959 u8 cq_period_start_from_cqe[0x1]; 960 u8 cd[0x1]; 961 u8 reserved_at_22d[0x1]; 962 u8 apm[0x1]; 963 u8 vector_calc[0x1]; 964 u8 umr_ptr_rlky[0x1]; 965 u8 imaicl[0x1]; 966 u8 reserved_at_232[0x4]; 967 u8 qkv[0x1]; 968 u8 pkv[0x1]; 969 u8 set_deth_sqpn[0x1]; 970 u8 reserved_at_239[0x3]; 971 u8 xrc[0x1]; 972 u8 ud[0x1]; 973 u8 uc[0x1]; 974 u8 rc[0x1]; 975 976 u8 uar_4k[0x1]; 977 u8 reserved_at_241[0x9]; 978 u8 uar_sz[0x6]; 979 u8 reserved_at_250[0x8]; 980 u8 log_pg_sz[0x8]; 981 982 u8 bf[0x1]; 983 u8 driver_version[0x1]; 984 u8 pad_tx_eth_packet[0x1]; 985 u8 reserved_at_263[0x8]; 986 u8 log_bf_reg_size[0x5]; 987 988 u8 reserved_at_270[0xb]; 989 u8 lag_master[0x1]; 990 u8 num_lag_ports[0x4]; 991 992 u8 reserved_at_280[0x10]; 993 u8 max_wqe_sz_sq[0x10]; 994 995 u8 reserved_at_2a0[0x10]; 996 u8 max_wqe_sz_rq[0x10]; 997 998 u8 max_flow_counter_31_16[0x10]; 999 u8 max_wqe_sz_sq_dc[0x10]; 1000 1001 u8 reserved_at_2e0[0x7]; 1002 u8 max_qp_mcg[0x19]; 1003 1004 u8 reserved_at_300[0x18]; 1005 u8 log_max_mcg[0x8]; 1006 1007 u8 reserved_at_320[0x3]; 1008 u8 log_max_transport_domain[0x5]; 1009 u8 reserved_at_328[0x3]; 1010 u8 log_max_pd[0x5]; 1011 u8 reserved_at_330[0xb]; 1012 u8 log_max_xrcd[0x5]; 1013 1014 u8 nic_receive_steering_discard[0x1]; 1015 u8 receive_discard_vport_down[0x1]; 1016 u8 transmit_discard_vport_down[0x1]; 1017 u8 reserved_at_343[0x5]; 1018 u8 log_max_flow_counter_bulk[0x8]; 1019 u8 max_flow_counter_15_0[0x10]; 1020 1021 1022 u8 reserved_at_360[0x3]; 1023 u8 log_max_rq[0x5]; 1024 u8 reserved_at_368[0x3]; 1025 u8 log_max_sq[0x5]; 1026 u8 reserved_at_370[0x3]; 1027 u8 log_max_tir[0x5]; 1028 u8 reserved_at_378[0x3]; 1029 u8 log_max_tis[0x5]; 1030 1031 u8 basic_cyclic_rcv_wqe[0x1]; 1032 u8 reserved_at_381[0x2]; 1033 u8 log_max_rmp[0x5]; 1034 u8 reserved_at_388[0x3]; 1035 u8 log_max_rqt[0x5]; 1036 u8 reserved_at_390[0x3]; 1037 u8 log_max_rqt_size[0x5]; 1038 u8 reserved_at_398[0x3]; 1039 u8 log_max_tis_per_sq[0x5]; 1040 1041 u8 ext_stride_num_range[0x1]; 1042 u8 reserved_at_3a1[0x2]; 1043 u8 log_max_stride_sz_rq[0x5]; 1044 u8 reserved_at_3a8[0x3]; 1045 u8 log_min_stride_sz_rq[0x5]; 1046 u8 reserved_at_3b0[0x3]; 1047 u8 log_max_stride_sz_sq[0x5]; 1048 u8 reserved_at_3b8[0x3]; 1049 u8 log_min_stride_sz_sq[0x5]; 1050 1051 u8 hairpin[0x1]; 1052 u8 reserved_at_3c1[0x2]; 1053 u8 log_max_hairpin_queues[0x5]; 1054 u8 reserved_at_3c8[0x3]; 1055 u8 log_max_hairpin_wq_data_sz[0x5]; 1056 u8 reserved_at_3d0[0x3]; 1057 u8 log_max_hairpin_num_packets[0x5]; 1058 u8 reserved_at_3d8[0x3]; 1059 u8 log_max_wq_sz[0x5]; 1060 1061 u8 nic_vport_change_event[0x1]; 1062 u8 disable_local_lb_uc[0x1]; 1063 u8 disable_local_lb_mc[0x1]; 1064 u8 log_min_hairpin_wq_data_sz[0x5]; 1065 u8 reserved_at_3e8[0x3]; 1066 u8 log_max_vlan_list[0x5]; 1067 u8 reserved_at_3f0[0x3]; 1068 u8 log_max_current_mc_list[0x5]; 1069 u8 reserved_at_3f8[0x3]; 1070 u8 log_max_current_uc_list[0x5]; 1071 1072 u8 reserved_at_400[0x80]; 1073 1074 u8 reserved_at_480[0x3]; 1075 u8 log_max_l2_table[0x5]; 1076 u8 reserved_at_488[0x8]; 1077 u8 log_uar_page_sz[0x10]; 1078 1079 u8 reserved_at_4a0[0x20]; 1080 u8 device_frequency_mhz[0x20]; 1081 u8 device_frequency_khz[0x20]; 1082 1083 u8 reserved_at_500[0x20]; 1084 u8 num_of_uars_per_page[0x20]; 1085 u8 reserved_at_540[0x40]; 1086 1087 u8 reserved_at_580[0x3d]; 1088 u8 cqe_128_always[0x1]; 1089 u8 cqe_compression_128[0x1]; 1090 u8 cqe_compression[0x1]; 1091 1092 u8 cqe_compression_timeout[0x10]; 1093 u8 cqe_compression_max_num[0x10]; 1094 1095 u8 reserved_at_5e0[0x10]; 1096 u8 tag_matching[0x1]; 1097 u8 rndv_offload_rc[0x1]; 1098 u8 rndv_offload_dc[0x1]; 1099 u8 log_tag_matching_list_sz[0x5]; 1100 u8 reserved_at_5f8[0x3]; 1101 u8 log_max_xrq[0x5]; 1102 1103 u8 affiliate_nic_vport_criteria[0x8]; 1104 u8 native_port_num[0x8]; 1105 u8 num_vhca_ports[0x8]; 1106 u8 reserved_at_618[0x6]; 1107 u8 sw_owner_id[0x1]; 1108 u8 reserved_at_61f[0x1e1]; 1109 }; 1110 1111 enum mlx5_flow_destination_type { 1112 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1113 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1114 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, 1115 1116 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99, 1117 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100, 1118 }; 1119 1120 struct mlx5_ifc_dest_format_struct_bits { 1121 u8 destination_type[0x8]; 1122 u8 destination_id[0x18]; 1123 1124 u8 reserved_at_20[0x20]; 1125 }; 1126 1127 struct mlx5_ifc_flow_counter_list_bits { 1128 u8 flow_counter_id[0x20]; 1129 1130 u8 reserved_at_20[0x20]; 1131 }; 1132 1133 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1134 struct mlx5_ifc_dest_format_struct_bits dest_format_struct; 1135 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1136 u8 reserved_at_0[0x40]; 1137 }; 1138 1139 struct mlx5_ifc_fte_match_param_bits { 1140 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1141 1142 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1143 1144 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1145 1146 u8 reserved_at_600[0xa00]; 1147 }; 1148 1149 enum { 1150 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1151 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1152 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1153 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1154 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1155 }; 1156 1157 struct mlx5_ifc_rx_hash_field_select_bits { 1158 u8 l3_prot_type[0x1]; 1159 u8 l4_prot_type[0x1]; 1160 u8 selected_fields[0x1e]; 1161 }; 1162 1163 enum { 1164 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 1165 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 1166 }; 1167 1168 enum { 1169 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 1170 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 1171 }; 1172 1173 struct mlx5_ifc_wq_bits { 1174 u8 wq_type[0x4]; 1175 u8 wq_signature[0x1]; 1176 u8 end_padding_mode[0x2]; 1177 u8 cd_slave[0x1]; 1178 u8 reserved_at_8[0x18]; 1179 1180 u8 hds_skip_first_sge[0x1]; 1181 u8 log2_hds_buf_size[0x3]; 1182 u8 reserved_at_24[0x7]; 1183 u8 page_offset[0x5]; 1184 u8 lwm[0x10]; 1185 1186 u8 reserved_at_40[0x8]; 1187 u8 pd[0x18]; 1188 1189 u8 reserved_at_60[0x8]; 1190 u8 uar_page[0x18]; 1191 1192 u8 dbr_addr[0x40]; 1193 1194 u8 hw_counter[0x20]; 1195 1196 u8 sw_counter[0x20]; 1197 1198 u8 reserved_at_100[0xc]; 1199 u8 log_wq_stride[0x4]; 1200 u8 reserved_at_110[0x3]; 1201 u8 log_wq_pg_sz[0x5]; 1202 u8 reserved_at_118[0x3]; 1203 u8 log_wq_sz[0x5]; 1204 1205 u8 reserved_at_120[0x3]; 1206 u8 log_hairpin_num_packets[0x5]; 1207 u8 reserved_at_128[0x3]; 1208 u8 log_hairpin_data_sz[0x5]; 1209 1210 u8 reserved_at_130[0x4]; 1211 u8 log_wqe_num_of_strides[0x4]; 1212 u8 two_byte_shift_en[0x1]; 1213 u8 reserved_at_139[0x4]; 1214 u8 log_wqe_stride_size[0x3]; 1215 1216 u8 reserved_at_140[0x4c0]; 1217 1218 struct mlx5_ifc_cmd_pas_bits pas[0]; 1219 }; 1220 1221 struct mlx5_ifc_rq_num_bits { 1222 u8 reserved_at_0[0x8]; 1223 u8 rq_num[0x18]; 1224 }; 1225 1226 struct mlx5_ifc_mac_address_layout_bits { 1227 u8 reserved_at_0[0x10]; 1228 u8 mac_addr_47_32[0x10]; 1229 1230 u8 mac_addr_31_0[0x20]; 1231 }; 1232 1233 struct mlx5_ifc_vlan_layout_bits { 1234 u8 reserved_at_0[0x14]; 1235 u8 vlan[0x0c]; 1236 1237 u8 reserved_at_20[0x20]; 1238 }; 1239 1240 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 1241 u8 reserved_at_0[0xa0]; 1242 1243 u8 min_time_between_cnps[0x20]; 1244 1245 u8 reserved_at_c0[0x12]; 1246 u8 cnp_dscp[0x6]; 1247 u8 reserved_at_d8[0x4]; 1248 u8 cnp_prio_mode[0x1]; 1249 u8 cnp_802p_prio[0x3]; 1250 1251 u8 reserved_at_e0[0x720]; 1252 }; 1253 1254 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 1255 u8 reserved_at_0[0x60]; 1256 1257 u8 reserved_at_60[0x4]; 1258 u8 clamp_tgt_rate[0x1]; 1259 u8 reserved_at_65[0x3]; 1260 u8 clamp_tgt_rate_after_time_inc[0x1]; 1261 u8 reserved_at_69[0x17]; 1262 1263 u8 reserved_at_80[0x20]; 1264 1265 u8 rpg_time_reset[0x20]; 1266 1267 u8 rpg_byte_reset[0x20]; 1268 1269 u8 rpg_threshold[0x20]; 1270 1271 u8 rpg_max_rate[0x20]; 1272 1273 u8 rpg_ai_rate[0x20]; 1274 1275 u8 rpg_hai_rate[0x20]; 1276 1277 u8 rpg_gd[0x20]; 1278 1279 u8 rpg_min_dec_fac[0x20]; 1280 1281 u8 rpg_min_rate[0x20]; 1282 1283 u8 reserved_at_1c0[0xe0]; 1284 1285 u8 rate_to_set_on_first_cnp[0x20]; 1286 1287 u8 dce_tcp_g[0x20]; 1288 1289 u8 dce_tcp_rtt[0x20]; 1290 1291 u8 rate_reduce_monitor_period[0x20]; 1292 1293 u8 reserved_at_320[0x20]; 1294 1295 u8 initial_alpha_value[0x20]; 1296 1297 u8 reserved_at_360[0x4a0]; 1298 }; 1299 1300 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 1301 u8 reserved_at_0[0x80]; 1302 1303 u8 rppp_max_rps[0x20]; 1304 1305 u8 rpg_time_reset[0x20]; 1306 1307 u8 rpg_byte_reset[0x20]; 1308 1309 u8 rpg_threshold[0x20]; 1310 1311 u8 rpg_max_rate[0x20]; 1312 1313 u8 rpg_ai_rate[0x20]; 1314 1315 u8 rpg_hai_rate[0x20]; 1316 1317 u8 rpg_gd[0x20]; 1318 1319 u8 rpg_min_dec_fac[0x20]; 1320 1321 u8 rpg_min_rate[0x20]; 1322 1323 u8 reserved_at_1c0[0x640]; 1324 }; 1325 1326 enum { 1327 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 1328 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 1329 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 1330 }; 1331 1332 struct mlx5_ifc_resize_field_select_bits { 1333 u8 resize_field_select[0x20]; 1334 }; 1335 1336 enum { 1337 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 1338 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 1339 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 1340 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 1341 }; 1342 1343 struct mlx5_ifc_modify_field_select_bits { 1344 u8 modify_field_select[0x20]; 1345 }; 1346 1347 struct mlx5_ifc_field_select_r_roce_np_bits { 1348 u8 field_select_r_roce_np[0x20]; 1349 }; 1350 1351 struct mlx5_ifc_field_select_r_roce_rp_bits { 1352 u8 field_select_r_roce_rp[0x20]; 1353 }; 1354 1355 enum { 1356 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 1357 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 1358 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 1359 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 1360 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 1361 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 1362 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 1363 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 1364 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 1365 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 1366 }; 1367 1368 struct mlx5_ifc_field_select_802_1qau_rp_bits { 1369 u8 field_select_8021qaurp[0x20]; 1370 }; 1371 1372 struct mlx5_ifc_phys_layer_cntrs_bits { 1373 u8 time_since_last_clear_high[0x20]; 1374 1375 u8 time_since_last_clear_low[0x20]; 1376 1377 u8 symbol_errors_high[0x20]; 1378 1379 u8 symbol_errors_low[0x20]; 1380 1381 u8 sync_headers_errors_high[0x20]; 1382 1383 u8 sync_headers_errors_low[0x20]; 1384 1385 u8 edpl_bip_errors_lane0_high[0x20]; 1386 1387 u8 edpl_bip_errors_lane0_low[0x20]; 1388 1389 u8 edpl_bip_errors_lane1_high[0x20]; 1390 1391 u8 edpl_bip_errors_lane1_low[0x20]; 1392 1393 u8 edpl_bip_errors_lane2_high[0x20]; 1394 1395 u8 edpl_bip_errors_lane2_low[0x20]; 1396 1397 u8 edpl_bip_errors_lane3_high[0x20]; 1398 1399 u8 edpl_bip_errors_lane3_low[0x20]; 1400 1401 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 1402 1403 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 1404 1405 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 1406 1407 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 1408 1409 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 1410 1411 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 1412 1413 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 1414 1415 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 1416 1417 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 1418 1419 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 1420 1421 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 1422 1423 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 1424 1425 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 1426 1427 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 1428 1429 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 1430 1431 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 1432 1433 u8 rs_fec_corrected_blocks_high[0x20]; 1434 1435 u8 rs_fec_corrected_blocks_low[0x20]; 1436 1437 u8 rs_fec_uncorrectable_blocks_high[0x20]; 1438 1439 u8 rs_fec_uncorrectable_blocks_low[0x20]; 1440 1441 u8 rs_fec_no_errors_blocks_high[0x20]; 1442 1443 u8 rs_fec_no_errors_blocks_low[0x20]; 1444 1445 u8 rs_fec_single_error_blocks_high[0x20]; 1446 1447 u8 rs_fec_single_error_blocks_low[0x20]; 1448 1449 u8 rs_fec_corrected_symbols_total_high[0x20]; 1450 1451 u8 rs_fec_corrected_symbols_total_low[0x20]; 1452 1453 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 1454 1455 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 1456 1457 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 1458 1459 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 1460 1461 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 1462 1463 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 1464 1465 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 1466 1467 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 1468 1469 u8 link_down_events[0x20]; 1470 1471 u8 successful_recovery_events[0x20]; 1472 1473 u8 reserved_at_640[0x180]; 1474 }; 1475 1476 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 1477 u8 time_since_last_clear_high[0x20]; 1478 1479 u8 time_since_last_clear_low[0x20]; 1480 1481 u8 phy_received_bits_high[0x20]; 1482 1483 u8 phy_received_bits_low[0x20]; 1484 1485 u8 phy_symbol_errors_high[0x20]; 1486 1487 u8 phy_symbol_errors_low[0x20]; 1488 1489 u8 phy_corrected_bits_high[0x20]; 1490 1491 u8 phy_corrected_bits_low[0x20]; 1492 1493 u8 phy_corrected_bits_lane0_high[0x20]; 1494 1495 u8 phy_corrected_bits_lane0_low[0x20]; 1496 1497 u8 phy_corrected_bits_lane1_high[0x20]; 1498 1499 u8 phy_corrected_bits_lane1_low[0x20]; 1500 1501 u8 phy_corrected_bits_lane2_high[0x20]; 1502 1503 u8 phy_corrected_bits_lane2_low[0x20]; 1504 1505 u8 phy_corrected_bits_lane3_high[0x20]; 1506 1507 u8 phy_corrected_bits_lane3_low[0x20]; 1508 1509 u8 reserved_at_200[0x5c0]; 1510 }; 1511 1512 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 1513 u8 symbol_error_counter[0x10]; 1514 1515 u8 link_error_recovery_counter[0x8]; 1516 1517 u8 link_downed_counter[0x8]; 1518 1519 u8 port_rcv_errors[0x10]; 1520 1521 u8 port_rcv_remote_physical_errors[0x10]; 1522 1523 u8 port_rcv_switch_relay_errors[0x10]; 1524 1525 u8 port_xmit_discards[0x10]; 1526 1527 u8 port_xmit_constraint_errors[0x8]; 1528 1529 u8 port_rcv_constraint_errors[0x8]; 1530 1531 u8 reserved_at_70[0x8]; 1532 1533 u8 link_overrun_errors[0x8]; 1534 1535 u8 reserved_at_80[0x10]; 1536 1537 u8 vl_15_dropped[0x10]; 1538 1539 u8 reserved_at_a0[0x80]; 1540 1541 u8 port_xmit_wait[0x20]; 1542 }; 1543 1544 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits { 1545 u8 transmit_queue_high[0x20]; 1546 1547 u8 transmit_queue_low[0x20]; 1548 1549 u8 reserved_at_40[0x780]; 1550 }; 1551 1552 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 1553 u8 rx_octets_high[0x20]; 1554 1555 u8 rx_octets_low[0x20]; 1556 1557 u8 reserved_at_40[0xc0]; 1558 1559 u8 rx_frames_high[0x20]; 1560 1561 u8 rx_frames_low[0x20]; 1562 1563 u8 tx_octets_high[0x20]; 1564 1565 u8 tx_octets_low[0x20]; 1566 1567 u8 reserved_at_180[0xc0]; 1568 1569 u8 tx_frames_high[0x20]; 1570 1571 u8 tx_frames_low[0x20]; 1572 1573 u8 rx_pause_high[0x20]; 1574 1575 u8 rx_pause_low[0x20]; 1576 1577 u8 rx_pause_duration_high[0x20]; 1578 1579 u8 rx_pause_duration_low[0x20]; 1580 1581 u8 tx_pause_high[0x20]; 1582 1583 u8 tx_pause_low[0x20]; 1584 1585 u8 tx_pause_duration_high[0x20]; 1586 1587 u8 tx_pause_duration_low[0x20]; 1588 1589 u8 rx_pause_transition_high[0x20]; 1590 1591 u8 rx_pause_transition_low[0x20]; 1592 1593 u8 reserved_at_3c0[0x40]; 1594 1595 u8 device_stall_minor_watermark_cnt_high[0x20]; 1596 1597 u8 device_stall_minor_watermark_cnt_low[0x20]; 1598 1599 u8 device_stall_critical_watermark_cnt_high[0x20]; 1600 1601 u8 device_stall_critical_watermark_cnt_low[0x20]; 1602 1603 u8 reserved_at_480[0x340]; 1604 }; 1605 1606 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 1607 u8 port_transmit_wait_high[0x20]; 1608 1609 u8 port_transmit_wait_low[0x20]; 1610 1611 u8 reserved_at_40[0x100]; 1612 1613 u8 rx_buffer_almost_full_high[0x20]; 1614 1615 u8 rx_buffer_almost_full_low[0x20]; 1616 1617 u8 rx_buffer_full_high[0x20]; 1618 1619 u8 rx_buffer_full_low[0x20]; 1620 1621 u8 reserved_at_1c0[0x600]; 1622 }; 1623 1624 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 1625 u8 dot3stats_alignment_errors_high[0x20]; 1626 1627 u8 dot3stats_alignment_errors_low[0x20]; 1628 1629 u8 dot3stats_fcs_errors_high[0x20]; 1630 1631 u8 dot3stats_fcs_errors_low[0x20]; 1632 1633 u8 dot3stats_single_collision_frames_high[0x20]; 1634 1635 u8 dot3stats_single_collision_frames_low[0x20]; 1636 1637 u8 dot3stats_multiple_collision_frames_high[0x20]; 1638 1639 u8 dot3stats_multiple_collision_frames_low[0x20]; 1640 1641 u8 dot3stats_sqe_test_errors_high[0x20]; 1642 1643 u8 dot3stats_sqe_test_errors_low[0x20]; 1644 1645 u8 dot3stats_deferred_transmissions_high[0x20]; 1646 1647 u8 dot3stats_deferred_transmissions_low[0x20]; 1648 1649 u8 dot3stats_late_collisions_high[0x20]; 1650 1651 u8 dot3stats_late_collisions_low[0x20]; 1652 1653 u8 dot3stats_excessive_collisions_high[0x20]; 1654 1655 u8 dot3stats_excessive_collisions_low[0x20]; 1656 1657 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 1658 1659 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 1660 1661 u8 dot3stats_carrier_sense_errors_high[0x20]; 1662 1663 u8 dot3stats_carrier_sense_errors_low[0x20]; 1664 1665 u8 dot3stats_frame_too_longs_high[0x20]; 1666 1667 u8 dot3stats_frame_too_longs_low[0x20]; 1668 1669 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 1670 1671 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 1672 1673 u8 dot3stats_symbol_errors_high[0x20]; 1674 1675 u8 dot3stats_symbol_errors_low[0x20]; 1676 1677 u8 dot3control_in_unknown_opcodes_high[0x20]; 1678 1679 u8 dot3control_in_unknown_opcodes_low[0x20]; 1680 1681 u8 dot3in_pause_frames_high[0x20]; 1682 1683 u8 dot3in_pause_frames_low[0x20]; 1684 1685 u8 dot3out_pause_frames_high[0x20]; 1686 1687 u8 dot3out_pause_frames_low[0x20]; 1688 1689 u8 reserved_at_400[0x3c0]; 1690 }; 1691 1692 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 1693 u8 ether_stats_drop_events_high[0x20]; 1694 1695 u8 ether_stats_drop_events_low[0x20]; 1696 1697 u8 ether_stats_octets_high[0x20]; 1698 1699 u8 ether_stats_octets_low[0x20]; 1700 1701 u8 ether_stats_pkts_high[0x20]; 1702 1703 u8 ether_stats_pkts_low[0x20]; 1704 1705 u8 ether_stats_broadcast_pkts_high[0x20]; 1706 1707 u8 ether_stats_broadcast_pkts_low[0x20]; 1708 1709 u8 ether_stats_multicast_pkts_high[0x20]; 1710 1711 u8 ether_stats_multicast_pkts_low[0x20]; 1712 1713 u8 ether_stats_crc_align_errors_high[0x20]; 1714 1715 u8 ether_stats_crc_align_errors_low[0x20]; 1716 1717 u8 ether_stats_undersize_pkts_high[0x20]; 1718 1719 u8 ether_stats_undersize_pkts_low[0x20]; 1720 1721 u8 ether_stats_oversize_pkts_high[0x20]; 1722 1723 u8 ether_stats_oversize_pkts_low[0x20]; 1724 1725 u8 ether_stats_fragments_high[0x20]; 1726 1727 u8 ether_stats_fragments_low[0x20]; 1728 1729 u8 ether_stats_jabbers_high[0x20]; 1730 1731 u8 ether_stats_jabbers_low[0x20]; 1732 1733 u8 ether_stats_collisions_high[0x20]; 1734 1735 u8 ether_stats_collisions_low[0x20]; 1736 1737 u8 ether_stats_pkts64octets_high[0x20]; 1738 1739 u8 ether_stats_pkts64octets_low[0x20]; 1740 1741 u8 ether_stats_pkts65to127octets_high[0x20]; 1742 1743 u8 ether_stats_pkts65to127octets_low[0x20]; 1744 1745 u8 ether_stats_pkts128to255octets_high[0x20]; 1746 1747 u8 ether_stats_pkts128to255octets_low[0x20]; 1748 1749 u8 ether_stats_pkts256to511octets_high[0x20]; 1750 1751 u8 ether_stats_pkts256to511octets_low[0x20]; 1752 1753 u8 ether_stats_pkts512to1023octets_high[0x20]; 1754 1755 u8 ether_stats_pkts512to1023octets_low[0x20]; 1756 1757 u8 ether_stats_pkts1024to1518octets_high[0x20]; 1758 1759 u8 ether_stats_pkts1024to1518octets_low[0x20]; 1760 1761 u8 ether_stats_pkts1519to2047octets_high[0x20]; 1762 1763 u8 ether_stats_pkts1519to2047octets_low[0x20]; 1764 1765 u8 ether_stats_pkts2048to4095octets_high[0x20]; 1766 1767 u8 ether_stats_pkts2048to4095octets_low[0x20]; 1768 1769 u8 ether_stats_pkts4096to8191octets_high[0x20]; 1770 1771 u8 ether_stats_pkts4096to8191octets_low[0x20]; 1772 1773 u8 ether_stats_pkts8192to10239octets_high[0x20]; 1774 1775 u8 ether_stats_pkts8192to10239octets_low[0x20]; 1776 1777 u8 reserved_at_540[0x280]; 1778 }; 1779 1780 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 1781 u8 if_in_octets_high[0x20]; 1782 1783 u8 if_in_octets_low[0x20]; 1784 1785 u8 if_in_ucast_pkts_high[0x20]; 1786 1787 u8 if_in_ucast_pkts_low[0x20]; 1788 1789 u8 if_in_discards_high[0x20]; 1790 1791 u8 if_in_discards_low[0x20]; 1792 1793 u8 if_in_errors_high[0x20]; 1794 1795 u8 if_in_errors_low[0x20]; 1796 1797 u8 if_in_unknown_protos_high[0x20]; 1798 1799 u8 if_in_unknown_protos_low[0x20]; 1800 1801 u8 if_out_octets_high[0x20]; 1802 1803 u8 if_out_octets_low[0x20]; 1804 1805 u8 if_out_ucast_pkts_high[0x20]; 1806 1807 u8 if_out_ucast_pkts_low[0x20]; 1808 1809 u8 if_out_discards_high[0x20]; 1810 1811 u8 if_out_discards_low[0x20]; 1812 1813 u8 if_out_errors_high[0x20]; 1814 1815 u8 if_out_errors_low[0x20]; 1816 1817 u8 if_in_multicast_pkts_high[0x20]; 1818 1819 u8 if_in_multicast_pkts_low[0x20]; 1820 1821 u8 if_in_broadcast_pkts_high[0x20]; 1822 1823 u8 if_in_broadcast_pkts_low[0x20]; 1824 1825 u8 if_out_multicast_pkts_high[0x20]; 1826 1827 u8 if_out_multicast_pkts_low[0x20]; 1828 1829 u8 if_out_broadcast_pkts_high[0x20]; 1830 1831 u8 if_out_broadcast_pkts_low[0x20]; 1832 1833 u8 reserved_at_340[0x480]; 1834 }; 1835 1836 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 1837 u8 a_frames_transmitted_ok_high[0x20]; 1838 1839 u8 a_frames_transmitted_ok_low[0x20]; 1840 1841 u8 a_frames_received_ok_high[0x20]; 1842 1843 u8 a_frames_received_ok_low[0x20]; 1844 1845 u8 a_frame_check_sequence_errors_high[0x20]; 1846 1847 u8 a_frame_check_sequence_errors_low[0x20]; 1848 1849 u8 a_alignment_errors_high[0x20]; 1850 1851 u8 a_alignment_errors_low[0x20]; 1852 1853 u8 a_octets_transmitted_ok_high[0x20]; 1854 1855 u8 a_octets_transmitted_ok_low[0x20]; 1856 1857 u8 a_octets_received_ok_high[0x20]; 1858 1859 u8 a_octets_received_ok_low[0x20]; 1860 1861 u8 a_multicast_frames_xmitted_ok_high[0x20]; 1862 1863 u8 a_multicast_frames_xmitted_ok_low[0x20]; 1864 1865 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 1866 1867 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 1868 1869 u8 a_multicast_frames_received_ok_high[0x20]; 1870 1871 u8 a_multicast_frames_received_ok_low[0x20]; 1872 1873 u8 a_broadcast_frames_received_ok_high[0x20]; 1874 1875 u8 a_broadcast_frames_received_ok_low[0x20]; 1876 1877 u8 a_in_range_length_errors_high[0x20]; 1878 1879 u8 a_in_range_length_errors_low[0x20]; 1880 1881 u8 a_out_of_range_length_field_high[0x20]; 1882 1883 u8 a_out_of_range_length_field_low[0x20]; 1884 1885 u8 a_frame_too_long_errors_high[0x20]; 1886 1887 u8 a_frame_too_long_errors_low[0x20]; 1888 1889 u8 a_symbol_error_during_carrier_high[0x20]; 1890 1891 u8 a_symbol_error_during_carrier_low[0x20]; 1892 1893 u8 a_mac_control_frames_transmitted_high[0x20]; 1894 1895 u8 a_mac_control_frames_transmitted_low[0x20]; 1896 1897 u8 a_mac_control_frames_received_high[0x20]; 1898 1899 u8 a_mac_control_frames_received_low[0x20]; 1900 1901 u8 a_unsupported_opcodes_received_high[0x20]; 1902 1903 u8 a_unsupported_opcodes_received_low[0x20]; 1904 1905 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 1906 1907 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 1908 1909 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 1910 1911 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 1912 1913 u8 reserved_at_4c0[0x300]; 1914 }; 1915 1916 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 1917 u8 life_time_counter_high[0x20]; 1918 1919 u8 life_time_counter_low[0x20]; 1920 1921 u8 rx_errors[0x20]; 1922 1923 u8 tx_errors[0x20]; 1924 1925 u8 l0_to_recovery_eieos[0x20]; 1926 1927 u8 l0_to_recovery_ts[0x20]; 1928 1929 u8 l0_to_recovery_framing[0x20]; 1930 1931 u8 l0_to_recovery_retrain[0x20]; 1932 1933 u8 crc_error_dllp[0x20]; 1934 1935 u8 crc_error_tlp[0x20]; 1936 1937 u8 tx_overflow_buffer_pkt_high[0x20]; 1938 1939 u8 tx_overflow_buffer_pkt_low[0x20]; 1940 1941 u8 outbound_stalled_reads[0x20]; 1942 1943 u8 outbound_stalled_writes[0x20]; 1944 1945 u8 outbound_stalled_reads_events[0x20]; 1946 1947 u8 outbound_stalled_writes_events[0x20]; 1948 1949 u8 reserved_at_200[0x5c0]; 1950 }; 1951 1952 struct mlx5_ifc_cmd_inter_comp_event_bits { 1953 u8 command_completion_vector[0x20]; 1954 1955 u8 reserved_at_20[0xc0]; 1956 }; 1957 1958 struct mlx5_ifc_stall_vl_event_bits { 1959 u8 reserved_at_0[0x18]; 1960 u8 port_num[0x1]; 1961 u8 reserved_at_19[0x3]; 1962 u8 vl[0x4]; 1963 1964 u8 reserved_at_20[0xa0]; 1965 }; 1966 1967 struct mlx5_ifc_db_bf_congestion_event_bits { 1968 u8 event_subtype[0x8]; 1969 u8 reserved_at_8[0x8]; 1970 u8 congestion_level[0x8]; 1971 u8 reserved_at_18[0x8]; 1972 1973 u8 reserved_at_20[0xa0]; 1974 }; 1975 1976 struct mlx5_ifc_gpio_event_bits { 1977 u8 reserved_at_0[0x60]; 1978 1979 u8 gpio_event_hi[0x20]; 1980 1981 u8 gpio_event_lo[0x20]; 1982 1983 u8 reserved_at_a0[0x40]; 1984 }; 1985 1986 struct mlx5_ifc_port_state_change_event_bits { 1987 u8 reserved_at_0[0x40]; 1988 1989 u8 port_num[0x4]; 1990 u8 reserved_at_44[0x1c]; 1991 1992 u8 reserved_at_60[0x80]; 1993 }; 1994 1995 struct mlx5_ifc_dropped_packet_logged_bits { 1996 u8 reserved_at_0[0xe0]; 1997 }; 1998 1999 enum { 2000 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 2001 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 2002 }; 2003 2004 struct mlx5_ifc_cq_error_bits { 2005 u8 reserved_at_0[0x8]; 2006 u8 cqn[0x18]; 2007 2008 u8 reserved_at_20[0x20]; 2009 2010 u8 reserved_at_40[0x18]; 2011 u8 syndrome[0x8]; 2012 2013 u8 reserved_at_60[0x80]; 2014 }; 2015 2016 struct mlx5_ifc_rdma_page_fault_event_bits { 2017 u8 bytes_committed[0x20]; 2018 2019 u8 r_key[0x20]; 2020 2021 u8 reserved_at_40[0x10]; 2022 u8 packet_len[0x10]; 2023 2024 u8 rdma_op_len[0x20]; 2025 2026 u8 rdma_va[0x40]; 2027 2028 u8 reserved_at_c0[0x5]; 2029 u8 rdma[0x1]; 2030 u8 write[0x1]; 2031 u8 requestor[0x1]; 2032 u8 qp_number[0x18]; 2033 }; 2034 2035 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 2036 u8 bytes_committed[0x20]; 2037 2038 u8 reserved_at_20[0x10]; 2039 u8 wqe_index[0x10]; 2040 2041 u8 reserved_at_40[0x10]; 2042 u8 len[0x10]; 2043 2044 u8 reserved_at_60[0x60]; 2045 2046 u8 reserved_at_c0[0x5]; 2047 u8 rdma[0x1]; 2048 u8 write_read[0x1]; 2049 u8 requestor[0x1]; 2050 u8 qpn[0x18]; 2051 }; 2052 2053 struct mlx5_ifc_qp_events_bits { 2054 u8 reserved_at_0[0xa0]; 2055 2056 u8 type[0x8]; 2057 u8 reserved_at_a8[0x18]; 2058 2059 u8 reserved_at_c0[0x8]; 2060 u8 qpn_rqn_sqn[0x18]; 2061 }; 2062 2063 struct mlx5_ifc_dct_events_bits { 2064 u8 reserved_at_0[0xc0]; 2065 2066 u8 reserved_at_c0[0x8]; 2067 u8 dct_number[0x18]; 2068 }; 2069 2070 struct mlx5_ifc_comp_event_bits { 2071 u8 reserved_at_0[0xc0]; 2072 2073 u8 reserved_at_c0[0x8]; 2074 u8 cq_number[0x18]; 2075 }; 2076 2077 enum { 2078 MLX5_QPC_STATE_RST = 0x0, 2079 MLX5_QPC_STATE_INIT = 0x1, 2080 MLX5_QPC_STATE_RTR = 0x2, 2081 MLX5_QPC_STATE_RTS = 0x3, 2082 MLX5_QPC_STATE_SQER = 0x4, 2083 MLX5_QPC_STATE_ERR = 0x6, 2084 MLX5_QPC_STATE_SQD = 0x7, 2085 MLX5_QPC_STATE_SUSPENDED = 0x9, 2086 }; 2087 2088 enum { 2089 MLX5_QPC_ST_RC = 0x0, 2090 MLX5_QPC_ST_UC = 0x1, 2091 MLX5_QPC_ST_UD = 0x2, 2092 MLX5_QPC_ST_XRC = 0x3, 2093 MLX5_QPC_ST_DCI = 0x5, 2094 MLX5_QPC_ST_QP0 = 0x7, 2095 MLX5_QPC_ST_QP1 = 0x8, 2096 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 2097 MLX5_QPC_ST_REG_UMR = 0xc, 2098 }; 2099 2100 enum { 2101 MLX5_QPC_PM_STATE_ARMED = 0x0, 2102 MLX5_QPC_PM_STATE_REARM = 0x1, 2103 MLX5_QPC_PM_STATE_RESERVED = 0x2, 2104 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 2105 }; 2106 2107 enum { 2108 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 2109 }; 2110 2111 enum { 2112 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 2113 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 2114 }; 2115 2116 enum { 2117 MLX5_QPC_MTU_256_BYTES = 0x1, 2118 MLX5_QPC_MTU_512_BYTES = 0x2, 2119 MLX5_QPC_MTU_1K_BYTES = 0x3, 2120 MLX5_QPC_MTU_2K_BYTES = 0x4, 2121 MLX5_QPC_MTU_4K_BYTES = 0x5, 2122 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 2123 }; 2124 2125 enum { 2126 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 2127 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 2128 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 2129 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 2130 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 2131 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 2132 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 2133 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 2134 }; 2135 2136 enum { 2137 MLX5_QPC_CS_REQ_DISABLE = 0x0, 2138 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 2139 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 2140 }; 2141 2142 enum { 2143 MLX5_QPC_CS_RES_DISABLE = 0x0, 2144 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 2145 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 2146 }; 2147 2148 struct mlx5_ifc_qpc_bits { 2149 u8 state[0x4]; 2150 u8 lag_tx_port_affinity[0x4]; 2151 u8 st[0x8]; 2152 u8 reserved_at_10[0x3]; 2153 u8 pm_state[0x2]; 2154 u8 reserved_at_15[0x3]; 2155 u8 offload_type[0x4]; 2156 u8 end_padding_mode[0x2]; 2157 u8 reserved_at_1e[0x2]; 2158 2159 u8 wq_signature[0x1]; 2160 u8 block_lb_mc[0x1]; 2161 u8 atomic_like_write_en[0x1]; 2162 u8 latency_sensitive[0x1]; 2163 u8 reserved_at_24[0x1]; 2164 u8 drain_sigerr[0x1]; 2165 u8 reserved_at_26[0x2]; 2166 u8 pd[0x18]; 2167 2168 u8 mtu[0x3]; 2169 u8 log_msg_max[0x5]; 2170 u8 reserved_at_48[0x1]; 2171 u8 log_rq_size[0x4]; 2172 u8 log_rq_stride[0x3]; 2173 u8 no_sq[0x1]; 2174 u8 log_sq_size[0x4]; 2175 u8 reserved_at_55[0x6]; 2176 u8 rlky[0x1]; 2177 u8 ulp_stateless_offload_mode[0x4]; 2178 2179 u8 counter_set_id[0x8]; 2180 u8 uar_page[0x18]; 2181 2182 u8 reserved_at_80[0x8]; 2183 u8 user_index[0x18]; 2184 2185 u8 reserved_at_a0[0x3]; 2186 u8 log_page_size[0x5]; 2187 u8 remote_qpn[0x18]; 2188 2189 struct mlx5_ifc_ads_bits primary_address_path; 2190 2191 struct mlx5_ifc_ads_bits secondary_address_path; 2192 2193 u8 log_ack_req_freq[0x4]; 2194 u8 reserved_at_384[0x4]; 2195 u8 log_sra_max[0x3]; 2196 u8 reserved_at_38b[0x2]; 2197 u8 retry_count[0x3]; 2198 u8 rnr_retry[0x3]; 2199 u8 reserved_at_393[0x1]; 2200 u8 fre[0x1]; 2201 u8 cur_rnr_retry[0x3]; 2202 u8 cur_retry_count[0x3]; 2203 u8 reserved_at_39b[0x5]; 2204 2205 u8 reserved_at_3a0[0x20]; 2206 2207 u8 reserved_at_3c0[0x8]; 2208 u8 next_send_psn[0x18]; 2209 2210 u8 reserved_at_3e0[0x8]; 2211 u8 cqn_snd[0x18]; 2212 2213 u8 reserved_at_400[0x8]; 2214 u8 deth_sqpn[0x18]; 2215 2216 u8 reserved_at_420[0x20]; 2217 2218 u8 reserved_at_440[0x8]; 2219 u8 last_acked_psn[0x18]; 2220 2221 u8 reserved_at_460[0x8]; 2222 u8 ssn[0x18]; 2223 2224 u8 reserved_at_480[0x8]; 2225 u8 log_rra_max[0x3]; 2226 u8 reserved_at_48b[0x1]; 2227 u8 atomic_mode[0x4]; 2228 u8 rre[0x1]; 2229 u8 rwe[0x1]; 2230 u8 rae[0x1]; 2231 u8 reserved_at_493[0x1]; 2232 u8 page_offset[0x6]; 2233 u8 reserved_at_49a[0x3]; 2234 u8 cd_slave_receive[0x1]; 2235 u8 cd_slave_send[0x1]; 2236 u8 cd_master[0x1]; 2237 2238 u8 reserved_at_4a0[0x3]; 2239 u8 min_rnr_nak[0x5]; 2240 u8 next_rcv_psn[0x18]; 2241 2242 u8 reserved_at_4c0[0x8]; 2243 u8 xrcd[0x18]; 2244 2245 u8 reserved_at_4e0[0x8]; 2246 u8 cqn_rcv[0x18]; 2247 2248 u8 dbr_addr[0x40]; 2249 2250 u8 q_key[0x20]; 2251 2252 u8 reserved_at_560[0x5]; 2253 u8 rq_type[0x3]; 2254 u8 srqn_rmpn_xrqn[0x18]; 2255 2256 u8 reserved_at_580[0x8]; 2257 u8 rmsn[0x18]; 2258 2259 u8 hw_sq_wqebb_counter[0x10]; 2260 u8 sw_sq_wqebb_counter[0x10]; 2261 2262 u8 hw_rq_counter[0x20]; 2263 2264 u8 sw_rq_counter[0x20]; 2265 2266 u8 reserved_at_600[0x20]; 2267 2268 u8 reserved_at_620[0xf]; 2269 u8 cgs[0x1]; 2270 u8 cs_req[0x8]; 2271 u8 cs_res[0x8]; 2272 2273 u8 dc_access_key[0x40]; 2274 2275 u8 reserved_at_680[0xc0]; 2276 }; 2277 2278 struct mlx5_ifc_roce_addr_layout_bits { 2279 u8 source_l3_address[16][0x8]; 2280 2281 u8 reserved_at_80[0x3]; 2282 u8 vlan_valid[0x1]; 2283 u8 vlan_id[0xc]; 2284 u8 source_mac_47_32[0x10]; 2285 2286 u8 source_mac_31_0[0x20]; 2287 2288 u8 reserved_at_c0[0x14]; 2289 u8 roce_l3_type[0x4]; 2290 u8 roce_version[0x8]; 2291 2292 u8 reserved_at_e0[0x20]; 2293 }; 2294 2295 union mlx5_ifc_hca_cap_union_bits { 2296 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 2297 struct mlx5_ifc_odp_cap_bits odp_cap; 2298 struct mlx5_ifc_atomic_caps_bits atomic_caps; 2299 struct mlx5_ifc_roce_cap_bits roce_cap; 2300 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 2301 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 2302 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 2303 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 2304 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 2305 struct mlx5_ifc_qos_cap_bits qos_cap; 2306 struct mlx5_ifc_fpga_cap_bits fpga_cap; 2307 u8 reserved_at_0[0x8000]; 2308 }; 2309 2310 enum { 2311 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 2312 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 2313 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 2314 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 2315 MLX5_FLOW_CONTEXT_ACTION_ENCAP = 0x10, 2316 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 2317 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 2318 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 2319 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 2320 }; 2321 2322 struct mlx5_ifc_vlan_bits { 2323 u8 ethtype[0x10]; 2324 u8 prio[0x3]; 2325 u8 cfi[0x1]; 2326 u8 vid[0xc]; 2327 }; 2328 2329 struct mlx5_ifc_flow_context_bits { 2330 struct mlx5_ifc_vlan_bits push_vlan; 2331 2332 u8 group_id[0x20]; 2333 2334 u8 reserved_at_40[0x8]; 2335 u8 flow_tag[0x18]; 2336 2337 u8 reserved_at_60[0x10]; 2338 u8 action[0x10]; 2339 2340 u8 reserved_at_80[0x8]; 2341 u8 destination_list_size[0x18]; 2342 2343 u8 reserved_at_a0[0x8]; 2344 u8 flow_counter_list_size[0x18]; 2345 2346 u8 encap_id[0x20]; 2347 2348 u8 modify_header_id[0x20]; 2349 2350 u8 reserved_at_100[0x100]; 2351 2352 struct mlx5_ifc_fte_match_param_bits match_value; 2353 2354 u8 reserved_at_1200[0x600]; 2355 2356 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0]; 2357 }; 2358 2359 enum { 2360 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 2361 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 2362 }; 2363 2364 struct mlx5_ifc_xrc_srqc_bits { 2365 u8 state[0x4]; 2366 u8 log_xrc_srq_size[0x4]; 2367 u8 reserved_at_8[0x18]; 2368 2369 u8 wq_signature[0x1]; 2370 u8 cont_srq[0x1]; 2371 u8 reserved_at_22[0x1]; 2372 u8 rlky[0x1]; 2373 u8 basic_cyclic_rcv_wqe[0x1]; 2374 u8 log_rq_stride[0x3]; 2375 u8 xrcd[0x18]; 2376 2377 u8 page_offset[0x6]; 2378 u8 reserved_at_46[0x2]; 2379 u8 cqn[0x18]; 2380 2381 u8 reserved_at_60[0x20]; 2382 2383 u8 user_index_equal_xrc_srqn[0x1]; 2384 u8 reserved_at_81[0x1]; 2385 u8 log_page_size[0x6]; 2386 u8 user_index[0x18]; 2387 2388 u8 reserved_at_a0[0x20]; 2389 2390 u8 reserved_at_c0[0x8]; 2391 u8 pd[0x18]; 2392 2393 u8 lwm[0x10]; 2394 u8 wqe_cnt[0x10]; 2395 2396 u8 reserved_at_100[0x40]; 2397 2398 u8 db_record_addr_h[0x20]; 2399 2400 u8 db_record_addr_l[0x1e]; 2401 u8 reserved_at_17e[0x2]; 2402 2403 u8 reserved_at_180[0x80]; 2404 }; 2405 2406 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 2407 u8 counter_error_queues[0x20]; 2408 2409 u8 total_error_queues[0x20]; 2410 2411 u8 send_queue_priority_update_flow[0x20]; 2412 2413 u8 reserved_at_60[0x20]; 2414 2415 u8 nic_receive_steering_discard[0x40]; 2416 2417 u8 receive_discard_vport_down[0x40]; 2418 2419 u8 transmit_discard_vport_down[0x40]; 2420 2421 u8 reserved_at_140[0xec0]; 2422 }; 2423 2424 struct mlx5_ifc_traffic_counter_bits { 2425 u8 packets[0x40]; 2426 2427 u8 octets[0x40]; 2428 }; 2429 2430 struct mlx5_ifc_tisc_bits { 2431 u8 strict_lag_tx_port_affinity[0x1]; 2432 u8 reserved_at_1[0x3]; 2433 u8 lag_tx_port_affinity[0x04]; 2434 2435 u8 reserved_at_8[0x4]; 2436 u8 prio[0x4]; 2437 u8 reserved_at_10[0x10]; 2438 2439 u8 reserved_at_20[0x100]; 2440 2441 u8 reserved_at_120[0x8]; 2442 u8 transport_domain[0x18]; 2443 2444 u8 reserved_at_140[0x8]; 2445 u8 underlay_qpn[0x18]; 2446 u8 reserved_at_160[0x3a0]; 2447 }; 2448 2449 enum { 2450 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 2451 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 2452 }; 2453 2454 enum { 2455 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 2456 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 2457 }; 2458 2459 enum { 2460 MLX5_RX_HASH_FN_NONE = 0x0, 2461 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 2462 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 2463 }; 2464 2465 enum { 2466 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1, 2467 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2, 2468 }; 2469 2470 struct mlx5_ifc_tirc_bits { 2471 u8 reserved_at_0[0x20]; 2472 2473 u8 disp_type[0x4]; 2474 u8 reserved_at_24[0x1c]; 2475 2476 u8 reserved_at_40[0x40]; 2477 2478 u8 reserved_at_80[0x4]; 2479 u8 lro_timeout_period_usecs[0x10]; 2480 u8 lro_enable_mask[0x4]; 2481 u8 lro_max_ip_payload_size[0x8]; 2482 2483 u8 reserved_at_a0[0x40]; 2484 2485 u8 reserved_at_e0[0x8]; 2486 u8 inline_rqn[0x18]; 2487 2488 u8 rx_hash_symmetric[0x1]; 2489 u8 reserved_at_101[0x1]; 2490 u8 tunneled_offload_en[0x1]; 2491 u8 reserved_at_103[0x5]; 2492 u8 indirect_table[0x18]; 2493 2494 u8 rx_hash_fn[0x4]; 2495 u8 reserved_at_124[0x2]; 2496 u8 self_lb_block[0x2]; 2497 u8 transport_domain[0x18]; 2498 2499 u8 rx_hash_toeplitz_key[10][0x20]; 2500 2501 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 2502 2503 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 2504 2505 u8 reserved_at_2c0[0x4c0]; 2506 }; 2507 2508 enum { 2509 MLX5_SRQC_STATE_GOOD = 0x0, 2510 MLX5_SRQC_STATE_ERROR = 0x1, 2511 }; 2512 2513 struct mlx5_ifc_srqc_bits { 2514 u8 state[0x4]; 2515 u8 log_srq_size[0x4]; 2516 u8 reserved_at_8[0x18]; 2517 2518 u8 wq_signature[0x1]; 2519 u8 cont_srq[0x1]; 2520 u8 reserved_at_22[0x1]; 2521 u8 rlky[0x1]; 2522 u8 reserved_at_24[0x1]; 2523 u8 log_rq_stride[0x3]; 2524 u8 xrcd[0x18]; 2525 2526 u8 page_offset[0x6]; 2527 u8 reserved_at_46[0x2]; 2528 u8 cqn[0x18]; 2529 2530 u8 reserved_at_60[0x20]; 2531 2532 u8 reserved_at_80[0x2]; 2533 u8 log_page_size[0x6]; 2534 u8 reserved_at_88[0x18]; 2535 2536 u8 reserved_at_a0[0x20]; 2537 2538 u8 reserved_at_c0[0x8]; 2539 u8 pd[0x18]; 2540 2541 u8 lwm[0x10]; 2542 u8 wqe_cnt[0x10]; 2543 2544 u8 reserved_at_100[0x40]; 2545 2546 u8 dbr_addr[0x40]; 2547 2548 u8 reserved_at_180[0x80]; 2549 }; 2550 2551 enum { 2552 MLX5_SQC_STATE_RST = 0x0, 2553 MLX5_SQC_STATE_RDY = 0x1, 2554 MLX5_SQC_STATE_ERR = 0x3, 2555 }; 2556 2557 struct mlx5_ifc_sqc_bits { 2558 u8 rlky[0x1]; 2559 u8 cd_master[0x1]; 2560 u8 fre[0x1]; 2561 u8 flush_in_error_en[0x1]; 2562 u8 allow_multi_pkt_send_wqe[0x1]; 2563 u8 min_wqe_inline_mode[0x3]; 2564 u8 state[0x4]; 2565 u8 reg_umr[0x1]; 2566 u8 allow_swp[0x1]; 2567 u8 hairpin[0x1]; 2568 u8 reserved_at_f[0x11]; 2569 2570 u8 reserved_at_20[0x8]; 2571 u8 user_index[0x18]; 2572 2573 u8 reserved_at_40[0x8]; 2574 u8 cqn[0x18]; 2575 2576 u8 reserved_at_60[0x8]; 2577 u8 hairpin_peer_rq[0x18]; 2578 2579 u8 reserved_at_80[0x10]; 2580 u8 hairpin_peer_vhca[0x10]; 2581 2582 u8 reserved_at_a0[0x50]; 2583 2584 u8 packet_pacing_rate_limit_index[0x10]; 2585 u8 tis_lst_sz[0x10]; 2586 u8 reserved_at_110[0x10]; 2587 2588 u8 reserved_at_120[0x40]; 2589 2590 u8 reserved_at_160[0x8]; 2591 u8 tis_num_0[0x18]; 2592 2593 struct mlx5_ifc_wq_bits wq; 2594 }; 2595 2596 enum { 2597 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 2598 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 2599 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 2600 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 2601 }; 2602 2603 struct mlx5_ifc_scheduling_context_bits { 2604 u8 element_type[0x8]; 2605 u8 reserved_at_8[0x18]; 2606 2607 u8 element_attributes[0x20]; 2608 2609 u8 parent_element_id[0x20]; 2610 2611 u8 reserved_at_60[0x40]; 2612 2613 u8 bw_share[0x20]; 2614 2615 u8 max_average_bw[0x20]; 2616 2617 u8 reserved_at_e0[0x120]; 2618 }; 2619 2620 struct mlx5_ifc_rqtc_bits { 2621 u8 reserved_at_0[0xa0]; 2622 2623 u8 reserved_at_a0[0x10]; 2624 u8 rqt_max_size[0x10]; 2625 2626 u8 reserved_at_c0[0x10]; 2627 u8 rqt_actual_size[0x10]; 2628 2629 u8 reserved_at_e0[0x6a0]; 2630 2631 struct mlx5_ifc_rq_num_bits rq_num[0]; 2632 }; 2633 2634 enum { 2635 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 2636 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 2637 }; 2638 2639 enum { 2640 MLX5_RQC_STATE_RST = 0x0, 2641 MLX5_RQC_STATE_RDY = 0x1, 2642 MLX5_RQC_STATE_ERR = 0x3, 2643 }; 2644 2645 struct mlx5_ifc_rqc_bits { 2646 u8 rlky[0x1]; 2647 u8 delay_drop_en[0x1]; 2648 u8 scatter_fcs[0x1]; 2649 u8 vsd[0x1]; 2650 u8 mem_rq_type[0x4]; 2651 u8 state[0x4]; 2652 u8 reserved_at_c[0x1]; 2653 u8 flush_in_error_en[0x1]; 2654 u8 hairpin[0x1]; 2655 u8 reserved_at_f[0x11]; 2656 2657 u8 reserved_at_20[0x8]; 2658 u8 user_index[0x18]; 2659 2660 u8 reserved_at_40[0x8]; 2661 u8 cqn[0x18]; 2662 2663 u8 counter_set_id[0x8]; 2664 u8 reserved_at_68[0x18]; 2665 2666 u8 reserved_at_80[0x8]; 2667 u8 rmpn[0x18]; 2668 2669 u8 reserved_at_a0[0x8]; 2670 u8 hairpin_peer_sq[0x18]; 2671 2672 u8 reserved_at_c0[0x10]; 2673 u8 hairpin_peer_vhca[0x10]; 2674 2675 u8 reserved_at_e0[0xa0]; 2676 2677 struct mlx5_ifc_wq_bits wq; 2678 }; 2679 2680 enum { 2681 MLX5_RMPC_STATE_RDY = 0x1, 2682 MLX5_RMPC_STATE_ERR = 0x3, 2683 }; 2684 2685 struct mlx5_ifc_rmpc_bits { 2686 u8 reserved_at_0[0x8]; 2687 u8 state[0x4]; 2688 u8 reserved_at_c[0x14]; 2689 2690 u8 basic_cyclic_rcv_wqe[0x1]; 2691 u8 reserved_at_21[0x1f]; 2692 2693 u8 reserved_at_40[0x140]; 2694 2695 struct mlx5_ifc_wq_bits wq; 2696 }; 2697 2698 struct mlx5_ifc_nic_vport_context_bits { 2699 u8 reserved_at_0[0x5]; 2700 u8 min_wqe_inline_mode[0x3]; 2701 u8 reserved_at_8[0x15]; 2702 u8 disable_mc_local_lb[0x1]; 2703 u8 disable_uc_local_lb[0x1]; 2704 u8 roce_en[0x1]; 2705 2706 u8 arm_change_event[0x1]; 2707 u8 reserved_at_21[0x1a]; 2708 u8 event_on_mtu[0x1]; 2709 u8 event_on_promisc_change[0x1]; 2710 u8 event_on_vlan_change[0x1]; 2711 u8 event_on_mc_address_change[0x1]; 2712 u8 event_on_uc_address_change[0x1]; 2713 2714 u8 reserved_at_40[0xc]; 2715 2716 u8 affiliation_criteria[0x4]; 2717 u8 affiliated_vhca_id[0x10]; 2718 2719 u8 reserved_at_60[0xd0]; 2720 2721 u8 mtu[0x10]; 2722 2723 u8 system_image_guid[0x40]; 2724 u8 port_guid[0x40]; 2725 u8 node_guid[0x40]; 2726 2727 u8 reserved_at_200[0x140]; 2728 u8 qkey_violation_counter[0x10]; 2729 u8 reserved_at_350[0x430]; 2730 2731 u8 promisc_uc[0x1]; 2732 u8 promisc_mc[0x1]; 2733 u8 promisc_all[0x1]; 2734 u8 reserved_at_783[0x2]; 2735 u8 allowed_list_type[0x3]; 2736 u8 reserved_at_788[0xc]; 2737 u8 allowed_list_size[0xc]; 2738 2739 struct mlx5_ifc_mac_address_layout_bits permanent_address; 2740 2741 u8 reserved_at_7e0[0x20]; 2742 2743 u8 current_uc_mac_address[0][0x40]; 2744 }; 2745 2746 enum { 2747 MLX5_MKC_ACCESS_MODE_PA = 0x0, 2748 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 2749 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 2750 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 2751 }; 2752 2753 struct mlx5_ifc_mkc_bits { 2754 u8 reserved_at_0[0x1]; 2755 u8 free[0x1]; 2756 u8 reserved_at_2[0xd]; 2757 u8 small_fence_on_rdma_read_response[0x1]; 2758 u8 umr_en[0x1]; 2759 u8 a[0x1]; 2760 u8 rw[0x1]; 2761 u8 rr[0x1]; 2762 u8 lw[0x1]; 2763 u8 lr[0x1]; 2764 u8 access_mode[0x2]; 2765 u8 reserved_at_18[0x8]; 2766 2767 u8 qpn[0x18]; 2768 u8 mkey_7_0[0x8]; 2769 2770 u8 reserved_at_40[0x20]; 2771 2772 u8 length64[0x1]; 2773 u8 bsf_en[0x1]; 2774 u8 sync_umr[0x1]; 2775 u8 reserved_at_63[0x2]; 2776 u8 expected_sigerr_count[0x1]; 2777 u8 reserved_at_66[0x1]; 2778 u8 en_rinval[0x1]; 2779 u8 pd[0x18]; 2780 2781 u8 start_addr[0x40]; 2782 2783 u8 len[0x40]; 2784 2785 u8 bsf_octword_size[0x20]; 2786 2787 u8 reserved_at_120[0x80]; 2788 2789 u8 translations_octword_size[0x20]; 2790 2791 u8 reserved_at_1c0[0x1b]; 2792 u8 log_page_size[0x5]; 2793 2794 u8 reserved_at_1e0[0x20]; 2795 }; 2796 2797 struct mlx5_ifc_pkey_bits { 2798 u8 reserved_at_0[0x10]; 2799 u8 pkey[0x10]; 2800 }; 2801 2802 struct mlx5_ifc_array128_auto_bits { 2803 u8 array128_auto[16][0x8]; 2804 }; 2805 2806 struct mlx5_ifc_hca_vport_context_bits { 2807 u8 field_select[0x20]; 2808 2809 u8 reserved_at_20[0xe0]; 2810 2811 u8 sm_virt_aware[0x1]; 2812 u8 has_smi[0x1]; 2813 u8 has_raw[0x1]; 2814 u8 grh_required[0x1]; 2815 u8 reserved_at_104[0xc]; 2816 u8 port_physical_state[0x4]; 2817 u8 vport_state_policy[0x4]; 2818 u8 port_state[0x4]; 2819 u8 vport_state[0x4]; 2820 2821 u8 reserved_at_120[0x20]; 2822 2823 u8 system_image_guid[0x40]; 2824 2825 u8 port_guid[0x40]; 2826 2827 u8 node_guid[0x40]; 2828 2829 u8 cap_mask1[0x20]; 2830 2831 u8 cap_mask1_field_select[0x20]; 2832 2833 u8 cap_mask2[0x20]; 2834 2835 u8 cap_mask2_field_select[0x20]; 2836 2837 u8 reserved_at_280[0x80]; 2838 2839 u8 lid[0x10]; 2840 u8 reserved_at_310[0x4]; 2841 u8 init_type_reply[0x4]; 2842 u8 lmc[0x3]; 2843 u8 subnet_timeout[0x5]; 2844 2845 u8 sm_lid[0x10]; 2846 u8 sm_sl[0x4]; 2847 u8 reserved_at_334[0xc]; 2848 2849 u8 qkey_violation_counter[0x10]; 2850 u8 pkey_violation_counter[0x10]; 2851 2852 u8 reserved_at_360[0xca0]; 2853 }; 2854 2855 struct mlx5_ifc_esw_vport_context_bits { 2856 u8 reserved_at_0[0x3]; 2857 u8 vport_svlan_strip[0x1]; 2858 u8 vport_cvlan_strip[0x1]; 2859 u8 vport_svlan_insert[0x1]; 2860 u8 vport_cvlan_insert[0x2]; 2861 u8 reserved_at_8[0x18]; 2862 2863 u8 reserved_at_20[0x20]; 2864 2865 u8 svlan_cfi[0x1]; 2866 u8 svlan_pcp[0x3]; 2867 u8 svlan_id[0xc]; 2868 u8 cvlan_cfi[0x1]; 2869 u8 cvlan_pcp[0x3]; 2870 u8 cvlan_id[0xc]; 2871 2872 u8 reserved_at_60[0x7a0]; 2873 }; 2874 2875 enum { 2876 MLX5_EQC_STATUS_OK = 0x0, 2877 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 2878 }; 2879 2880 enum { 2881 MLX5_EQC_ST_ARMED = 0x9, 2882 MLX5_EQC_ST_FIRED = 0xa, 2883 }; 2884 2885 struct mlx5_ifc_eqc_bits { 2886 u8 status[0x4]; 2887 u8 reserved_at_4[0x9]; 2888 u8 ec[0x1]; 2889 u8 oi[0x1]; 2890 u8 reserved_at_f[0x5]; 2891 u8 st[0x4]; 2892 u8 reserved_at_18[0x8]; 2893 2894 u8 reserved_at_20[0x20]; 2895 2896 u8 reserved_at_40[0x14]; 2897 u8 page_offset[0x6]; 2898 u8 reserved_at_5a[0x6]; 2899 2900 u8 reserved_at_60[0x3]; 2901 u8 log_eq_size[0x5]; 2902 u8 uar_page[0x18]; 2903 2904 u8 reserved_at_80[0x20]; 2905 2906 u8 reserved_at_a0[0x18]; 2907 u8 intr[0x8]; 2908 2909 u8 reserved_at_c0[0x3]; 2910 u8 log_page_size[0x5]; 2911 u8 reserved_at_c8[0x18]; 2912 2913 u8 reserved_at_e0[0x60]; 2914 2915 u8 reserved_at_140[0x8]; 2916 u8 consumer_counter[0x18]; 2917 2918 u8 reserved_at_160[0x8]; 2919 u8 producer_counter[0x18]; 2920 2921 u8 reserved_at_180[0x80]; 2922 }; 2923 2924 enum { 2925 MLX5_DCTC_STATE_ACTIVE = 0x0, 2926 MLX5_DCTC_STATE_DRAINING = 0x1, 2927 MLX5_DCTC_STATE_DRAINED = 0x2, 2928 }; 2929 2930 enum { 2931 MLX5_DCTC_CS_RES_DISABLE = 0x0, 2932 MLX5_DCTC_CS_RES_NA = 0x1, 2933 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 2934 }; 2935 2936 enum { 2937 MLX5_DCTC_MTU_256_BYTES = 0x1, 2938 MLX5_DCTC_MTU_512_BYTES = 0x2, 2939 MLX5_DCTC_MTU_1K_BYTES = 0x3, 2940 MLX5_DCTC_MTU_2K_BYTES = 0x4, 2941 MLX5_DCTC_MTU_4K_BYTES = 0x5, 2942 }; 2943 2944 struct mlx5_ifc_dctc_bits { 2945 u8 reserved_at_0[0x4]; 2946 u8 state[0x4]; 2947 u8 reserved_at_8[0x18]; 2948 2949 u8 reserved_at_20[0x8]; 2950 u8 user_index[0x18]; 2951 2952 u8 reserved_at_40[0x8]; 2953 u8 cqn[0x18]; 2954 2955 u8 counter_set_id[0x8]; 2956 u8 atomic_mode[0x4]; 2957 u8 rre[0x1]; 2958 u8 rwe[0x1]; 2959 u8 rae[0x1]; 2960 u8 atomic_like_write_en[0x1]; 2961 u8 latency_sensitive[0x1]; 2962 u8 rlky[0x1]; 2963 u8 free_ar[0x1]; 2964 u8 reserved_at_73[0xd]; 2965 2966 u8 reserved_at_80[0x8]; 2967 u8 cs_res[0x8]; 2968 u8 reserved_at_90[0x3]; 2969 u8 min_rnr_nak[0x5]; 2970 u8 reserved_at_98[0x8]; 2971 2972 u8 reserved_at_a0[0x8]; 2973 u8 srqn_xrqn[0x18]; 2974 2975 u8 reserved_at_c0[0x8]; 2976 u8 pd[0x18]; 2977 2978 u8 tclass[0x8]; 2979 u8 reserved_at_e8[0x4]; 2980 u8 flow_label[0x14]; 2981 2982 u8 dc_access_key[0x40]; 2983 2984 u8 reserved_at_140[0x5]; 2985 u8 mtu[0x3]; 2986 u8 port[0x8]; 2987 u8 pkey_index[0x10]; 2988 2989 u8 reserved_at_160[0x8]; 2990 u8 my_addr_index[0x8]; 2991 u8 reserved_at_170[0x8]; 2992 u8 hop_limit[0x8]; 2993 2994 u8 dc_access_key_violation_count[0x20]; 2995 2996 u8 reserved_at_1a0[0x14]; 2997 u8 dei_cfi[0x1]; 2998 u8 eth_prio[0x3]; 2999 u8 ecn[0x2]; 3000 u8 dscp[0x6]; 3001 3002 u8 reserved_at_1c0[0x40]; 3003 }; 3004 3005 enum { 3006 MLX5_CQC_STATUS_OK = 0x0, 3007 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 3008 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 3009 }; 3010 3011 enum { 3012 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 3013 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 3014 }; 3015 3016 enum { 3017 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 3018 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 3019 MLX5_CQC_ST_FIRED = 0xa, 3020 }; 3021 3022 enum { 3023 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 3024 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 3025 MLX5_CQ_PERIOD_NUM_MODES 3026 }; 3027 3028 struct mlx5_ifc_cqc_bits { 3029 u8 status[0x4]; 3030 u8 reserved_at_4[0x4]; 3031 u8 cqe_sz[0x3]; 3032 u8 cc[0x1]; 3033 u8 reserved_at_c[0x1]; 3034 u8 scqe_break_moderation_en[0x1]; 3035 u8 oi[0x1]; 3036 u8 cq_period_mode[0x2]; 3037 u8 cqe_comp_en[0x1]; 3038 u8 mini_cqe_res_format[0x2]; 3039 u8 st[0x4]; 3040 u8 reserved_at_18[0x8]; 3041 3042 u8 reserved_at_20[0x20]; 3043 3044 u8 reserved_at_40[0x14]; 3045 u8 page_offset[0x6]; 3046 u8 reserved_at_5a[0x6]; 3047 3048 u8 reserved_at_60[0x3]; 3049 u8 log_cq_size[0x5]; 3050 u8 uar_page[0x18]; 3051 3052 u8 reserved_at_80[0x4]; 3053 u8 cq_period[0xc]; 3054 u8 cq_max_count[0x10]; 3055 3056 u8 reserved_at_a0[0x18]; 3057 u8 c_eqn[0x8]; 3058 3059 u8 reserved_at_c0[0x3]; 3060 u8 log_page_size[0x5]; 3061 u8 reserved_at_c8[0x18]; 3062 3063 u8 reserved_at_e0[0x20]; 3064 3065 u8 reserved_at_100[0x8]; 3066 u8 last_notified_index[0x18]; 3067 3068 u8 reserved_at_120[0x8]; 3069 u8 last_solicit_index[0x18]; 3070 3071 u8 reserved_at_140[0x8]; 3072 u8 consumer_counter[0x18]; 3073 3074 u8 reserved_at_160[0x8]; 3075 u8 producer_counter[0x18]; 3076 3077 u8 reserved_at_180[0x40]; 3078 3079 u8 dbr_addr[0x40]; 3080 }; 3081 3082 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 3083 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 3084 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 3085 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 3086 u8 reserved_at_0[0x800]; 3087 }; 3088 3089 struct mlx5_ifc_query_adapter_param_block_bits { 3090 u8 reserved_at_0[0xc0]; 3091 3092 u8 reserved_at_c0[0x8]; 3093 u8 ieee_vendor_id[0x18]; 3094 3095 u8 reserved_at_e0[0x10]; 3096 u8 vsd_vendor_id[0x10]; 3097 3098 u8 vsd[208][0x8]; 3099 3100 u8 vsd_contd_psid[16][0x8]; 3101 }; 3102 3103 enum { 3104 MLX5_XRQC_STATE_GOOD = 0x0, 3105 MLX5_XRQC_STATE_ERROR = 0x1, 3106 }; 3107 3108 enum { 3109 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 3110 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 3111 }; 3112 3113 enum { 3114 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 3115 }; 3116 3117 struct mlx5_ifc_tag_matching_topology_context_bits { 3118 u8 log_matching_list_sz[0x4]; 3119 u8 reserved_at_4[0xc]; 3120 u8 append_next_index[0x10]; 3121 3122 u8 sw_phase_cnt[0x10]; 3123 u8 hw_phase_cnt[0x10]; 3124 3125 u8 reserved_at_40[0x40]; 3126 }; 3127 3128 struct mlx5_ifc_xrqc_bits { 3129 u8 state[0x4]; 3130 u8 rlkey[0x1]; 3131 u8 reserved_at_5[0xf]; 3132 u8 topology[0x4]; 3133 u8 reserved_at_18[0x4]; 3134 u8 offload[0x4]; 3135 3136 u8 reserved_at_20[0x8]; 3137 u8 user_index[0x18]; 3138 3139 u8 reserved_at_40[0x8]; 3140 u8 cqn[0x18]; 3141 3142 u8 reserved_at_60[0xa0]; 3143 3144 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 3145 3146 u8 reserved_at_180[0x280]; 3147 3148 struct mlx5_ifc_wq_bits wq; 3149 }; 3150 3151 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 3152 struct mlx5_ifc_modify_field_select_bits modify_field_select; 3153 struct mlx5_ifc_resize_field_select_bits resize_field_select; 3154 u8 reserved_at_0[0x20]; 3155 }; 3156 3157 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 3158 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 3159 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 3160 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 3161 u8 reserved_at_0[0x20]; 3162 }; 3163 3164 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 3165 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 3166 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 3167 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 3168 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 3169 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 3170 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 3171 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout; 3172 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 3173 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 3174 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 3175 u8 reserved_at_0[0x7c0]; 3176 }; 3177 3178 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 3179 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 3180 u8 reserved_at_0[0x7c0]; 3181 }; 3182 3183 union mlx5_ifc_event_auto_bits { 3184 struct mlx5_ifc_comp_event_bits comp_event; 3185 struct mlx5_ifc_dct_events_bits dct_events; 3186 struct mlx5_ifc_qp_events_bits qp_events; 3187 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 3188 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 3189 struct mlx5_ifc_cq_error_bits cq_error; 3190 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 3191 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 3192 struct mlx5_ifc_gpio_event_bits gpio_event; 3193 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 3194 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 3195 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 3196 u8 reserved_at_0[0xe0]; 3197 }; 3198 3199 struct mlx5_ifc_health_buffer_bits { 3200 u8 reserved_at_0[0x100]; 3201 3202 u8 assert_existptr[0x20]; 3203 3204 u8 assert_callra[0x20]; 3205 3206 u8 reserved_at_140[0x40]; 3207 3208 u8 fw_version[0x20]; 3209 3210 u8 hw_id[0x20]; 3211 3212 u8 reserved_at_1c0[0x20]; 3213 3214 u8 irisc_index[0x8]; 3215 u8 synd[0x8]; 3216 u8 ext_synd[0x10]; 3217 }; 3218 3219 struct mlx5_ifc_register_loopback_control_bits { 3220 u8 no_lb[0x1]; 3221 u8 reserved_at_1[0x7]; 3222 u8 port[0x8]; 3223 u8 reserved_at_10[0x10]; 3224 3225 u8 reserved_at_20[0x60]; 3226 }; 3227 3228 struct mlx5_ifc_vport_tc_element_bits { 3229 u8 traffic_class[0x4]; 3230 u8 reserved_at_4[0xc]; 3231 u8 vport_number[0x10]; 3232 }; 3233 3234 struct mlx5_ifc_vport_element_bits { 3235 u8 reserved_at_0[0x10]; 3236 u8 vport_number[0x10]; 3237 }; 3238 3239 enum { 3240 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 3241 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 3242 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 3243 }; 3244 3245 struct mlx5_ifc_tsar_element_bits { 3246 u8 reserved_at_0[0x8]; 3247 u8 tsar_type[0x8]; 3248 u8 reserved_at_10[0x10]; 3249 }; 3250 3251 enum { 3252 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 3253 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 3254 }; 3255 3256 struct mlx5_ifc_teardown_hca_out_bits { 3257 u8 status[0x8]; 3258 u8 reserved_at_8[0x18]; 3259 3260 u8 syndrome[0x20]; 3261 3262 u8 reserved_at_40[0x3f]; 3263 3264 u8 force_state[0x1]; 3265 }; 3266 3267 enum { 3268 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 3269 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 3270 }; 3271 3272 struct mlx5_ifc_teardown_hca_in_bits { 3273 u8 opcode[0x10]; 3274 u8 reserved_at_10[0x10]; 3275 3276 u8 reserved_at_20[0x10]; 3277 u8 op_mod[0x10]; 3278 3279 u8 reserved_at_40[0x10]; 3280 u8 profile[0x10]; 3281 3282 u8 reserved_at_60[0x20]; 3283 }; 3284 3285 struct mlx5_ifc_sqerr2rts_qp_out_bits { 3286 u8 status[0x8]; 3287 u8 reserved_at_8[0x18]; 3288 3289 u8 syndrome[0x20]; 3290 3291 u8 reserved_at_40[0x40]; 3292 }; 3293 3294 struct mlx5_ifc_sqerr2rts_qp_in_bits { 3295 u8 opcode[0x10]; 3296 u8 reserved_at_10[0x10]; 3297 3298 u8 reserved_at_20[0x10]; 3299 u8 op_mod[0x10]; 3300 3301 u8 reserved_at_40[0x8]; 3302 u8 qpn[0x18]; 3303 3304 u8 reserved_at_60[0x20]; 3305 3306 u8 opt_param_mask[0x20]; 3307 3308 u8 reserved_at_a0[0x20]; 3309 3310 struct mlx5_ifc_qpc_bits qpc; 3311 3312 u8 reserved_at_800[0x80]; 3313 }; 3314 3315 struct mlx5_ifc_sqd2rts_qp_out_bits { 3316 u8 status[0x8]; 3317 u8 reserved_at_8[0x18]; 3318 3319 u8 syndrome[0x20]; 3320 3321 u8 reserved_at_40[0x40]; 3322 }; 3323 3324 struct mlx5_ifc_sqd2rts_qp_in_bits { 3325 u8 opcode[0x10]; 3326 u8 reserved_at_10[0x10]; 3327 3328 u8 reserved_at_20[0x10]; 3329 u8 op_mod[0x10]; 3330 3331 u8 reserved_at_40[0x8]; 3332 u8 qpn[0x18]; 3333 3334 u8 reserved_at_60[0x20]; 3335 3336 u8 opt_param_mask[0x20]; 3337 3338 u8 reserved_at_a0[0x20]; 3339 3340 struct mlx5_ifc_qpc_bits qpc; 3341 3342 u8 reserved_at_800[0x80]; 3343 }; 3344 3345 struct mlx5_ifc_set_roce_address_out_bits { 3346 u8 status[0x8]; 3347 u8 reserved_at_8[0x18]; 3348 3349 u8 syndrome[0x20]; 3350 3351 u8 reserved_at_40[0x40]; 3352 }; 3353 3354 struct mlx5_ifc_set_roce_address_in_bits { 3355 u8 opcode[0x10]; 3356 u8 reserved_at_10[0x10]; 3357 3358 u8 reserved_at_20[0x10]; 3359 u8 op_mod[0x10]; 3360 3361 u8 roce_address_index[0x10]; 3362 u8 reserved_at_50[0xc]; 3363 u8 vhca_port_num[0x4]; 3364 3365 u8 reserved_at_60[0x20]; 3366 3367 struct mlx5_ifc_roce_addr_layout_bits roce_address; 3368 }; 3369 3370 struct mlx5_ifc_set_mad_demux_out_bits { 3371 u8 status[0x8]; 3372 u8 reserved_at_8[0x18]; 3373 3374 u8 syndrome[0x20]; 3375 3376 u8 reserved_at_40[0x40]; 3377 }; 3378 3379 enum { 3380 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 3381 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 3382 }; 3383 3384 struct mlx5_ifc_set_mad_demux_in_bits { 3385 u8 opcode[0x10]; 3386 u8 reserved_at_10[0x10]; 3387 3388 u8 reserved_at_20[0x10]; 3389 u8 op_mod[0x10]; 3390 3391 u8 reserved_at_40[0x20]; 3392 3393 u8 reserved_at_60[0x6]; 3394 u8 demux_mode[0x2]; 3395 u8 reserved_at_68[0x18]; 3396 }; 3397 3398 struct mlx5_ifc_set_l2_table_entry_out_bits { 3399 u8 status[0x8]; 3400 u8 reserved_at_8[0x18]; 3401 3402 u8 syndrome[0x20]; 3403 3404 u8 reserved_at_40[0x40]; 3405 }; 3406 3407 struct mlx5_ifc_set_l2_table_entry_in_bits { 3408 u8 opcode[0x10]; 3409 u8 reserved_at_10[0x10]; 3410 3411 u8 reserved_at_20[0x10]; 3412 u8 op_mod[0x10]; 3413 3414 u8 reserved_at_40[0x60]; 3415 3416 u8 reserved_at_a0[0x8]; 3417 u8 table_index[0x18]; 3418 3419 u8 reserved_at_c0[0x20]; 3420 3421 u8 reserved_at_e0[0x13]; 3422 u8 vlan_valid[0x1]; 3423 u8 vlan[0xc]; 3424 3425 struct mlx5_ifc_mac_address_layout_bits mac_address; 3426 3427 u8 reserved_at_140[0xc0]; 3428 }; 3429 3430 struct mlx5_ifc_set_issi_out_bits { 3431 u8 status[0x8]; 3432 u8 reserved_at_8[0x18]; 3433 3434 u8 syndrome[0x20]; 3435 3436 u8 reserved_at_40[0x40]; 3437 }; 3438 3439 struct mlx5_ifc_set_issi_in_bits { 3440 u8 opcode[0x10]; 3441 u8 reserved_at_10[0x10]; 3442 3443 u8 reserved_at_20[0x10]; 3444 u8 op_mod[0x10]; 3445 3446 u8 reserved_at_40[0x10]; 3447 u8 current_issi[0x10]; 3448 3449 u8 reserved_at_60[0x20]; 3450 }; 3451 3452 struct mlx5_ifc_set_hca_cap_out_bits { 3453 u8 status[0x8]; 3454 u8 reserved_at_8[0x18]; 3455 3456 u8 syndrome[0x20]; 3457 3458 u8 reserved_at_40[0x40]; 3459 }; 3460 3461 struct mlx5_ifc_set_hca_cap_in_bits { 3462 u8 opcode[0x10]; 3463 u8 reserved_at_10[0x10]; 3464 3465 u8 reserved_at_20[0x10]; 3466 u8 op_mod[0x10]; 3467 3468 u8 reserved_at_40[0x40]; 3469 3470 union mlx5_ifc_hca_cap_union_bits capability; 3471 }; 3472 3473 enum { 3474 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 3475 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 3476 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 3477 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3 3478 }; 3479 3480 struct mlx5_ifc_set_fte_out_bits { 3481 u8 status[0x8]; 3482 u8 reserved_at_8[0x18]; 3483 3484 u8 syndrome[0x20]; 3485 3486 u8 reserved_at_40[0x40]; 3487 }; 3488 3489 struct mlx5_ifc_set_fte_in_bits { 3490 u8 opcode[0x10]; 3491 u8 reserved_at_10[0x10]; 3492 3493 u8 reserved_at_20[0x10]; 3494 u8 op_mod[0x10]; 3495 3496 u8 other_vport[0x1]; 3497 u8 reserved_at_41[0xf]; 3498 u8 vport_number[0x10]; 3499 3500 u8 reserved_at_60[0x20]; 3501 3502 u8 table_type[0x8]; 3503 u8 reserved_at_88[0x18]; 3504 3505 u8 reserved_at_a0[0x8]; 3506 u8 table_id[0x18]; 3507 3508 u8 reserved_at_c0[0x18]; 3509 u8 modify_enable_mask[0x8]; 3510 3511 u8 reserved_at_e0[0x20]; 3512 3513 u8 flow_index[0x20]; 3514 3515 u8 reserved_at_120[0xe0]; 3516 3517 struct mlx5_ifc_flow_context_bits flow_context; 3518 }; 3519 3520 struct mlx5_ifc_rts2rts_qp_out_bits { 3521 u8 status[0x8]; 3522 u8 reserved_at_8[0x18]; 3523 3524 u8 syndrome[0x20]; 3525 3526 u8 reserved_at_40[0x40]; 3527 }; 3528 3529 struct mlx5_ifc_rts2rts_qp_in_bits { 3530 u8 opcode[0x10]; 3531 u8 reserved_at_10[0x10]; 3532 3533 u8 reserved_at_20[0x10]; 3534 u8 op_mod[0x10]; 3535 3536 u8 reserved_at_40[0x8]; 3537 u8 qpn[0x18]; 3538 3539 u8 reserved_at_60[0x20]; 3540 3541 u8 opt_param_mask[0x20]; 3542 3543 u8 reserved_at_a0[0x20]; 3544 3545 struct mlx5_ifc_qpc_bits qpc; 3546 3547 u8 reserved_at_800[0x80]; 3548 }; 3549 3550 struct mlx5_ifc_rtr2rts_qp_out_bits { 3551 u8 status[0x8]; 3552 u8 reserved_at_8[0x18]; 3553 3554 u8 syndrome[0x20]; 3555 3556 u8 reserved_at_40[0x40]; 3557 }; 3558 3559 struct mlx5_ifc_rtr2rts_qp_in_bits { 3560 u8 opcode[0x10]; 3561 u8 reserved_at_10[0x10]; 3562 3563 u8 reserved_at_20[0x10]; 3564 u8 op_mod[0x10]; 3565 3566 u8 reserved_at_40[0x8]; 3567 u8 qpn[0x18]; 3568 3569 u8 reserved_at_60[0x20]; 3570 3571 u8 opt_param_mask[0x20]; 3572 3573 u8 reserved_at_a0[0x20]; 3574 3575 struct mlx5_ifc_qpc_bits qpc; 3576 3577 u8 reserved_at_800[0x80]; 3578 }; 3579 3580 struct mlx5_ifc_rst2init_qp_out_bits { 3581 u8 status[0x8]; 3582 u8 reserved_at_8[0x18]; 3583 3584 u8 syndrome[0x20]; 3585 3586 u8 reserved_at_40[0x40]; 3587 }; 3588 3589 struct mlx5_ifc_rst2init_qp_in_bits { 3590 u8 opcode[0x10]; 3591 u8 reserved_at_10[0x10]; 3592 3593 u8 reserved_at_20[0x10]; 3594 u8 op_mod[0x10]; 3595 3596 u8 reserved_at_40[0x8]; 3597 u8 qpn[0x18]; 3598 3599 u8 reserved_at_60[0x20]; 3600 3601 u8 opt_param_mask[0x20]; 3602 3603 u8 reserved_at_a0[0x20]; 3604 3605 struct mlx5_ifc_qpc_bits qpc; 3606 3607 u8 reserved_at_800[0x80]; 3608 }; 3609 3610 struct mlx5_ifc_query_xrq_out_bits { 3611 u8 status[0x8]; 3612 u8 reserved_at_8[0x18]; 3613 3614 u8 syndrome[0x20]; 3615 3616 u8 reserved_at_40[0x40]; 3617 3618 struct mlx5_ifc_xrqc_bits xrq_context; 3619 }; 3620 3621 struct mlx5_ifc_query_xrq_in_bits { 3622 u8 opcode[0x10]; 3623 u8 reserved_at_10[0x10]; 3624 3625 u8 reserved_at_20[0x10]; 3626 u8 op_mod[0x10]; 3627 3628 u8 reserved_at_40[0x8]; 3629 u8 xrqn[0x18]; 3630 3631 u8 reserved_at_60[0x20]; 3632 }; 3633 3634 struct mlx5_ifc_query_xrc_srq_out_bits { 3635 u8 status[0x8]; 3636 u8 reserved_at_8[0x18]; 3637 3638 u8 syndrome[0x20]; 3639 3640 u8 reserved_at_40[0x40]; 3641 3642 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 3643 3644 u8 reserved_at_280[0x600]; 3645 3646 u8 pas[0][0x40]; 3647 }; 3648 3649 struct mlx5_ifc_query_xrc_srq_in_bits { 3650 u8 opcode[0x10]; 3651 u8 reserved_at_10[0x10]; 3652 3653 u8 reserved_at_20[0x10]; 3654 u8 op_mod[0x10]; 3655 3656 u8 reserved_at_40[0x8]; 3657 u8 xrc_srqn[0x18]; 3658 3659 u8 reserved_at_60[0x20]; 3660 }; 3661 3662 enum { 3663 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 3664 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 3665 }; 3666 3667 struct mlx5_ifc_query_vport_state_out_bits { 3668 u8 status[0x8]; 3669 u8 reserved_at_8[0x18]; 3670 3671 u8 syndrome[0x20]; 3672 3673 u8 reserved_at_40[0x20]; 3674 3675 u8 reserved_at_60[0x18]; 3676 u8 admin_state[0x4]; 3677 u8 state[0x4]; 3678 }; 3679 3680 enum { 3681 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0, 3682 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1, 3683 }; 3684 3685 struct mlx5_ifc_query_vport_state_in_bits { 3686 u8 opcode[0x10]; 3687 u8 reserved_at_10[0x10]; 3688 3689 u8 reserved_at_20[0x10]; 3690 u8 op_mod[0x10]; 3691 3692 u8 other_vport[0x1]; 3693 u8 reserved_at_41[0xf]; 3694 u8 vport_number[0x10]; 3695 3696 u8 reserved_at_60[0x20]; 3697 }; 3698 3699 struct mlx5_ifc_query_vnic_env_out_bits { 3700 u8 status[0x8]; 3701 u8 reserved_at_8[0x18]; 3702 3703 u8 syndrome[0x20]; 3704 3705 u8 reserved_at_40[0x40]; 3706 3707 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 3708 }; 3709 3710 enum { 3711 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 3712 }; 3713 3714 struct mlx5_ifc_query_vnic_env_in_bits { 3715 u8 opcode[0x10]; 3716 u8 reserved_at_10[0x10]; 3717 3718 u8 reserved_at_20[0x10]; 3719 u8 op_mod[0x10]; 3720 3721 u8 other_vport[0x1]; 3722 u8 reserved_at_41[0xf]; 3723 u8 vport_number[0x10]; 3724 3725 u8 reserved_at_60[0x20]; 3726 }; 3727 3728 struct mlx5_ifc_query_vport_counter_out_bits { 3729 u8 status[0x8]; 3730 u8 reserved_at_8[0x18]; 3731 3732 u8 syndrome[0x20]; 3733 3734 u8 reserved_at_40[0x40]; 3735 3736 struct mlx5_ifc_traffic_counter_bits received_errors; 3737 3738 struct mlx5_ifc_traffic_counter_bits transmit_errors; 3739 3740 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 3741 3742 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 3743 3744 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 3745 3746 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 3747 3748 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 3749 3750 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 3751 3752 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 3753 3754 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 3755 3756 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 3757 3758 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 3759 3760 u8 reserved_at_680[0xa00]; 3761 }; 3762 3763 enum { 3764 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 3765 }; 3766 3767 struct mlx5_ifc_query_vport_counter_in_bits { 3768 u8 opcode[0x10]; 3769 u8 reserved_at_10[0x10]; 3770 3771 u8 reserved_at_20[0x10]; 3772 u8 op_mod[0x10]; 3773 3774 u8 other_vport[0x1]; 3775 u8 reserved_at_41[0xb]; 3776 u8 port_num[0x4]; 3777 u8 vport_number[0x10]; 3778 3779 u8 reserved_at_60[0x60]; 3780 3781 u8 clear[0x1]; 3782 u8 reserved_at_c1[0x1f]; 3783 3784 u8 reserved_at_e0[0x20]; 3785 }; 3786 3787 struct mlx5_ifc_query_tis_out_bits { 3788 u8 status[0x8]; 3789 u8 reserved_at_8[0x18]; 3790 3791 u8 syndrome[0x20]; 3792 3793 u8 reserved_at_40[0x40]; 3794 3795 struct mlx5_ifc_tisc_bits tis_context; 3796 }; 3797 3798 struct mlx5_ifc_query_tis_in_bits { 3799 u8 opcode[0x10]; 3800 u8 reserved_at_10[0x10]; 3801 3802 u8 reserved_at_20[0x10]; 3803 u8 op_mod[0x10]; 3804 3805 u8 reserved_at_40[0x8]; 3806 u8 tisn[0x18]; 3807 3808 u8 reserved_at_60[0x20]; 3809 }; 3810 3811 struct mlx5_ifc_query_tir_out_bits { 3812 u8 status[0x8]; 3813 u8 reserved_at_8[0x18]; 3814 3815 u8 syndrome[0x20]; 3816 3817 u8 reserved_at_40[0xc0]; 3818 3819 struct mlx5_ifc_tirc_bits tir_context; 3820 }; 3821 3822 struct mlx5_ifc_query_tir_in_bits { 3823 u8 opcode[0x10]; 3824 u8 reserved_at_10[0x10]; 3825 3826 u8 reserved_at_20[0x10]; 3827 u8 op_mod[0x10]; 3828 3829 u8 reserved_at_40[0x8]; 3830 u8 tirn[0x18]; 3831 3832 u8 reserved_at_60[0x20]; 3833 }; 3834 3835 struct mlx5_ifc_query_srq_out_bits { 3836 u8 status[0x8]; 3837 u8 reserved_at_8[0x18]; 3838 3839 u8 syndrome[0x20]; 3840 3841 u8 reserved_at_40[0x40]; 3842 3843 struct mlx5_ifc_srqc_bits srq_context_entry; 3844 3845 u8 reserved_at_280[0x600]; 3846 3847 u8 pas[0][0x40]; 3848 }; 3849 3850 struct mlx5_ifc_query_srq_in_bits { 3851 u8 opcode[0x10]; 3852 u8 reserved_at_10[0x10]; 3853 3854 u8 reserved_at_20[0x10]; 3855 u8 op_mod[0x10]; 3856 3857 u8 reserved_at_40[0x8]; 3858 u8 srqn[0x18]; 3859 3860 u8 reserved_at_60[0x20]; 3861 }; 3862 3863 struct mlx5_ifc_query_sq_out_bits { 3864 u8 status[0x8]; 3865 u8 reserved_at_8[0x18]; 3866 3867 u8 syndrome[0x20]; 3868 3869 u8 reserved_at_40[0xc0]; 3870 3871 struct mlx5_ifc_sqc_bits sq_context; 3872 }; 3873 3874 struct mlx5_ifc_query_sq_in_bits { 3875 u8 opcode[0x10]; 3876 u8 reserved_at_10[0x10]; 3877 3878 u8 reserved_at_20[0x10]; 3879 u8 op_mod[0x10]; 3880 3881 u8 reserved_at_40[0x8]; 3882 u8 sqn[0x18]; 3883 3884 u8 reserved_at_60[0x20]; 3885 }; 3886 3887 struct mlx5_ifc_query_special_contexts_out_bits { 3888 u8 status[0x8]; 3889 u8 reserved_at_8[0x18]; 3890 3891 u8 syndrome[0x20]; 3892 3893 u8 dump_fill_mkey[0x20]; 3894 3895 u8 resd_lkey[0x20]; 3896 3897 u8 null_mkey[0x20]; 3898 3899 u8 reserved_at_a0[0x60]; 3900 }; 3901 3902 struct mlx5_ifc_query_special_contexts_in_bits { 3903 u8 opcode[0x10]; 3904 u8 reserved_at_10[0x10]; 3905 3906 u8 reserved_at_20[0x10]; 3907 u8 op_mod[0x10]; 3908 3909 u8 reserved_at_40[0x40]; 3910 }; 3911 3912 struct mlx5_ifc_query_scheduling_element_out_bits { 3913 u8 opcode[0x10]; 3914 u8 reserved_at_10[0x10]; 3915 3916 u8 reserved_at_20[0x10]; 3917 u8 op_mod[0x10]; 3918 3919 u8 reserved_at_40[0xc0]; 3920 3921 struct mlx5_ifc_scheduling_context_bits scheduling_context; 3922 3923 u8 reserved_at_300[0x100]; 3924 }; 3925 3926 enum { 3927 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 3928 }; 3929 3930 struct mlx5_ifc_query_scheduling_element_in_bits { 3931 u8 opcode[0x10]; 3932 u8 reserved_at_10[0x10]; 3933 3934 u8 reserved_at_20[0x10]; 3935 u8 op_mod[0x10]; 3936 3937 u8 scheduling_hierarchy[0x8]; 3938 u8 reserved_at_48[0x18]; 3939 3940 u8 scheduling_element_id[0x20]; 3941 3942 u8 reserved_at_80[0x180]; 3943 }; 3944 3945 struct mlx5_ifc_query_rqt_out_bits { 3946 u8 status[0x8]; 3947 u8 reserved_at_8[0x18]; 3948 3949 u8 syndrome[0x20]; 3950 3951 u8 reserved_at_40[0xc0]; 3952 3953 struct mlx5_ifc_rqtc_bits rqt_context; 3954 }; 3955 3956 struct mlx5_ifc_query_rqt_in_bits { 3957 u8 opcode[0x10]; 3958 u8 reserved_at_10[0x10]; 3959 3960 u8 reserved_at_20[0x10]; 3961 u8 op_mod[0x10]; 3962 3963 u8 reserved_at_40[0x8]; 3964 u8 rqtn[0x18]; 3965 3966 u8 reserved_at_60[0x20]; 3967 }; 3968 3969 struct mlx5_ifc_query_rq_out_bits { 3970 u8 status[0x8]; 3971 u8 reserved_at_8[0x18]; 3972 3973 u8 syndrome[0x20]; 3974 3975 u8 reserved_at_40[0xc0]; 3976 3977 struct mlx5_ifc_rqc_bits rq_context; 3978 }; 3979 3980 struct mlx5_ifc_query_rq_in_bits { 3981 u8 opcode[0x10]; 3982 u8 reserved_at_10[0x10]; 3983 3984 u8 reserved_at_20[0x10]; 3985 u8 op_mod[0x10]; 3986 3987 u8 reserved_at_40[0x8]; 3988 u8 rqn[0x18]; 3989 3990 u8 reserved_at_60[0x20]; 3991 }; 3992 3993 struct mlx5_ifc_query_roce_address_out_bits { 3994 u8 status[0x8]; 3995 u8 reserved_at_8[0x18]; 3996 3997 u8 syndrome[0x20]; 3998 3999 u8 reserved_at_40[0x40]; 4000 4001 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4002 }; 4003 4004 struct mlx5_ifc_query_roce_address_in_bits { 4005 u8 opcode[0x10]; 4006 u8 reserved_at_10[0x10]; 4007 4008 u8 reserved_at_20[0x10]; 4009 u8 op_mod[0x10]; 4010 4011 u8 roce_address_index[0x10]; 4012 u8 reserved_at_50[0xc]; 4013 u8 vhca_port_num[0x4]; 4014 4015 u8 reserved_at_60[0x20]; 4016 }; 4017 4018 struct mlx5_ifc_query_rmp_out_bits { 4019 u8 status[0x8]; 4020 u8 reserved_at_8[0x18]; 4021 4022 u8 syndrome[0x20]; 4023 4024 u8 reserved_at_40[0xc0]; 4025 4026 struct mlx5_ifc_rmpc_bits rmp_context; 4027 }; 4028 4029 struct mlx5_ifc_query_rmp_in_bits { 4030 u8 opcode[0x10]; 4031 u8 reserved_at_10[0x10]; 4032 4033 u8 reserved_at_20[0x10]; 4034 u8 op_mod[0x10]; 4035 4036 u8 reserved_at_40[0x8]; 4037 u8 rmpn[0x18]; 4038 4039 u8 reserved_at_60[0x20]; 4040 }; 4041 4042 struct mlx5_ifc_query_qp_out_bits { 4043 u8 status[0x8]; 4044 u8 reserved_at_8[0x18]; 4045 4046 u8 syndrome[0x20]; 4047 4048 u8 reserved_at_40[0x40]; 4049 4050 u8 opt_param_mask[0x20]; 4051 4052 u8 reserved_at_a0[0x20]; 4053 4054 struct mlx5_ifc_qpc_bits qpc; 4055 4056 u8 reserved_at_800[0x80]; 4057 4058 u8 pas[0][0x40]; 4059 }; 4060 4061 struct mlx5_ifc_query_qp_in_bits { 4062 u8 opcode[0x10]; 4063 u8 reserved_at_10[0x10]; 4064 4065 u8 reserved_at_20[0x10]; 4066 u8 op_mod[0x10]; 4067 4068 u8 reserved_at_40[0x8]; 4069 u8 qpn[0x18]; 4070 4071 u8 reserved_at_60[0x20]; 4072 }; 4073 4074 struct mlx5_ifc_query_q_counter_out_bits { 4075 u8 status[0x8]; 4076 u8 reserved_at_8[0x18]; 4077 4078 u8 syndrome[0x20]; 4079 4080 u8 reserved_at_40[0x40]; 4081 4082 u8 rx_write_requests[0x20]; 4083 4084 u8 reserved_at_a0[0x20]; 4085 4086 u8 rx_read_requests[0x20]; 4087 4088 u8 reserved_at_e0[0x20]; 4089 4090 u8 rx_atomic_requests[0x20]; 4091 4092 u8 reserved_at_120[0x20]; 4093 4094 u8 rx_dct_connect[0x20]; 4095 4096 u8 reserved_at_160[0x20]; 4097 4098 u8 out_of_buffer[0x20]; 4099 4100 u8 reserved_at_1a0[0x20]; 4101 4102 u8 out_of_sequence[0x20]; 4103 4104 u8 reserved_at_1e0[0x20]; 4105 4106 u8 duplicate_request[0x20]; 4107 4108 u8 reserved_at_220[0x20]; 4109 4110 u8 rnr_nak_retry_err[0x20]; 4111 4112 u8 reserved_at_260[0x20]; 4113 4114 u8 packet_seq_err[0x20]; 4115 4116 u8 reserved_at_2a0[0x20]; 4117 4118 u8 implied_nak_seq_err[0x20]; 4119 4120 u8 reserved_at_2e0[0x20]; 4121 4122 u8 local_ack_timeout_err[0x20]; 4123 4124 u8 reserved_at_320[0xa0]; 4125 4126 u8 resp_local_length_error[0x20]; 4127 4128 u8 req_local_length_error[0x20]; 4129 4130 u8 resp_local_qp_error[0x20]; 4131 4132 u8 local_operation_error[0x20]; 4133 4134 u8 resp_local_protection[0x20]; 4135 4136 u8 req_local_protection[0x20]; 4137 4138 u8 resp_cqe_error[0x20]; 4139 4140 u8 req_cqe_error[0x20]; 4141 4142 u8 req_mw_binding[0x20]; 4143 4144 u8 req_bad_response[0x20]; 4145 4146 u8 req_remote_invalid_request[0x20]; 4147 4148 u8 resp_remote_invalid_request[0x20]; 4149 4150 u8 req_remote_access_errors[0x20]; 4151 4152 u8 resp_remote_access_errors[0x20]; 4153 4154 u8 req_remote_operation_errors[0x20]; 4155 4156 u8 req_transport_retries_exceeded[0x20]; 4157 4158 u8 cq_overflow[0x20]; 4159 4160 u8 resp_cqe_flush_error[0x20]; 4161 4162 u8 req_cqe_flush_error[0x20]; 4163 4164 u8 reserved_at_620[0x1e0]; 4165 }; 4166 4167 struct mlx5_ifc_query_q_counter_in_bits { 4168 u8 opcode[0x10]; 4169 u8 reserved_at_10[0x10]; 4170 4171 u8 reserved_at_20[0x10]; 4172 u8 op_mod[0x10]; 4173 4174 u8 reserved_at_40[0x80]; 4175 4176 u8 clear[0x1]; 4177 u8 reserved_at_c1[0x1f]; 4178 4179 u8 reserved_at_e0[0x18]; 4180 u8 counter_set_id[0x8]; 4181 }; 4182 4183 struct mlx5_ifc_query_pages_out_bits { 4184 u8 status[0x8]; 4185 u8 reserved_at_8[0x18]; 4186 4187 u8 syndrome[0x20]; 4188 4189 u8 reserved_at_40[0x10]; 4190 u8 function_id[0x10]; 4191 4192 u8 num_pages[0x20]; 4193 }; 4194 4195 enum { 4196 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 4197 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 4198 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 4199 }; 4200 4201 struct mlx5_ifc_query_pages_in_bits { 4202 u8 opcode[0x10]; 4203 u8 reserved_at_10[0x10]; 4204 4205 u8 reserved_at_20[0x10]; 4206 u8 op_mod[0x10]; 4207 4208 u8 reserved_at_40[0x10]; 4209 u8 function_id[0x10]; 4210 4211 u8 reserved_at_60[0x20]; 4212 }; 4213 4214 struct mlx5_ifc_query_nic_vport_context_out_bits { 4215 u8 status[0x8]; 4216 u8 reserved_at_8[0x18]; 4217 4218 u8 syndrome[0x20]; 4219 4220 u8 reserved_at_40[0x40]; 4221 4222 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 4223 }; 4224 4225 struct mlx5_ifc_query_nic_vport_context_in_bits { 4226 u8 opcode[0x10]; 4227 u8 reserved_at_10[0x10]; 4228 4229 u8 reserved_at_20[0x10]; 4230 u8 op_mod[0x10]; 4231 4232 u8 other_vport[0x1]; 4233 u8 reserved_at_41[0xf]; 4234 u8 vport_number[0x10]; 4235 4236 u8 reserved_at_60[0x5]; 4237 u8 allowed_list_type[0x3]; 4238 u8 reserved_at_68[0x18]; 4239 }; 4240 4241 struct mlx5_ifc_query_mkey_out_bits { 4242 u8 status[0x8]; 4243 u8 reserved_at_8[0x18]; 4244 4245 u8 syndrome[0x20]; 4246 4247 u8 reserved_at_40[0x40]; 4248 4249 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 4250 4251 u8 reserved_at_280[0x600]; 4252 4253 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 4254 4255 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 4256 }; 4257 4258 struct mlx5_ifc_query_mkey_in_bits { 4259 u8 opcode[0x10]; 4260 u8 reserved_at_10[0x10]; 4261 4262 u8 reserved_at_20[0x10]; 4263 u8 op_mod[0x10]; 4264 4265 u8 reserved_at_40[0x8]; 4266 u8 mkey_index[0x18]; 4267 4268 u8 pg_access[0x1]; 4269 u8 reserved_at_61[0x1f]; 4270 }; 4271 4272 struct mlx5_ifc_query_mad_demux_out_bits { 4273 u8 status[0x8]; 4274 u8 reserved_at_8[0x18]; 4275 4276 u8 syndrome[0x20]; 4277 4278 u8 reserved_at_40[0x40]; 4279 4280 u8 mad_dumux_parameters_block[0x20]; 4281 }; 4282 4283 struct mlx5_ifc_query_mad_demux_in_bits { 4284 u8 opcode[0x10]; 4285 u8 reserved_at_10[0x10]; 4286 4287 u8 reserved_at_20[0x10]; 4288 u8 op_mod[0x10]; 4289 4290 u8 reserved_at_40[0x40]; 4291 }; 4292 4293 struct mlx5_ifc_query_l2_table_entry_out_bits { 4294 u8 status[0x8]; 4295 u8 reserved_at_8[0x18]; 4296 4297 u8 syndrome[0x20]; 4298 4299 u8 reserved_at_40[0xa0]; 4300 4301 u8 reserved_at_e0[0x13]; 4302 u8 vlan_valid[0x1]; 4303 u8 vlan[0xc]; 4304 4305 struct mlx5_ifc_mac_address_layout_bits mac_address; 4306 4307 u8 reserved_at_140[0xc0]; 4308 }; 4309 4310 struct mlx5_ifc_query_l2_table_entry_in_bits { 4311 u8 opcode[0x10]; 4312 u8 reserved_at_10[0x10]; 4313 4314 u8 reserved_at_20[0x10]; 4315 u8 op_mod[0x10]; 4316 4317 u8 reserved_at_40[0x60]; 4318 4319 u8 reserved_at_a0[0x8]; 4320 u8 table_index[0x18]; 4321 4322 u8 reserved_at_c0[0x140]; 4323 }; 4324 4325 struct mlx5_ifc_query_issi_out_bits { 4326 u8 status[0x8]; 4327 u8 reserved_at_8[0x18]; 4328 4329 u8 syndrome[0x20]; 4330 4331 u8 reserved_at_40[0x10]; 4332 u8 current_issi[0x10]; 4333 4334 u8 reserved_at_60[0xa0]; 4335 4336 u8 reserved_at_100[76][0x8]; 4337 u8 supported_issi_dw0[0x20]; 4338 }; 4339 4340 struct mlx5_ifc_query_issi_in_bits { 4341 u8 opcode[0x10]; 4342 u8 reserved_at_10[0x10]; 4343 4344 u8 reserved_at_20[0x10]; 4345 u8 op_mod[0x10]; 4346 4347 u8 reserved_at_40[0x40]; 4348 }; 4349 4350 struct mlx5_ifc_set_driver_version_out_bits { 4351 u8 status[0x8]; 4352 u8 reserved_0[0x18]; 4353 4354 u8 syndrome[0x20]; 4355 u8 reserved_1[0x40]; 4356 }; 4357 4358 struct mlx5_ifc_set_driver_version_in_bits { 4359 u8 opcode[0x10]; 4360 u8 reserved_0[0x10]; 4361 4362 u8 reserved_1[0x10]; 4363 u8 op_mod[0x10]; 4364 4365 u8 reserved_2[0x40]; 4366 u8 driver_version[64][0x8]; 4367 }; 4368 4369 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 4370 u8 status[0x8]; 4371 u8 reserved_at_8[0x18]; 4372 4373 u8 syndrome[0x20]; 4374 4375 u8 reserved_at_40[0x40]; 4376 4377 struct mlx5_ifc_pkey_bits pkey[0]; 4378 }; 4379 4380 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 4381 u8 opcode[0x10]; 4382 u8 reserved_at_10[0x10]; 4383 4384 u8 reserved_at_20[0x10]; 4385 u8 op_mod[0x10]; 4386 4387 u8 other_vport[0x1]; 4388 u8 reserved_at_41[0xb]; 4389 u8 port_num[0x4]; 4390 u8 vport_number[0x10]; 4391 4392 u8 reserved_at_60[0x10]; 4393 u8 pkey_index[0x10]; 4394 }; 4395 4396 enum { 4397 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 4398 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 4399 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 4400 }; 4401 4402 struct mlx5_ifc_query_hca_vport_gid_out_bits { 4403 u8 status[0x8]; 4404 u8 reserved_at_8[0x18]; 4405 4406 u8 syndrome[0x20]; 4407 4408 u8 reserved_at_40[0x20]; 4409 4410 u8 gids_num[0x10]; 4411 u8 reserved_at_70[0x10]; 4412 4413 struct mlx5_ifc_array128_auto_bits gid[0]; 4414 }; 4415 4416 struct mlx5_ifc_query_hca_vport_gid_in_bits { 4417 u8 opcode[0x10]; 4418 u8 reserved_at_10[0x10]; 4419 4420 u8 reserved_at_20[0x10]; 4421 u8 op_mod[0x10]; 4422 4423 u8 other_vport[0x1]; 4424 u8 reserved_at_41[0xb]; 4425 u8 port_num[0x4]; 4426 u8 vport_number[0x10]; 4427 4428 u8 reserved_at_60[0x10]; 4429 u8 gid_index[0x10]; 4430 }; 4431 4432 struct mlx5_ifc_query_hca_vport_context_out_bits { 4433 u8 status[0x8]; 4434 u8 reserved_at_8[0x18]; 4435 4436 u8 syndrome[0x20]; 4437 4438 u8 reserved_at_40[0x40]; 4439 4440 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 4441 }; 4442 4443 struct mlx5_ifc_query_hca_vport_context_in_bits { 4444 u8 opcode[0x10]; 4445 u8 reserved_at_10[0x10]; 4446 4447 u8 reserved_at_20[0x10]; 4448 u8 op_mod[0x10]; 4449 4450 u8 other_vport[0x1]; 4451 u8 reserved_at_41[0xb]; 4452 u8 port_num[0x4]; 4453 u8 vport_number[0x10]; 4454 4455 u8 reserved_at_60[0x20]; 4456 }; 4457 4458 struct mlx5_ifc_query_hca_cap_out_bits { 4459 u8 status[0x8]; 4460 u8 reserved_at_8[0x18]; 4461 4462 u8 syndrome[0x20]; 4463 4464 u8 reserved_at_40[0x40]; 4465 4466 union mlx5_ifc_hca_cap_union_bits capability; 4467 }; 4468 4469 struct mlx5_ifc_query_hca_cap_in_bits { 4470 u8 opcode[0x10]; 4471 u8 reserved_at_10[0x10]; 4472 4473 u8 reserved_at_20[0x10]; 4474 u8 op_mod[0x10]; 4475 4476 u8 reserved_at_40[0x40]; 4477 }; 4478 4479 struct mlx5_ifc_query_flow_table_out_bits { 4480 u8 status[0x8]; 4481 u8 reserved_at_8[0x18]; 4482 4483 u8 syndrome[0x20]; 4484 4485 u8 reserved_at_40[0x80]; 4486 4487 u8 reserved_at_c0[0x8]; 4488 u8 level[0x8]; 4489 u8 reserved_at_d0[0x8]; 4490 u8 log_size[0x8]; 4491 4492 u8 reserved_at_e0[0x120]; 4493 }; 4494 4495 struct mlx5_ifc_query_flow_table_in_bits { 4496 u8 opcode[0x10]; 4497 u8 reserved_at_10[0x10]; 4498 4499 u8 reserved_at_20[0x10]; 4500 u8 op_mod[0x10]; 4501 4502 u8 reserved_at_40[0x40]; 4503 4504 u8 table_type[0x8]; 4505 u8 reserved_at_88[0x18]; 4506 4507 u8 reserved_at_a0[0x8]; 4508 u8 table_id[0x18]; 4509 4510 u8 reserved_at_c0[0x140]; 4511 }; 4512 4513 struct mlx5_ifc_query_fte_out_bits { 4514 u8 status[0x8]; 4515 u8 reserved_at_8[0x18]; 4516 4517 u8 syndrome[0x20]; 4518 4519 u8 reserved_at_40[0x1c0]; 4520 4521 struct mlx5_ifc_flow_context_bits flow_context; 4522 }; 4523 4524 struct mlx5_ifc_query_fte_in_bits { 4525 u8 opcode[0x10]; 4526 u8 reserved_at_10[0x10]; 4527 4528 u8 reserved_at_20[0x10]; 4529 u8 op_mod[0x10]; 4530 4531 u8 reserved_at_40[0x40]; 4532 4533 u8 table_type[0x8]; 4534 u8 reserved_at_88[0x18]; 4535 4536 u8 reserved_at_a0[0x8]; 4537 u8 table_id[0x18]; 4538 4539 u8 reserved_at_c0[0x40]; 4540 4541 u8 flow_index[0x20]; 4542 4543 u8 reserved_at_120[0xe0]; 4544 }; 4545 4546 enum { 4547 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 4548 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 4549 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 4550 }; 4551 4552 struct mlx5_ifc_query_flow_group_out_bits { 4553 u8 status[0x8]; 4554 u8 reserved_at_8[0x18]; 4555 4556 u8 syndrome[0x20]; 4557 4558 u8 reserved_at_40[0xa0]; 4559 4560 u8 start_flow_index[0x20]; 4561 4562 u8 reserved_at_100[0x20]; 4563 4564 u8 end_flow_index[0x20]; 4565 4566 u8 reserved_at_140[0xa0]; 4567 4568 u8 reserved_at_1e0[0x18]; 4569 u8 match_criteria_enable[0x8]; 4570 4571 struct mlx5_ifc_fte_match_param_bits match_criteria; 4572 4573 u8 reserved_at_1200[0xe00]; 4574 }; 4575 4576 struct mlx5_ifc_query_flow_group_in_bits { 4577 u8 opcode[0x10]; 4578 u8 reserved_at_10[0x10]; 4579 4580 u8 reserved_at_20[0x10]; 4581 u8 op_mod[0x10]; 4582 4583 u8 reserved_at_40[0x40]; 4584 4585 u8 table_type[0x8]; 4586 u8 reserved_at_88[0x18]; 4587 4588 u8 reserved_at_a0[0x8]; 4589 u8 table_id[0x18]; 4590 4591 u8 group_id[0x20]; 4592 4593 u8 reserved_at_e0[0x120]; 4594 }; 4595 4596 struct mlx5_ifc_query_flow_counter_out_bits { 4597 u8 status[0x8]; 4598 u8 reserved_at_8[0x18]; 4599 4600 u8 syndrome[0x20]; 4601 4602 u8 reserved_at_40[0x40]; 4603 4604 struct mlx5_ifc_traffic_counter_bits flow_statistics[0]; 4605 }; 4606 4607 struct mlx5_ifc_query_flow_counter_in_bits { 4608 u8 opcode[0x10]; 4609 u8 reserved_at_10[0x10]; 4610 4611 u8 reserved_at_20[0x10]; 4612 u8 op_mod[0x10]; 4613 4614 u8 reserved_at_40[0x80]; 4615 4616 u8 clear[0x1]; 4617 u8 reserved_at_c1[0xf]; 4618 u8 num_of_counters[0x10]; 4619 4620 u8 flow_counter_id[0x20]; 4621 }; 4622 4623 struct mlx5_ifc_query_esw_vport_context_out_bits { 4624 u8 status[0x8]; 4625 u8 reserved_at_8[0x18]; 4626 4627 u8 syndrome[0x20]; 4628 4629 u8 reserved_at_40[0x40]; 4630 4631 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 4632 }; 4633 4634 struct mlx5_ifc_query_esw_vport_context_in_bits { 4635 u8 opcode[0x10]; 4636 u8 reserved_at_10[0x10]; 4637 4638 u8 reserved_at_20[0x10]; 4639 u8 op_mod[0x10]; 4640 4641 u8 other_vport[0x1]; 4642 u8 reserved_at_41[0xf]; 4643 u8 vport_number[0x10]; 4644 4645 u8 reserved_at_60[0x20]; 4646 }; 4647 4648 struct mlx5_ifc_modify_esw_vport_context_out_bits { 4649 u8 status[0x8]; 4650 u8 reserved_at_8[0x18]; 4651 4652 u8 syndrome[0x20]; 4653 4654 u8 reserved_at_40[0x40]; 4655 }; 4656 4657 struct mlx5_ifc_esw_vport_context_fields_select_bits { 4658 u8 reserved_at_0[0x1c]; 4659 u8 vport_cvlan_insert[0x1]; 4660 u8 vport_svlan_insert[0x1]; 4661 u8 vport_cvlan_strip[0x1]; 4662 u8 vport_svlan_strip[0x1]; 4663 }; 4664 4665 struct mlx5_ifc_modify_esw_vport_context_in_bits { 4666 u8 opcode[0x10]; 4667 u8 reserved_at_10[0x10]; 4668 4669 u8 reserved_at_20[0x10]; 4670 u8 op_mod[0x10]; 4671 4672 u8 other_vport[0x1]; 4673 u8 reserved_at_41[0xf]; 4674 u8 vport_number[0x10]; 4675 4676 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 4677 4678 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 4679 }; 4680 4681 struct mlx5_ifc_query_eq_out_bits { 4682 u8 status[0x8]; 4683 u8 reserved_at_8[0x18]; 4684 4685 u8 syndrome[0x20]; 4686 4687 u8 reserved_at_40[0x40]; 4688 4689 struct mlx5_ifc_eqc_bits eq_context_entry; 4690 4691 u8 reserved_at_280[0x40]; 4692 4693 u8 event_bitmask[0x40]; 4694 4695 u8 reserved_at_300[0x580]; 4696 4697 u8 pas[0][0x40]; 4698 }; 4699 4700 struct mlx5_ifc_query_eq_in_bits { 4701 u8 opcode[0x10]; 4702 u8 reserved_at_10[0x10]; 4703 4704 u8 reserved_at_20[0x10]; 4705 u8 op_mod[0x10]; 4706 4707 u8 reserved_at_40[0x18]; 4708 u8 eq_number[0x8]; 4709 4710 u8 reserved_at_60[0x20]; 4711 }; 4712 4713 struct mlx5_ifc_encap_header_in_bits { 4714 u8 reserved_at_0[0x5]; 4715 u8 header_type[0x3]; 4716 u8 reserved_at_8[0xe]; 4717 u8 encap_header_size[0xa]; 4718 4719 u8 reserved_at_20[0x10]; 4720 u8 encap_header[2][0x8]; 4721 4722 u8 more_encap_header[0][0x8]; 4723 }; 4724 4725 struct mlx5_ifc_query_encap_header_out_bits { 4726 u8 status[0x8]; 4727 u8 reserved_at_8[0x18]; 4728 4729 u8 syndrome[0x20]; 4730 4731 u8 reserved_at_40[0xa0]; 4732 4733 struct mlx5_ifc_encap_header_in_bits encap_header[0]; 4734 }; 4735 4736 struct mlx5_ifc_query_encap_header_in_bits { 4737 u8 opcode[0x10]; 4738 u8 reserved_at_10[0x10]; 4739 4740 u8 reserved_at_20[0x10]; 4741 u8 op_mod[0x10]; 4742 4743 u8 encap_id[0x20]; 4744 4745 u8 reserved_at_60[0xa0]; 4746 }; 4747 4748 struct mlx5_ifc_alloc_encap_header_out_bits { 4749 u8 status[0x8]; 4750 u8 reserved_at_8[0x18]; 4751 4752 u8 syndrome[0x20]; 4753 4754 u8 encap_id[0x20]; 4755 4756 u8 reserved_at_60[0x20]; 4757 }; 4758 4759 struct mlx5_ifc_alloc_encap_header_in_bits { 4760 u8 opcode[0x10]; 4761 u8 reserved_at_10[0x10]; 4762 4763 u8 reserved_at_20[0x10]; 4764 u8 op_mod[0x10]; 4765 4766 u8 reserved_at_40[0xa0]; 4767 4768 struct mlx5_ifc_encap_header_in_bits encap_header; 4769 }; 4770 4771 struct mlx5_ifc_dealloc_encap_header_out_bits { 4772 u8 status[0x8]; 4773 u8 reserved_at_8[0x18]; 4774 4775 u8 syndrome[0x20]; 4776 4777 u8 reserved_at_40[0x40]; 4778 }; 4779 4780 struct mlx5_ifc_dealloc_encap_header_in_bits { 4781 u8 opcode[0x10]; 4782 u8 reserved_at_10[0x10]; 4783 4784 u8 reserved_20[0x10]; 4785 u8 op_mod[0x10]; 4786 4787 u8 encap_id[0x20]; 4788 4789 u8 reserved_60[0x20]; 4790 }; 4791 4792 struct mlx5_ifc_set_action_in_bits { 4793 u8 action_type[0x4]; 4794 u8 field[0xc]; 4795 u8 reserved_at_10[0x3]; 4796 u8 offset[0x5]; 4797 u8 reserved_at_18[0x3]; 4798 u8 length[0x5]; 4799 4800 u8 data[0x20]; 4801 }; 4802 4803 struct mlx5_ifc_add_action_in_bits { 4804 u8 action_type[0x4]; 4805 u8 field[0xc]; 4806 u8 reserved_at_10[0x10]; 4807 4808 u8 data[0x20]; 4809 }; 4810 4811 union mlx5_ifc_set_action_in_add_action_in_auto_bits { 4812 struct mlx5_ifc_set_action_in_bits set_action_in; 4813 struct mlx5_ifc_add_action_in_bits add_action_in; 4814 u8 reserved_at_0[0x40]; 4815 }; 4816 4817 enum { 4818 MLX5_ACTION_TYPE_SET = 0x1, 4819 MLX5_ACTION_TYPE_ADD = 0x2, 4820 }; 4821 4822 enum { 4823 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 4824 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 4825 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 4826 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 4827 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 4828 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 4829 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 4830 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 4831 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 4832 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 4833 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 4834 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 4835 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 4836 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 4837 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 4838 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 4839 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 4840 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 4841 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 4842 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 4843 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 4844 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 4845 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 4846 }; 4847 4848 struct mlx5_ifc_alloc_modify_header_context_out_bits { 4849 u8 status[0x8]; 4850 u8 reserved_at_8[0x18]; 4851 4852 u8 syndrome[0x20]; 4853 4854 u8 modify_header_id[0x20]; 4855 4856 u8 reserved_at_60[0x20]; 4857 }; 4858 4859 struct mlx5_ifc_alloc_modify_header_context_in_bits { 4860 u8 opcode[0x10]; 4861 u8 reserved_at_10[0x10]; 4862 4863 u8 reserved_at_20[0x10]; 4864 u8 op_mod[0x10]; 4865 4866 u8 reserved_at_40[0x20]; 4867 4868 u8 table_type[0x8]; 4869 u8 reserved_at_68[0x10]; 4870 u8 num_of_actions[0x8]; 4871 4872 union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0]; 4873 }; 4874 4875 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 4876 u8 status[0x8]; 4877 u8 reserved_at_8[0x18]; 4878 4879 u8 syndrome[0x20]; 4880 4881 u8 reserved_at_40[0x40]; 4882 }; 4883 4884 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 4885 u8 opcode[0x10]; 4886 u8 reserved_at_10[0x10]; 4887 4888 u8 reserved_at_20[0x10]; 4889 u8 op_mod[0x10]; 4890 4891 u8 modify_header_id[0x20]; 4892 4893 u8 reserved_at_60[0x20]; 4894 }; 4895 4896 struct mlx5_ifc_query_dct_out_bits { 4897 u8 status[0x8]; 4898 u8 reserved_at_8[0x18]; 4899 4900 u8 syndrome[0x20]; 4901 4902 u8 reserved_at_40[0x40]; 4903 4904 struct mlx5_ifc_dctc_bits dct_context_entry; 4905 4906 u8 reserved_at_280[0x180]; 4907 }; 4908 4909 struct mlx5_ifc_query_dct_in_bits { 4910 u8 opcode[0x10]; 4911 u8 reserved_at_10[0x10]; 4912 4913 u8 reserved_at_20[0x10]; 4914 u8 op_mod[0x10]; 4915 4916 u8 reserved_at_40[0x8]; 4917 u8 dctn[0x18]; 4918 4919 u8 reserved_at_60[0x20]; 4920 }; 4921 4922 struct mlx5_ifc_query_cq_out_bits { 4923 u8 status[0x8]; 4924 u8 reserved_at_8[0x18]; 4925 4926 u8 syndrome[0x20]; 4927 4928 u8 reserved_at_40[0x40]; 4929 4930 struct mlx5_ifc_cqc_bits cq_context; 4931 4932 u8 reserved_at_280[0x600]; 4933 4934 u8 pas[0][0x40]; 4935 }; 4936 4937 struct mlx5_ifc_query_cq_in_bits { 4938 u8 opcode[0x10]; 4939 u8 reserved_at_10[0x10]; 4940 4941 u8 reserved_at_20[0x10]; 4942 u8 op_mod[0x10]; 4943 4944 u8 reserved_at_40[0x8]; 4945 u8 cqn[0x18]; 4946 4947 u8 reserved_at_60[0x20]; 4948 }; 4949 4950 struct mlx5_ifc_query_cong_status_out_bits { 4951 u8 status[0x8]; 4952 u8 reserved_at_8[0x18]; 4953 4954 u8 syndrome[0x20]; 4955 4956 u8 reserved_at_40[0x20]; 4957 4958 u8 enable[0x1]; 4959 u8 tag_enable[0x1]; 4960 u8 reserved_at_62[0x1e]; 4961 }; 4962 4963 struct mlx5_ifc_query_cong_status_in_bits { 4964 u8 opcode[0x10]; 4965 u8 reserved_at_10[0x10]; 4966 4967 u8 reserved_at_20[0x10]; 4968 u8 op_mod[0x10]; 4969 4970 u8 reserved_at_40[0x18]; 4971 u8 priority[0x4]; 4972 u8 cong_protocol[0x4]; 4973 4974 u8 reserved_at_60[0x20]; 4975 }; 4976 4977 struct mlx5_ifc_query_cong_statistics_out_bits { 4978 u8 status[0x8]; 4979 u8 reserved_at_8[0x18]; 4980 4981 u8 syndrome[0x20]; 4982 4983 u8 reserved_at_40[0x40]; 4984 4985 u8 rp_cur_flows[0x20]; 4986 4987 u8 sum_flows[0x20]; 4988 4989 u8 rp_cnp_ignored_high[0x20]; 4990 4991 u8 rp_cnp_ignored_low[0x20]; 4992 4993 u8 rp_cnp_handled_high[0x20]; 4994 4995 u8 rp_cnp_handled_low[0x20]; 4996 4997 u8 reserved_at_140[0x100]; 4998 4999 u8 time_stamp_high[0x20]; 5000 5001 u8 time_stamp_low[0x20]; 5002 5003 u8 accumulators_period[0x20]; 5004 5005 u8 np_ecn_marked_roce_packets_high[0x20]; 5006 5007 u8 np_ecn_marked_roce_packets_low[0x20]; 5008 5009 u8 np_cnp_sent_high[0x20]; 5010 5011 u8 np_cnp_sent_low[0x20]; 5012 5013 u8 reserved_at_320[0x560]; 5014 }; 5015 5016 struct mlx5_ifc_query_cong_statistics_in_bits { 5017 u8 opcode[0x10]; 5018 u8 reserved_at_10[0x10]; 5019 5020 u8 reserved_at_20[0x10]; 5021 u8 op_mod[0x10]; 5022 5023 u8 clear[0x1]; 5024 u8 reserved_at_41[0x1f]; 5025 5026 u8 reserved_at_60[0x20]; 5027 }; 5028 5029 struct mlx5_ifc_query_cong_params_out_bits { 5030 u8 status[0x8]; 5031 u8 reserved_at_8[0x18]; 5032 5033 u8 syndrome[0x20]; 5034 5035 u8 reserved_at_40[0x40]; 5036 5037 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5038 }; 5039 5040 struct mlx5_ifc_query_cong_params_in_bits { 5041 u8 opcode[0x10]; 5042 u8 reserved_at_10[0x10]; 5043 5044 u8 reserved_at_20[0x10]; 5045 u8 op_mod[0x10]; 5046 5047 u8 reserved_at_40[0x1c]; 5048 u8 cong_protocol[0x4]; 5049 5050 u8 reserved_at_60[0x20]; 5051 }; 5052 5053 struct mlx5_ifc_query_adapter_out_bits { 5054 u8 status[0x8]; 5055 u8 reserved_at_8[0x18]; 5056 5057 u8 syndrome[0x20]; 5058 5059 u8 reserved_at_40[0x40]; 5060 5061 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 5062 }; 5063 5064 struct mlx5_ifc_query_adapter_in_bits { 5065 u8 opcode[0x10]; 5066 u8 reserved_at_10[0x10]; 5067 5068 u8 reserved_at_20[0x10]; 5069 u8 op_mod[0x10]; 5070 5071 u8 reserved_at_40[0x40]; 5072 }; 5073 5074 struct mlx5_ifc_qp_2rst_out_bits { 5075 u8 status[0x8]; 5076 u8 reserved_at_8[0x18]; 5077 5078 u8 syndrome[0x20]; 5079 5080 u8 reserved_at_40[0x40]; 5081 }; 5082 5083 struct mlx5_ifc_qp_2rst_in_bits { 5084 u8 opcode[0x10]; 5085 u8 reserved_at_10[0x10]; 5086 5087 u8 reserved_at_20[0x10]; 5088 u8 op_mod[0x10]; 5089 5090 u8 reserved_at_40[0x8]; 5091 u8 qpn[0x18]; 5092 5093 u8 reserved_at_60[0x20]; 5094 }; 5095 5096 struct mlx5_ifc_qp_2err_out_bits { 5097 u8 status[0x8]; 5098 u8 reserved_at_8[0x18]; 5099 5100 u8 syndrome[0x20]; 5101 5102 u8 reserved_at_40[0x40]; 5103 }; 5104 5105 struct mlx5_ifc_qp_2err_in_bits { 5106 u8 opcode[0x10]; 5107 u8 reserved_at_10[0x10]; 5108 5109 u8 reserved_at_20[0x10]; 5110 u8 op_mod[0x10]; 5111 5112 u8 reserved_at_40[0x8]; 5113 u8 qpn[0x18]; 5114 5115 u8 reserved_at_60[0x20]; 5116 }; 5117 5118 struct mlx5_ifc_page_fault_resume_out_bits { 5119 u8 status[0x8]; 5120 u8 reserved_at_8[0x18]; 5121 5122 u8 syndrome[0x20]; 5123 5124 u8 reserved_at_40[0x40]; 5125 }; 5126 5127 struct mlx5_ifc_page_fault_resume_in_bits { 5128 u8 opcode[0x10]; 5129 u8 reserved_at_10[0x10]; 5130 5131 u8 reserved_at_20[0x10]; 5132 u8 op_mod[0x10]; 5133 5134 u8 error[0x1]; 5135 u8 reserved_at_41[0x4]; 5136 u8 page_fault_type[0x3]; 5137 u8 wq_number[0x18]; 5138 5139 u8 reserved_at_60[0x8]; 5140 u8 token[0x18]; 5141 }; 5142 5143 struct mlx5_ifc_nop_out_bits { 5144 u8 status[0x8]; 5145 u8 reserved_at_8[0x18]; 5146 5147 u8 syndrome[0x20]; 5148 5149 u8 reserved_at_40[0x40]; 5150 }; 5151 5152 struct mlx5_ifc_nop_in_bits { 5153 u8 opcode[0x10]; 5154 u8 reserved_at_10[0x10]; 5155 5156 u8 reserved_at_20[0x10]; 5157 u8 op_mod[0x10]; 5158 5159 u8 reserved_at_40[0x40]; 5160 }; 5161 5162 struct mlx5_ifc_modify_vport_state_out_bits { 5163 u8 status[0x8]; 5164 u8 reserved_at_8[0x18]; 5165 5166 u8 syndrome[0x20]; 5167 5168 u8 reserved_at_40[0x40]; 5169 }; 5170 5171 struct mlx5_ifc_modify_vport_state_in_bits { 5172 u8 opcode[0x10]; 5173 u8 reserved_at_10[0x10]; 5174 5175 u8 reserved_at_20[0x10]; 5176 u8 op_mod[0x10]; 5177 5178 u8 other_vport[0x1]; 5179 u8 reserved_at_41[0xf]; 5180 u8 vport_number[0x10]; 5181 5182 u8 reserved_at_60[0x18]; 5183 u8 admin_state[0x4]; 5184 u8 reserved_at_7c[0x4]; 5185 }; 5186 5187 struct mlx5_ifc_modify_tis_out_bits { 5188 u8 status[0x8]; 5189 u8 reserved_at_8[0x18]; 5190 5191 u8 syndrome[0x20]; 5192 5193 u8 reserved_at_40[0x40]; 5194 }; 5195 5196 struct mlx5_ifc_modify_tis_bitmask_bits { 5197 u8 reserved_at_0[0x20]; 5198 5199 u8 reserved_at_20[0x1d]; 5200 u8 lag_tx_port_affinity[0x1]; 5201 u8 strict_lag_tx_port_affinity[0x1]; 5202 u8 prio[0x1]; 5203 }; 5204 5205 struct mlx5_ifc_modify_tis_in_bits { 5206 u8 opcode[0x10]; 5207 u8 reserved_at_10[0x10]; 5208 5209 u8 reserved_at_20[0x10]; 5210 u8 op_mod[0x10]; 5211 5212 u8 reserved_at_40[0x8]; 5213 u8 tisn[0x18]; 5214 5215 u8 reserved_at_60[0x20]; 5216 5217 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 5218 5219 u8 reserved_at_c0[0x40]; 5220 5221 struct mlx5_ifc_tisc_bits ctx; 5222 }; 5223 5224 struct mlx5_ifc_modify_tir_bitmask_bits { 5225 u8 reserved_at_0[0x20]; 5226 5227 u8 reserved_at_20[0x1b]; 5228 u8 self_lb_en[0x1]; 5229 u8 reserved_at_3c[0x1]; 5230 u8 hash[0x1]; 5231 u8 reserved_at_3e[0x1]; 5232 u8 lro[0x1]; 5233 }; 5234 5235 struct mlx5_ifc_modify_tir_out_bits { 5236 u8 status[0x8]; 5237 u8 reserved_at_8[0x18]; 5238 5239 u8 syndrome[0x20]; 5240 5241 u8 reserved_at_40[0x40]; 5242 }; 5243 5244 struct mlx5_ifc_modify_tir_in_bits { 5245 u8 opcode[0x10]; 5246 u8 reserved_at_10[0x10]; 5247 5248 u8 reserved_at_20[0x10]; 5249 u8 op_mod[0x10]; 5250 5251 u8 reserved_at_40[0x8]; 5252 u8 tirn[0x18]; 5253 5254 u8 reserved_at_60[0x20]; 5255 5256 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 5257 5258 u8 reserved_at_c0[0x40]; 5259 5260 struct mlx5_ifc_tirc_bits ctx; 5261 }; 5262 5263 struct mlx5_ifc_modify_sq_out_bits { 5264 u8 status[0x8]; 5265 u8 reserved_at_8[0x18]; 5266 5267 u8 syndrome[0x20]; 5268 5269 u8 reserved_at_40[0x40]; 5270 }; 5271 5272 struct mlx5_ifc_modify_sq_in_bits { 5273 u8 opcode[0x10]; 5274 u8 reserved_at_10[0x10]; 5275 5276 u8 reserved_at_20[0x10]; 5277 u8 op_mod[0x10]; 5278 5279 u8 sq_state[0x4]; 5280 u8 reserved_at_44[0x4]; 5281 u8 sqn[0x18]; 5282 5283 u8 reserved_at_60[0x20]; 5284 5285 u8 modify_bitmask[0x40]; 5286 5287 u8 reserved_at_c0[0x40]; 5288 5289 struct mlx5_ifc_sqc_bits ctx; 5290 }; 5291 5292 struct mlx5_ifc_modify_scheduling_element_out_bits { 5293 u8 status[0x8]; 5294 u8 reserved_at_8[0x18]; 5295 5296 u8 syndrome[0x20]; 5297 5298 u8 reserved_at_40[0x1c0]; 5299 }; 5300 5301 enum { 5302 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 5303 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 5304 }; 5305 5306 struct mlx5_ifc_modify_scheduling_element_in_bits { 5307 u8 opcode[0x10]; 5308 u8 reserved_at_10[0x10]; 5309 5310 u8 reserved_at_20[0x10]; 5311 u8 op_mod[0x10]; 5312 5313 u8 scheduling_hierarchy[0x8]; 5314 u8 reserved_at_48[0x18]; 5315 5316 u8 scheduling_element_id[0x20]; 5317 5318 u8 reserved_at_80[0x20]; 5319 5320 u8 modify_bitmask[0x20]; 5321 5322 u8 reserved_at_c0[0x40]; 5323 5324 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5325 5326 u8 reserved_at_300[0x100]; 5327 }; 5328 5329 struct mlx5_ifc_modify_rqt_out_bits { 5330 u8 status[0x8]; 5331 u8 reserved_at_8[0x18]; 5332 5333 u8 syndrome[0x20]; 5334 5335 u8 reserved_at_40[0x40]; 5336 }; 5337 5338 struct mlx5_ifc_rqt_bitmask_bits { 5339 u8 reserved_at_0[0x20]; 5340 5341 u8 reserved_at_20[0x1f]; 5342 u8 rqn_list[0x1]; 5343 }; 5344 5345 struct mlx5_ifc_modify_rqt_in_bits { 5346 u8 opcode[0x10]; 5347 u8 reserved_at_10[0x10]; 5348 5349 u8 reserved_at_20[0x10]; 5350 u8 op_mod[0x10]; 5351 5352 u8 reserved_at_40[0x8]; 5353 u8 rqtn[0x18]; 5354 5355 u8 reserved_at_60[0x20]; 5356 5357 struct mlx5_ifc_rqt_bitmask_bits bitmask; 5358 5359 u8 reserved_at_c0[0x40]; 5360 5361 struct mlx5_ifc_rqtc_bits ctx; 5362 }; 5363 5364 struct mlx5_ifc_modify_rq_out_bits { 5365 u8 status[0x8]; 5366 u8 reserved_at_8[0x18]; 5367 5368 u8 syndrome[0x20]; 5369 5370 u8 reserved_at_40[0x40]; 5371 }; 5372 5373 enum { 5374 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 5375 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 5376 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 5377 }; 5378 5379 struct mlx5_ifc_modify_rq_in_bits { 5380 u8 opcode[0x10]; 5381 u8 reserved_at_10[0x10]; 5382 5383 u8 reserved_at_20[0x10]; 5384 u8 op_mod[0x10]; 5385 5386 u8 rq_state[0x4]; 5387 u8 reserved_at_44[0x4]; 5388 u8 rqn[0x18]; 5389 5390 u8 reserved_at_60[0x20]; 5391 5392 u8 modify_bitmask[0x40]; 5393 5394 u8 reserved_at_c0[0x40]; 5395 5396 struct mlx5_ifc_rqc_bits ctx; 5397 }; 5398 5399 struct mlx5_ifc_modify_rmp_out_bits { 5400 u8 status[0x8]; 5401 u8 reserved_at_8[0x18]; 5402 5403 u8 syndrome[0x20]; 5404 5405 u8 reserved_at_40[0x40]; 5406 }; 5407 5408 struct mlx5_ifc_rmp_bitmask_bits { 5409 u8 reserved_at_0[0x20]; 5410 5411 u8 reserved_at_20[0x1f]; 5412 u8 lwm[0x1]; 5413 }; 5414 5415 struct mlx5_ifc_modify_rmp_in_bits { 5416 u8 opcode[0x10]; 5417 u8 reserved_at_10[0x10]; 5418 5419 u8 reserved_at_20[0x10]; 5420 u8 op_mod[0x10]; 5421 5422 u8 rmp_state[0x4]; 5423 u8 reserved_at_44[0x4]; 5424 u8 rmpn[0x18]; 5425 5426 u8 reserved_at_60[0x20]; 5427 5428 struct mlx5_ifc_rmp_bitmask_bits bitmask; 5429 5430 u8 reserved_at_c0[0x40]; 5431 5432 struct mlx5_ifc_rmpc_bits ctx; 5433 }; 5434 5435 struct mlx5_ifc_modify_nic_vport_context_out_bits { 5436 u8 status[0x8]; 5437 u8 reserved_at_8[0x18]; 5438 5439 u8 syndrome[0x20]; 5440 5441 u8 reserved_at_40[0x40]; 5442 }; 5443 5444 struct mlx5_ifc_modify_nic_vport_field_select_bits { 5445 u8 reserved_at_0[0x12]; 5446 u8 affiliation[0x1]; 5447 u8 reserved_at_e[0x1]; 5448 u8 disable_uc_local_lb[0x1]; 5449 u8 disable_mc_local_lb[0x1]; 5450 u8 node_guid[0x1]; 5451 u8 port_guid[0x1]; 5452 u8 min_inline[0x1]; 5453 u8 mtu[0x1]; 5454 u8 change_event[0x1]; 5455 u8 promisc[0x1]; 5456 u8 permanent_address[0x1]; 5457 u8 addresses_list[0x1]; 5458 u8 roce_en[0x1]; 5459 u8 reserved_at_1f[0x1]; 5460 }; 5461 5462 struct mlx5_ifc_modify_nic_vport_context_in_bits { 5463 u8 opcode[0x10]; 5464 u8 reserved_at_10[0x10]; 5465 5466 u8 reserved_at_20[0x10]; 5467 u8 op_mod[0x10]; 5468 5469 u8 other_vport[0x1]; 5470 u8 reserved_at_41[0xf]; 5471 u8 vport_number[0x10]; 5472 5473 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 5474 5475 u8 reserved_at_80[0x780]; 5476 5477 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5478 }; 5479 5480 struct mlx5_ifc_modify_hca_vport_context_out_bits { 5481 u8 status[0x8]; 5482 u8 reserved_at_8[0x18]; 5483 5484 u8 syndrome[0x20]; 5485 5486 u8 reserved_at_40[0x40]; 5487 }; 5488 5489 struct mlx5_ifc_modify_hca_vport_context_in_bits { 5490 u8 opcode[0x10]; 5491 u8 reserved_at_10[0x10]; 5492 5493 u8 reserved_at_20[0x10]; 5494 u8 op_mod[0x10]; 5495 5496 u8 other_vport[0x1]; 5497 u8 reserved_at_41[0xb]; 5498 u8 port_num[0x4]; 5499 u8 vport_number[0x10]; 5500 5501 u8 reserved_at_60[0x20]; 5502 5503 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5504 }; 5505 5506 struct mlx5_ifc_modify_cq_out_bits { 5507 u8 status[0x8]; 5508 u8 reserved_at_8[0x18]; 5509 5510 u8 syndrome[0x20]; 5511 5512 u8 reserved_at_40[0x40]; 5513 }; 5514 5515 enum { 5516 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 5517 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 5518 }; 5519 5520 struct mlx5_ifc_modify_cq_in_bits { 5521 u8 opcode[0x10]; 5522 u8 reserved_at_10[0x10]; 5523 5524 u8 reserved_at_20[0x10]; 5525 u8 op_mod[0x10]; 5526 5527 u8 reserved_at_40[0x8]; 5528 u8 cqn[0x18]; 5529 5530 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 5531 5532 struct mlx5_ifc_cqc_bits cq_context; 5533 5534 u8 reserved_at_280[0x600]; 5535 5536 u8 pas[0][0x40]; 5537 }; 5538 5539 struct mlx5_ifc_modify_cong_status_out_bits { 5540 u8 status[0x8]; 5541 u8 reserved_at_8[0x18]; 5542 5543 u8 syndrome[0x20]; 5544 5545 u8 reserved_at_40[0x40]; 5546 }; 5547 5548 struct mlx5_ifc_modify_cong_status_in_bits { 5549 u8 opcode[0x10]; 5550 u8 reserved_at_10[0x10]; 5551 5552 u8 reserved_at_20[0x10]; 5553 u8 op_mod[0x10]; 5554 5555 u8 reserved_at_40[0x18]; 5556 u8 priority[0x4]; 5557 u8 cong_protocol[0x4]; 5558 5559 u8 enable[0x1]; 5560 u8 tag_enable[0x1]; 5561 u8 reserved_at_62[0x1e]; 5562 }; 5563 5564 struct mlx5_ifc_modify_cong_params_out_bits { 5565 u8 status[0x8]; 5566 u8 reserved_at_8[0x18]; 5567 5568 u8 syndrome[0x20]; 5569 5570 u8 reserved_at_40[0x40]; 5571 }; 5572 5573 struct mlx5_ifc_modify_cong_params_in_bits { 5574 u8 opcode[0x10]; 5575 u8 reserved_at_10[0x10]; 5576 5577 u8 reserved_at_20[0x10]; 5578 u8 op_mod[0x10]; 5579 5580 u8 reserved_at_40[0x1c]; 5581 u8 cong_protocol[0x4]; 5582 5583 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 5584 5585 u8 reserved_at_80[0x80]; 5586 5587 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5588 }; 5589 5590 struct mlx5_ifc_manage_pages_out_bits { 5591 u8 status[0x8]; 5592 u8 reserved_at_8[0x18]; 5593 5594 u8 syndrome[0x20]; 5595 5596 u8 output_num_entries[0x20]; 5597 5598 u8 reserved_at_60[0x20]; 5599 5600 u8 pas[0][0x40]; 5601 }; 5602 5603 enum { 5604 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 5605 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 5606 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 5607 }; 5608 5609 struct mlx5_ifc_manage_pages_in_bits { 5610 u8 opcode[0x10]; 5611 u8 reserved_at_10[0x10]; 5612 5613 u8 reserved_at_20[0x10]; 5614 u8 op_mod[0x10]; 5615 5616 u8 reserved_at_40[0x10]; 5617 u8 function_id[0x10]; 5618 5619 u8 input_num_entries[0x20]; 5620 5621 u8 pas[0][0x40]; 5622 }; 5623 5624 struct mlx5_ifc_mad_ifc_out_bits { 5625 u8 status[0x8]; 5626 u8 reserved_at_8[0x18]; 5627 5628 u8 syndrome[0x20]; 5629 5630 u8 reserved_at_40[0x40]; 5631 5632 u8 response_mad_packet[256][0x8]; 5633 }; 5634 5635 struct mlx5_ifc_mad_ifc_in_bits { 5636 u8 opcode[0x10]; 5637 u8 reserved_at_10[0x10]; 5638 5639 u8 reserved_at_20[0x10]; 5640 u8 op_mod[0x10]; 5641 5642 u8 remote_lid[0x10]; 5643 u8 reserved_at_50[0x8]; 5644 u8 port[0x8]; 5645 5646 u8 reserved_at_60[0x20]; 5647 5648 u8 mad[256][0x8]; 5649 }; 5650 5651 struct mlx5_ifc_init_hca_out_bits { 5652 u8 status[0x8]; 5653 u8 reserved_at_8[0x18]; 5654 5655 u8 syndrome[0x20]; 5656 5657 u8 reserved_at_40[0x40]; 5658 }; 5659 5660 struct mlx5_ifc_init_hca_in_bits { 5661 u8 opcode[0x10]; 5662 u8 reserved_at_10[0x10]; 5663 5664 u8 reserved_at_20[0x10]; 5665 u8 op_mod[0x10]; 5666 5667 u8 reserved_at_40[0x40]; 5668 u8 sw_owner_id[4][0x20]; 5669 }; 5670 5671 struct mlx5_ifc_init2rtr_qp_out_bits { 5672 u8 status[0x8]; 5673 u8 reserved_at_8[0x18]; 5674 5675 u8 syndrome[0x20]; 5676 5677 u8 reserved_at_40[0x40]; 5678 }; 5679 5680 struct mlx5_ifc_init2rtr_qp_in_bits { 5681 u8 opcode[0x10]; 5682 u8 reserved_at_10[0x10]; 5683 5684 u8 reserved_at_20[0x10]; 5685 u8 op_mod[0x10]; 5686 5687 u8 reserved_at_40[0x8]; 5688 u8 qpn[0x18]; 5689 5690 u8 reserved_at_60[0x20]; 5691 5692 u8 opt_param_mask[0x20]; 5693 5694 u8 reserved_at_a0[0x20]; 5695 5696 struct mlx5_ifc_qpc_bits qpc; 5697 5698 u8 reserved_at_800[0x80]; 5699 }; 5700 5701 struct mlx5_ifc_init2init_qp_out_bits { 5702 u8 status[0x8]; 5703 u8 reserved_at_8[0x18]; 5704 5705 u8 syndrome[0x20]; 5706 5707 u8 reserved_at_40[0x40]; 5708 }; 5709 5710 struct mlx5_ifc_init2init_qp_in_bits { 5711 u8 opcode[0x10]; 5712 u8 reserved_at_10[0x10]; 5713 5714 u8 reserved_at_20[0x10]; 5715 u8 op_mod[0x10]; 5716 5717 u8 reserved_at_40[0x8]; 5718 u8 qpn[0x18]; 5719 5720 u8 reserved_at_60[0x20]; 5721 5722 u8 opt_param_mask[0x20]; 5723 5724 u8 reserved_at_a0[0x20]; 5725 5726 struct mlx5_ifc_qpc_bits qpc; 5727 5728 u8 reserved_at_800[0x80]; 5729 }; 5730 5731 struct mlx5_ifc_get_dropped_packet_log_out_bits { 5732 u8 status[0x8]; 5733 u8 reserved_at_8[0x18]; 5734 5735 u8 syndrome[0x20]; 5736 5737 u8 reserved_at_40[0x40]; 5738 5739 u8 packet_headers_log[128][0x8]; 5740 5741 u8 packet_syndrome[64][0x8]; 5742 }; 5743 5744 struct mlx5_ifc_get_dropped_packet_log_in_bits { 5745 u8 opcode[0x10]; 5746 u8 reserved_at_10[0x10]; 5747 5748 u8 reserved_at_20[0x10]; 5749 u8 op_mod[0x10]; 5750 5751 u8 reserved_at_40[0x40]; 5752 }; 5753 5754 struct mlx5_ifc_gen_eqe_in_bits { 5755 u8 opcode[0x10]; 5756 u8 reserved_at_10[0x10]; 5757 5758 u8 reserved_at_20[0x10]; 5759 u8 op_mod[0x10]; 5760 5761 u8 reserved_at_40[0x18]; 5762 u8 eq_number[0x8]; 5763 5764 u8 reserved_at_60[0x20]; 5765 5766 u8 eqe[64][0x8]; 5767 }; 5768 5769 struct mlx5_ifc_gen_eq_out_bits { 5770 u8 status[0x8]; 5771 u8 reserved_at_8[0x18]; 5772 5773 u8 syndrome[0x20]; 5774 5775 u8 reserved_at_40[0x40]; 5776 }; 5777 5778 struct mlx5_ifc_enable_hca_out_bits { 5779 u8 status[0x8]; 5780 u8 reserved_at_8[0x18]; 5781 5782 u8 syndrome[0x20]; 5783 5784 u8 reserved_at_40[0x20]; 5785 }; 5786 5787 struct mlx5_ifc_enable_hca_in_bits { 5788 u8 opcode[0x10]; 5789 u8 reserved_at_10[0x10]; 5790 5791 u8 reserved_at_20[0x10]; 5792 u8 op_mod[0x10]; 5793 5794 u8 reserved_at_40[0x10]; 5795 u8 function_id[0x10]; 5796 5797 u8 reserved_at_60[0x20]; 5798 }; 5799 5800 struct mlx5_ifc_drain_dct_out_bits { 5801 u8 status[0x8]; 5802 u8 reserved_at_8[0x18]; 5803 5804 u8 syndrome[0x20]; 5805 5806 u8 reserved_at_40[0x40]; 5807 }; 5808 5809 struct mlx5_ifc_drain_dct_in_bits { 5810 u8 opcode[0x10]; 5811 u8 reserved_at_10[0x10]; 5812 5813 u8 reserved_at_20[0x10]; 5814 u8 op_mod[0x10]; 5815 5816 u8 reserved_at_40[0x8]; 5817 u8 dctn[0x18]; 5818 5819 u8 reserved_at_60[0x20]; 5820 }; 5821 5822 struct mlx5_ifc_disable_hca_out_bits { 5823 u8 status[0x8]; 5824 u8 reserved_at_8[0x18]; 5825 5826 u8 syndrome[0x20]; 5827 5828 u8 reserved_at_40[0x20]; 5829 }; 5830 5831 struct mlx5_ifc_disable_hca_in_bits { 5832 u8 opcode[0x10]; 5833 u8 reserved_at_10[0x10]; 5834 5835 u8 reserved_at_20[0x10]; 5836 u8 op_mod[0x10]; 5837 5838 u8 reserved_at_40[0x10]; 5839 u8 function_id[0x10]; 5840 5841 u8 reserved_at_60[0x20]; 5842 }; 5843 5844 struct mlx5_ifc_detach_from_mcg_out_bits { 5845 u8 status[0x8]; 5846 u8 reserved_at_8[0x18]; 5847 5848 u8 syndrome[0x20]; 5849 5850 u8 reserved_at_40[0x40]; 5851 }; 5852 5853 struct mlx5_ifc_detach_from_mcg_in_bits { 5854 u8 opcode[0x10]; 5855 u8 reserved_at_10[0x10]; 5856 5857 u8 reserved_at_20[0x10]; 5858 u8 op_mod[0x10]; 5859 5860 u8 reserved_at_40[0x8]; 5861 u8 qpn[0x18]; 5862 5863 u8 reserved_at_60[0x20]; 5864 5865 u8 multicast_gid[16][0x8]; 5866 }; 5867 5868 struct mlx5_ifc_destroy_xrq_out_bits { 5869 u8 status[0x8]; 5870 u8 reserved_at_8[0x18]; 5871 5872 u8 syndrome[0x20]; 5873 5874 u8 reserved_at_40[0x40]; 5875 }; 5876 5877 struct mlx5_ifc_destroy_xrq_in_bits { 5878 u8 opcode[0x10]; 5879 u8 reserved_at_10[0x10]; 5880 5881 u8 reserved_at_20[0x10]; 5882 u8 op_mod[0x10]; 5883 5884 u8 reserved_at_40[0x8]; 5885 u8 xrqn[0x18]; 5886 5887 u8 reserved_at_60[0x20]; 5888 }; 5889 5890 struct mlx5_ifc_destroy_xrc_srq_out_bits { 5891 u8 status[0x8]; 5892 u8 reserved_at_8[0x18]; 5893 5894 u8 syndrome[0x20]; 5895 5896 u8 reserved_at_40[0x40]; 5897 }; 5898 5899 struct mlx5_ifc_destroy_xrc_srq_in_bits { 5900 u8 opcode[0x10]; 5901 u8 reserved_at_10[0x10]; 5902 5903 u8 reserved_at_20[0x10]; 5904 u8 op_mod[0x10]; 5905 5906 u8 reserved_at_40[0x8]; 5907 u8 xrc_srqn[0x18]; 5908 5909 u8 reserved_at_60[0x20]; 5910 }; 5911 5912 struct mlx5_ifc_destroy_tis_out_bits { 5913 u8 status[0x8]; 5914 u8 reserved_at_8[0x18]; 5915 5916 u8 syndrome[0x20]; 5917 5918 u8 reserved_at_40[0x40]; 5919 }; 5920 5921 struct mlx5_ifc_destroy_tis_in_bits { 5922 u8 opcode[0x10]; 5923 u8 reserved_at_10[0x10]; 5924 5925 u8 reserved_at_20[0x10]; 5926 u8 op_mod[0x10]; 5927 5928 u8 reserved_at_40[0x8]; 5929 u8 tisn[0x18]; 5930 5931 u8 reserved_at_60[0x20]; 5932 }; 5933 5934 struct mlx5_ifc_destroy_tir_out_bits { 5935 u8 status[0x8]; 5936 u8 reserved_at_8[0x18]; 5937 5938 u8 syndrome[0x20]; 5939 5940 u8 reserved_at_40[0x40]; 5941 }; 5942 5943 struct mlx5_ifc_destroy_tir_in_bits { 5944 u8 opcode[0x10]; 5945 u8 reserved_at_10[0x10]; 5946 5947 u8 reserved_at_20[0x10]; 5948 u8 op_mod[0x10]; 5949 5950 u8 reserved_at_40[0x8]; 5951 u8 tirn[0x18]; 5952 5953 u8 reserved_at_60[0x20]; 5954 }; 5955 5956 struct mlx5_ifc_destroy_srq_out_bits { 5957 u8 status[0x8]; 5958 u8 reserved_at_8[0x18]; 5959 5960 u8 syndrome[0x20]; 5961 5962 u8 reserved_at_40[0x40]; 5963 }; 5964 5965 struct mlx5_ifc_destroy_srq_in_bits { 5966 u8 opcode[0x10]; 5967 u8 reserved_at_10[0x10]; 5968 5969 u8 reserved_at_20[0x10]; 5970 u8 op_mod[0x10]; 5971 5972 u8 reserved_at_40[0x8]; 5973 u8 srqn[0x18]; 5974 5975 u8 reserved_at_60[0x20]; 5976 }; 5977 5978 struct mlx5_ifc_destroy_sq_out_bits { 5979 u8 status[0x8]; 5980 u8 reserved_at_8[0x18]; 5981 5982 u8 syndrome[0x20]; 5983 5984 u8 reserved_at_40[0x40]; 5985 }; 5986 5987 struct mlx5_ifc_destroy_sq_in_bits { 5988 u8 opcode[0x10]; 5989 u8 reserved_at_10[0x10]; 5990 5991 u8 reserved_at_20[0x10]; 5992 u8 op_mod[0x10]; 5993 5994 u8 reserved_at_40[0x8]; 5995 u8 sqn[0x18]; 5996 5997 u8 reserved_at_60[0x20]; 5998 }; 5999 6000 struct mlx5_ifc_destroy_scheduling_element_out_bits { 6001 u8 status[0x8]; 6002 u8 reserved_at_8[0x18]; 6003 6004 u8 syndrome[0x20]; 6005 6006 u8 reserved_at_40[0x1c0]; 6007 }; 6008 6009 struct mlx5_ifc_destroy_scheduling_element_in_bits { 6010 u8 opcode[0x10]; 6011 u8 reserved_at_10[0x10]; 6012 6013 u8 reserved_at_20[0x10]; 6014 u8 op_mod[0x10]; 6015 6016 u8 scheduling_hierarchy[0x8]; 6017 u8 reserved_at_48[0x18]; 6018 6019 u8 scheduling_element_id[0x20]; 6020 6021 u8 reserved_at_80[0x180]; 6022 }; 6023 6024 struct mlx5_ifc_destroy_rqt_out_bits { 6025 u8 status[0x8]; 6026 u8 reserved_at_8[0x18]; 6027 6028 u8 syndrome[0x20]; 6029 6030 u8 reserved_at_40[0x40]; 6031 }; 6032 6033 struct mlx5_ifc_destroy_rqt_in_bits { 6034 u8 opcode[0x10]; 6035 u8 reserved_at_10[0x10]; 6036 6037 u8 reserved_at_20[0x10]; 6038 u8 op_mod[0x10]; 6039 6040 u8 reserved_at_40[0x8]; 6041 u8 rqtn[0x18]; 6042 6043 u8 reserved_at_60[0x20]; 6044 }; 6045 6046 struct mlx5_ifc_destroy_rq_out_bits { 6047 u8 status[0x8]; 6048 u8 reserved_at_8[0x18]; 6049 6050 u8 syndrome[0x20]; 6051 6052 u8 reserved_at_40[0x40]; 6053 }; 6054 6055 struct mlx5_ifc_destroy_rq_in_bits { 6056 u8 opcode[0x10]; 6057 u8 reserved_at_10[0x10]; 6058 6059 u8 reserved_at_20[0x10]; 6060 u8 op_mod[0x10]; 6061 6062 u8 reserved_at_40[0x8]; 6063 u8 rqn[0x18]; 6064 6065 u8 reserved_at_60[0x20]; 6066 }; 6067 6068 struct mlx5_ifc_set_delay_drop_params_in_bits { 6069 u8 opcode[0x10]; 6070 u8 reserved_at_10[0x10]; 6071 6072 u8 reserved_at_20[0x10]; 6073 u8 op_mod[0x10]; 6074 6075 u8 reserved_at_40[0x20]; 6076 6077 u8 reserved_at_60[0x10]; 6078 u8 delay_drop_timeout[0x10]; 6079 }; 6080 6081 struct mlx5_ifc_set_delay_drop_params_out_bits { 6082 u8 status[0x8]; 6083 u8 reserved_at_8[0x18]; 6084 6085 u8 syndrome[0x20]; 6086 6087 u8 reserved_at_40[0x40]; 6088 }; 6089 6090 struct mlx5_ifc_destroy_rmp_out_bits { 6091 u8 status[0x8]; 6092 u8 reserved_at_8[0x18]; 6093 6094 u8 syndrome[0x20]; 6095 6096 u8 reserved_at_40[0x40]; 6097 }; 6098 6099 struct mlx5_ifc_destroy_rmp_in_bits { 6100 u8 opcode[0x10]; 6101 u8 reserved_at_10[0x10]; 6102 6103 u8 reserved_at_20[0x10]; 6104 u8 op_mod[0x10]; 6105 6106 u8 reserved_at_40[0x8]; 6107 u8 rmpn[0x18]; 6108 6109 u8 reserved_at_60[0x20]; 6110 }; 6111 6112 struct mlx5_ifc_destroy_qp_out_bits { 6113 u8 status[0x8]; 6114 u8 reserved_at_8[0x18]; 6115 6116 u8 syndrome[0x20]; 6117 6118 u8 reserved_at_40[0x40]; 6119 }; 6120 6121 struct mlx5_ifc_destroy_qp_in_bits { 6122 u8 opcode[0x10]; 6123 u8 reserved_at_10[0x10]; 6124 6125 u8 reserved_at_20[0x10]; 6126 u8 op_mod[0x10]; 6127 6128 u8 reserved_at_40[0x8]; 6129 u8 qpn[0x18]; 6130 6131 u8 reserved_at_60[0x20]; 6132 }; 6133 6134 struct mlx5_ifc_destroy_psv_out_bits { 6135 u8 status[0x8]; 6136 u8 reserved_at_8[0x18]; 6137 6138 u8 syndrome[0x20]; 6139 6140 u8 reserved_at_40[0x40]; 6141 }; 6142 6143 struct mlx5_ifc_destroy_psv_in_bits { 6144 u8 opcode[0x10]; 6145 u8 reserved_at_10[0x10]; 6146 6147 u8 reserved_at_20[0x10]; 6148 u8 op_mod[0x10]; 6149 6150 u8 reserved_at_40[0x8]; 6151 u8 psvn[0x18]; 6152 6153 u8 reserved_at_60[0x20]; 6154 }; 6155 6156 struct mlx5_ifc_destroy_mkey_out_bits { 6157 u8 status[0x8]; 6158 u8 reserved_at_8[0x18]; 6159 6160 u8 syndrome[0x20]; 6161 6162 u8 reserved_at_40[0x40]; 6163 }; 6164 6165 struct mlx5_ifc_destroy_mkey_in_bits { 6166 u8 opcode[0x10]; 6167 u8 reserved_at_10[0x10]; 6168 6169 u8 reserved_at_20[0x10]; 6170 u8 op_mod[0x10]; 6171 6172 u8 reserved_at_40[0x8]; 6173 u8 mkey_index[0x18]; 6174 6175 u8 reserved_at_60[0x20]; 6176 }; 6177 6178 struct mlx5_ifc_destroy_flow_table_out_bits { 6179 u8 status[0x8]; 6180 u8 reserved_at_8[0x18]; 6181 6182 u8 syndrome[0x20]; 6183 6184 u8 reserved_at_40[0x40]; 6185 }; 6186 6187 struct mlx5_ifc_destroy_flow_table_in_bits { 6188 u8 opcode[0x10]; 6189 u8 reserved_at_10[0x10]; 6190 6191 u8 reserved_at_20[0x10]; 6192 u8 op_mod[0x10]; 6193 6194 u8 other_vport[0x1]; 6195 u8 reserved_at_41[0xf]; 6196 u8 vport_number[0x10]; 6197 6198 u8 reserved_at_60[0x20]; 6199 6200 u8 table_type[0x8]; 6201 u8 reserved_at_88[0x18]; 6202 6203 u8 reserved_at_a0[0x8]; 6204 u8 table_id[0x18]; 6205 6206 u8 reserved_at_c0[0x140]; 6207 }; 6208 6209 struct mlx5_ifc_destroy_flow_group_out_bits { 6210 u8 status[0x8]; 6211 u8 reserved_at_8[0x18]; 6212 6213 u8 syndrome[0x20]; 6214 6215 u8 reserved_at_40[0x40]; 6216 }; 6217 6218 struct mlx5_ifc_destroy_flow_group_in_bits { 6219 u8 opcode[0x10]; 6220 u8 reserved_at_10[0x10]; 6221 6222 u8 reserved_at_20[0x10]; 6223 u8 op_mod[0x10]; 6224 6225 u8 other_vport[0x1]; 6226 u8 reserved_at_41[0xf]; 6227 u8 vport_number[0x10]; 6228 6229 u8 reserved_at_60[0x20]; 6230 6231 u8 table_type[0x8]; 6232 u8 reserved_at_88[0x18]; 6233 6234 u8 reserved_at_a0[0x8]; 6235 u8 table_id[0x18]; 6236 6237 u8 group_id[0x20]; 6238 6239 u8 reserved_at_e0[0x120]; 6240 }; 6241 6242 struct mlx5_ifc_destroy_eq_out_bits { 6243 u8 status[0x8]; 6244 u8 reserved_at_8[0x18]; 6245 6246 u8 syndrome[0x20]; 6247 6248 u8 reserved_at_40[0x40]; 6249 }; 6250 6251 struct mlx5_ifc_destroy_eq_in_bits { 6252 u8 opcode[0x10]; 6253 u8 reserved_at_10[0x10]; 6254 6255 u8 reserved_at_20[0x10]; 6256 u8 op_mod[0x10]; 6257 6258 u8 reserved_at_40[0x18]; 6259 u8 eq_number[0x8]; 6260 6261 u8 reserved_at_60[0x20]; 6262 }; 6263 6264 struct mlx5_ifc_destroy_dct_out_bits { 6265 u8 status[0x8]; 6266 u8 reserved_at_8[0x18]; 6267 6268 u8 syndrome[0x20]; 6269 6270 u8 reserved_at_40[0x40]; 6271 }; 6272 6273 struct mlx5_ifc_destroy_dct_in_bits { 6274 u8 opcode[0x10]; 6275 u8 reserved_at_10[0x10]; 6276 6277 u8 reserved_at_20[0x10]; 6278 u8 op_mod[0x10]; 6279 6280 u8 reserved_at_40[0x8]; 6281 u8 dctn[0x18]; 6282 6283 u8 reserved_at_60[0x20]; 6284 }; 6285 6286 struct mlx5_ifc_destroy_cq_out_bits { 6287 u8 status[0x8]; 6288 u8 reserved_at_8[0x18]; 6289 6290 u8 syndrome[0x20]; 6291 6292 u8 reserved_at_40[0x40]; 6293 }; 6294 6295 struct mlx5_ifc_destroy_cq_in_bits { 6296 u8 opcode[0x10]; 6297 u8 reserved_at_10[0x10]; 6298 6299 u8 reserved_at_20[0x10]; 6300 u8 op_mod[0x10]; 6301 6302 u8 reserved_at_40[0x8]; 6303 u8 cqn[0x18]; 6304 6305 u8 reserved_at_60[0x20]; 6306 }; 6307 6308 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 6309 u8 status[0x8]; 6310 u8 reserved_at_8[0x18]; 6311 6312 u8 syndrome[0x20]; 6313 6314 u8 reserved_at_40[0x40]; 6315 }; 6316 6317 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 6318 u8 opcode[0x10]; 6319 u8 reserved_at_10[0x10]; 6320 6321 u8 reserved_at_20[0x10]; 6322 u8 op_mod[0x10]; 6323 6324 u8 reserved_at_40[0x20]; 6325 6326 u8 reserved_at_60[0x10]; 6327 u8 vxlan_udp_port[0x10]; 6328 }; 6329 6330 struct mlx5_ifc_delete_l2_table_entry_out_bits { 6331 u8 status[0x8]; 6332 u8 reserved_at_8[0x18]; 6333 6334 u8 syndrome[0x20]; 6335 6336 u8 reserved_at_40[0x40]; 6337 }; 6338 6339 struct mlx5_ifc_delete_l2_table_entry_in_bits { 6340 u8 opcode[0x10]; 6341 u8 reserved_at_10[0x10]; 6342 6343 u8 reserved_at_20[0x10]; 6344 u8 op_mod[0x10]; 6345 6346 u8 reserved_at_40[0x60]; 6347 6348 u8 reserved_at_a0[0x8]; 6349 u8 table_index[0x18]; 6350 6351 u8 reserved_at_c0[0x140]; 6352 }; 6353 6354 struct mlx5_ifc_delete_fte_out_bits { 6355 u8 status[0x8]; 6356 u8 reserved_at_8[0x18]; 6357 6358 u8 syndrome[0x20]; 6359 6360 u8 reserved_at_40[0x40]; 6361 }; 6362 6363 struct mlx5_ifc_delete_fte_in_bits { 6364 u8 opcode[0x10]; 6365 u8 reserved_at_10[0x10]; 6366 6367 u8 reserved_at_20[0x10]; 6368 u8 op_mod[0x10]; 6369 6370 u8 other_vport[0x1]; 6371 u8 reserved_at_41[0xf]; 6372 u8 vport_number[0x10]; 6373 6374 u8 reserved_at_60[0x20]; 6375 6376 u8 table_type[0x8]; 6377 u8 reserved_at_88[0x18]; 6378 6379 u8 reserved_at_a0[0x8]; 6380 u8 table_id[0x18]; 6381 6382 u8 reserved_at_c0[0x40]; 6383 6384 u8 flow_index[0x20]; 6385 6386 u8 reserved_at_120[0xe0]; 6387 }; 6388 6389 struct mlx5_ifc_dealloc_xrcd_out_bits { 6390 u8 status[0x8]; 6391 u8 reserved_at_8[0x18]; 6392 6393 u8 syndrome[0x20]; 6394 6395 u8 reserved_at_40[0x40]; 6396 }; 6397 6398 struct mlx5_ifc_dealloc_xrcd_in_bits { 6399 u8 opcode[0x10]; 6400 u8 reserved_at_10[0x10]; 6401 6402 u8 reserved_at_20[0x10]; 6403 u8 op_mod[0x10]; 6404 6405 u8 reserved_at_40[0x8]; 6406 u8 xrcd[0x18]; 6407 6408 u8 reserved_at_60[0x20]; 6409 }; 6410 6411 struct mlx5_ifc_dealloc_uar_out_bits { 6412 u8 status[0x8]; 6413 u8 reserved_at_8[0x18]; 6414 6415 u8 syndrome[0x20]; 6416 6417 u8 reserved_at_40[0x40]; 6418 }; 6419 6420 struct mlx5_ifc_dealloc_uar_in_bits { 6421 u8 opcode[0x10]; 6422 u8 reserved_at_10[0x10]; 6423 6424 u8 reserved_at_20[0x10]; 6425 u8 op_mod[0x10]; 6426 6427 u8 reserved_at_40[0x8]; 6428 u8 uar[0x18]; 6429 6430 u8 reserved_at_60[0x20]; 6431 }; 6432 6433 struct mlx5_ifc_dealloc_transport_domain_out_bits { 6434 u8 status[0x8]; 6435 u8 reserved_at_8[0x18]; 6436 6437 u8 syndrome[0x20]; 6438 6439 u8 reserved_at_40[0x40]; 6440 }; 6441 6442 struct mlx5_ifc_dealloc_transport_domain_in_bits { 6443 u8 opcode[0x10]; 6444 u8 reserved_at_10[0x10]; 6445 6446 u8 reserved_at_20[0x10]; 6447 u8 op_mod[0x10]; 6448 6449 u8 reserved_at_40[0x8]; 6450 u8 transport_domain[0x18]; 6451 6452 u8 reserved_at_60[0x20]; 6453 }; 6454 6455 struct mlx5_ifc_dealloc_q_counter_out_bits { 6456 u8 status[0x8]; 6457 u8 reserved_at_8[0x18]; 6458 6459 u8 syndrome[0x20]; 6460 6461 u8 reserved_at_40[0x40]; 6462 }; 6463 6464 struct mlx5_ifc_dealloc_q_counter_in_bits { 6465 u8 opcode[0x10]; 6466 u8 reserved_at_10[0x10]; 6467 6468 u8 reserved_at_20[0x10]; 6469 u8 op_mod[0x10]; 6470 6471 u8 reserved_at_40[0x18]; 6472 u8 counter_set_id[0x8]; 6473 6474 u8 reserved_at_60[0x20]; 6475 }; 6476 6477 struct mlx5_ifc_dealloc_pd_out_bits { 6478 u8 status[0x8]; 6479 u8 reserved_at_8[0x18]; 6480 6481 u8 syndrome[0x20]; 6482 6483 u8 reserved_at_40[0x40]; 6484 }; 6485 6486 struct mlx5_ifc_dealloc_pd_in_bits { 6487 u8 opcode[0x10]; 6488 u8 reserved_at_10[0x10]; 6489 6490 u8 reserved_at_20[0x10]; 6491 u8 op_mod[0x10]; 6492 6493 u8 reserved_at_40[0x8]; 6494 u8 pd[0x18]; 6495 6496 u8 reserved_at_60[0x20]; 6497 }; 6498 6499 struct mlx5_ifc_dealloc_flow_counter_out_bits { 6500 u8 status[0x8]; 6501 u8 reserved_at_8[0x18]; 6502 6503 u8 syndrome[0x20]; 6504 6505 u8 reserved_at_40[0x40]; 6506 }; 6507 6508 struct mlx5_ifc_dealloc_flow_counter_in_bits { 6509 u8 opcode[0x10]; 6510 u8 reserved_at_10[0x10]; 6511 6512 u8 reserved_at_20[0x10]; 6513 u8 op_mod[0x10]; 6514 6515 u8 flow_counter_id[0x20]; 6516 6517 u8 reserved_at_60[0x20]; 6518 }; 6519 6520 struct mlx5_ifc_create_xrq_out_bits { 6521 u8 status[0x8]; 6522 u8 reserved_at_8[0x18]; 6523 6524 u8 syndrome[0x20]; 6525 6526 u8 reserved_at_40[0x8]; 6527 u8 xrqn[0x18]; 6528 6529 u8 reserved_at_60[0x20]; 6530 }; 6531 6532 struct mlx5_ifc_create_xrq_in_bits { 6533 u8 opcode[0x10]; 6534 u8 reserved_at_10[0x10]; 6535 6536 u8 reserved_at_20[0x10]; 6537 u8 op_mod[0x10]; 6538 6539 u8 reserved_at_40[0x40]; 6540 6541 struct mlx5_ifc_xrqc_bits xrq_context; 6542 }; 6543 6544 struct mlx5_ifc_create_xrc_srq_out_bits { 6545 u8 status[0x8]; 6546 u8 reserved_at_8[0x18]; 6547 6548 u8 syndrome[0x20]; 6549 6550 u8 reserved_at_40[0x8]; 6551 u8 xrc_srqn[0x18]; 6552 6553 u8 reserved_at_60[0x20]; 6554 }; 6555 6556 struct mlx5_ifc_create_xrc_srq_in_bits { 6557 u8 opcode[0x10]; 6558 u8 reserved_at_10[0x10]; 6559 6560 u8 reserved_at_20[0x10]; 6561 u8 op_mod[0x10]; 6562 6563 u8 reserved_at_40[0x40]; 6564 6565 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 6566 6567 u8 reserved_at_280[0x600]; 6568 6569 u8 pas[0][0x40]; 6570 }; 6571 6572 struct mlx5_ifc_create_tis_out_bits { 6573 u8 status[0x8]; 6574 u8 reserved_at_8[0x18]; 6575 6576 u8 syndrome[0x20]; 6577 6578 u8 reserved_at_40[0x8]; 6579 u8 tisn[0x18]; 6580 6581 u8 reserved_at_60[0x20]; 6582 }; 6583 6584 struct mlx5_ifc_create_tis_in_bits { 6585 u8 opcode[0x10]; 6586 u8 reserved_at_10[0x10]; 6587 6588 u8 reserved_at_20[0x10]; 6589 u8 op_mod[0x10]; 6590 6591 u8 reserved_at_40[0xc0]; 6592 6593 struct mlx5_ifc_tisc_bits ctx; 6594 }; 6595 6596 struct mlx5_ifc_create_tir_out_bits { 6597 u8 status[0x8]; 6598 u8 reserved_at_8[0x18]; 6599 6600 u8 syndrome[0x20]; 6601 6602 u8 reserved_at_40[0x8]; 6603 u8 tirn[0x18]; 6604 6605 u8 reserved_at_60[0x20]; 6606 }; 6607 6608 struct mlx5_ifc_create_tir_in_bits { 6609 u8 opcode[0x10]; 6610 u8 reserved_at_10[0x10]; 6611 6612 u8 reserved_at_20[0x10]; 6613 u8 op_mod[0x10]; 6614 6615 u8 reserved_at_40[0xc0]; 6616 6617 struct mlx5_ifc_tirc_bits ctx; 6618 }; 6619 6620 struct mlx5_ifc_create_srq_out_bits { 6621 u8 status[0x8]; 6622 u8 reserved_at_8[0x18]; 6623 6624 u8 syndrome[0x20]; 6625 6626 u8 reserved_at_40[0x8]; 6627 u8 srqn[0x18]; 6628 6629 u8 reserved_at_60[0x20]; 6630 }; 6631 6632 struct mlx5_ifc_create_srq_in_bits { 6633 u8 opcode[0x10]; 6634 u8 reserved_at_10[0x10]; 6635 6636 u8 reserved_at_20[0x10]; 6637 u8 op_mod[0x10]; 6638 6639 u8 reserved_at_40[0x40]; 6640 6641 struct mlx5_ifc_srqc_bits srq_context_entry; 6642 6643 u8 reserved_at_280[0x600]; 6644 6645 u8 pas[0][0x40]; 6646 }; 6647 6648 struct mlx5_ifc_create_sq_out_bits { 6649 u8 status[0x8]; 6650 u8 reserved_at_8[0x18]; 6651 6652 u8 syndrome[0x20]; 6653 6654 u8 reserved_at_40[0x8]; 6655 u8 sqn[0x18]; 6656 6657 u8 reserved_at_60[0x20]; 6658 }; 6659 6660 struct mlx5_ifc_create_sq_in_bits { 6661 u8 opcode[0x10]; 6662 u8 reserved_at_10[0x10]; 6663 6664 u8 reserved_at_20[0x10]; 6665 u8 op_mod[0x10]; 6666 6667 u8 reserved_at_40[0xc0]; 6668 6669 struct mlx5_ifc_sqc_bits ctx; 6670 }; 6671 6672 struct mlx5_ifc_create_scheduling_element_out_bits { 6673 u8 status[0x8]; 6674 u8 reserved_at_8[0x18]; 6675 6676 u8 syndrome[0x20]; 6677 6678 u8 reserved_at_40[0x40]; 6679 6680 u8 scheduling_element_id[0x20]; 6681 6682 u8 reserved_at_a0[0x160]; 6683 }; 6684 6685 struct mlx5_ifc_create_scheduling_element_in_bits { 6686 u8 opcode[0x10]; 6687 u8 reserved_at_10[0x10]; 6688 6689 u8 reserved_at_20[0x10]; 6690 u8 op_mod[0x10]; 6691 6692 u8 scheduling_hierarchy[0x8]; 6693 u8 reserved_at_48[0x18]; 6694 6695 u8 reserved_at_60[0xa0]; 6696 6697 struct mlx5_ifc_scheduling_context_bits scheduling_context; 6698 6699 u8 reserved_at_300[0x100]; 6700 }; 6701 6702 struct mlx5_ifc_create_rqt_out_bits { 6703 u8 status[0x8]; 6704 u8 reserved_at_8[0x18]; 6705 6706 u8 syndrome[0x20]; 6707 6708 u8 reserved_at_40[0x8]; 6709 u8 rqtn[0x18]; 6710 6711 u8 reserved_at_60[0x20]; 6712 }; 6713 6714 struct mlx5_ifc_create_rqt_in_bits { 6715 u8 opcode[0x10]; 6716 u8 reserved_at_10[0x10]; 6717 6718 u8 reserved_at_20[0x10]; 6719 u8 op_mod[0x10]; 6720 6721 u8 reserved_at_40[0xc0]; 6722 6723 struct mlx5_ifc_rqtc_bits rqt_context; 6724 }; 6725 6726 struct mlx5_ifc_create_rq_out_bits { 6727 u8 status[0x8]; 6728 u8 reserved_at_8[0x18]; 6729 6730 u8 syndrome[0x20]; 6731 6732 u8 reserved_at_40[0x8]; 6733 u8 rqn[0x18]; 6734 6735 u8 reserved_at_60[0x20]; 6736 }; 6737 6738 struct mlx5_ifc_create_rq_in_bits { 6739 u8 opcode[0x10]; 6740 u8 reserved_at_10[0x10]; 6741 6742 u8 reserved_at_20[0x10]; 6743 u8 op_mod[0x10]; 6744 6745 u8 reserved_at_40[0xc0]; 6746 6747 struct mlx5_ifc_rqc_bits ctx; 6748 }; 6749 6750 struct mlx5_ifc_create_rmp_out_bits { 6751 u8 status[0x8]; 6752 u8 reserved_at_8[0x18]; 6753 6754 u8 syndrome[0x20]; 6755 6756 u8 reserved_at_40[0x8]; 6757 u8 rmpn[0x18]; 6758 6759 u8 reserved_at_60[0x20]; 6760 }; 6761 6762 struct mlx5_ifc_create_rmp_in_bits { 6763 u8 opcode[0x10]; 6764 u8 reserved_at_10[0x10]; 6765 6766 u8 reserved_at_20[0x10]; 6767 u8 op_mod[0x10]; 6768 6769 u8 reserved_at_40[0xc0]; 6770 6771 struct mlx5_ifc_rmpc_bits ctx; 6772 }; 6773 6774 struct mlx5_ifc_create_qp_out_bits { 6775 u8 status[0x8]; 6776 u8 reserved_at_8[0x18]; 6777 6778 u8 syndrome[0x20]; 6779 6780 u8 reserved_at_40[0x8]; 6781 u8 qpn[0x18]; 6782 6783 u8 reserved_at_60[0x20]; 6784 }; 6785 6786 struct mlx5_ifc_create_qp_in_bits { 6787 u8 opcode[0x10]; 6788 u8 reserved_at_10[0x10]; 6789 6790 u8 reserved_at_20[0x10]; 6791 u8 op_mod[0x10]; 6792 6793 u8 reserved_at_40[0x40]; 6794 6795 u8 opt_param_mask[0x20]; 6796 6797 u8 reserved_at_a0[0x20]; 6798 6799 struct mlx5_ifc_qpc_bits qpc; 6800 6801 u8 reserved_at_800[0x80]; 6802 6803 u8 pas[0][0x40]; 6804 }; 6805 6806 struct mlx5_ifc_create_psv_out_bits { 6807 u8 status[0x8]; 6808 u8 reserved_at_8[0x18]; 6809 6810 u8 syndrome[0x20]; 6811 6812 u8 reserved_at_40[0x40]; 6813 6814 u8 reserved_at_80[0x8]; 6815 u8 psv0_index[0x18]; 6816 6817 u8 reserved_at_a0[0x8]; 6818 u8 psv1_index[0x18]; 6819 6820 u8 reserved_at_c0[0x8]; 6821 u8 psv2_index[0x18]; 6822 6823 u8 reserved_at_e0[0x8]; 6824 u8 psv3_index[0x18]; 6825 }; 6826 6827 struct mlx5_ifc_create_psv_in_bits { 6828 u8 opcode[0x10]; 6829 u8 reserved_at_10[0x10]; 6830 6831 u8 reserved_at_20[0x10]; 6832 u8 op_mod[0x10]; 6833 6834 u8 num_psv[0x4]; 6835 u8 reserved_at_44[0x4]; 6836 u8 pd[0x18]; 6837 6838 u8 reserved_at_60[0x20]; 6839 }; 6840 6841 struct mlx5_ifc_create_mkey_out_bits { 6842 u8 status[0x8]; 6843 u8 reserved_at_8[0x18]; 6844 6845 u8 syndrome[0x20]; 6846 6847 u8 reserved_at_40[0x8]; 6848 u8 mkey_index[0x18]; 6849 6850 u8 reserved_at_60[0x20]; 6851 }; 6852 6853 struct mlx5_ifc_create_mkey_in_bits { 6854 u8 opcode[0x10]; 6855 u8 reserved_at_10[0x10]; 6856 6857 u8 reserved_at_20[0x10]; 6858 u8 op_mod[0x10]; 6859 6860 u8 reserved_at_40[0x20]; 6861 6862 u8 pg_access[0x1]; 6863 u8 reserved_at_61[0x1f]; 6864 6865 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 6866 6867 u8 reserved_at_280[0x80]; 6868 6869 u8 translations_octword_actual_size[0x20]; 6870 6871 u8 reserved_at_320[0x560]; 6872 6873 u8 klm_pas_mtt[0][0x20]; 6874 }; 6875 6876 struct mlx5_ifc_create_flow_table_out_bits { 6877 u8 status[0x8]; 6878 u8 reserved_at_8[0x18]; 6879 6880 u8 syndrome[0x20]; 6881 6882 u8 reserved_at_40[0x8]; 6883 u8 table_id[0x18]; 6884 6885 u8 reserved_at_60[0x20]; 6886 }; 6887 6888 struct mlx5_ifc_flow_table_context_bits { 6889 u8 encap_en[0x1]; 6890 u8 decap_en[0x1]; 6891 u8 reserved_at_2[0x2]; 6892 u8 table_miss_action[0x4]; 6893 u8 level[0x8]; 6894 u8 reserved_at_10[0x8]; 6895 u8 log_size[0x8]; 6896 6897 u8 reserved_at_20[0x8]; 6898 u8 table_miss_id[0x18]; 6899 6900 u8 reserved_at_40[0x8]; 6901 u8 lag_master_next_table_id[0x18]; 6902 6903 u8 reserved_at_60[0xe0]; 6904 }; 6905 6906 struct mlx5_ifc_create_flow_table_in_bits { 6907 u8 opcode[0x10]; 6908 u8 reserved_at_10[0x10]; 6909 6910 u8 reserved_at_20[0x10]; 6911 u8 op_mod[0x10]; 6912 6913 u8 other_vport[0x1]; 6914 u8 reserved_at_41[0xf]; 6915 u8 vport_number[0x10]; 6916 6917 u8 reserved_at_60[0x20]; 6918 6919 u8 table_type[0x8]; 6920 u8 reserved_at_88[0x18]; 6921 6922 u8 reserved_at_a0[0x20]; 6923 6924 struct mlx5_ifc_flow_table_context_bits flow_table_context; 6925 }; 6926 6927 struct mlx5_ifc_create_flow_group_out_bits { 6928 u8 status[0x8]; 6929 u8 reserved_at_8[0x18]; 6930 6931 u8 syndrome[0x20]; 6932 6933 u8 reserved_at_40[0x8]; 6934 u8 group_id[0x18]; 6935 6936 u8 reserved_at_60[0x20]; 6937 }; 6938 6939 enum { 6940 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 6941 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 6942 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 6943 }; 6944 6945 struct mlx5_ifc_create_flow_group_in_bits { 6946 u8 opcode[0x10]; 6947 u8 reserved_at_10[0x10]; 6948 6949 u8 reserved_at_20[0x10]; 6950 u8 op_mod[0x10]; 6951 6952 u8 other_vport[0x1]; 6953 u8 reserved_at_41[0xf]; 6954 u8 vport_number[0x10]; 6955 6956 u8 reserved_at_60[0x20]; 6957 6958 u8 table_type[0x8]; 6959 u8 reserved_at_88[0x18]; 6960 6961 u8 reserved_at_a0[0x8]; 6962 u8 table_id[0x18]; 6963 6964 u8 reserved_at_c0[0x20]; 6965 6966 u8 start_flow_index[0x20]; 6967 6968 u8 reserved_at_100[0x20]; 6969 6970 u8 end_flow_index[0x20]; 6971 6972 u8 reserved_at_140[0xa0]; 6973 6974 u8 reserved_at_1e0[0x18]; 6975 u8 match_criteria_enable[0x8]; 6976 6977 struct mlx5_ifc_fte_match_param_bits match_criteria; 6978 6979 u8 reserved_at_1200[0xe00]; 6980 }; 6981 6982 struct mlx5_ifc_create_eq_out_bits { 6983 u8 status[0x8]; 6984 u8 reserved_at_8[0x18]; 6985 6986 u8 syndrome[0x20]; 6987 6988 u8 reserved_at_40[0x18]; 6989 u8 eq_number[0x8]; 6990 6991 u8 reserved_at_60[0x20]; 6992 }; 6993 6994 struct mlx5_ifc_create_eq_in_bits { 6995 u8 opcode[0x10]; 6996 u8 reserved_at_10[0x10]; 6997 6998 u8 reserved_at_20[0x10]; 6999 u8 op_mod[0x10]; 7000 7001 u8 reserved_at_40[0x40]; 7002 7003 struct mlx5_ifc_eqc_bits eq_context_entry; 7004 7005 u8 reserved_at_280[0x40]; 7006 7007 u8 event_bitmask[0x40]; 7008 7009 u8 reserved_at_300[0x580]; 7010 7011 u8 pas[0][0x40]; 7012 }; 7013 7014 struct mlx5_ifc_create_dct_out_bits { 7015 u8 status[0x8]; 7016 u8 reserved_at_8[0x18]; 7017 7018 u8 syndrome[0x20]; 7019 7020 u8 reserved_at_40[0x8]; 7021 u8 dctn[0x18]; 7022 7023 u8 reserved_at_60[0x20]; 7024 }; 7025 7026 struct mlx5_ifc_create_dct_in_bits { 7027 u8 opcode[0x10]; 7028 u8 reserved_at_10[0x10]; 7029 7030 u8 reserved_at_20[0x10]; 7031 u8 op_mod[0x10]; 7032 7033 u8 reserved_at_40[0x40]; 7034 7035 struct mlx5_ifc_dctc_bits dct_context_entry; 7036 7037 u8 reserved_at_280[0x180]; 7038 }; 7039 7040 struct mlx5_ifc_create_cq_out_bits { 7041 u8 status[0x8]; 7042 u8 reserved_at_8[0x18]; 7043 7044 u8 syndrome[0x20]; 7045 7046 u8 reserved_at_40[0x8]; 7047 u8 cqn[0x18]; 7048 7049 u8 reserved_at_60[0x20]; 7050 }; 7051 7052 struct mlx5_ifc_create_cq_in_bits { 7053 u8 opcode[0x10]; 7054 u8 reserved_at_10[0x10]; 7055 7056 u8 reserved_at_20[0x10]; 7057 u8 op_mod[0x10]; 7058 7059 u8 reserved_at_40[0x40]; 7060 7061 struct mlx5_ifc_cqc_bits cq_context; 7062 7063 u8 reserved_at_280[0x600]; 7064 7065 u8 pas[0][0x40]; 7066 }; 7067 7068 struct mlx5_ifc_config_int_moderation_out_bits { 7069 u8 status[0x8]; 7070 u8 reserved_at_8[0x18]; 7071 7072 u8 syndrome[0x20]; 7073 7074 u8 reserved_at_40[0x4]; 7075 u8 min_delay[0xc]; 7076 u8 int_vector[0x10]; 7077 7078 u8 reserved_at_60[0x20]; 7079 }; 7080 7081 enum { 7082 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 7083 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 7084 }; 7085 7086 struct mlx5_ifc_config_int_moderation_in_bits { 7087 u8 opcode[0x10]; 7088 u8 reserved_at_10[0x10]; 7089 7090 u8 reserved_at_20[0x10]; 7091 u8 op_mod[0x10]; 7092 7093 u8 reserved_at_40[0x4]; 7094 u8 min_delay[0xc]; 7095 u8 int_vector[0x10]; 7096 7097 u8 reserved_at_60[0x20]; 7098 }; 7099 7100 struct mlx5_ifc_attach_to_mcg_out_bits { 7101 u8 status[0x8]; 7102 u8 reserved_at_8[0x18]; 7103 7104 u8 syndrome[0x20]; 7105 7106 u8 reserved_at_40[0x40]; 7107 }; 7108 7109 struct mlx5_ifc_attach_to_mcg_in_bits { 7110 u8 opcode[0x10]; 7111 u8 reserved_at_10[0x10]; 7112 7113 u8 reserved_at_20[0x10]; 7114 u8 op_mod[0x10]; 7115 7116 u8 reserved_at_40[0x8]; 7117 u8 qpn[0x18]; 7118 7119 u8 reserved_at_60[0x20]; 7120 7121 u8 multicast_gid[16][0x8]; 7122 }; 7123 7124 struct mlx5_ifc_arm_xrq_out_bits { 7125 u8 status[0x8]; 7126 u8 reserved_at_8[0x18]; 7127 7128 u8 syndrome[0x20]; 7129 7130 u8 reserved_at_40[0x40]; 7131 }; 7132 7133 struct mlx5_ifc_arm_xrq_in_bits { 7134 u8 opcode[0x10]; 7135 u8 reserved_at_10[0x10]; 7136 7137 u8 reserved_at_20[0x10]; 7138 u8 op_mod[0x10]; 7139 7140 u8 reserved_at_40[0x8]; 7141 u8 xrqn[0x18]; 7142 7143 u8 reserved_at_60[0x10]; 7144 u8 lwm[0x10]; 7145 }; 7146 7147 struct mlx5_ifc_arm_xrc_srq_out_bits { 7148 u8 status[0x8]; 7149 u8 reserved_at_8[0x18]; 7150 7151 u8 syndrome[0x20]; 7152 7153 u8 reserved_at_40[0x40]; 7154 }; 7155 7156 enum { 7157 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 7158 }; 7159 7160 struct mlx5_ifc_arm_xrc_srq_in_bits { 7161 u8 opcode[0x10]; 7162 u8 reserved_at_10[0x10]; 7163 7164 u8 reserved_at_20[0x10]; 7165 u8 op_mod[0x10]; 7166 7167 u8 reserved_at_40[0x8]; 7168 u8 xrc_srqn[0x18]; 7169 7170 u8 reserved_at_60[0x10]; 7171 u8 lwm[0x10]; 7172 }; 7173 7174 struct mlx5_ifc_arm_rq_out_bits { 7175 u8 status[0x8]; 7176 u8 reserved_at_8[0x18]; 7177 7178 u8 syndrome[0x20]; 7179 7180 u8 reserved_at_40[0x40]; 7181 }; 7182 7183 enum { 7184 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 7185 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 7186 }; 7187 7188 struct mlx5_ifc_arm_rq_in_bits { 7189 u8 opcode[0x10]; 7190 u8 reserved_at_10[0x10]; 7191 7192 u8 reserved_at_20[0x10]; 7193 u8 op_mod[0x10]; 7194 7195 u8 reserved_at_40[0x8]; 7196 u8 srq_number[0x18]; 7197 7198 u8 reserved_at_60[0x10]; 7199 u8 lwm[0x10]; 7200 }; 7201 7202 struct mlx5_ifc_arm_dct_out_bits { 7203 u8 status[0x8]; 7204 u8 reserved_at_8[0x18]; 7205 7206 u8 syndrome[0x20]; 7207 7208 u8 reserved_at_40[0x40]; 7209 }; 7210 7211 struct mlx5_ifc_arm_dct_in_bits { 7212 u8 opcode[0x10]; 7213 u8 reserved_at_10[0x10]; 7214 7215 u8 reserved_at_20[0x10]; 7216 u8 op_mod[0x10]; 7217 7218 u8 reserved_at_40[0x8]; 7219 u8 dct_number[0x18]; 7220 7221 u8 reserved_at_60[0x20]; 7222 }; 7223 7224 struct mlx5_ifc_alloc_xrcd_out_bits { 7225 u8 status[0x8]; 7226 u8 reserved_at_8[0x18]; 7227 7228 u8 syndrome[0x20]; 7229 7230 u8 reserved_at_40[0x8]; 7231 u8 xrcd[0x18]; 7232 7233 u8 reserved_at_60[0x20]; 7234 }; 7235 7236 struct mlx5_ifc_alloc_xrcd_in_bits { 7237 u8 opcode[0x10]; 7238 u8 reserved_at_10[0x10]; 7239 7240 u8 reserved_at_20[0x10]; 7241 u8 op_mod[0x10]; 7242 7243 u8 reserved_at_40[0x40]; 7244 }; 7245 7246 struct mlx5_ifc_alloc_uar_out_bits { 7247 u8 status[0x8]; 7248 u8 reserved_at_8[0x18]; 7249 7250 u8 syndrome[0x20]; 7251 7252 u8 reserved_at_40[0x8]; 7253 u8 uar[0x18]; 7254 7255 u8 reserved_at_60[0x20]; 7256 }; 7257 7258 struct mlx5_ifc_alloc_uar_in_bits { 7259 u8 opcode[0x10]; 7260 u8 reserved_at_10[0x10]; 7261 7262 u8 reserved_at_20[0x10]; 7263 u8 op_mod[0x10]; 7264 7265 u8 reserved_at_40[0x40]; 7266 }; 7267 7268 struct mlx5_ifc_alloc_transport_domain_out_bits { 7269 u8 status[0x8]; 7270 u8 reserved_at_8[0x18]; 7271 7272 u8 syndrome[0x20]; 7273 7274 u8 reserved_at_40[0x8]; 7275 u8 transport_domain[0x18]; 7276 7277 u8 reserved_at_60[0x20]; 7278 }; 7279 7280 struct mlx5_ifc_alloc_transport_domain_in_bits { 7281 u8 opcode[0x10]; 7282 u8 reserved_at_10[0x10]; 7283 7284 u8 reserved_at_20[0x10]; 7285 u8 op_mod[0x10]; 7286 7287 u8 reserved_at_40[0x40]; 7288 }; 7289 7290 struct mlx5_ifc_alloc_q_counter_out_bits { 7291 u8 status[0x8]; 7292 u8 reserved_at_8[0x18]; 7293 7294 u8 syndrome[0x20]; 7295 7296 u8 reserved_at_40[0x18]; 7297 u8 counter_set_id[0x8]; 7298 7299 u8 reserved_at_60[0x20]; 7300 }; 7301 7302 struct mlx5_ifc_alloc_q_counter_in_bits { 7303 u8 opcode[0x10]; 7304 u8 reserved_at_10[0x10]; 7305 7306 u8 reserved_at_20[0x10]; 7307 u8 op_mod[0x10]; 7308 7309 u8 reserved_at_40[0x40]; 7310 }; 7311 7312 struct mlx5_ifc_alloc_pd_out_bits { 7313 u8 status[0x8]; 7314 u8 reserved_at_8[0x18]; 7315 7316 u8 syndrome[0x20]; 7317 7318 u8 reserved_at_40[0x8]; 7319 u8 pd[0x18]; 7320 7321 u8 reserved_at_60[0x20]; 7322 }; 7323 7324 struct mlx5_ifc_alloc_pd_in_bits { 7325 u8 opcode[0x10]; 7326 u8 reserved_at_10[0x10]; 7327 7328 u8 reserved_at_20[0x10]; 7329 u8 op_mod[0x10]; 7330 7331 u8 reserved_at_40[0x40]; 7332 }; 7333 7334 struct mlx5_ifc_alloc_flow_counter_out_bits { 7335 u8 status[0x8]; 7336 u8 reserved_at_8[0x18]; 7337 7338 u8 syndrome[0x20]; 7339 7340 u8 flow_counter_id[0x20]; 7341 7342 u8 reserved_at_60[0x20]; 7343 }; 7344 7345 struct mlx5_ifc_alloc_flow_counter_in_bits { 7346 u8 opcode[0x10]; 7347 u8 reserved_at_10[0x10]; 7348 7349 u8 reserved_at_20[0x10]; 7350 u8 op_mod[0x10]; 7351 7352 u8 reserved_at_40[0x40]; 7353 }; 7354 7355 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 7356 u8 status[0x8]; 7357 u8 reserved_at_8[0x18]; 7358 7359 u8 syndrome[0x20]; 7360 7361 u8 reserved_at_40[0x40]; 7362 }; 7363 7364 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 7365 u8 opcode[0x10]; 7366 u8 reserved_at_10[0x10]; 7367 7368 u8 reserved_at_20[0x10]; 7369 u8 op_mod[0x10]; 7370 7371 u8 reserved_at_40[0x20]; 7372 7373 u8 reserved_at_60[0x10]; 7374 u8 vxlan_udp_port[0x10]; 7375 }; 7376 7377 struct mlx5_ifc_set_pp_rate_limit_out_bits { 7378 u8 status[0x8]; 7379 u8 reserved_at_8[0x18]; 7380 7381 u8 syndrome[0x20]; 7382 7383 u8 reserved_at_40[0x40]; 7384 }; 7385 7386 struct mlx5_ifc_set_pp_rate_limit_in_bits { 7387 u8 opcode[0x10]; 7388 u8 reserved_at_10[0x10]; 7389 7390 u8 reserved_at_20[0x10]; 7391 u8 op_mod[0x10]; 7392 7393 u8 reserved_at_40[0x10]; 7394 u8 rate_limit_index[0x10]; 7395 7396 u8 reserved_at_60[0x20]; 7397 7398 u8 rate_limit[0x20]; 7399 7400 u8 reserved_at_a0[0x160]; 7401 }; 7402 7403 struct mlx5_ifc_access_register_out_bits { 7404 u8 status[0x8]; 7405 u8 reserved_at_8[0x18]; 7406 7407 u8 syndrome[0x20]; 7408 7409 u8 reserved_at_40[0x40]; 7410 7411 u8 register_data[0][0x20]; 7412 }; 7413 7414 enum { 7415 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 7416 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 7417 }; 7418 7419 struct mlx5_ifc_access_register_in_bits { 7420 u8 opcode[0x10]; 7421 u8 reserved_at_10[0x10]; 7422 7423 u8 reserved_at_20[0x10]; 7424 u8 op_mod[0x10]; 7425 7426 u8 reserved_at_40[0x10]; 7427 u8 register_id[0x10]; 7428 7429 u8 argument[0x20]; 7430 7431 u8 register_data[0][0x20]; 7432 }; 7433 7434 struct mlx5_ifc_sltp_reg_bits { 7435 u8 status[0x4]; 7436 u8 version[0x4]; 7437 u8 local_port[0x8]; 7438 u8 pnat[0x2]; 7439 u8 reserved_at_12[0x2]; 7440 u8 lane[0x4]; 7441 u8 reserved_at_18[0x8]; 7442 7443 u8 reserved_at_20[0x20]; 7444 7445 u8 reserved_at_40[0x7]; 7446 u8 polarity[0x1]; 7447 u8 ob_tap0[0x8]; 7448 u8 ob_tap1[0x8]; 7449 u8 ob_tap2[0x8]; 7450 7451 u8 reserved_at_60[0xc]; 7452 u8 ob_preemp_mode[0x4]; 7453 u8 ob_reg[0x8]; 7454 u8 ob_bias[0x8]; 7455 7456 u8 reserved_at_80[0x20]; 7457 }; 7458 7459 struct mlx5_ifc_slrg_reg_bits { 7460 u8 status[0x4]; 7461 u8 version[0x4]; 7462 u8 local_port[0x8]; 7463 u8 pnat[0x2]; 7464 u8 reserved_at_12[0x2]; 7465 u8 lane[0x4]; 7466 u8 reserved_at_18[0x8]; 7467 7468 u8 time_to_link_up[0x10]; 7469 u8 reserved_at_30[0xc]; 7470 u8 grade_lane_speed[0x4]; 7471 7472 u8 grade_version[0x8]; 7473 u8 grade[0x18]; 7474 7475 u8 reserved_at_60[0x4]; 7476 u8 height_grade_type[0x4]; 7477 u8 height_grade[0x18]; 7478 7479 u8 height_dz[0x10]; 7480 u8 height_dv[0x10]; 7481 7482 u8 reserved_at_a0[0x10]; 7483 u8 height_sigma[0x10]; 7484 7485 u8 reserved_at_c0[0x20]; 7486 7487 u8 reserved_at_e0[0x4]; 7488 u8 phase_grade_type[0x4]; 7489 u8 phase_grade[0x18]; 7490 7491 u8 reserved_at_100[0x8]; 7492 u8 phase_eo_pos[0x8]; 7493 u8 reserved_at_110[0x8]; 7494 u8 phase_eo_neg[0x8]; 7495 7496 u8 ffe_set_tested[0x10]; 7497 u8 test_errors_per_lane[0x10]; 7498 }; 7499 7500 struct mlx5_ifc_pvlc_reg_bits { 7501 u8 reserved_at_0[0x8]; 7502 u8 local_port[0x8]; 7503 u8 reserved_at_10[0x10]; 7504 7505 u8 reserved_at_20[0x1c]; 7506 u8 vl_hw_cap[0x4]; 7507 7508 u8 reserved_at_40[0x1c]; 7509 u8 vl_admin[0x4]; 7510 7511 u8 reserved_at_60[0x1c]; 7512 u8 vl_operational[0x4]; 7513 }; 7514 7515 struct mlx5_ifc_pude_reg_bits { 7516 u8 swid[0x8]; 7517 u8 local_port[0x8]; 7518 u8 reserved_at_10[0x4]; 7519 u8 admin_status[0x4]; 7520 u8 reserved_at_18[0x4]; 7521 u8 oper_status[0x4]; 7522 7523 u8 reserved_at_20[0x60]; 7524 }; 7525 7526 struct mlx5_ifc_ptys_reg_bits { 7527 u8 reserved_at_0[0x1]; 7528 u8 an_disable_admin[0x1]; 7529 u8 an_disable_cap[0x1]; 7530 u8 reserved_at_3[0x5]; 7531 u8 local_port[0x8]; 7532 u8 reserved_at_10[0xd]; 7533 u8 proto_mask[0x3]; 7534 7535 u8 an_status[0x4]; 7536 u8 reserved_at_24[0x3c]; 7537 7538 u8 eth_proto_capability[0x20]; 7539 7540 u8 ib_link_width_capability[0x10]; 7541 u8 ib_proto_capability[0x10]; 7542 7543 u8 reserved_at_a0[0x20]; 7544 7545 u8 eth_proto_admin[0x20]; 7546 7547 u8 ib_link_width_admin[0x10]; 7548 u8 ib_proto_admin[0x10]; 7549 7550 u8 reserved_at_100[0x20]; 7551 7552 u8 eth_proto_oper[0x20]; 7553 7554 u8 ib_link_width_oper[0x10]; 7555 u8 ib_proto_oper[0x10]; 7556 7557 u8 reserved_at_160[0x1c]; 7558 u8 connector_type[0x4]; 7559 7560 u8 eth_proto_lp_advertise[0x20]; 7561 7562 u8 reserved_at_1a0[0x60]; 7563 }; 7564 7565 struct mlx5_ifc_mlcr_reg_bits { 7566 u8 reserved_at_0[0x8]; 7567 u8 local_port[0x8]; 7568 u8 reserved_at_10[0x20]; 7569 7570 u8 beacon_duration[0x10]; 7571 u8 reserved_at_40[0x10]; 7572 7573 u8 beacon_remain[0x10]; 7574 }; 7575 7576 struct mlx5_ifc_ptas_reg_bits { 7577 u8 reserved_at_0[0x20]; 7578 7579 u8 algorithm_options[0x10]; 7580 u8 reserved_at_30[0x4]; 7581 u8 repetitions_mode[0x4]; 7582 u8 num_of_repetitions[0x8]; 7583 7584 u8 grade_version[0x8]; 7585 u8 height_grade_type[0x4]; 7586 u8 phase_grade_type[0x4]; 7587 u8 height_grade_weight[0x8]; 7588 u8 phase_grade_weight[0x8]; 7589 7590 u8 gisim_measure_bits[0x10]; 7591 u8 adaptive_tap_measure_bits[0x10]; 7592 7593 u8 ber_bath_high_error_threshold[0x10]; 7594 u8 ber_bath_mid_error_threshold[0x10]; 7595 7596 u8 ber_bath_low_error_threshold[0x10]; 7597 u8 one_ratio_high_threshold[0x10]; 7598 7599 u8 one_ratio_high_mid_threshold[0x10]; 7600 u8 one_ratio_low_mid_threshold[0x10]; 7601 7602 u8 one_ratio_low_threshold[0x10]; 7603 u8 ndeo_error_threshold[0x10]; 7604 7605 u8 mixer_offset_step_size[0x10]; 7606 u8 reserved_at_110[0x8]; 7607 u8 mix90_phase_for_voltage_bath[0x8]; 7608 7609 u8 mixer_offset_start[0x10]; 7610 u8 mixer_offset_end[0x10]; 7611 7612 u8 reserved_at_140[0x15]; 7613 u8 ber_test_time[0xb]; 7614 }; 7615 7616 struct mlx5_ifc_pspa_reg_bits { 7617 u8 swid[0x8]; 7618 u8 local_port[0x8]; 7619 u8 sub_port[0x8]; 7620 u8 reserved_at_18[0x8]; 7621 7622 u8 reserved_at_20[0x20]; 7623 }; 7624 7625 struct mlx5_ifc_pqdr_reg_bits { 7626 u8 reserved_at_0[0x8]; 7627 u8 local_port[0x8]; 7628 u8 reserved_at_10[0x5]; 7629 u8 prio[0x3]; 7630 u8 reserved_at_18[0x6]; 7631 u8 mode[0x2]; 7632 7633 u8 reserved_at_20[0x20]; 7634 7635 u8 reserved_at_40[0x10]; 7636 u8 min_threshold[0x10]; 7637 7638 u8 reserved_at_60[0x10]; 7639 u8 max_threshold[0x10]; 7640 7641 u8 reserved_at_80[0x10]; 7642 u8 mark_probability_denominator[0x10]; 7643 7644 u8 reserved_at_a0[0x60]; 7645 }; 7646 7647 struct mlx5_ifc_ppsc_reg_bits { 7648 u8 reserved_at_0[0x8]; 7649 u8 local_port[0x8]; 7650 u8 reserved_at_10[0x10]; 7651 7652 u8 reserved_at_20[0x60]; 7653 7654 u8 reserved_at_80[0x1c]; 7655 u8 wrps_admin[0x4]; 7656 7657 u8 reserved_at_a0[0x1c]; 7658 u8 wrps_status[0x4]; 7659 7660 u8 reserved_at_c0[0x8]; 7661 u8 up_threshold[0x8]; 7662 u8 reserved_at_d0[0x8]; 7663 u8 down_threshold[0x8]; 7664 7665 u8 reserved_at_e0[0x20]; 7666 7667 u8 reserved_at_100[0x1c]; 7668 u8 srps_admin[0x4]; 7669 7670 u8 reserved_at_120[0x1c]; 7671 u8 srps_status[0x4]; 7672 7673 u8 reserved_at_140[0x40]; 7674 }; 7675 7676 struct mlx5_ifc_pplr_reg_bits { 7677 u8 reserved_at_0[0x8]; 7678 u8 local_port[0x8]; 7679 u8 reserved_at_10[0x10]; 7680 7681 u8 reserved_at_20[0x8]; 7682 u8 lb_cap[0x8]; 7683 u8 reserved_at_30[0x8]; 7684 u8 lb_en[0x8]; 7685 }; 7686 7687 struct mlx5_ifc_pplm_reg_bits { 7688 u8 reserved_at_0[0x8]; 7689 u8 local_port[0x8]; 7690 u8 reserved_at_10[0x10]; 7691 7692 u8 reserved_at_20[0x20]; 7693 7694 u8 port_profile_mode[0x8]; 7695 u8 static_port_profile[0x8]; 7696 u8 active_port_profile[0x8]; 7697 u8 reserved_at_58[0x8]; 7698 7699 u8 retransmission_active[0x8]; 7700 u8 fec_mode_active[0x18]; 7701 7702 u8 reserved_at_80[0x20]; 7703 }; 7704 7705 struct mlx5_ifc_ppcnt_reg_bits { 7706 u8 swid[0x8]; 7707 u8 local_port[0x8]; 7708 u8 pnat[0x2]; 7709 u8 reserved_at_12[0x8]; 7710 u8 grp[0x6]; 7711 7712 u8 clr[0x1]; 7713 u8 reserved_at_21[0x1c]; 7714 u8 prio_tc[0x3]; 7715 7716 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 7717 }; 7718 7719 struct mlx5_ifc_mpcnt_reg_bits { 7720 u8 reserved_at_0[0x8]; 7721 u8 pcie_index[0x8]; 7722 u8 reserved_at_10[0xa]; 7723 u8 grp[0x6]; 7724 7725 u8 clr[0x1]; 7726 u8 reserved_at_21[0x1f]; 7727 7728 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 7729 }; 7730 7731 struct mlx5_ifc_ppad_reg_bits { 7732 u8 reserved_at_0[0x3]; 7733 u8 single_mac[0x1]; 7734 u8 reserved_at_4[0x4]; 7735 u8 local_port[0x8]; 7736 u8 mac_47_32[0x10]; 7737 7738 u8 mac_31_0[0x20]; 7739 7740 u8 reserved_at_40[0x40]; 7741 }; 7742 7743 struct mlx5_ifc_pmtu_reg_bits { 7744 u8 reserved_at_0[0x8]; 7745 u8 local_port[0x8]; 7746 u8 reserved_at_10[0x10]; 7747 7748 u8 max_mtu[0x10]; 7749 u8 reserved_at_30[0x10]; 7750 7751 u8 admin_mtu[0x10]; 7752 u8 reserved_at_50[0x10]; 7753 7754 u8 oper_mtu[0x10]; 7755 u8 reserved_at_70[0x10]; 7756 }; 7757 7758 struct mlx5_ifc_pmpr_reg_bits { 7759 u8 reserved_at_0[0x8]; 7760 u8 module[0x8]; 7761 u8 reserved_at_10[0x10]; 7762 7763 u8 reserved_at_20[0x18]; 7764 u8 attenuation_5g[0x8]; 7765 7766 u8 reserved_at_40[0x18]; 7767 u8 attenuation_7g[0x8]; 7768 7769 u8 reserved_at_60[0x18]; 7770 u8 attenuation_12g[0x8]; 7771 }; 7772 7773 struct mlx5_ifc_pmpe_reg_bits { 7774 u8 reserved_at_0[0x8]; 7775 u8 module[0x8]; 7776 u8 reserved_at_10[0xc]; 7777 u8 module_status[0x4]; 7778 7779 u8 reserved_at_20[0x60]; 7780 }; 7781 7782 struct mlx5_ifc_pmpc_reg_bits { 7783 u8 module_state_updated[32][0x8]; 7784 }; 7785 7786 struct mlx5_ifc_pmlpn_reg_bits { 7787 u8 reserved_at_0[0x4]; 7788 u8 mlpn_status[0x4]; 7789 u8 local_port[0x8]; 7790 u8 reserved_at_10[0x10]; 7791 7792 u8 e[0x1]; 7793 u8 reserved_at_21[0x1f]; 7794 }; 7795 7796 struct mlx5_ifc_pmlp_reg_bits { 7797 u8 rxtx[0x1]; 7798 u8 reserved_at_1[0x7]; 7799 u8 local_port[0x8]; 7800 u8 reserved_at_10[0x8]; 7801 u8 width[0x8]; 7802 7803 u8 lane0_module_mapping[0x20]; 7804 7805 u8 lane1_module_mapping[0x20]; 7806 7807 u8 lane2_module_mapping[0x20]; 7808 7809 u8 lane3_module_mapping[0x20]; 7810 7811 u8 reserved_at_a0[0x160]; 7812 }; 7813 7814 struct mlx5_ifc_pmaos_reg_bits { 7815 u8 reserved_at_0[0x8]; 7816 u8 module[0x8]; 7817 u8 reserved_at_10[0x4]; 7818 u8 admin_status[0x4]; 7819 u8 reserved_at_18[0x4]; 7820 u8 oper_status[0x4]; 7821 7822 u8 ase[0x1]; 7823 u8 ee[0x1]; 7824 u8 reserved_at_22[0x1c]; 7825 u8 e[0x2]; 7826 7827 u8 reserved_at_40[0x40]; 7828 }; 7829 7830 struct mlx5_ifc_plpc_reg_bits { 7831 u8 reserved_at_0[0x4]; 7832 u8 profile_id[0xc]; 7833 u8 reserved_at_10[0x4]; 7834 u8 proto_mask[0x4]; 7835 u8 reserved_at_18[0x8]; 7836 7837 u8 reserved_at_20[0x10]; 7838 u8 lane_speed[0x10]; 7839 7840 u8 reserved_at_40[0x17]; 7841 u8 lpbf[0x1]; 7842 u8 fec_mode_policy[0x8]; 7843 7844 u8 retransmission_capability[0x8]; 7845 u8 fec_mode_capability[0x18]; 7846 7847 u8 retransmission_support_admin[0x8]; 7848 u8 fec_mode_support_admin[0x18]; 7849 7850 u8 retransmission_request_admin[0x8]; 7851 u8 fec_mode_request_admin[0x18]; 7852 7853 u8 reserved_at_c0[0x80]; 7854 }; 7855 7856 struct mlx5_ifc_plib_reg_bits { 7857 u8 reserved_at_0[0x8]; 7858 u8 local_port[0x8]; 7859 u8 reserved_at_10[0x8]; 7860 u8 ib_port[0x8]; 7861 7862 u8 reserved_at_20[0x60]; 7863 }; 7864 7865 struct mlx5_ifc_plbf_reg_bits { 7866 u8 reserved_at_0[0x8]; 7867 u8 local_port[0x8]; 7868 u8 reserved_at_10[0xd]; 7869 u8 lbf_mode[0x3]; 7870 7871 u8 reserved_at_20[0x20]; 7872 }; 7873 7874 struct mlx5_ifc_pipg_reg_bits { 7875 u8 reserved_at_0[0x8]; 7876 u8 local_port[0x8]; 7877 u8 reserved_at_10[0x10]; 7878 7879 u8 dic[0x1]; 7880 u8 reserved_at_21[0x19]; 7881 u8 ipg[0x4]; 7882 u8 reserved_at_3e[0x2]; 7883 }; 7884 7885 struct mlx5_ifc_pifr_reg_bits { 7886 u8 reserved_at_0[0x8]; 7887 u8 local_port[0x8]; 7888 u8 reserved_at_10[0x10]; 7889 7890 u8 reserved_at_20[0xe0]; 7891 7892 u8 port_filter[8][0x20]; 7893 7894 u8 port_filter_update_en[8][0x20]; 7895 }; 7896 7897 struct mlx5_ifc_pfcc_reg_bits { 7898 u8 reserved_at_0[0x8]; 7899 u8 local_port[0x8]; 7900 u8 reserved_at_10[0xb]; 7901 u8 ppan_mask_n[0x1]; 7902 u8 minor_stall_mask[0x1]; 7903 u8 critical_stall_mask[0x1]; 7904 u8 reserved_at_1e[0x2]; 7905 7906 u8 ppan[0x4]; 7907 u8 reserved_at_24[0x4]; 7908 u8 prio_mask_tx[0x8]; 7909 u8 reserved_at_30[0x8]; 7910 u8 prio_mask_rx[0x8]; 7911 7912 u8 pptx[0x1]; 7913 u8 aptx[0x1]; 7914 u8 pptx_mask_n[0x1]; 7915 u8 reserved_at_43[0x5]; 7916 u8 pfctx[0x8]; 7917 u8 reserved_at_50[0x10]; 7918 7919 u8 pprx[0x1]; 7920 u8 aprx[0x1]; 7921 u8 pprx_mask_n[0x1]; 7922 u8 reserved_at_63[0x5]; 7923 u8 pfcrx[0x8]; 7924 u8 reserved_at_70[0x10]; 7925 7926 u8 device_stall_minor_watermark[0x10]; 7927 u8 device_stall_critical_watermark[0x10]; 7928 7929 u8 reserved_at_a0[0x60]; 7930 }; 7931 7932 struct mlx5_ifc_pelc_reg_bits { 7933 u8 op[0x4]; 7934 u8 reserved_at_4[0x4]; 7935 u8 local_port[0x8]; 7936 u8 reserved_at_10[0x10]; 7937 7938 u8 op_admin[0x8]; 7939 u8 op_capability[0x8]; 7940 u8 op_request[0x8]; 7941 u8 op_active[0x8]; 7942 7943 u8 admin[0x40]; 7944 7945 u8 capability[0x40]; 7946 7947 u8 request[0x40]; 7948 7949 u8 active[0x40]; 7950 7951 u8 reserved_at_140[0x80]; 7952 }; 7953 7954 struct mlx5_ifc_peir_reg_bits { 7955 u8 reserved_at_0[0x8]; 7956 u8 local_port[0x8]; 7957 u8 reserved_at_10[0x10]; 7958 7959 u8 reserved_at_20[0xc]; 7960 u8 error_count[0x4]; 7961 u8 reserved_at_30[0x10]; 7962 7963 u8 reserved_at_40[0xc]; 7964 u8 lane[0x4]; 7965 u8 reserved_at_50[0x8]; 7966 u8 error_type[0x8]; 7967 }; 7968 7969 struct mlx5_ifc_pcam_enhanced_features_bits { 7970 u8 reserved_at_0[0x76]; 7971 7972 u8 pfcc_mask[0x1]; 7973 u8 reserved_at_77[0x4]; 7974 u8 rx_buffer_fullness_counters[0x1]; 7975 u8 ptys_connector_type[0x1]; 7976 u8 reserved_at_7d[0x1]; 7977 u8 ppcnt_discard_group[0x1]; 7978 u8 ppcnt_statistical_group[0x1]; 7979 }; 7980 7981 struct mlx5_ifc_pcam_reg_bits { 7982 u8 reserved_at_0[0x8]; 7983 u8 feature_group[0x8]; 7984 u8 reserved_at_10[0x8]; 7985 u8 access_reg_group[0x8]; 7986 7987 u8 reserved_at_20[0x20]; 7988 7989 union { 7990 u8 reserved_at_0[0x80]; 7991 } port_access_reg_cap_mask; 7992 7993 u8 reserved_at_c0[0x80]; 7994 7995 union { 7996 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 7997 u8 reserved_at_0[0x80]; 7998 } feature_cap_mask; 7999 8000 u8 reserved_at_1c0[0xc0]; 8001 }; 8002 8003 struct mlx5_ifc_mcam_enhanced_features_bits { 8004 u8 reserved_at_0[0x7b]; 8005 u8 pcie_outbound_stalled[0x1]; 8006 u8 tx_overflow_buffer_pkt[0x1]; 8007 u8 mtpps_enh_out_per_adj[0x1]; 8008 u8 mtpps_fs[0x1]; 8009 u8 pcie_performance_group[0x1]; 8010 }; 8011 8012 struct mlx5_ifc_mcam_access_reg_bits { 8013 u8 reserved_at_0[0x1c]; 8014 u8 mcda[0x1]; 8015 u8 mcc[0x1]; 8016 u8 mcqi[0x1]; 8017 u8 reserved_at_1f[0x1]; 8018 8019 u8 regs_95_to_64[0x20]; 8020 u8 regs_63_to_32[0x20]; 8021 u8 regs_31_to_0[0x20]; 8022 }; 8023 8024 struct mlx5_ifc_mcam_reg_bits { 8025 u8 reserved_at_0[0x8]; 8026 u8 feature_group[0x8]; 8027 u8 reserved_at_10[0x8]; 8028 u8 access_reg_group[0x8]; 8029 8030 u8 reserved_at_20[0x20]; 8031 8032 union { 8033 struct mlx5_ifc_mcam_access_reg_bits access_regs; 8034 u8 reserved_at_0[0x80]; 8035 } mng_access_reg_cap_mask; 8036 8037 u8 reserved_at_c0[0x80]; 8038 8039 union { 8040 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 8041 u8 reserved_at_0[0x80]; 8042 } mng_feature_cap_mask; 8043 8044 u8 reserved_at_1c0[0x80]; 8045 }; 8046 8047 struct mlx5_ifc_qcam_access_reg_cap_mask { 8048 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 8049 u8 qpdpm[0x1]; 8050 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 8051 u8 qdpm[0x1]; 8052 u8 qpts[0x1]; 8053 u8 qcap[0x1]; 8054 u8 qcam_access_reg_cap_mask_0[0x1]; 8055 }; 8056 8057 struct mlx5_ifc_qcam_qos_feature_cap_mask { 8058 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 8059 u8 qpts_trust_both[0x1]; 8060 }; 8061 8062 struct mlx5_ifc_qcam_reg_bits { 8063 u8 reserved_at_0[0x8]; 8064 u8 feature_group[0x8]; 8065 u8 reserved_at_10[0x8]; 8066 u8 access_reg_group[0x8]; 8067 u8 reserved_at_20[0x20]; 8068 8069 union { 8070 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 8071 u8 reserved_at_0[0x80]; 8072 } qos_access_reg_cap_mask; 8073 8074 u8 reserved_at_c0[0x80]; 8075 8076 union { 8077 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 8078 u8 reserved_at_0[0x80]; 8079 } qos_feature_cap_mask; 8080 8081 u8 reserved_at_1c0[0x80]; 8082 }; 8083 8084 struct mlx5_ifc_pcap_reg_bits { 8085 u8 reserved_at_0[0x8]; 8086 u8 local_port[0x8]; 8087 u8 reserved_at_10[0x10]; 8088 8089 u8 port_capability_mask[4][0x20]; 8090 }; 8091 8092 struct mlx5_ifc_paos_reg_bits { 8093 u8 swid[0x8]; 8094 u8 local_port[0x8]; 8095 u8 reserved_at_10[0x4]; 8096 u8 admin_status[0x4]; 8097 u8 reserved_at_18[0x4]; 8098 u8 oper_status[0x4]; 8099 8100 u8 ase[0x1]; 8101 u8 ee[0x1]; 8102 u8 reserved_at_22[0x1c]; 8103 u8 e[0x2]; 8104 8105 u8 reserved_at_40[0x40]; 8106 }; 8107 8108 struct mlx5_ifc_pamp_reg_bits { 8109 u8 reserved_at_0[0x8]; 8110 u8 opamp_group[0x8]; 8111 u8 reserved_at_10[0xc]; 8112 u8 opamp_group_type[0x4]; 8113 8114 u8 start_index[0x10]; 8115 u8 reserved_at_30[0x4]; 8116 u8 num_of_indices[0xc]; 8117 8118 u8 index_data[18][0x10]; 8119 }; 8120 8121 struct mlx5_ifc_pcmr_reg_bits { 8122 u8 reserved_at_0[0x8]; 8123 u8 local_port[0x8]; 8124 u8 reserved_at_10[0x2e]; 8125 u8 fcs_cap[0x1]; 8126 u8 reserved_at_3f[0x1f]; 8127 u8 fcs_chk[0x1]; 8128 u8 reserved_at_5f[0x1]; 8129 }; 8130 8131 struct mlx5_ifc_lane_2_module_mapping_bits { 8132 u8 reserved_at_0[0x6]; 8133 u8 rx_lane[0x2]; 8134 u8 reserved_at_8[0x6]; 8135 u8 tx_lane[0x2]; 8136 u8 reserved_at_10[0x8]; 8137 u8 module[0x8]; 8138 }; 8139 8140 struct mlx5_ifc_bufferx_reg_bits { 8141 u8 reserved_at_0[0x6]; 8142 u8 lossy[0x1]; 8143 u8 epsb[0x1]; 8144 u8 reserved_at_8[0xc]; 8145 u8 size[0xc]; 8146 8147 u8 xoff_threshold[0x10]; 8148 u8 xon_threshold[0x10]; 8149 }; 8150 8151 struct mlx5_ifc_set_node_in_bits { 8152 u8 node_description[64][0x8]; 8153 }; 8154 8155 struct mlx5_ifc_register_power_settings_bits { 8156 u8 reserved_at_0[0x18]; 8157 u8 power_settings_level[0x8]; 8158 8159 u8 reserved_at_20[0x60]; 8160 }; 8161 8162 struct mlx5_ifc_register_host_endianness_bits { 8163 u8 he[0x1]; 8164 u8 reserved_at_1[0x1f]; 8165 8166 u8 reserved_at_20[0x60]; 8167 }; 8168 8169 struct mlx5_ifc_umr_pointer_desc_argument_bits { 8170 u8 reserved_at_0[0x20]; 8171 8172 u8 mkey[0x20]; 8173 8174 u8 addressh_63_32[0x20]; 8175 8176 u8 addressl_31_0[0x20]; 8177 }; 8178 8179 struct mlx5_ifc_ud_adrs_vector_bits { 8180 u8 dc_key[0x40]; 8181 8182 u8 ext[0x1]; 8183 u8 reserved_at_41[0x7]; 8184 u8 destination_qp_dct[0x18]; 8185 8186 u8 static_rate[0x4]; 8187 u8 sl_eth_prio[0x4]; 8188 u8 fl[0x1]; 8189 u8 mlid[0x7]; 8190 u8 rlid_udp_sport[0x10]; 8191 8192 u8 reserved_at_80[0x20]; 8193 8194 u8 rmac_47_16[0x20]; 8195 8196 u8 rmac_15_0[0x10]; 8197 u8 tclass[0x8]; 8198 u8 hop_limit[0x8]; 8199 8200 u8 reserved_at_e0[0x1]; 8201 u8 grh[0x1]; 8202 u8 reserved_at_e2[0x2]; 8203 u8 src_addr_index[0x8]; 8204 u8 flow_label[0x14]; 8205 8206 u8 rgid_rip[16][0x8]; 8207 }; 8208 8209 struct mlx5_ifc_pages_req_event_bits { 8210 u8 reserved_at_0[0x10]; 8211 u8 function_id[0x10]; 8212 8213 u8 num_pages[0x20]; 8214 8215 u8 reserved_at_40[0xa0]; 8216 }; 8217 8218 struct mlx5_ifc_eqe_bits { 8219 u8 reserved_at_0[0x8]; 8220 u8 event_type[0x8]; 8221 u8 reserved_at_10[0x8]; 8222 u8 event_sub_type[0x8]; 8223 8224 u8 reserved_at_20[0xe0]; 8225 8226 union mlx5_ifc_event_auto_bits event_data; 8227 8228 u8 reserved_at_1e0[0x10]; 8229 u8 signature[0x8]; 8230 u8 reserved_at_1f8[0x7]; 8231 u8 owner[0x1]; 8232 }; 8233 8234 enum { 8235 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 8236 }; 8237 8238 struct mlx5_ifc_cmd_queue_entry_bits { 8239 u8 type[0x8]; 8240 u8 reserved_at_8[0x18]; 8241 8242 u8 input_length[0x20]; 8243 8244 u8 input_mailbox_pointer_63_32[0x20]; 8245 8246 u8 input_mailbox_pointer_31_9[0x17]; 8247 u8 reserved_at_77[0x9]; 8248 8249 u8 command_input_inline_data[16][0x8]; 8250 8251 u8 command_output_inline_data[16][0x8]; 8252 8253 u8 output_mailbox_pointer_63_32[0x20]; 8254 8255 u8 output_mailbox_pointer_31_9[0x17]; 8256 u8 reserved_at_1b7[0x9]; 8257 8258 u8 output_length[0x20]; 8259 8260 u8 token[0x8]; 8261 u8 signature[0x8]; 8262 u8 reserved_at_1f0[0x8]; 8263 u8 status[0x7]; 8264 u8 ownership[0x1]; 8265 }; 8266 8267 struct mlx5_ifc_cmd_out_bits { 8268 u8 status[0x8]; 8269 u8 reserved_at_8[0x18]; 8270 8271 u8 syndrome[0x20]; 8272 8273 u8 command_output[0x20]; 8274 }; 8275 8276 struct mlx5_ifc_cmd_in_bits { 8277 u8 opcode[0x10]; 8278 u8 reserved_at_10[0x10]; 8279 8280 u8 reserved_at_20[0x10]; 8281 u8 op_mod[0x10]; 8282 8283 u8 command[0][0x20]; 8284 }; 8285 8286 struct mlx5_ifc_cmd_if_box_bits { 8287 u8 mailbox_data[512][0x8]; 8288 8289 u8 reserved_at_1000[0x180]; 8290 8291 u8 next_pointer_63_32[0x20]; 8292 8293 u8 next_pointer_31_10[0x16]; 8294 u8 reserved_at_11b6[0xa]; 8295 8296 u8 block_number[0x20]; 8297 8298 u8 reserved_at_11e0[0x8]; 8299 u8 token[0x8]; 8300 u8 ctrl_signature[0x8]; 8301 u8 signature[0x8]; 8302 }; 8303 8304 struct mlx5_ifc_mtt_bits { 8305 u8 ptag_63_32[0x20]; 8306 8307 u8 ptag_31_8[0x18]; 8308 u8 reserved_at_38[0x6]; 8309 u8 wr_en[0x1]; 8310 u8 rd_en[0x1]; 8311 }; 8312 8313 struct mlx5_ifc_query_wol_rol_out_bits { 8314 u8 status[0x8]; 8315 u8 reserved_at_8[0x18]; 8316 8317 u8 syndrome[0x20]; 8318 8319 u8 reserved_at_40[0x10]; 8320 u8 rol_mode[0x8]; 8321 u8 wol_mode[0x8]; 8322 8323 u8 reserved_at_60[0x20]; 8324 }; 8325 8326 struct mlx5_ifc_query_wol_rol_in_bits { 8327 u8 opcode[0x10]; 8328 u8 reserved_at_10[0x10]; 8329 8330 u8 reserved_at_20[0x10]; 8331 u8 op_mod[0x10]; 8332 8333 u8 reserved_at_40[0x40]; 8334 }; 8335 8336 struct mlx5_ifc_set_wol_rol_out_bits { 8337 u8 status[0x8]; 8338 u8 reserved_at_8[0x18]; 8339 8340 u8 syndrome[0x20]; 8341 8342 u8 reserved_at_40[0x40]; 8343 }; 8344 8345 struct mlx5_ifc_set_wol_rol_in_bits { 8346 u8 opcode[0x10]; 8347 u8 reserved_at_10[0x10]; 8348 8349 u8 reserved_at_20[0x10]; 8350 u8 op_mod[0x10]; 8351 8352 u8 rol_mode_valid[0x1]; 8353 u8 wol_mode_valid[0x1]; 8354 u8 reserved_at_42[0xe]; 8355 u8 rol_mode[0x8]; 8356 u8 wol_mode[0x8]; 8357 8358 u8 reserved_at_60[0x20]; 8359 }; 8360 8361 enum { 8362 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 8363 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 8364 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 8365 }; 8366 8367 enum { 8368 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 8369 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 8370 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 8371 }; 8372 8373 enum { 8374 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 8375 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 8376 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 8377 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 8378 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 8379 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 8380 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 8381 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 8382 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 8383 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 8384 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 8385 }; 8386 8387 struct mlx5_ifc_initial_seg_bits { 8388 u8 fw_rev_minor[0x10]; 8389 u8 fw_rev_major[0x10]; 8390 8391 u8 cmd_interface_rev[0x10]; 8392 u8 fw_rev_subminor[0x10]; 8393 8394 u8 reserved_at_40[0x40]; 8395 8396 u8 cmdq_phy_addr_63_32[0x20]; 8397 8398 u8 cmdq_phy_addr_31_12[0x14]; 8399 u8 reserved_at_b4[0x2]; 8400 u8 nic_interface[0x2]; 8401 u8 log_cmdq_size[0x4]; 8402 u8 log_cmdq_stride[0x4]; 8403 8404 u8 command_doorbell_vector[0x20]; 8405 8406 u8 reserved_at_e0[0xf00]; 8407 8408 u8 initializing[0x1]; 8409 u8 reserved_at_fe1[0x4]; 8410 u8 nic_interface_supported[0x3]; 8411 u8 reserved_at_fe8[0x18]; 8412 8413 struct mlx5_ifc_health_buffer_bits health_buffer; 8414 8415 u8 no_dram_nic_offset[0x20]; 8416 8417 u8 reserved_at_1220[0x6e40]; 8418 8419 u8 reserved_at_8060[0x1f]; 8420 u8 clear_int[0x1]; 8421 8422 u8 health_syndrome[0x8]; 8423 u8 health_counter[0x18]; 8424 8425 u8 reserved_at_80a0[0x17fc0]; 8426 }; 8427 8428 struct mlx5_ifc_mtpps_reg_bits { 8429 u8 reserved_at_0[0xc]; 8430 u8 cap_number_of_pps_pins[0x4]; 8431 u8 reserved_at_10[0x4]; 8432 u8 cap_max_num_of_pps_in_pins[0x4]; 8433 u8 reserved_at_18[0x4]; 8434 u8 cap_max_num_of_pps_out_pins[0x4]; 8435 8436 u8 reserved_at_20[0x24]; 8437 u8 cap_pin_3_mode[0x4]; 8438 u8 reserved_at_48[0x4]; 8439 u8 cap_pin_2_mode[0x4]; 8440 u8 reserved_at_50[0x4]; 8441 u8 cap_pin_1_mode[0x4]; 8442 u8 reserved_at_58[0x4]; 8443 u8 cap_pin_0_mode[0x4]; 8444 8445 u8 reserved_at_60[0x4]; 8446 u8 cap_pin_7_mode[0x4]; 8447 u8 reserved_at_68[0x4]; 8448 u8 cap_pin_6_mode[0x4]; 8449 u8 reserved_at_70[0x4]; 8450 u8 cap_pin_5_mode[0x4]; 8451 u8 reserved_at_78[0x4]; 8452 u8 cap_pin_4_mode[0x4]; 8453 8454 u8 field_select[0x20]; 8455 u8 reserved_at_a0[0x60]; 8456 8457 u8 enable[0x1]; 8458 u8 reserved_at_101[0xb]; 8459 u8 pattern[0x4]; 8460 u8 reserved_at_110[0x4]; 8461 u8 pin_mode[0x4]; 8462 u8 pin[0x8]; 8463 8464 u8 reserved_at_120[0x20]; 8465 8466 u8 time_stamp[0x40]; 8467 8468 u8 out_pulse_duration[0x10]; 8469 u8 out_periodic_adjustment[0x10]; 8470 u8 enhanced_out_periodic_adjustment[0x20]; 8471 8472 u8 reserved_at_1c0[0x20]; 8473 }; 8474 8475 struct mlx5_ifc_mtppse_reg_bits { 8476 u8 reserved_at_0[0x18]; 8477 u8 pin[0x8]; 8478 u8 event_arm[0x1]; 8479 u8 reserved_at_21[0x1b]; 8480 u8 event_generation_mode[0x4]; 8481 u8 reserved_at_40[0x40]; 8482 }; 8483 8484 struct mlx5_ifc_mcqi_cap_bits { 8485 u8 supported_info_bitmask[0x20]; 8486 8487 u8 component_size[0x20]; 8488 8489 u8 max_component_size[0x20]; 8490 8491 u8 log_mcda_word_size[0x4]; 8492 u8 reserved_at_64[0xc]; 8493 u8 mcda_max_write_size[0x10]; 8494 8495 u8 rd_en[0x1]; 8496 u8 reserved_at_81[0x1]; 8497 u8 match_chip_id[0x1]; 8498 u8 match_psid[0x1]; 8499 u8 check_user_timestamp[0x1]; 8500 u8 match_base_guid_mac[0x1]; 8501 u8 reserved_at_86[0x1a]; 8502 }; 8503 8504 struct mlx5_ifc_mcqi_reg_bits { 8505 u8 read_pending_component[0x1]; 8506 u8 reserved_at_1[0xf]; 8507 u8 component_index[0x10]; 8508 8509 u8 reserved_at_20[0x20]; 8510 8511 u8 reserved_at_40[0x1b]; 8512 u8 info_type[0x5]; 8513 8514 u8 info_size[0x20]; 8515 8516 u8 offset[0x20]; 8517 8518 u8 reserved_at_a0[0x10]; 8519 u8 data_size[0x10]; 8520 8521 u8 data[0][0x20]; 8522 }; 8523 8524 struct mlx5_ifc_mcc_reg_bits { 8525 u8 reserved_at_0[0x4]; 8526 u8 time_elapsed_since_last_cmd[0xc]; 8527 u8 reserved_at_10[0x8]; 8528 u8 instruction[0x8]; 8529 8530 u8 reserved_at_20[0x10]; 8531 u8 component_index[0x10]; 8532 8533 u8 reserved_at_40[0x8]; 8534 u8 update_handle[0x18]; 8535 8536 u8 handle_owner_type[0x4]; 8537 u8 handle_owner_host_id[0x4]; 8538 u8 reserved_at_68[0x1]; 8539 u8 control_progress[0x7]; 8540 u8 error_code[0x8]; 8541 u8 reserved_at_78[0x4]; 8542 u8 control_state[0x4]; 8543 8544 u8 component_size[0x20]; 8545 8546 u8 reserved_at_a0[0x60]; 8547 }; 8548 8549 struct mlx5_ifc_mcda_reg_bits { 8550 u8 reserved_at_0[0x8]; 8551 u8 update_handle[0x18]; 8552 8553 u8 offset[0x20]; 8554 8555 u8 reserved_at_40[0x10]; 8556 u8 size[0x10]; 8557 8558 u8 reserved_at_60[0x20]; 8559 8560 u8 data[0][0x20]; 8561 }; 8562 8563 union mlx5_ifc_ports_control_registers_document_bits { 8564 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 8565 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 8566 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 8567 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 8568 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 8569 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 8570 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 8571 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout; 8572 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 8573 struct mlx5_ifc_pamp_reg_bits pamp_reg; 8574 struct mlx5_ifc_paos_reg_bits paos_reg; 8575 struct mlx5_ifc_pcap_reg_bits pcap_reg; 8576 struct mlx5_ifc_peir_reg_bits peir_reg; 8577 struct mlx5_ifc_pelc_reg_bits pelc_reg; 8578 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 8579 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 8580 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 8581 struct mlx5_ifc_pifr_reg_bits pifr_reg; 8582 struct mlx5_ifc_pipg_reg_bits pipg_reg; 8583 struct mlx5_ifc_plbf_reg_bits plbf_reg; 8584 struct mlx5_ifc_plib_reg_bits plib_reg; 8585 struct mlx5_ifc_plpc_reg_bits plpc_reg; 8586 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 8587 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 8588 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 8589 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 8590 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 8591 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 8592 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 8593 struct mlx5_ifc_ppad_reg_bits ppad_reg; 8594 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 8595 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 8596 struct mlx5_ifc_pplm_reg_bits pplm_reg; 8597 struct mlx5_ifc_pplr_reg_bits pplr_reg; 8598 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 8599 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 8600 struct mlx5_ifc_pspa_reg_bits pspa_reg; 8601 struct mlx5_ifc_ptas_reg_bits ptas_reg; 8602 struct mlx5_ifc_ptys_reg_bits ptys_reg; 8603 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 8604 struct mlx5_ifc_pude_reg_bits pude_reg; 8605 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 8606 struct mlx5_ifc_slrg_reg_bits slrg_reg; 8607 struct mlx5_ifc_sltp_reg_bits sltp_reg; 8608 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 8609 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 8610 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 8611 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 8612 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 8613 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 8614 struct mlx5_ifc_mcc_reg_bits mcc_reg; 8615 struct mlx5_ifc_mcda_reg_bits mcda_reg; 8616 u8 reserved_at_0[0x60e0]; 8617 }; 8618 8619 union mlx5_ifc_debug_enhancements_document_bits { 8620 struct mlx5_ifc_health_buffer_bits health_buffer; 8621 u8 reserved_at_0[0x200]; 8622 }; 8623 8624 union mlx5_ifc_uplink_pci_interface_document_bits { 8625 struct mlx5_ifc_initial_seg_bits initial_seg; 8626 u8 reserved_at_0[0x20060]; 8627 }; 8628 8629 struct mlx5_ifc_set_flow_table_root_out_bits { 8630 u8 status[0x8]; 8631 u8 reserved_at_8[0x18]; 8632 8633 u8 syndrome[0x20]; 8634 8635 u8 reserved_at_40[0x40]; 8636 }; 8637 8638 struct mlx5_ifc_set_flow_table_root_in_bits { 8639 u8 opcode[0x10]; 8640 u8 reserved_at_10[0x10]; 8641 8642 u8 reserved_at_20[0x10]; 8643 u8 op_mod[0x10]; 8644 8645 u8 other_vport[0x1]; 8646 u8 reserved_at_41[0xf]; 8647 u8 vport_number[0x10]; 8648 8649 u8 reserved_at_60[0x20]; 8650 8651 u8 table_type[0x8]; 8652 u8 reserved_at_88[0x18]; 8653 8654 u8 reserved_at_a0[0x8]; 8655 u8 table_id[0x18]; 8656 8657 u8 reserved_at_c0[0x8]; 8658 u8 underlay_qpn[0x18]; 8659 u8 reserved_at_e0[0x120]; 8660 }; 8661 8662 enum { 8663 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 8664 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 8665 }; 8666 8667 struct mlx5_ifc_modify_flow_table_out_bits { 8668 u8 status[0x8]; 8669 u8 reserved_at_8[0x18]; 8670 8671 u8 syndrome[0x20]; 8672 8673 u8 reserved_at_40[0x40]; 8674 }; 8675 8676 struct mlx5_ifc_modify_flow_table_in_bits { 8677 u8 opcode[0x10]; 8678 u8 reserved_at_10[0x10]; 8679 8680 u8 reserved_at_20[0x10]; 8681 u8 op_mod[0x10]; 8682 8683 u8 other_vport[0x1]; 8684 u8 reserved_at_41[0xf]; 8685 u8 vport_number[0x10]; 8686 8687 u8 reserved_at_60[0x10]; 8688 u8 modify_field_select[0x10]; 8689 8690 u8 table_type[0x8]; 8691 u8 reserved_at_88[0x18]; 8692 8693 u8 reserved_at_a0[0x8]; 8694 u8 table_id[0x18]; 8695 8696 struct mlx5_ifc_flow_table_context_bits flow_table_context; 8697 }; 8698 8699 struct mlx5_ifc_ets_tcn_config_reg_bits { 8700 u8 g[0x1]; 8701 u8 b[0x1]; 8702 u8 r[0x1]; 8703 u8 reserved_at_3[0x9]; 8704 u8 group[0x4]; 8705 u8 reserved_at_10[0x9]; 8706 u8 bw_allocation[0x7]; 8707 8708 u8 reserved_at_20[0xc]; 8709 u8 max_bw_units[0x4]; 8710 u8 reserved_at_30[0x8]; 8711 u8 max_bw_value[0x8]; 8712 }; 8713 8714 struct mlx5_ifc_ets_global_config_reg_bits { 8715 u8 reserved_at_0[0x2]; 8716 u8 r[0x1]; 8717 u8 reserved_at_3[0x1d]; 8718 8719 u8 reserved_at_20[0xc]; 8720 u8 max_bw_units[0x4]; 8721 u8 reserved_at_30[0x8]; 8722 u8 max_bw_value[0x8]; 8723 }; 8724 8725 struct mlx5_ifc_qetc_reg_bits { 8726 u8 reserved_at_0[0x8]; 8727 u8 port_number[0x8]; 8728 u8 reserved_at_10[0x30]; 8729 8730 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 8731 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 8732 }; 8733 8734 struct mlx5_ifc_qpdpm_dscp_reg_bits { 8735 u8 e[0x1]; 8736 u8 reserved_at_01[0x0b]; 8737 u8 prio[0x04]; 8738 }; 8739 8740 struct mlx5_ifc_qpdpm_reg_bits { 8741 u8 reserved_at_0[0x8]; 8742 u8 local_port[0x8]; 8743 u8 reserved_at_10[0x10]; 8744 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 8745 }; 8746 8747 struct mlx5_ifc_qpts_reg_bits { 8748 u8 reserved_at_0[0x8]; 8749 u8 local_port[0x8]; 8750 u8 reserved_at_10[0x2d]; 8751 u8 trust_state[0x3]; 8752 }; 8753 8754 struct mlx5_ifc_qtct_reg_bits { 8755 u8 reserved_at_0[0x8]; 8756 u8 port_number[0x8]; 8757 u8 reserved_at_10[0xd]; 8758 u8 prio[0x3]; 8759 8760 u8 reserved_at_20[0x1d]; 8761 u8 tclass[0x3]; 8762 }; 8763 8764 struct mlx5_ifc_mcia_reg_bits { 8765 u8 l[0x1]; 8766 u8 reserved_at_1[0x7]; 8767 u8 module[0x8]; 8768 u8 reserved_at_10[0x8]; 8769 u8 status[0x8]; 8770 8771 u8 i2c_device_address[0x8]; 8772 u8 page_number[0x8]; 8773 u8 device_address[0x10]; 8774 8775 u8 reserved_at_40[0x10]; 8776 u8 size[0x10]; 8777 8778 u8 reserved_at_60[0x20]; 8779 8780 u8 dword_0[0x20]; 8781 u8 dword_1[0x20]; 8782 u8 dword_2[0x20]; 8783 u8 dword_3[0x20]; 8784 u8 dword_4[0x20]; 8785 u8 dword_5[0x20]; 8786 u8 dword_6[0x20]; 8787 u8 dword_7[0x20]; 8788 u8 dword_8[0x20]; 8789 u8 dword_9[0x20]; 8790 u8 dword_10[0x20]; 8791 u8 dword_11[0x20]; 8792 }; 8793 8794 struct mlx5_ifc_dcbx_param_bits { 8795 u8 dcbx_cee_cap[0x1]; 8796 u8 dcbx_ieee_cap[0x1]; 8797 u8 dcbx_standby_cap[0x1]; 8798 u8 reserved_at_0[0x5]; 8799 u8 port_number[0x8]; 8800 u8 reserved_at_10[0xa]; 8801 u8 max_application_table_size[6]; 8802 u8 reserved_at_20[0x15]; 8803 u8 version_oper[0x3]; 8804 u8 reserved_at_38[5]; 8805 u8 version_admin[0x3]; 8806 u8 willing_admin[0x1]; 8807 u8 reserved_at_41[0x3]; 8808 u8 pfc_cap_oper[0x4]; 8809 u8 reserved_at_48[0x4]; 8810 u8 pfc_cap_admin[0x4]; 8811 u8 reserved_at_50[0x4]; 8812 u8 num_of_tc_oper[0x4]; 8813 u8 reserved_at_58[0x4]; 8814 u8 num_of_tc_admin[0x4]; 8815 u8 remote_willing[0x1]; 8816 u8 reserved_at_61[3]; 8817 u8 remote_pfc_cap[4]; 8818 u8 reserved_at_68[0x14]; 8819 u8 remote_num_of_tc[0x4]; 8820 u8 reserved_at_80[0x18]; 8821 u8 error[0x8]; 8822 u8 reserved_at_a0[0x160]; 8823 }; 8824 8825 struct mlx5_ifc_lagc_bits { 8826 u8 reserved_at_0[0x1d]; 8827 u8 lag_state[0x3]; 8828 8829 u8 reserved_at_20[0x14]; 8830 u8 tx_remap_affinity_2[0x4]; 8831 u8 reserved_at_38[0x4]; 8832 u8 tx_remap_affinity_1[0x4]; 8833 }; 8834 8835 struct mlx5_ifc_create_lag_out_bits { 8836 u8 status[0x8]; 8837 u8 reserved_at_8[0x18]; 8838 8839 u8 syndrome[0x20]; 8840 8841 u8 reserved_at_40[0x40]; 8842 }; 8843 8844 struct mlx5_ifc_create_lag_in_bits { 8845 u8 opcode[0x10]; 8846 u8 reserved_at_10[0x10]; 8847 8848 u8 reserved_at_20[0x10]; 8849 u8 op_mod[0x10]; 8850 8851 struct mlx5_ifc_lagc_bits ctx; 8852 }; 8853 8854 struct mlx5_ifc_modify_lag_out_bits { 8855 u8 status[0x8]; 8856 u8 reserved_at_8[0x18]; 8857 8858 u8 syndrome[0x20]; 8859 8860 u8 reserved_at_40[0x40]; 8861 }; 8862 8863 struct mlx5_ifc_modify_lag_in_bits { 8864 u8 opcode[0x10]; 8865 u8 reserved_at_10[0x10]; 8866 8867 u8 reserved_at_20[0x10]; 8868 u8 op_mod[0x10]; 8869 8870 u8 reserved_at_40[0x20]; 8871 u8 field_select[0x20]; 8872 8873 struct mlx5_ifc_lagc_bits ctx; 8874 }; 8875 8876 struct mlx5_ifc_query_lag_out_bits { 8877 u8 status[0x8]; 8878 u8 reserved_at_8[0x18]; 8879 8880 u8 syndrome[0x20]; 8881 8882 u8 reserved_at_40[0x40]; 8883 8884 struct mlx5_ifc_lagc_bits ctx; 8885 }; 8886 8887 struct mlx5_ifc_query_lag_in_bits { 8888 u8 opcode[0x10]; 8889 u8 reserved_at_10[0x10]; 8890 8891 u8 reserved_at_20[0x10]; 8892 u8 op_mod[0x10]; 8893 8894 u8 reserved_at_40[0x40]; 8895 }; 8896 8897 struct mlx5_ifc_destroy_lag_out_bits { 8898 u8 status[0x8]; 8899 u8 reserved_at_8[0x18]; 8900 8901 u8 syndrome[0x20]; 8902 8903 u8 reserved_at_40[0x40]; 8904 }; 8905 8906 struct mlx5_ifc_destroy_lag_in_bits { 8907 u8 opcode[0x10]; 8908 u8 reserved_at_10[0x10]; 8909 8910 u8 reserved_at_20[0x10]; 8911 u8 op_mod[0x10]; 8912 8913 u8 reserved_at_40[0x40]; 8914 }; 8915 8916 struct mlx5_ifc_create_vport_lag_out_bits { 8917 u8 status[0x8]; 8918 u8 reserved_at_8[0x18]; 8919 8920 u8 syndrome[0x20]; 8921 8922 u8 reserved_at_40[0x40]; 8923 }; 8924 8925 struct mlx5_ifc_create_vport_lag_in_bits { 8926 u8 opcode[0x10]; 8927 u8 reserved_at_10[0x10]; 8928 8929 u8 reserved_at_20[0x10]; 8930 u8 op_mod[0x10]; 8931 8932 u8 reserved_at_40[0x40]; 8933 }; 8934 8935 struct mlx5_ifc_destroy_vport_lag_out_bits { 8936 u8 status[0x8]; 8937 u8 reserved_at_8[0x18]; 8938 8939 u8 syndrome[0x20]; 8940 8941 u8 reserved_at_40[0x40]; 8942 }; 8943 8944 struct mlx5_ifc_destroy_vport_lag_in_bits { 8945 u8 opcode[0x10]; 8946 u8 reserved_at_10[0x10]; 8947 8948 u8 reserved_at_20[0x10]; 8949 u8 op_mod[0x10]; 8950 8951 u8 reserved_at_40[0x40]; 8952 }; 8953 8954 #endif /* MLX5_IFC_H */ 8955