1 /* QLogic qedr NIC Driver 2 * Copyright (c) 2015-2016 QLogic Corporation 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and /or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef __QED_HSI_RDMA__ 33 #define __QED_HSI_RDMA__ 34 35 #include <linux/qed/rdma_common.h> 36 37 /* rdma completion notification queue element */ 38 struct rdma_cnqe { 39 struct regpair cq_handle; 40 }; 41 42 struct rdma_cqe_responder { 43 struct regpair srq_wr_id; 44 struct regpair qp_handle; 45 __le32 imm_data_or_inv_r_Key; 46 __le32 length; 47 __le32 imm_data_hi; 48 __le16 rq_cons_or_srq_id; 49 u8 flags; 50 #define RDMA_CQE_RESPONDER_TOGGLE_BIT_MASK 0x1 51 #define RDMA_CQE_RESPONDER_TOGGLE_BIT_SHIFT 0 52 #define RDMA_CQE_RESPONDER_TYPE_MASK 0x3 53 #define RDMA_CQE_RESPONDER_TYPE_SHIFT 1 54 #define RDMA_CQE_RESPONDER_INV_FLG_MASK 0x1 55 #define RDMA_CQE_RESPONDER_INV_FLG_SHIFT 3 56 #define RDMA_CQE_RESPONDER_IMM_FLG_MASK 0x1 57 #define RDMA_CQE_RESPONDER_IMM_FLG_SHIFT 4 58 #define RDMA_CQE_RESPONDER_RDMA_FLG_MASK 0x1 59 #define RDMA_CQE_RESPONDER_RDMA_FLG_SHIFT 5 60 #define RDMA_CQE_RESPONDER_RESERVED2_MASK 0x3 61 #define RDMA_CQE_RESPONDER_RESERVED2_SHIFT 6 62 u8 status; 63 }; 64 65 struct rdma_cqe_requester { 66 __le16 sq_cons; 67 __le16 reserved0; 68 __le32 reserved1; 69 struct regpair qp_handle; 70 struct regpair reserved2; 71 __le32 reserved3; 72 __le16 reserved4; 73 u8 flags; 74 #define RDMA_CQE_REQUESTER_TOGGLE_BIT_MASK 0x1 75 #define RDMA_CQE_REQUESTER_TOGGLE_BIT_SHIFT 0 76 #define RDMA_CQE_REQUESTER_TYPE_MASK 0x3 77 #define RDMA_CQE_REQUESTER_TYPE_SHIFT 1 78 #define RDMA_CQE_REQUESTER_RESERVED5_MASK 0x1F 79 #define RDMA_CQE_REQUESTER_RESERVED5_SHIFT 3 80 u8 status; 81 }; 82 83 struct rdma_cqe_common { 84 struct regpair reserved0; 85 struct regpair qp_handle; 86 __le16 reserved1[7]; 87 u8 flags; 88 #define RDMA_CQE_COMMON_TOGGLE_BIT_MASK 0x1 89 #define RDMA_CQE_COMMON_TOGGLE_BIT_SHIFT 0 90 #define RDMA_CQE_COMMON_TYPE_MASK 0x3 91 #define RDMA_CQE_COMMON_TYPE_SHIFT 1 92 #define RDMA_CQE_COMMON_RESERVED2_MASK 0x1F 93 #define RDMA_CQE_COMMON_RESERVED2_SHIFT 3 94 u8 status; 95 }; 96 97 /* rdma completion queue element */ 98 union rdma_cqe { 99 struct rdma_cqe_responder resp; 100 struct rdma_cqe_requester req; 101 struct rdma_cqe_common cmn; 102 }; 103 104 /* * CQE requester status enumeration */ 105 enum rdma_cqe_requester_status_enum { 106 RDMA_CQE_REQ_STS_OK, 107 RDMA_CQE_REQ_STS_BAD_RESPONSE_ERR, 108 RDMA_CQE_REQ_STS_LOCAL_LENGTH_ERR, 109 RDMA_CQE_REQ_STS_LOCAL_QP_OPERATION_ERR, 110 RDMA_CQE_REQ_STS_LOCAL_PROTECTION_ERR, 111 RDMA_CQE_REQ_STS_MEMORY_MGT_OPERATION_ERR, 112 RDMA_CQE_REQ_STS_REMOTE_INVALID_REQUEST_ERR, 113 RDMA_CQE_REQ_STS_REMOTE_ACCESS_ERR, 114 RDMA_CQE_REQ_STS_REMOTE_OPERATION_ERR, 115 RDMA_CQE_REQ_STS_RNR_NAK_RETRY_CNT_ERR, 116 RDMA_CQE_REQ_STS_TRANSPORT_RETRY_CNT_ERR, 117 RDMA_CQE_REQ_STS_WORK_REQUEST_FLUSHED_ERR, 118 RDMA_CQE_REQ_STS_XRC_VOILATION_ERR, 119 MAX_RDMA_CQE_REQUESTER_STATUS_ENUM 120 }; 121 122 /* CQE responder status enumeration */ 123 enum rdma_cqe_responder_status_enum { 124 RDMA_CQE_RESP_STS_OK, 125 RDMA_CQE_RESP_STS_LOCAL_ACCESS_ERR, 126 RDMA_CQE_RESP_STS_LOCAL_LENGTH_ERR, 127 RDMA_CQE_RESP_STS_LOCAL_QP_OPERATION_ERR, 128 RDMA_CQE_RESP_STS_LOCAL_PROTECTION_ERR, 129 RDMA_CQE_RESP_STS_MEMORY_MGT_OPERATION_ERR, 130 RDMA_CQE_RESP_STS_REMOTE_INVALID_REQUEST_ERR, 131 RDMA_CQE_RESP_STS_WORK_REQUEST_FLUSHED_ERR, 132 MAX_RDMA_CQE_RESPONDER_STATUS_ENUM 133 }; 134 135 /* CQE type enumeration */ 136 enum rdma_cqe_type { 137 RDMA_CQE_TYPE_REQUESTER, 138 RDMA_CQE_TYPE_RESPONDER_RQ, 139 RDMA_CQE_TYPE_RESPONDER_SRQ, 140 RDMA_CQE_TYPE_RESPONDER_XRC_SRQ, 141 RDMA_CQE_TYPE_INVALID, 142 MAX_RDMA_CQE_TYPE 143 }; 144 145 struct rdma_sq_sge { 146 __le32 length; 147 struct regpair addr; 148 __le32 l_key; 149 }; 150 151 struct rdma_rq_sge { 152 struct regpair addr; 153 __le32 length; 154 __le32 flags; 155 #define RDMA_RQ_SGE_L_KEY_MASK 0x3FFFFFF 156 #define RDMA_RQ_SGE_L_KEY_SHIFT 0 157 #define RDMA_RQ_SGE_NUM_SGES_MASK 0x7 158 #define RDMA_RQ_SGE_NUM_SGES_SHIFT 26 159 #define RDMA_RQ_SGE_RESERVED0_MASK 0x7 160 #define RDMA_RQ_SGE_RESERVED0_SHIFT 29 161 }; 162 163 struct rdma_srq_sge { 164 struct regpair addr; 165 __le32 length; 166 __le32 l_key; 167 }; 168 169 /* Rdma doorbell data for flags update */ 170 struct rdma_pwm_flags_data { 171 __le16 icid; /* internal CID */ 172 u8 agg_flags; /* aggregative flags */ 173 u8 reserved; 174 }; 175 176 /* Rdma doorbell data for SQ and RQ */ 177 struct rdma_pwm_val16_data { 178 __le16 icid; 179 __le16 value; 180 }; 181 182 union rdma_pwm_val16_data_union { 183 struct rdma_pwm_val16_data as_struct; 184 __le32 as_dword; 185 }; 186 187 /* Rdma doorbell data for CQ */ 188 struct rdma_pwm_val32_data { 189 __le16 icid; 190 u8 agg_flags; 191 u8 params; 192 #define RDMA_PWM_VAL32_DATA_AGG_CMD_MASK 0x3 193 #define RDMA_PWM_VAL32_DATA_AGG_CMD_SHIFT 0 194 #define RDMA_PWM_VAL32_DATA_BYPASS_EN_MASK 0x1 195 #define RDMA_PWM_VAL32_DATA_BYPASS_EN_SHIFT 2 196 #define RDMA_PWM_VAL32_DATA_CONN_TYPE_IS_IWARP_MASK 0x1 197 #define RDMA_PWM_VAL32_DATA_CONN_TYPE_IS_IWARP_SHIFT 3 198 #define RDMA_PWM_VAL32_DATA_SET_16B_VAL_MASK 0x1 199 #define RDMA_PWM_VAL32_DATA_SET_16B_VAL_SHIFT 4 200 #define RDMA_PWM_VAL32_DATA_RESERVED_MASK 0x7 201 #define RDMA_PWM_VAL32_DATA_RESERVED_SHIFT 5 202 __le32 value; 203 }; 204 205 /* DIF Block size options */ 206 enum rdma_dif_block_size { 207 RDMA_DIF_BLOCK_512 = 0, 208 RDMA_DIF_BLOCK_4096 = 1, 209 MAX_RDMA_DIF_BLOCK_SIZE 210 }; 211 212 /* DIF CRC initial value */ 213 enum rdma_dif_crc_seed { 214 RDMA_DIF_CRC_SEED_0000 = 0, 215 RDMA_DIF_CRC_SEED_FFFF = 1, 216 MAX_RDMA_DIF_CRC_SEED 217 }; 218 219 /* RDMA DIF Error Result Structure */ 220 struct rdma_dif_error_result { 221 __le32 error_intervals; 222 __le32 dif_error_1st_interval; 223 u8 flags; 224 #define RDMA_DIF_ERROR_RESULT_DIF_ERROR_TYPE_CRC_MASK 0x1 225 #define RDMA_DIF_ERROR_RESULT_DIF_ERROR_TYPE_CRC_SHIFT 0 226 #define RDMA_DIF_ERROR_RESULT_DIF_ERROR_TYPE_APP_TAG_MASK 0x1 227 #define RDMA_DIF_ERROR_RESULT_DIF_ERROR_TYPE_APP_TAG_SHIFT 1 228 #define RDMA_DIF_ERROR_RESULT_DIF_ERROR_TYPE_REF_TAG_MASK 0x1 229 #define RDMA_DIF_ERROR_RESULT_DIF_ERROR_TYPE_REF_TAG_SHIFT 2 230 #define RDMA_DIF_ERROR_RESULT_RESERVED0_MASK 0xF 231 #define RDMA_DIF_ERROR_RESULT_RESERVED0_SHIFT 3 232 #define RDMA_DIF_ERROR_RESULT_TOGGLE_BIT_MASK 0x1 233 #define RDMA_DIF_ERROR_RESULT_TOGGLE_BIT_SHIFT 7 234 u8 reserved1[55]; 235 }; 236 237 /* DIF IO direction */ 238 enum rdma_dif_io_direction_flg { 239 RDMA_DIF_DIR_RX = 0, 240 RDMA_DIF_DIR_TX = 1, 241 MAX_RDMA_DIF_IO_DIRECTION_FLG 242 }; 243 244 /* RDMA DIF Runt Result Structure */ 245 struct rdma_dif_runt_result { 246 __le16 guard_tag; 247 __le16 reserved[3]; 248 }; 249 250 /* Memory window type enumeration */ 251 enum rdma_mw_type { 252 RDMA_MW_TYPE_1, 253 RDMA_MW_TYPE_2A, 254 MAX_RDMA_MW_TYPE 255 }; 256 257 struct rdma_sq_atomic_wqe { 258 __le32 reserved1; 259 __le32 length; 260 __le32 xrc_srq; 261 u8 req_type; 262 u8 flags; 263 #define RDMA_SQ_ATOMIC_WQE_COMP_FLG_MASK 0x1 264 #define RDMA_SQ_ATOMIC_WQE_COMP_FLG_SHIFT 0 265 #define RDMA_SQ_ATOMIC_WQE_RD_FENCE_FLG_MASK 0x1 266 #define RDMA_SQ_ATOMIC_WQE_RD_FENCE_FLG_SHIFT 1 267 #define RDMA_SQ_ATOMIC_WQE_INV_FENCE_FLG_MASK 0x1 268 #define RDMA_SQ_ATOMIC_WQE_INV_FENCE_FLG_SHIFT 2 269 #define RDMA_SQ_ATOMIC_WQE_SE_FLG_MASK 0x1 270 #define RDMA_SQ_ATOMIC_WQE_SE_FLG_SHIFT 3 271 #define RDMA_SQ_ATOMIC_WQE_INLINE_FLG_MASK 0x1 272 #define RDMA_SQ_ATOMIC_WQE_INLINE_FLG_SHIFT 4 273 #define RDMA_SQ_ATOMIC_WQE_DIF_ON_HOST_FLG_MASK 0x1 274 #define RDMA_SQ_ATOMIC_WQE_DIF_ON_HOST_FLG_SHIFT 5 275 #define RDMA_SQ_ATOMIC_WQE_RESERVED0_MASK 0x3 276 #define RDMA_SQ_ATOMIC_WQE_RESERVED0_SHIFT 6 277 u8 wqe_size; 278 u8 prev_wqe_size; 279 struct regpair remote_va; 280 __le32 r_key; 281 __le32 reserved2; 282 struct regpair cmp_data; 283 struct regpair swap_data; 284 }; 285 286 /* First element (16 bytes) of atomic wqe */ 287 struct rdma_sq_atomic_wqe_1st { 288 __le32 reserved1; 289 __le32 length; 290 __le32 xrc_srq; 291 u8 req_type; 292 u8 flags; 293 #define RDMA_SQ_ATOMIC_WQE_1ST_COMP_FLG_MASK 0x1 294 #define RDMA_SQ_ATOMIC_WQE_1ST_COMP_FLG_SHIFT 0 295 #define RDMA_SQ_ATOMIC_WQE_1ST_RD_FENCE_FLG_MASK 0x1 296 #define RDMA_SQ_ATOMIC_WQE_1ST_RD_FENCE_FLG_SHIFT 1 297 #define RDMA_SQ_ATOMIC_WQE_1ST_INV_FENCE_FLG_MASK 0x1 298 #define RDMA_SQ_ATOMIC_WQE_1ST_INV_FENCE_FLG_SHIFT 2 299 #define RDMA_SQ_ATOMIC_WQE_1ST_SE_FLG_MASK 0x1 300 #define RDMA_SQ_ATOMIC_WQE_1ST_SE_FLG_SHIFT 3 301 #define RDMA_SQ_ATOMIC_WQE_1ST_INLINE_FLG_MASK 0x1 302 #define RDMA_SQ_ATOMIC_WQE_1ST_INLINE_FLG_SHIFT 4 303 #define RDMA_SQ_ATOMIC_WQE_1ST_RESERVED0_MASK 0x7 304 #define RDMA_SQ_ATOMIC_WQE_1ST_RESERVED0_SHIFT 5 305 u8 wqe_size; 306 u8 prev_wqe_size; 307 }; 308 309 /* Second element (16 bytes) of atomic wqe */ 310 struct rdma_sq_atomic_wqe_2nd { 311 struct regpair remote_va; 312 __le32 r_key; 313 __le32 reserved2; 314 }; 315 316 /* Third element (16 bytes) of atomic wqe */ 317 struct rdma_sq_atomic_wqe_3rd { 318 struct regpair cmp_data; 319 struct regpair swap_data; 320 }; 321 322 struct rdma_sq_bind_wqe { 323 struct regpair addr; 324 __le32 l_key; 325 u8 req_type; 326 u8 flags; 327 #define RDMA_SQ_BIND_WQE_COMP_FLG_MASK 0x1 328 #define RDMA_SQ_BIND_WQE_COMP_FLG_SHIFT 0 329 #define RDMA_SQ_BIND_WQE_RD_FENCE_FLG_MASK 0x1 330 #define RDMA_SQ_BIND_WQE_RD_FENCE_FLG_SHIFT 1 331 #define RDMA_SQ_BIND_WQE_INV_FENCE_FLG_MASK 0x1 332 #define RDMA_SQ_BIND_WQE_INV_FENCE_FLG_SHIFT 2 333 #define RDMA_SQ_BIND_WQE_SE_FLG_MASK 0x1 334 #define RDMA_SQ_BIND_WQE_SE_FLG_SHIFT 3 335 #define RDMA_SQ_BIND_WQE_INLINE_FLG_MASK 0x1 336 #define RDMA_SQ_BIND_WQE_INLINE_FLG_SHIFT 4 337 #define RDMA_SQ_BIND_WQE_RESERVED0_MASK 0x7 338 #define RDMA_SQ_BIND_WQE_RESERVED0_SHIFT 5 339 u8 wqe_size; 340 u8 prev_wqe_size; 341 u8 bind_ctrl; 342 #define RDMA_SQ_BIND_WQE_ZERO_BASED_MASK 0x1 343 #define RDMA_SQ_BIND_WQE_ZERO_BASED_SHIFT 0 344 #define RDMA_SQ_BIND_WQE_MW_TYPE_MASK 0x1 345 #define RDMA_SQ_BIND_WQE_MW_TYPE_SHIFT 1 346 #define RDMA_SQ_BIND_WQE_RESERVED1_MASK 0x3F 347 #define RDMA_SQ_BIND_WQE_RESERVED1_SHIFT 2 348 u8 access_ctrl; 349 #define RDMA_SQ_BIND_WQE_REMOTE_READ_MASK 0x1 350 #define RDMA_SQ_BIND_WQE_REMOTE_READ_SHIFT 0 351 #define RDMA_SQ_BIND_WQE_REMOTE_WRITE_MASK 0x1 352 #define RDMA_SQ_BIND_WQE_REMOTE_WRITE_SHIFT 1 353 #define RDMA_SQ_BIND_WQE_ENABLE_ATOMIC_MASK 0x1 354 #define RDMA_SQ_BIND_WQE_ENABLE_ATOMIC_SHIFT 2 355 #define RDMA_SQ_BIND_WQE_LOCAL_READ_MASK 0x1 356 #define RDMA_SQ_BIND_WQE_LOCAL_READ_SHIFT 3 357 #define RDMA_SQ_BIND_WQE_LOCAL_WRITE_MASK 0x1 358 #define RDMA_SQ_BIND_WQE_LOCAL_WRITE_SHIFT 4 359 #define RDMA_SQ_BIND_WQE_RESERVED2_MASK 0x7 360 #define RDMA_SQ_BIND_WQE_RESERVED2_SHIFT 5 361 u8 reserved3; 362 u8 length_hi; 363 __le32 length_lo; 364 __le32 parent_l_key; 365 __le32 reserved4; 366 }; 367 368 /* First element (16 bytes) of bind wqe */ 369 struct rdma_sq_bind_wqe_1st { 370 struct regpair addr; 371 __le32 l_key; 372 u8 req_type; 373 u8 flags; 374 #define RDMA_SQ_BIND_WQE_1ST_COMP_FLG_MASK 0x1 375 #define RDMA_SQ_BIND_WQE_1ST_COMP_FLG_SHIFT 0 376 #define RDMA_SQ_BIND_WQE_1ST_RD_FENCE_FLG_MASK 0x1 377 #define RDMA_SQ_BIND_WQE_1ST_RD_FENCE_FLG_SHIFT 1 378 #define RDMA_SQ_BIND_WQE_1ST_INV_FENCE_FLG_MASK 0x1 379 #define RDMA_SQ_BIND_WQE_1ST_INV_FENCE_FLG_SHIFT 2 380 #define RDMA_SQ_BIND_WQE_1ST_SE_FLG_MASK 0x1 381 #define RDMA_SQ_BIND_WQE_1ST_SE_FLG_SHIFT 3 382 #define RDMA_SQ_BIND_WQE_1ST_INLINE_FLG_MASK 0x1 383 #define RDMA_SQ_BIND_WQE_1ST_INLINE_FLG_SHIFT 4 384 #define RDMA_SQ_BIND_WQE_1ST_RESERVED0_MASK 0x7 385 #define RDMA_SQ_BIND_WQE_1ST_RESERVED0_SHIFT 5 386 u8 wqe_size; 387 u8 prev_wqe_size; 388 }; 389 390 /* Second element (16 bytes) of bind wqe */ 391 struct rdma_sq_bind_wqe_2nd { 392 u8 bind_ctrl; 393 #define RDMA_SQ_BIND_WQE_2ND_ZERO_BASED_MASK 0x1 394 #define RDMA_SQ_BIND_WQE_2ND_ZERO_BASED_SHIFT 0 395 #define RDMA_SQ_BIND_WQE_2ND_MW_TYPE_MASK 0x1 396 #define RDMA_SQ_BIND_WQE_2ND_MW_TYPE_SHIFT 1 397 #define RDMA_SQ_BIND_WQE_2ND_RESERVED1_MASK 0x3F 398 #define RDMA_SQ_BIND_WQE_2ND_RESERVED1_SHIFT 2 399 u8 access_ctrl; 400 #define RDMA_SQ_BIND_WQE_2ND_REMOTE_READ_MASK 0x1 401 #define RDMA_SQ_BIND_WQE_2ND_REMOTE_READ_SHIFT 0 402 #define RDMA_SQ_BIND_WQE_2ND_REMOTE_WRITE_MASK 0x1 403 #define RDMA_SQ_BIND_WQE_2ND_REMOTE_WRITE_SHIFT 1 404 #define RDMA_SQ_BIND_WQE_2ND_ENABLE_ATOMIC_MASK 0x1 405 #define RDMA_SQ_BIND_WQE_2ND_ENABLE_ATOMIC_SHIFT 2 406 #define RDMA_SQ_BIND_WQE_2ND_LOCAL_READ_MASK 0x1 407 #define RDMA_SQ_BIND_WQE_2ND_LOCAL_READ_SHIFT 3 408 #define RDMA_SQ_BIND_WQE_2ND_LOCAL_WRITE_MASK 0x1 409 #define RDMA_SQ_BIND_WQE_2ND_LOCAL_WRITE_SHIFT 4 410 #define RDMA_SQ_BIND_WQE_2ND_RESERVED2_MASK 0x7 411 #define RDMA_SQ_BIND_WQE_2ND_RESERVED2_SHIFT 5 412 u8 reserved3; 413 u8 length_hi; 414 __le32 length_lo; 415 __le32 parent_l_key; 416 __le32 reserved4; 417 }; 418 419 /* Structure with only the SQ WQE common 420 * fields. Size is of one SQ element (16B) 421 */ 422 struct rdma_sq_common_wqe { 423 __le32 reserved1[3]; 424 u8 req_type; 425 u8 flags; 426 #define RDMA_SQ_COMMON_WQE_COMP_FLG_MASK 0x1 427 #define RDMA_SQ_COMMON_WQE_COMP_FLG_SHIFT 0 428 #define RDMA_SQ_COMMON_WQE_RD_FENCE_FLG_MASK 0x1 429 #define RDMA_SQ_COMMON_WQE_RD_FENCE_FLG_SHIFT 1 430 #define RDMA_SQ_COMMON_WQE_INV_FENCE_FLG_MASK 0x1 431 #define RDMA_SQ_COMMON_WQE_INV_FENCE_FLG_SHIFT 2 432 #define RDMA_SQ_COMMON_WQE_SE_FLG_MASK 0x1 433 #define RDMA_SQ_COMMON_WQE_SE_FLG_SHIFT 3 434 #define RDMA_SQ_COMMON_WQE_INLINE_FLG_MASK 0x1 435 #define RDMA_SQ_COMMON_WQE_INLINE_FLG_SHIFT 4 436 #define RDMA_SQ_COMMON_WQE_RESERVED0_MASK 0x7 437 #define RDMA_SQ_COMMON_WQE_RESERVED0_SHIFT 5 438 u8 wqe_size; 439 u8 prev_wqe_size; 440 }; 441 442 struct rdma_sq_fmr_wqe { 443 struct regpair addr; 444 __le32 l_key; 445 u8 req_type; 446 u8 flags; 447 #define RDMA_SQ_FMR_WQE_COMP_FLG_MASK 0x1 448 #define RDMA_SQ_FMR_WQE_COMP_FLG_SHIFT 0 449 #define RDMA_SQ_FMR_WQE_RD_FENCE_FLG_MASK 0x1 450 #define RDMA_SQ_FMR_WQE_RD_FENCE_FLG_SHIFT 1 451 #define RDMA_SQ_FMR_WQE_INV_FENCE_FLG_MASK 0x1 452 #define RDMA_SQ_FMR_WQE_INV_FENCE_FLG_SHIFT 2 453 #define RDMA_SQ_FMR_WQE_SE_FLG_MASK 0x1 454 #define RDMA_SQ_FMR_WQE_SE_FLG_SHIFT 3 455 #define RDMA_SQ_FMR_WQE_INLINE_FLG_MASK 0x1 456 #define RDMA_SQ_FMR_WQE_INLINE_FLG_SHIFT 4 457 #define RDMA_SQ_FMR_WQE_DIF_ON_HOST_FLG_MASK 0x1 458 #define RDMA_SQ_FMR_WQE_DIF_ON_HOST_FLG_SHIFT 5 459 #define RDMA_SQ_FMR_WQE_RESERVED0_MASK 0x3 460 #define RDMA_SQ_FMR_WQE_RESERVED0_SHIFT 6 461 u8 wqe_size; 462 u8 prev_wqe_size; 463 u8 fmr_ctrl; 464 #define RDMA_SQ_FMR_WQE_PAGE_SIZE_LOG_MASK 0x1F 465 #define RDMA_SQ_FMR_WQE_PAGE_SIZE_LOG_SHIFT 0 466 #define RDMA_SQ_FMR_WQE_ZERO_BASED_MASK 0x1 467 #define RDMA_SQ_FMR_WQE_ZERO_BASED_SHIFT 5 468 #define RDMA_SQ_FMR_WQE_BIND_EN_MASK 0x1 469 #define RDMA_SQ_FMR_WQE_BIND_EN_SHIFT 6 470 #define RDMA_SQ_FMR_WQE_RESERVED1_MASK 0x1 471 #define RDMA_SQ_FMR_WQE_RESERVED1_SHIFT 7 472 u8 access_ctrl; 473 #define RDMA_SQ_FMR_WQE_REMOTE_READ_MASK 0x1 474 #define RDMA_SQ_FMR_WQE_REMOTE_READ_SHIFT 0 475 #define RDMA_SQ_FMR_WQE_REMOTE_WRITE_MASK 0x1 476 #define RDMA_SQ_FMR_WQE_REMOTE_WRITE_SHIFT 1 477 #define RDMA_SQ_FMR_WQE_ENABLE_ATOMIC_MASK 0x1 478 #define RDMA_SQ_FMR_WQE_ENABLE_ATOMIC_SHIFT 2 479 #define RDMA_SQ_FMR_WQE_LOCAL_READ_MASK 0x1 480 #define RDMA_SQ_FMR_WQE_LOCAL_READ_SHIFT 3 481 #define RDMA_SQ_FMR_WQE_LOCAL_WRITE_MASK 0x1 482 #define RDMA_SQ_FMR_WQE_LOCAL_WRITE_SHIFT 4 483 #define RDMA_SQ_FMR_WQE_RESERVED2_MASK 0x7 484 #define RDMA_SQ_FMR_WQE_RESERVED2_SHIFT 5 485 u8 reserved3; 486 u8 length_hi; 487 __le32 length_lo; 488 struct regpair pbl_addr; 489 __le32 dif_base_ref_tag; 490 __le16 dif_app_tag; 491 __le16 dif_app_tag_mask; 492 __le16 dif_runt_crc_value; 493 __le16 dif_flags; 494 #define RDMA_SQ_FMR_WQE_DIF_IO_DIRECTION_FLG_MASK 0x1 495 #define RDMA_SQ_FMR_WQE_DIF_IO_DIRECTION_FLG_SHIFT 0 496 #define RDMA_SQ_FMR_WQE_DIF_BLOCK_SIZE_MASK 0x1 497 #define RDMA_SQ_FMR_WQE_DIF_BLOCK_SIZE_SHIFT 1 498 #define RDMA_SQ_FMR_WQE_DIF_RUNT_VALID_FLG_MASK 0x1 499 #define RDMA_SQ_FMR_WQE_DIF_RUNT_VALID_FLG_SHIFT 2 500 #define RDMA_SQ_FMR_WQE_DIF_VALIDATE_CRC_GUARD_MASK 0x1 501 #define RDMA_SQ_FMR_WQE_DIF_VALIDATE_CRC_GUARD_SHIFT 3 502 #define RDMA_SQ_FMR_WQE_DIF_VALIDATE_REF_TAG_MASK 0x1 503 #define RDMA_SQ_FMR_WQE_DIF_VALIDATE_REF_TAG_SHIFT 4 504 #define RDMA_SQ_FMR_WQE_DIF_VALIDATE_APP_TAG_MASK 0x1 505 #define RDMA_SQ_FMR_WQE_DIF_VALIDATE_APP_TAG_SHIFT 5 506 #define RDMA_SQ_FMR_WQE_DIF_CRC_SEED_MASK 0x1 507 #define RDMA_SQ_FMR_WQE_DIF_CRC_SEED_SHIFT 6 508 #define RDMA_SQ_FMR_WQE_DIF_RX_REF_TAG_CONST_MASK 0x1 509 #define RDMA_SQ_FMR_WQE_DIF_RX_REF_TAG_CONST_SHIFT 7 510 #define RDMA_SQ_FMR_WQE_RESERVED4_MASK 0xFF 511 #define RDMA_SQ_FMR_WQE_RESERVED4_SHIFT 8 512 __le32 reserved5; 513 }; 514 515 /* First element (16 bytes) of fmr wqe */ 516 struct rdma_sq_fmr_wqe_1st { 517 struct regpair addr; 518 __le32 l_key; 519 u8 req_type; 520 u8 flags; 521 #define RDMA_SQ_FMR_WQE_1ST_COMP_FLG_MASK 0x1 522 #define RDMA_SQ_FMR_WQE_1ST_COMP_FLG_SHIFT 0 523 #define RDMA_SQ_FMR_WQE_1ST_RD_FENCE_FLG_MASK 0x1 524 #define RDMA_SQ_FMR_WQE_1ST_RD_FENCE_FLG_SHIFT 1 525 #define RDMA_SQ_FMR_WQE_1ST_INV_FENCE_FLG_MASK 0x1 526 #define RDMA_SQ_FMR_WQE_1ST_INV_FENCE_FLG_SHIFT 2 527 #define RDMA_SQ_FMR_WQE_1ST_SE_FLG_MASK 0x1 528 #define RDMA_SQ_FMR_WQE_1ST_SE_FLG_SHIFT 3 529 #define RDMA_SQ_FMR_WQE_1ST_INLINE_FLG_MASK 0x1 530 #define RDMA_SQ_FMR_WQE_1ST_INLINE_FLG_SHIFT 4 531 #define RDMA_SQ_FMR_WQE_1ST_DIF_ON_HOST_FLG_MASK 0x1 532 #define RDMA_SQ_FMR_WQE_1ST_DIF_ON_HOST_FLG_SHIFT 5 533 #define RDMA_SQ_FMR_WQE_1ST_RESERVED0_MASK 0x3 534 #define RDMA_SQ_FMR_WQE_1ST_RESERVED0_SHIFT 6 535 u8 wqe_size; 536 u8 prev_wqe_size; 537 }; 538 539 /* Second element (16 bytes) of fmr wqe */ 540 struct rdma_sq_fmr_wqe_2nd { 541 u8 fmr_ctrl; 542 #define RDMA_SQ_FMR_WQE_2ND_PAGE_SIZE_LOG_MASK 0x1F 543 #define RDMA_SQ_FMR_WQE_2ND_PAGE_SIZE_LOG_SHIFT 0 544 #define RDMA_SQ_FMR_WQE_2ND_ZERO_BASED_MASK 0x1 545 #define RDMA_SQ_FMR_WQE_2ND_ZERO_BASED_SHIFT 5 546 #define RDMA_SQ_FMR_WQE_2ND_BIND_EN_MASK 0x1 547 #define RDMA_SQ_FMR_WQE_2ND_BIND_EN_SHIFT 6 548 #define RDMA_SQ_FMR_WQE_2ND_RESERVED1_MASK 0x1 549 #define RDMA_SQ_FMR_WQE_2ND_RESERVED1_SHIFT 7 550 u8 access_ctrl; 551 #define RDMA_SQ_FMR_WQE_2ND_REMOTE_READ_MASK 0x1 552 #define RDMA_SQ_FMR_WQE_2ND_REMOTE_READ_SHIFT 0 553 #define RDMA_SQ_FMR_WQE_2ND_REMOTE_WRITE_MASK 0x1 554 #define RDMA_SQ_FMR_WQE_2ND_REMOTE_WRITE_SHIFT 1 555 #define RDMA_SQ_FMR_WQE_2ND_ENABLE_ATOMIC_MASK 0x1 556 #define RDMA_SQ_FMR_WQE_2ND_ENABLE_ATOMIC_SHIFT 2 557 #define RDMA_SQ_FMR_WQE_2ND_LOCAL_READ_MASK 0x1 558 #define RDMA_SQ_FMR_WQE_2ND_LOCAL_READ_SHIFT 3 559 #define RDMA_SQ_FMR_WQE_2ND_LOCAL_WRITE_MASK 0x1 560 #define RDMA_SQ_FMR_WQE_2ND_LOCAL_WRITE_SHIFT 4 561 #define RDMA_SQ_FMR_WQE_2ND_RESERVED2_MASK 0x7 562 #define RDMA_SQ_FMR_WQE_2ND_RESERVED2_SHIFT 5 563 u8 reserved3; 564 u8 length_hi; 565 __le32 length_lo; 566 struct regpair pbl_addr; 567 }; 568 569 /* Third element (16 bytes) of fmr wqe */ 570 struct rdma_sq_fmr_wqe_3rd { 571 __le32 dif_base_ref_tag; 572 __le16 dif_app_tag; 573 __le16 dif_app_tag_mask; 574 __le16 dif_runt_crc_value; 575 __le16 dif_flags; 576 #define RDMA_SQ_FMR_WQE_3RD_DIF_IO_DIRECTION_FLG_MASK 0x1 577 #define RDMA_SQ_FMR_WQE_3RD_DIF_IO_DIRECTION_FLG_SHIFT 0 578 #define RDMA_SQ_FMR_WQE_3RD_DIF_BLOCK_SIZE_MASK 0x1 579 #define RDMA_SQ_FMR_WQE_3RD_DIF_BLOCK_SIZE_SHIFT 1 580 #define RDMA_SQ_FMR_WQE_3RD_DIF_RUNT_VALID_FLG_MASK 0x1 581 #define RDMA_SQ_FMR_WQE_3RD_DIF_RUNT_VALID_FLG_SHIFT 2 582 #define RDMA_SQ_FMR_WQE_3RD_DIF_VALIDATE_CRC_GUARD_MASK 0x1 583 #define RDMA_SQ_FMR_WQE_3RD_DIF_VALIDATE_CRC_GUARD_SHIFT 3 584 #define RDMA_SQ_FMR_WQE_3RD_DIF_VALIDATE_REF_TAG_MASK 0x1 585 #define RDMA_SQ_FMR_WQE_3RD_DIF_VALIDATE_REF_TAG_SHIFT 4 586 #define RDMA_SQ_FMR_WQE_3RD_DIF_VALIDATE_APP_TAG_MASK 0x1 587 #define RDMA_SQ_FMR_WQE_3RD_DIF_VALIDATE_APP_TAG_SHIFT 5 588 #define RDMA_SQ_FMR_WQE_3RD_DIF_CRC_SEED_MASK 0x1 589 #define RDMA_SQ_FMR_WQE_3RD_DIF_CRC_SEED_SHIFT 6 590 #define RDMA_SQ_FMR_WQE_3RD_DIF_RX_REF_TAG_CONST_MASK 0x1 591 #define RDMA_SQ_FMR_WQE_3RD_DIF_RX_REF_TAG_CONST_SHIFT 7 592 #define RDMA_SQ_FMR_WQE_3RD_RESERVED4_MASK 0xFF 593 #define RDMA_SQ_FMR_WQE_RESERVED4_SHIFT 8 594 __le32 reserved5; 595 }; 596 597 struct rdma_sq_local_inv_wqe { 598 struct regpair reserved; 599 __le32 inv_l_key; 600 u8 req_type; 601 u8 flags; 602 #define RDMA_SQ_LOCAL_INV_WQE_COMP_FLG_MASK 0x1 603 #define RDMA_SQ_LOCAL_INV_WQE_COMP_FLG_SHIFT 0 604 #define RDMA_SQ_LOCAL_INV_WQE_RD_FENCE_FLG_MASK 0x1 605 #define RDMA_SQ_LOCAL_INV_WQE_RD_FENCE_FLG_SHIFT 1 606 #define RDMA_SQ_LOCAL_INV_WQE_INV_FENCE_FLG_MASK 0x1 607 #define RDMA_SQ_LOCAL_INV_WQE_INV_FENCE_FLG_SHIFT 2 608 #define RDMA_SQ_LOCAL_INV_WQE_SE_FLG_MASK 0x1 609 #define RDMA_SQ_LOCAL_INV_WQE_SE_FLG_SHIFT 3 610 #define RDMA_SQ_LOCAL_INV_WQE_INLINE_FLG_MASK 0x1 611 #define RDMA_SQ_LOCAL_INV_WQE_INLINE_FLG_SHIFT 4 612 #define RDMA_SQ_LOCAL_INV_WQE_DIF_ON_HOST_FLG_MASK 0x1 613 #define RDMA_SQ_LOCAL_INV_WQE_DIF_ON_HOST_FLG_SHIFT 5 614 #define RDMA_SQ_LOCAL_INV_WQE_RESERVED0_MASK 0x3 615 #define RDMA_SQ_LOCAL_INV_WQE_RESERVED0_SHIFT 6 616 u8 wqe_size; 617 u8 prev_wqe_size; 618 }; 619 620 struct rdma_sq_rdma_wqe { 621 __le32 imm_data; 622 __le32 length; 623 __le32 xrc_srq; 624 u8 req_type; 625 u8 flags; 626 #define RDMA_SQ_RDMA_WQE_COMP_FLG_MASK 0x1 627 #define RDMA_SQ_RDMA_WQE_COMP_FLG_SHIFT 0 628 #define RDMA_SQ_RDMA_WQE_RD_FENCE_FLG_MASK 0x1 629 #define RDMA_SQ_RDMA_WQE_RD_FENCE_FLG_SHIFT 1 630 #define RDMA_SQ_RDMA_WQE_INV_FENCE_FLG_MASK 0x1 631 #define RDMA_SQ_RDMA_WQE_INV_FENCE_FLG_SHIFT 2 632 #define RDMA_SQ_RDMA_WQE_SE_FLG_MASK 0x1 633 #define RDMA_SQ_RDMA_WQE_SE_FLG_SHIFT 3 634 #define RDMA_SQ_RDMA_WQE_INLINE_FLG_MASK 0x1 635 #define RDMA_SQ_RDMA_WQE_INLINE_FLG_SHIFT 4 636 #define RDMA_SQ_RDMA_WQE_DIF_ON_HOST_FLG_MASK 0x1 637 #define RDMA_SQ_RDMA_WQE_DIF_ON_HOST_FLG_SHIFT 5 638 #define RDMA_SQ_RDMA_WQE_READ_INV_FLG_MASK 0x1 639 #define RDMA_SQ_RDMA_WQE_READ_INV_FLG_SHIFT 6 640 #define RDMA_SQ_RDMA_WQE_RESERVED0_MASK 0x1 641 #define RDMA_SQ_RDMA_WQE_RESERVED0_SHIFT 7 642 u8 wqe_size; 643 u8 prev_wqe_size; 644 struct regpair remote_va; 645 __le32 r_key; 646 u8 dif_flags; 647 #define RDMA_SQ_RDMA_WQE_DIF_BLOCK_SIZE_MASK 0x1 648 #define RDMA_SQ_RDMA_WQE_DIF_BLOCK_SIZE_SHIFT 0 649 #define RDMA_SQ_RDMA_WQE_DIF_FIRST_RDMA_IN_IO_FLG_MASK 0x1 650 #define RDMA_SQ_RDMA_WQE_DIF_FIRST_RDMA_IN_IO_FLG_SHIFT 1 651 #define RDMA_SQ_RDMA_WQE_DIF_LAST_RDMA_IN_IO_FLG_MASK 0x1 652 #define RDMA_SQ_RDMA_WQE_DIF_LAST_RDMA_IN_IO_FLG_SHIFT 2 653 #define RDMA_SQ_RDMA_WQE_RESERVED1_MASK 0x1F 654 #define RDMA_SQ_RDMA_WQE_RESERVED1_SHIFT 3 655 u8 reserved2[3]; 656 }; 657 658 /* First element (16 bytes) of rdma wqe */ 659 struct rdma_sq_rdma_wqe_1st { 660 __le32 imm_data; 661 __le32 length; 662 __le32 xrc_srq; 663 u8 req_type; 664 u8 flags; 665 #define RDMA_SQ_RDMA_WQE_1ST_COMP_FLG_MASK 0x1 666 #define RDMA_SQ_RDMA_WQE_1ST_COMP_FLG_SHIFT 0 667 #define RDMA_SQ_RDMA_WQE_1ST_RD_FENCE_FLG_MASK 0x1 668 #define RDMA_SQ_RDMA_WQE_1ST_RD_FENCE_FLG_SHIFT 1 669 #define RDMA_SQ_RDMA_WQE_1ST_INV_FENCE_FLG_MASK 0x1 670 #define RDMA_SQ_RDMA_WQE_1ST_INV_FENCE_FLG_SHIFT 2 671 #define RDMA_SQ_RDMA_WQE_1ST_SE_FLG_MASK 0x1 672 #define RDMA_SQ_RDMA_WQE_1ST_SE_FLG_SHIFT 3 673 #define RDMA_SQ_RDMA_WQE_1ST_INLINE_FLG_MASK 0x1 674 #define RDMA_SQ_RDMA_WQE_1ST_INLINE_FLG_SHIFT 4 675 #define RDMA_SQ_RDMA_WQE_1ST_DIF_ON_HOST_FLG_MASK 0x1 676 #define RDMA_SQ_RDMA_WQE_1ST_DIF_ON_HOST_FLG_SHIFT 5 677 #define RDMA_SQ_RDMA_WQE_1ST_READ_INV_FLG_MASK 0x1 678 #define RDMA_SQ_RDMA_WQE_1ST_READ_INV_FLG_SHIFT 6 679 #define RDMA_SQ_RDMA_WQE_1ST_RESERVED0_MASK 0x1 680 #define RDMA_SQ_RDMA_WQE_1ST_RESERVED0_SHIFT 7 681 u8 wqe_size; 682 u8 prev_wqe_size; 683 }; 684 685 /* Second element (16 bytes) of rdma wqe */ 686 struct rdma_sq_rdma_wqe_2nd { 687 struct regpair remote_va; 688 __le32 r_key; 689 u8 dif_flags; 690 #define RDMA_SQ_RDMA_WQE_2ND_DIF_BLOCK_SIZE_MASK 0x1 691 #define RDMA_SQ_RDMA_WQE_2ND_DIF_BLOCK_SIZE_SHIFT 0 692 #define RDMA_SQ_RDMA_WQE_2ND_DIF_FIRST_SEGMENT_FLG_MASK 0x1 693 #define RDMA_SQ_RDMA_WQE_2ND_DIF_FIRST_SEGMENT_FLG_SHIFT 1 694 #define RDMA_SQ_RDMA_WQE_2ND_DIF_LAST_SEGMENT_FLG_MASK 0x1 695 #define RDMA_SQ_RDMA_WQE_2ND_DIF_LAST_SEGMENT_FLG_SHIFT 2 696 #define RDMA_SQ_RDMA_WQE_2ND_RESERVED1_MASK 0x1F 697 #define RDMA_SQ_RDMA_WQE_2ND_RESERVED1_SHIFT 3 698 u8 reserved2[3]; 699 }; 700 701 /* SQ WQE req type enumeration */ 702 enum rdma_sq_req_type { 703 RDMA_SQ_REQ_TYPE_SEND, 704 RDMA_SQ_REQ_TYPE_SEND_WITH_IMM, 705 RDMA_SQ_REQ_TYPE_SEND_WITH_INVALIDATE, 706 RDMA_SQ_REQ_TYPE_RDMA_WR, 707 RDMA_SQ_REQ_TYPE_RDMA_WR_WITH_IMM, 708 RDMA_SQ_REQ_TYPE_RDMA_RD, 709 RDMA_SQ_REQ_TYPE_ATOMIC_CMP_AND_SWAP, 710 RDMA_SQ_REQ_TYPE_ATOMIC_ADD, 711 RDMA_SQ_REQ_TYPE_LOCAL_INVALIDATE, 712 RDMA_SQ_REQ_TYPE_FAST_MR, 713 RDMA_SQ_REQ_TYPE_BIND, 714 RDMA_SQ_REQ_TYPE_INVALID, 715 MAX_RDMA_SQ_REQ_TYPE 716 }; 717 718 struct rdma_sq_send_wqe { 719 __le32 inv_key_or_imm_data; 720 __le32 length; 721 __le32 xrc_srq; 722 u8 req_type; 723 u8 flags; 724 #define RDMA_SQ_SEND_WQE_COMP_FLG_MASK 0x1 725 #define RDMA_SQ_SEND_WQE_COMP_FLG_SHIFT 0 726 #define RDMA_SQ_SEND_WQE_RD_FENCE_FLG_MASK 0x1 727 #define RDMA_SQ_SEND_WQE_RD_FENCE_FLG_SHIFT 1 728 #define RDMA_SQ_SEND_WQE_INV_FENCE_FLG_MASK 0x1 729 #define RDMA_SQ_SEND_WQE_INV_FENCE_FLG_SHIFT 2 730 #define RDMA_SQ_SEND_WQE_SE_FLG_MASK 0x1 731 #define RDMA_SQ_SEND_WQE_SE_FLG_SHIFT 3 732 #define RDMA_SQ_SEND_WQE_INLINE_FLG_MASK 0x1 733 #define RDMA_SQ_SEND_WQE_INLINE_FLG_SHIFT 4 734 #define RDMA_SQ_SEND_WQE_DIF_ON_HOST_FLG_MASK 0x1 735 #define RDMA_SQ_SEND_WQE_DIF_ON_HOST_FLG_SHIFT 5 736 #define RDMA_SQ_SEND_WQE_RESERVED0_MASK 0x3 737 #define RDMA_SQ_SEND_WQE_RESERVED0_SHIFT 6 738 u8 wqe_size; 739 u8 prev_wqe_size; 740 __le32 reserved1[4]; 741 }; 742 743 struct rdma_sq_send_wqe_1st { 744 __le32 inv_key_or_imm_data; 745 __le32 length; 746 __le32 xrc_srq; 747 u8 req_type; 748 u8 flags; 749 #define RDMA_SQ_SEND_WQE_1ST_COMP_FLG_MASK 0x1 750 #define RDMA_SQ_SEND_WQE_1ST_COMP_FLG_SHIFT 0 751 #define RDMA_SQ_SEND_WQE_1ST_RD_FENCE_FLG_MASK 0x1 752 #define RDMA_SQ_SEND_WQE_1ST_RD_FENCE_FLG_SHIFT 1 753 #define RDMA_SQ_SEND_WQE_1ST_INV_FENCE_FLG_MASK 0x1 754 #define RDMA_SQ_SEND_WQE_1ST_INV_FENCE_FLG_SHIFT 2 755 #define RDMA_SQ_SEND_WQE_1ST_SE_FLG_MASK 0x1 756 #define RDMA_SQ_SEND_WQE_1ST_SE_FLG_SHIFT 3 757 #define RDMA_SQ_SEND_WQE_1ST_INLINE_FLG_MASK 0x1 758 #define RDMA_SQ_SEND_WQE_1ST_INLINE_FLG_SHIFT 4 759 #define RDMA_SQ_SEND_WQE_1ST_RESERVED0_MASK 0x7 760 #define RDMA_SQ_SEND_WQE_1ST_RESERVED0_SHIFT 5 761 u8 wqe_size; 762 u8 prev_wqe_size; 763 }; 764 765 struct rdma_sq_send_wqe_2st { 766 __le32 reserved1[4]; 767 }; 768 769 #endif /* __QED_HSI_RDMA__ */ 770