1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ 3 #define _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ 4 5 #include <asm-generic/5level-fixup.h> 6 7 #ifndef __ASSEMBLY__ 8 #include <linux/mmdebug.h> 9 #include <linux/bug.h> 10 #endif 11 12 /* 13 * Common bits between hash and Radix page table 14 */ 15 #define _PAGE_BIT_SWAP_TYPE 0 16 17 #define _PAGE_NA 0 18 #define _PAGE_RO 0 19 #define _PAGE_USER 0 20 21 #define _PAGE_EXEC 0x00001 /* execute permission */ 22 #define _PAGE_WRITE 0x00002 /* write access allowed */ 23 #define _PAGE_READ 0x00004 /* read access allowed */ 24 #define _PAGE_RW (_PAGE_READ | _PAGE_WRITE) 25 #define _PAGE_RWX (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC) 26 #define _PAGE_PRIVILEGED 0x00008 /* kernel access only */ 27 #define _PAGE_SAO 0x00010 /* Strong access order */ 28 #define _PAGE_NON_IDEMPOTENT 0x00020 /* non idempotent memory */ 29 #define _PAGE_TOLERANT 0x00030 /* tolerant memory, cache inhibited */ 30 #define _PAGE_DIRTY 0x00080 /* C: page changed */ 31 #define _PAGE_ACCESSED 0x00100 /* R: page referenced */ 32 /* 33 * Software bits 34 */ 35 #define _RPAGE_SW0 0x2000000000000000UL 36 #define _RPAGE_SW1 0x00800 37 #define _RPAGE_SW2 0x00400 38 #define _RPAGE_SW3 0x00200 39 #define _RPAGE_RSV1 0x1000000000000000UL 40 #define _RPAGE_RSV2 0x0800000000000000UL 41 #define _RPAGE_RSV3 0x0400000000000000UL 42 #define _RPAGE_RSV4 0x0200000000000000UL 43 #define _RPAGE_RSV5 0x00040UL 44 45 #define _PAGE_PTE 0x4000000000000000UL /* distinguishes PTEs from pointers */ 46 #define _PAGE_PRESENT 0x8000000000000000UL /* pte contains a translation */ 47 48 /* 49 * Top and bottom bits of RPN which can be used by hash 50 * translation mode, because we expect them to be zero 51 * otherwise. 52 */ 53 #define _RPAGE_RPN0 0x01000 54 #define _RPAGE_RPN1 0x02000 55 #define _RPAGE_RPN44 0x0100000000000000UL 56 #define _RPAGE_RPN43 0x0080000000000000UL 57 #define _RPAGE_RPN42 0x0040000000000000UL 58 #define _RPAGE_RPN41 0x0020000000000000UL 59 60 /* Max physical address bit as per radix table */ 61 #define _RPAGE_PA_MAX 57 62 63 /* 64 * Max physical address bit we will use for now. 65 * 66 * This is mostly a hardware limitation and for now Power9 has 67 * a 51 bit limit. 68 * 69 * This is different from the number of physical bit required to address 70 * the last byte of memory. That is defined by MAX_PHYSMEM_BITS. 71 * MAX_PHYSMEM_BITS is a linux limitation imposed by the maximum 72 * number of sections we can support (SECTIONS_SHIFT). 73 * 74 * This is different from Radix page table limitation above and 75 * should always be less than that. The limit is done such that 76 * we can overload the bits between _RPAGE_PA_MAX and _PAGE_PA_MAX 77 * for hash linux page table specific bits. 78 * 79 * In order to be compatible with future hardware generations we keep 80 * some offsets and limit this for now to 53 81 */ 82 #define _PAGE_PA_MAX 53 83 84 #define _PAGE_SOFT_DIRTY _RPAGE_SW3 /* software: software dirty tracking */ 85 #define _PAGE_SPECIAL _RPAGE_SW2 /* software: special page */ 86 #define _PAGE_DEVMAP _RPAGE_SW1 /* software: ZONE_DEVICE page */ 87 #define __HAVE_ARCH_PTE_DEVMAP 88 89 /* 90 * Drivers request for cache inhibited pte mapping using _PAGE_NO_CACHE 91 * Instead of fixing all of them, add an alternate define which 92 * maps CI pte mapping. 93 */ 94 #define _PAGE_NO_CACHE _PAGE_TOLERANT 95 /* 96 * We support _RPAGE_PA_MAX bit real address in pte. On the linux side 97 * we are limited by _PAGE_PA_MAX. Clear everything above _PAGE_PA_MAX 98 * and every thing below PAGE_SHIFT; 99 */ 100 #define PTE_RPN_MASK (((1UL << _PAGE_PA_MAX) - 1) & (PAGE_MASK)) 101 /* 102 * set of bits not changed in pmd_modify. Even though we have hash specific bits 103 * in here, on radix we expect them to be zero. 104 */ 105 #define _HPAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ 106 _PAGE_ACCESSED | H_PAGE_THP_HUGE | _PAGE_PTE | \ 107 _PAGE_SOFT_DIRTY) 108 /* 109 * user access blocked by key 110 */ 111 #define _PAGE_KERNEL_RW (_PAGE_PRIVILEGED | _PAGE_RW | _PAGE_DIRTY) 112 #define _PAGE_KERNEL_RO (_PAGE_PRIVILEGED | _PAGE_READ) 113 #define _PAGE_KERNEL_RWX (_PAGE_PRIVILEGED | _PAGE_DIRTY | \ 114 _PAGE_RW | _PAGE_EXEC) 115 /* 116 * No page size encoding in the linux PTE 117 */ 118 #define _PAGE_PSIZE 0 119 /* 120 * _PAGE_CHG_MASK masks of bits that are to be preserved across 121 * pgprot changes 122 */ 123 #define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ 124 _PAGE_ACCESSED | _PAGE_SPECIAL | _PAGE_PTE | \ 125 _PAGE_SOFT_DIRTY) 126 127 #define H_PTE_PKEY (H_PTE_PKEY_BIT0 | H_PTE_PKEY_BIT1 | H_PTE_PKEY_BIT2 | \ 128 H_PTE_PKEY_BIT3 | H_PTE_PKEY_BIT4) 129 /* 130 * Mask of bits returned by pte_pgprot() 131 */ 132 #define PAGE_PROT_BITS (_PAGE_SAO | _PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT | \ 133 H_PAGE_4K_PFN | _PAGE_PRIVILEGED | _PAGE_ACCESSED | \ 134 _PAGE_READ | _PAGE_WRITE | _PAGE_DIRTY | _PAGE_EXEC | \ 135 _PAGE_SOFT_DIRTY | H_PTE_PKEY) 136 /* 137 * We define 2 sets of base prot bits, one for basic pages (ie, 138 * cacheable kernel and user pages) and one for non cacheable 139 * pages. We always set _PAGE_COHERENT when SMP is enabled or 140 * the processor might need it for DMA coherency. 141 */ 142 #define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_PSIZE) 143 #define _PAGE_BASE (_PAGE_BASE_NC) 144 145 /* Permission masks used to generate the __P and __S table, 146 * 147 * Note:__pgprot is defined in arch/powerpc/include/asm/page.h 148 * 149 * Write permissions imply read permissions for now (we could make write-only 150 * pages on BookE but we don't bother for now). Execute permission control is 151 * possible on platforms that define _PAGE_EXEC 152 * 153 * Note due to the way vm flags are laid out, the bits are XWR 154 */ 155 #define PAGE_NONE __pgprot(_PAGE_BASE | _PAGE_PRIVILEGED) 156 #define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_RW) 157 #define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_EXEC) 158 #define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_READ) 159 #define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) 160 #define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_READ) 161 #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) 162 163 #define __P000 PAGE_NONE 164 #define __P001 PAGE_READONLY 165 #define __P010 PAGE_COPY 166 #define __P011 PAGE_COPY 167 #define __P100 PAGE_READONLY_X 168 #define __P101 PAGE_READONLY_X 169 #define __P110 PAGE_COPY_X 170 #define __P111 PAGE_COPY_X 171 172 #define __S000 PAGE_NONE 173 #define __S001 PAGE_READONLY 174 #define __S010 PAGE_SHARED 175 #define __S011 PAGE_SHARED 176 #define __S100 PAGE_READONLY_X 177 #define __S101 PAGE_READONLY_X 178 #define __S110 PAGE_SHARED_X 179 #define __S111 PAGE_SHARED_X 180 181 /* Permission masks used for kernel mappings */ 182 #define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW) 183 #define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \ 184 _PAGE_TOLERANT) 185 #define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \ 186 _PAGE_NON_IDEMPOTENT) 187 #define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX) 188 #define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO) 189 #define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX) 190 191 /* 192 * Protection used for kernel text. We want the debuggers to be able to 193 * set breakpoints anywhere, so don't write protect the kernel text 194 * on platforms where such control is possible. 195 */ 196 #if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) || \ 197 defined(CONFIG_KPROBES) || defined(CONFIG_DYNAMIC_FTRACE) 198 #define PAGE_KERNEL_TEXT PAGE_KERNEL_X 199 #else 200 #define PAGE_KERNEL_TEXT PAGE_KERNEL_ROX 201 #endif 202 203 /* Make modules code happy. We don't set RO yet */ 204 #define PAGE_KERNEL_EXEC PAGE_KERNEL_X 205 #define PAGE_AGP (PAGE_KERNEL_NC) 206 207 #ifndef __ASSEMBLY__ 208 /* 209 * page table defines 210 */ 211 extern unsigned long __pte_index_size; 212 extern unsigned long __pmd_index_size; 213 extern unsigned long __pud_index_size; 214 extern unsigned long __pgd_index_size; 215 extern unsigned long __pmd_cache_index; 216 extern unsigned long __pud_cache_index; 217 #define PTE_INDEX_SIZE __pte_index_size 218 #define PMD_INDEX_SIZE __pmd_index_size 219 #define PUD_INDEX_SIZE __pud_index_size 220 #define PGD_INDEX_SIZE __pgd_index_size 221 #define PMD_CACHE_INDEX __pmd_cache_index 222 #define PUD_CACHE_INDEX __pud_cache_index 223 /* 224 * Because of use of pte fragments and THP, size of page table 225 * are not always derived out of index size above. 226 */ 227 extern unsigned long __pte_table_size; 228 extern unsigned long __pmd_table_size; 229 extern unsigned long __pud_table_size; 230 extern unsigned long __pgd_table_size; 231 #define PTE_TABLE_SIZE __pte_table_size 232 #define PMD_TABLE_SIZE __pmd_table_size 233 #define PUD_TABLE_SIZE __pud_table_size 234 #define PGD_TABLE_SIZE __pgd_table_size 235 236 extern unsigned long __pmd_val_bits; 237 extern unsigned long __pud_val_bits; 238 extern unsigned long __pgd_val_bits; 239 #define PMD_VAL_BITS __pmd_val_bits 240 #define PUD_VAL_BITS __pud_val_bits 241 #define PGD_VAL_BITS __pgd_val_bits 242 243 extern unsigned long __pte_frag_nr; 244 #define PTE_FRAG_NR __pte_frag_nr 245 extern unsigned long __pte_frag_size_shift; 246 #define PTE_FRAG_SIZE_SHIFT __pte_frag_size_shift 247 #define PTE_FRAG_SIZE (1UL << PTE_FRAG_SIZE_SHIFT) 248 249 #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE) 250 #define PTRS_PER_PMD (1 << PMD_INDEX_SIZE) 251 #define PTRS_PER_PUD (1 << PUD_INDEX_SIZE) 252 #define PTRS_PER_PGD (1 << PGD_INDEX_SIZE) 253 254 /* PMD_SHIFT determines what a second-level page table entry can map */ 255 #define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE) 256 #define PMD_SIZE (1UL << PMD_SHIFT) 257 #define PMD_MASK (~(PMD_SIZE-1)) 258 259 /* PUD_SHIFT determines what a third-level page table entry can map */ 260 #define PUD_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE) 261 #define PUD_SIZE (1UL << PUD_SHIFT) 262 #define PUD_MASK (~(PUD_SIZE-1)) 263 264 /* PGDIR_SHIFT determines what a fourth-level page table entry can map */ 265 #define PGDIR_SHIFT (PUD_SHIFT + PUD_INDEX_SIZE) 266 #define PGDIR_SIZE (1UL << PGDIR_SHIFT) 267 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 268 269 /* Bits to mask out from a PMD to get to the PTE page */ 270 #define PMD_MASKED_BITS 0xc0000000000000ffUL 271 /* Bits to mask out from a PUD to get to the PMD page */ 272 #define PUD_MASKED_BITS 0xc0000000000000ffUL 273 /* Bits to mask out from a PGD to get to the PUD page */ 274 #define PGD_MASKED_BITS 0xc0000000000000ffUL 275 276 extern unsigned long __vmalloc_start; 277 extern unsigned long __vmalloc_end; 278 #define VMALLOC_START __vmalloc_start 279 #define VMALLOC_END __vmalloc_end 280 281 extern unsigned long __kernel_virt_start; 282 extern unsigned long __kernel_virt_size; 283 extern unsigned long __kernel_io_start; 284 #define KERN_VIRT_START __kernel_virt_start 285 #define KERN_VIRT_SIZE __kernel_virt_size 286 #define KERN_IO_START __kernel_io_start 287 extern struct page *vmemmap; 288 extern unsigned long ioremap_bot; 289 extern unsigned long pci_io_base; 290 #endif /* __ASSEMBLY__ */ 291 292 #include <asm/book3s/64/hash.h> 293 #include <asm/book3s/64/radix.h> 294 295 #ifdef CONFIG_PPC_64K_PAGES 296 #include <asm/book3s/64/pgtable-64k.h> 297 #else 298 #include <asm/book3s/64/pgtable-4k.h> 299 #endif 300 301 #include <asm/barrier.h> 302 /* 303 * The second half of the kernel virtual space is used for IO mappings, 304 * it's itself carved into the PIO region (ISA and PHB IO space) and 305 * the ioremap space 306 * 307 * ISA_IO_BASE = KERN_IO_START, 64K reserved area 308 * PHB_IO_BASE = ISA_IO_BASE + 64K to ISA_IO_BASE + 2G, PHB IO spaces 309 * IOREMAP_BASE = ISA_IO_BASE + 2G to VMALLOC_START + PGTABLE_RANGE 310 */ 311 #define FULL_IO_SIZE 0x80000000ul 312 #define ISA_IO_BASE (KERN_IO_START) 313 #define ISA_IO_END (KERN_IO_START + 0x10000ul) 314 #define PHB_IO_BASE (ISA_IO_END) 315 #define PHB_IO_END (KERN_IO_START + FULL_IO_SIZE) 316 #define IOREMAP_BASE (PHB_IO_END) 317 #define IOREMAP_END (KERN_VIRT_START + KERN_VIRT_SIZE) 318 319 /* Advertise special mapping type for AGP */ 320 #define HAVE_PAGE_AGP 321 322 /* Advertise support for _PAGE_SPECIAL */ 323 #define __HAVE_ARCH_PTE_SPECIAL 324 325 #ifndef __ASSEMBLY__ 326 327 /* 328 * This is the default implementation of various PTE accessors, it's 329 * used in all cases except Book3S with 64K pages where we have a 330 * concept of sub-pages 331 */ 332 #ifndef __real_pte 333 334 #define __real_pte(e, p, o) ((real_pte_t){(e)}) 335 #define __rpte_to_pte(r) ((r).pte) 336 #define __rpte_to_hidx(r,index) (pte_val(__rpte_to_pte(r)) >> H_PAGE_F_GIX_SHIFT) 337 338 #define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \ 339 do { \ 340 index = 0; \ 341 shift = mmu_psize_defs[psize].shift; \ 342 343 #define pte_iterate_hashed_end() } while(0) 344 345 /* 346 * We expect this to be called only for user addresses or kernel virtual 347 * addresses other than the linear mapping. 348 */ 349 #define pte_pagesize_index(mm, addr, pte) MMU_PAGE_4K 350 351 #endif /* __real_pte */ 352 353 static inline unsigned long pte_update(struct mm_struct *mm, unsigned long addr, 354 pte_t *ptep, unsigned long clr, 355 unsigned long set, int huge) 356 { 357 if (radix_enabled()) 358 return radix__pte_update(mm, addr, ptep, clr, set, huge); 359 return hash__pte_update(mm, addr, ptep, clr, set, huge); 360 } 361 /* 362 * For hash even if we have _PAGE_ACCESSED = 0, we do a pte_update. 363 * We currently remove entries from the hashtable regardless of whether 364 * the entry was young or dirty. 365 * 366 * We should be more intelligent about this but for the moment we override 367 * these functions and force a tlb flush unconditionally 368 * For radix: H_PAGE_HASHPTE should be zero. Hence we can use the same 369 * function for both hash and radix. 370 */ 371 static inline int __ptep_test_and_clear_young(struct mm_struct *mm, 372 unsigned long addr, pte_t *ptep) 373 { 374 unsigned long old; 375 376 if ((pte_raw(*ptep) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) 377 return 0; 378 old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0); 379 return (old & _PAGE_ACCESSED) != 0; 380 } 381 382 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 383 #define ptep_test_and_clear_young(__vma, __addr, __ptep) \ 384 ({ \ 385 int __r; \ 386 __r = __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \ 387 __r; \ 388 }) 389 390 static inline int __pte_write(pte_t pte) 391 { 392 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_WRITE)); 393 } 394 395 #ifdef CONFIG_NUMA_BALANCING 396 #define pte_savedwrite pte_savedwrite 397 static inline bool pte_savedwrite(pte_t pte) 398 { 399 /* 400 * Saved write ptes are prot none ptes that doesn't have 401 * privileged bit sit. We mark prot none as one which has 402 * present and pviliged bit set and RWX cleared. To mark 403 * protnone which used to have _PAGE_WRITE set we clear 404 * the privileged bit. 405 */ 406 return !(pte_raw(pte) & cpu_to_be64(_PAGE_RWX | _PAGE_PRIVILEGED)); 407 } 408 #else 409 #define pte_savedwrite pte_savedwrite 410 static inline bool pte_savedwrite(pte_t pte) 411 { 412 return false; 413 } 414 #endif 415 416 static inline int pte_write(pte_t pte) 417 { 418 return __pte_write(pte) || pte_savedwrite(pte); 419 } 420 421 static inline int pte_read(pte_t pte) 422 { 423 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_READ)); 424 } 425 426 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 427 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, 428 pte_t *ptep) 429 { 430 if (__pte_write(*ptep)) 431 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 0); 432 else if (unlikely(pte_savedwrite(*ptep))) 433 pte_update(mm, addr, ptep, 0, _PAGE_PRIVILEGED, 0); 434 } 435 436 static inline void huge_ptep_set_wrprotect(struct mm_struct *mm, 437 unsigned long addr, pte_t *ptep) 438 { 439 /* 440 * We should not find protnone for hugetlb, but this complete the 441 * interface. 442 */ 443 if (__pte_write(*ptep)) 444 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 1); 445 else if (unlikely(pte_savedwrite(*ptep))) 446 pte_update(mm, addr, ptep, 0, _PAGE_PRIVILEGED, 1); 447 } 448 449 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 450 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 451 unsigned long addr, pte_t *ptep) 452 { 453 unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0, 0); 454 return __pte(old); 455 } 456 457 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL 458 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, 459 unsigned long addr, 460 pte_t *ptep, int full) 461 { 462 if (full && radix_enabled()) { 463 /* 464 * Let's skip the DD1 style pte update here. We know that 465 * this is a full mm pte clear and hence can be sure there is 466 * no parallel set_pte. 467 */ 468 return radix__ptep_get_and_clear_full(mm, addr, ptep, full); 469 } 470 return ptep_get_and_clear(mm, addr, ptep); 471 } 472 473 474 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, 475 pte_t * ptep) 476 { 477 pte_update(mm, addr, ptep, ~0UL, 0, 0); 478 } 479 480 static inline int pte_dirty(pte_t pte) 481 { 482 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_DIRTY)); 483 } 484 485 static inline int pte_young(pte_t pte) 486 { 487 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_ACCESSED)); 488 } 489 490 static inline int pte_special(pte_t pte) 491 { 492 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SPECIAL)); 493 } 494 495 static inline pgprot_t pte_pgprot(pte_t pte) { return __pgprot(pte_val(pte) & PAGE_PROT_BITS); } 496 497 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 498 static inline bool pte_soft_dirty(pte_t pte) 499 { 500 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SOFT_DIRTY)); 501 } 502 503 static inline pte_t pte_mksoft_dirty(pte_t pte) 504 { 505 return __pte(pte_val(pte) | _PAGE_SOFT_DIRTY); 506 } 507 508 static inline pte_t pte_clear_soft_dirty(pte_t pte) 509 { 510 return __pte(pte_val(pte) & ~_PAGE_SOFT_DIRTY); 511 } 512 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 513 514 #ifdef CONFIG_NUMA_BALANCING 515 static inline int pte_protnone(pte_t pte) 516 { 517 return (pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE | _PAGE_RWX)) == 518 cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE); 519 } 520 521 #define pte_mk_savedwrite pte_mk_savedwrite 522 static inline pte_t pte_mk_savedwrite(pte_t pte) 523 { 524 /* 525 * Used by Autonuma subsystem to preserve the write bit 526 * while marking the pte PROT_NONE. Only allow this 527 * on PROT_NONE pte 528 */ 529 VM_BUG_ON((pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_RWX | _PAGE_PRIVILEGED)) != 530 cpu_to_be64(_PAGE_PRESENT | _PAGE_PRIVILEGED)); 531 return __pte(pte_val(pte) & ~_PAGE_PRIVILEGED); 532 } 533 534 #define pte_clear_savedwrite pte_clear_savedwrite 535 static inline pte_t pte_clear_savedwrite(pte_t pte) 536 { 537 /* 538 * Used by KSM subsystem to make a protnone pte readonly. 539 */ 540 VM_BUG_ON(!pte_protnone(pte)); 541 return __pte(pte_val(pte) | _PAGE_PRIVILEGED); 542 } 543 #else 544 #define pte_clear_savedwrite pte_clear_savedwrite 545 static inline pte_t pte_clear_savedwrite(pte_t pte) 546 { 547 VM_WARN_ON(1); 548 return __pte(pte_val(pte) & ~_PAGE_WRITE); 549 } 550 #endif /* CONFIG_NUMA_BALANCING */ 551 552 static inline int pte_present(pte_t pte) 553 { 554 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT)); 555 } 556 557 #ifdef CONFIG_PPC_MEM_KEYS 558 extern bool arch_pte_access_permitted(u64 pte, bool write, bool execute); 559 #else 560 static inline bool arch_pte_access_permitted(u64 pte, bool write, bool execute) 561 { 562 return true; 563 } 564 #endif /* CONFIG_PPC_MEM_KEYS */ 565 566 #define pte_access_permitted pte_access_permitted 567 static inline bool pte_access_permitted(pte_t pte, bool write) 568 { 569 unsigned long pteval = pte_val(pte); 570 /* Also check for pte_user */ 571 unsigned long clear_pte_bits = _PAGE_PRIVILEGED; 572 /* 573 * _PAGE_READ is needed for any access and will be 574 * cleared for PROT_NONE 575 */ 576 unsigned long need_pte_bits = _PAGE_PRESENT | _PAGE_READ; 577 578 if (write) 579 need_pte_bits |= _PAGE_WRITE; 580 581 if ((pteval & need_pte_bits) != need_pte_bits) 582 return false; 583 584 if ((pteval & clear_pte_bits) == clear_pte_bits) 585 return false; 586 587 return arch_pte_access_permitted(pte_val(pte), write, 0); 588 } 589 590 /* 591 * Conversion functions: convert a page and protection to a page entry, 592 * and a page entry and page directory to the page they refer to. 593 * 594 * Even if PTEs can be unsigned long long, a PFN is always an unsigned 595 * long for now. 596 */ 597 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot) 598 { 599 return __pte((((pte_basic_t)(pfn) << PAGE_SHIFT) & PTE_RPN_MASK) | 600 pgprot_val(pgprot)); 601 } 602 603 static inline unsigned long pte_pfn(pte_t pte) 604 { 605 return (pte_val(pte) & PTE_RPN_MASK) >> PAGE_SHIFT; 606 } 607 608 /* Generic modifiers for PTE bits */ 609 static inline pte_t pte_wrprotect(pte_t pte) 610 { 611 if (unlikely(pte_savedwrite(pte))) 612 return pte_clear_savedwrite(pte); 613 return __pte(pte_val(pte) & ~_PAGE_WRITE); 614 } 615 616 static inline pte_t pte_mkclean(pte_t pte) 617 { 618 return __pte(pte_val(pte) & ~_PAGE_DIRTY); 619 } 620 621 static inline pte_t pte_mkold(pte_t pte) 622 { 623 return __pte(pte_val(pte) & ~_PAGE_ACCESSED); 624 } 625 626 static inline pte_t pte_mkwrite(pte_t pte) 627 { 628 /* 629 * write implies read, hence set both 630 */ 631 return __pte(pte_val(pte) | _PAGE_RW); 632 } 633 634 static inline pte_t pte_mkdirty(pte_t pte) 635 { 636 return __pte(pte_val(pte) | _PAGE_DIRTY | _PAGE_SOFT_DIRTY); 637 } 638 639 static inline pte_t pte_mkyoung(pte_t pte) 640 { 641 return __pte(pte_val(pte) | _PAGE_ACCESSED); 642 } 643 644 static inline pte_t pte_mkspecial(pte_t pte) 645 { 646 return __pte(pte_val(pte) | _PAGE_SPECIAL); 647 } 648 649 static inline pte_t pte_mkhuge(pte_t pte) 650 { 651 return pte; 652 } 653 654 static inline pte_t pte_mkdevmap(pte_t pte) 655 { 656 return __pte(pte_val(pte) | _PAGE_SPECIAL|_PAGE_DEVMAP); 657 } 658 659 /* 660 * This is potentially called with a pmd as the argument, in which case it's not 661 * safe to check _PAGE_DEVMAP unless we also confirm that _PAGE_PTE is set. 662 * That's because the bit we use for _PAGE_DEVMAP is not reserved for software 663 * use in page directory entries (ie. non-ptes). 664 */ 665 static inline int pte_devmap(pte_t pte) 666 { 667 u64 mask = cpu_to_be64(_PAGE_DEVMAP | _PAGE_PTE); 668 669 return (pte_raw(pte) & mask) == mask; 670 } 671 672 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 673 { 674 /* FIXME!! check whether this need to be a conditional */ 675 return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot)); 676 } 677 678 static inline bool pte_user(pte_t pte) 679 { 680 return !(pte_raw(pte) & cpu_to_be64(_PAGE_PRIVILEGED)); 681 } 682 683 /* Encode and de-code a swap entry */ 684 #define MAX_SWAPFILES_CHECK() do { \ 685 BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS); \ 686 /* \ 687 * Don't have overlapping bits with _PAGE_HPTEFLAGS \ 688 * We filter HPTEFLAGS on set_pte. \ 689 */ \ 690 BUILD_BUG_ON(_PAGE_HPTEFLAGS & (0x1f << _PAGE_BIT_SWAP_TYPE)); \ 691 BUILD_BUG_ON(_PAGE_HPTEFLAGS & _PAGE_SWP_SOFT_DIRTY); \ 692 } while (0) 693 /* 694 * on pte we don't need handle RADIX_TREE_EXCEPTIONAL_SHIFT; 695 */ 696 #define SWP_TYPE_BITS 5 697 #define __swp_type(x) (((x).val >> _PAGE_BIT_SWAP_TYPE) \ 698 & ((1UL << SWP_TYPE_BITS) - 1)) 699 #define __swp_offset(x) (((x).val & PTE_RPN_MASK) >> PAGE_SHIFT) 700 #define __swp_entry(type, offset) ((swp_entry_t) { \ 701 ((type) << _PAGE_BIT_SWAP_TYPE) \ 702 | (((offset) << PAGE_SHIFT) & PTE_RPN_MASK)}) 703 /* 704 * swp_entry_t must be independent of pte bits. We build a swp_entry_t from 705 * swap type and offset we get from swap and convert that to pte to find a 706 * matching pte in linux page table. 707 * Clear bits not found in swap entries here. 708 */ 709 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val((pte)) & ~_PAGE_PTE }) 710 #define __swp_entry_to_pte(x) __pte((x).val | _PAGE_PTE) 711 712 #ifdef CONFIG_MEM_SOFT_DIRTY 713 #define _PAGE_SWP_SOFT_DIRTY (1UL << (SWP_TYPE_BITS + _PAGE_BIT_SWAP_TYPE)) 714 #else 715 #define _PAGE_SWP_SOFT_DIRTY 0UL 716 #endif /* CONFIG_MEM_SOFT_DIRTY */ 717 718 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 719 static inline pte_t pte_swp_mksoft_dirty(pte_t pte) 720 { 721 return __pte(pte_val(pte) | _PAGE_SWP_SOFT_DIRTY); 722 } 723 724 static inline bool pte_swp_soft_dirty(pte_t pte) 725 { 726 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SWP_SOFT_DIRTY)); 727 } 728 729 static inline pte_t pte_swp_clear_soft_dirty(pte_t pte) 730 { 731 return __pte(pte_val(pte) & ~_PAGE_SWP_SOFT_DIRTY); 732 } 733 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 734 735 static inline bool check_pte_access(unsigned long access, unsigned long ptev) 736 { 737 /* 738 * This check for _PAGE_RWX and _PAGE_PRESENT bits 739 */ 740 if (access & ~ptev) 741 return false; 742 /* 743 * This check for access to privilege space 744 */ 745 if ((access & _PAGE_PRIVILEGED) != (ptev & _PAGE_PRIVILEGED)) 746 return false; 747 748 return true; 749 } 750 /* 751 * Generic functions with hash/radix callbacks 752 */ 753 754 static inline void __ptep_set_access_flags(struct mm_struct *mm, 755 pte_t *ptep, pte_t entry, 756 unsigned long address) 757 { 758 if (radix_enabled()) 759 return radix__ptep_set_access_flags(mm, ptep, entry, address); 760 return hash__ptep_set_access_flags(ptep, entry); 761 } 762 763 #define __HAVE_ARCH_PTE_SAME 764 static inline int pte_same(pte_t pte_a, pte_t pte_b) 765 { 766 if (radix_enabled()) 767 return radix__pte_same(pte_a, pte_b); 768 return hash__pte_same(pte_a, pte_b); 769 } 770 771 static inline int pte_none(pte_t pte) 772 { 773 if (radix_enabled()) 774 return radix__pte_none(pte); 775 return hash__pte_none(pte); 776 } 777 778 static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr, 779 pte_t *ptep, pte_t pte, int percpu) 780 { 781 if (radix_enabled()) 782 return radix__set_pte_at(mm, addr, ptep, pte, percpu); 783 return hash__set_pte_at(mm, addr, ptep, pte, percpu); 784 } 785 786 #define _PAGE_CACHE_CTL (_PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT) 787 788 #define pgprot_noncached pgprot_noncached 789 static inline pgprot_t pgprot_noncached(pgprot_t prot) 790 { 791 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | 792 _PAGE_NON_IDEMPOTENT); 793 } 794 795 #define pgprot_noncached_wc pgprot_noncached_wc 796 static inline pgprot_t pgprot_noncached_wc(pgprot_t prot) 797 { 798 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | 799 _PAGE_TOLERANT); 800 } 801 802 #define pgprot_cached pgprot_cached 803 static inline pgprot_t pgprot_cached(pgprot_t prot) 804 { 805 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL)); 806 } 807 808 #define pgprot_writecombine pgprot_writecombine 809 static inline pgprot_t pgprot_writecombine(pgprot_t prot) 810 { 811 return pgprot_noncached_wc(prot); 812 } 813 /* 814 * check a pte mapping have cache inhibited property 815 */ 816 static inline bool pte_ci(pte_t pte) 817 { 818 unsigned long pte_v = pte_val(pte); 819 820 if (((pte_v & _PAGE_CACHE_CTL) == _PAGE_TOLERANT) || 821 ((pte_v & _PAGE_CACHE_CTL) == _PAGE_NON_IDEMPOTENT)) 822 return true; 823 return false; 824 } 825 826 static inline void pmd_set(pmd_t *pmdp, unsigned long val) 827 { 828 *pmdp = __pmd(val); 829 } 830 831 static inline void pmd_clear(pmd_t *pmdp) 832 { 833 *pmdp = __pmd(0); 834 } 835 836 static inline int pmd_none(pmd_t pmd) 837 { 838 return !pmd_raw(pmd); 839 } 840 841 static inline int pmd_present(pmd_t pmd) 842 { 843 844 return !pmd_none(pmd); 845 } 846 847 static inline int pmd_bad(pmd_t pmd) 848 { 849 if (radix_enabled()) 850 return radix__pmd_bad(pmd); 851 return hash__pmd_bad(pmd); 852 } 853 854 static inline void pud_set(pud_t *pudp, unsigned long val) 855 { 856 *pudp = __pud(val); 857 } 858 859 static inline void pud_clear(pud_t *pudp) 860 { 861 *pudp = __pud(0); 862 } 863 864 static inline int pud_none(pud_t pud) 865 { 866 return !pud_raw(pud); 867 } 868 869 static inline int pud_present(pud_t pud) 870 { 871 return !pud_none(pud); 872 } 873 874 extern struct page *pud_page(pud_t pud); 875 extern struct page *pmd_page(pmd_t pmd); 876 static inline pte_t pud_pte(pud_t pud) 877 { 878 return __pte_raw(pud_raw(pud)); 879 } 880 881 static inline pud_t pte_pud(pte_t pte) 882 { 883 return __pud_raw(pte_raw(pte)); 884 } 885 #define pud_write(pud) pte_write(pud_pte(pud)) 886 887 static inline int pud_bad(pud_t pud) 888 { 889 if (radix_enabled()) 890 return radix__pud_bad(pud); 891 return hash__pud_bad(pud); 892 } 893 894 #define pud_access_permitted pud_access_permitted 895 static inline bool pud_access_permitted(pud_t pud, bool write) 896 { 897 return pte_access_permitted(pud_pte(pud), write); 898 } 899 900 #define pgd_write(pgd) pte_write(pgd_pte(pgd)) 901 static inline void pgd_set(pgd_t *pgdp, unsigned long val) 902 { 903 *pgdp = __pgd(val); 904 } 905 906 static inline void pgd_clear(pgd_t *pgdp) 907 { 908 *pgdp = __pgd(0); 909 } 910 911 static inline int pgd_none(pgd_t pgd) 912 { 913 return !pgd_raw(pgd); 914 } 915 916 static inline int pgd_present(pgd_t pgd) 917 { 918 return !pgd_none(pgd); 919 } 920 921 static inline pte_t pgd_pte(pgd_t pgd) 922 { 923 return __pte_raw(pgd_raw(pgd)); 924 } 925 926 static inline pgd_t pte_pgd(pte_t pte) 927 { 928 return __pgd_raw(pte_raw(pte)); 929 } 930 931 static inline int pgd_bad(pgd_t pgd) 932 { 933 if (radix_enabled()) 934 return radix__pgd_bad(pgd); 935 return hash__pgd_bad(pgd); 936 } 937 938 #define pgd_access_permitted pgd_access_permitted 939 static inline bool pgd_access_permitted(pgd_t pgd, bool write) 940 { 941 return pte_access_permitted(pgd_pte(pgd), write); 942 } 943 944 extern struct page *pgd_page(pgd_t pgd); 945 946 /* Pointers in the page table tree are physical addresses */ 947 #define __pgtable_ptr_val(ptr) __pa(ptr) 948 949 #define pmd_page_vaddr(pmd) __va(pmd_val(pmd) & ~PMD_MASKED_BITS) 950 #define pud_page_vaddr(pud) __va(pud_val(pud) & ~PUD_MASKED_BITS) 951 #define pgd_page_vaddr(pgd) __va(pgd_val(pgd) & ~PGD_MASKED_BITS) 952 953 #define pgd_index(address) (((address) >> (PGDIR_SHIFT)) & (PTRS_PER_PGD - 1)) 954 #define pud_index(address) (((address) >> (PUD_SHIFT)) & (PTRS_PER_PUD - 1)) 955 #define pmd_index(address) (((address) >> (PMD_SHIFT)) & (PTRS_PER_PMD - 1)) 956 #define pte_index(address) (((address) >> (PAGE_SHIFT)) & (PTRS_PER_PTE - 1)) 957 958 /* 959 * Find an entry in a page-table-directory. We combine the address region 960 * (the high order N bits) and the pgd portion of the address. 961 */ 962 963 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) 964 965 #define pud_offset(pgdp, addr) \ 966 (((pud_t *) pgd_page_vaddr(*(pgdp))) + pud_index(addr)) 967 #define pmd_offset(pudp,addr) \ 968 (((pmd_t *) pud_page_vaddr(*(pudp))) + pmd_index(addr)) 969 #define pte_offset_kernel(dir,addr) \ 970 (((pte_t *) pmd_page_vaddr(*(dir))) + pte_index(addr)) 971 972 #define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr)) 973 #define pte_unmap(pte) do { } while(0) 974 975 /* to find an entry in a kernel page-table-directory */ 976 /* This now only contains the vmalloc pages */ 977 #define pgd_offset_k(address) pgd_offset(&init_mm, address) 978 979 #define pte_ERROR(e) \ 980 pr_err("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e)) 981 #define pmd_ERROR(e) \ 982 pr_err("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e)) 983 #define pud_ERROR(e) \ 984 pr_err("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e)) 985 #define pgd_ERROR(e) \ 986 pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) 987 988 static inline int map_kernel_page(unsigned long ea, unsigned long pa, 989 unsigned long flags) 990 { 991 if (radix_enabled()) { 992 #if defined(CONFIG_PPC_RADIX_MMU) && defined(DEBUG_VM) 993 unsigned long page_size = 1 << mmu_psize_defs[mmu_io_psize].shift; 994 WARN((page_size != PAGE_SIZE), "I/O page size != PAGE_SIZE"); 995 #endif 996 return radix__map_kernel_page(ea, pa, __pgprot(flags), PAGE_SIZE); 997 } 998 return hash__map_kernel_page(ea, pa, flags); 999 } 1000 1001 static inline int __meminit vmemmap_create_mapping(unsigned long start, 1002 unsigned long page_size, 1003 unsigned long phys) 1004 { 1005 if (radix_enabled()) 1006 return radix__vmemmap_create_mapping(start, page_size, phys); 1007 return hash__vmemmap_create_mapping(start, page_size, phys); 1008 } 1009 1010 #ifdef CONFIG_MEMORY_HOTPLUG 1011 static inline void vmemmap_remove_mapping(unsigned long start, 1012 unsigned long page_size) 1013 { 1014 if (radix_enabled()) 1015 return radix__vmemmap_remove_mapping(start, page_size); 1016 return hash__vmemmap_remove_mapping(start, page_size); 1017 } 1018 #endif 1019 struct page *realmode_pfn_to_page(unsigned long pfn); 1020 1021 static inline pte_t pmd_pte(pmd_t pmd) 1022 { 1023 return __pte_raw(pmd_raw(pmd)); 1024 } 1025 1026 static inline pmd_t pte_pmd(pte_t pte) 1027 { 1028 return __pmd_raw(pte_raw(pte)); 1029 } 1030 1031 static inline pte_t *pmdp_ptep(pmd_t *pmd) 1032 { 1033 return (pte_t *)pmd; 1034 } 1035 #define pmd_pfn(pmd) pte_pfn(pmd_pte(pmd)) 1036 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) 1037 #define pmd_young(pmd) pte_young(pmd_pte(pmd)) 1038 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) 1039 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) 1040 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) 1041 #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) 1042 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) 1043 #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd))) 1044 #define pmd_mk_savedwrite(pmd) pte_pmd(pte_mk_savedwrite(pmd_pte(pmd))) 1045 #define pmd_clear_savedwrite(pmd) pte_pmd(pte_clear_savedwrite(pmd_pte(pmd))) 1046 1047 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 1048 #define pmd_soft_dirty(pmd) pte_soft_dirty(pmd_pte(pmd)) 1049 #define pmd_mksoft_dirty(pmd) pte_pmd(pte_mksoft_dirty(pmd_pte(pmd))) 1050 #define pmd_clear_soft_dirty(pmd) pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd))) 1051 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 1052 1053 #ifdef CONFIG_NUMA_BALANCING 1054 static inline int pmd_protnone(pmd_t pmd) 1055 { 1056 return pte_protnone(pmd_pte(pmd)); 1057 } 1058 #endif /* CONFIG_NUMA_BALANCING */ 1059 1060 #define pmd_write(pmd) pte_write(pmd_pte(pmd)) 1061 #define __pmd_write(pmd) __pte_write(pmd_pte(pmd)) 1062 #define pmd_savedwrite(pmd) pte_savedwrite(pmd_pte(pmd)) 1063 1064 #define pmd_access_permitted pmd_access_permitted 1065 static inline bool pmd_access_permitted(pmd_t pmd, bool write) 1066 { 1067 return pte_access_permitted(pmd_pte(pmd), write); 1068 } 1069 1070 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1071 extern pmd_t pfn_pmd(unsigned long pfn, pgprot_t pgprot); 1072 extern pmd_t mk_pmd(struct page *page, pgprot_t pgprot); 1073 extern pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot); 1074 extern void set_pmd_at(struct mm_struct *mm, unsigned long addr, 1075 pmd_t *pmdp, pmd_t pmd); 1076 extern void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr, 1077 pmd_t *pmd); 1078 extern int hash__has_transparent_hugepage(void); 1079 static inline int has_transparent_hugepage(void) 1080 { 1081 if (radix_enabled()) 1082 return radix__has_transparent_hugepage(); 1083 return hash__has_transparent_hugepage(); 1084 } 1085 #define has_transparent_hugepage has_transparent_hugepage 1086 1087 static inline unsigned long 1088 pmd_hugepage_update(struct mm_struct *mm, unsigned long addr, pmd_t *pmdp, 1089 unsigned long clr, unsigned long set) 1090 { 1091 if (radix_enabled()) 1092 return radix__pmd_hugepage_update(mm, addr, pmdp, clr, set); 1093 return hash__pmd_hugepage_update(mm, addr, pmdp, clr, set); 1094 } 1095 1096 static inline int pmd_large(pmd_t pmd) 1097 { 1098 return !!(pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE)); 1099 } 1100 1101 static inline pmd_t pmd_mknotpresent(pmd_t pmd) 1102 { 1103 return __pmd(pmd_val(pmd) & ~_PAGE_PRESENT); 1104 } 1105 /* 1106 * For radix we should always find H_PAGE_HASHPTE zero. Hence 1107 * the below will work for radix too 1108 */ 1109 static inline int __pmdp_test_and_clear_young(struct mm_struct *mm, 1110 unsigned long addr, pmd_t *pmdp) 1111 { 1112 unsigned long old; 1113 1114 if ((pmd_raw(*pmdp) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) 1115 return 0; 1116 old = pmd_hugepage_update(mm, addr, pmdp, _PAGE_ACCESSED, 0); 1117 return ((old & _PAGE_ACCESSED) != 0); 1118 } 1119 1120 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 1121 static inline void pmdp_set_wrprotect(struct mm_struct *mm, unsigned long addr, 1122 pmd_t *pmdp) 1123 { 1124 if (__pmd_write((*pmdp))) 1125 pmd_hugepage_update(mm, addr, pmdp, _PAGE_WRITE, 0); 1126 else if (unlikely(pmd_savedwrite(*pmdp))) 1127 pmd_hugepage_update(mm, addr, pmdp, 0, _PAGE_PRIVILEGED); 1128 } 1129 1130 static inline int pmd_trans_huge(pmd_t pmd) 1131 { 1132 if (radix_enabled()) 1133 return radix__pmd_trans_huge(pmd); 1134 return hash__pmd_trans_huge(pmd); 1135 } 1136 1137 #define __HAVE_ARCH_PMD_SAME 1138 static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b) 1139 { 1140 if (radix_enabled()) 1141 return radix__pmd_same(pmd_a, pmd_b); 1142 return hash__pmd_same(pmd_a, pmd_b); 1143 } 1144 1145 static inline pmd_t pmd_mkhuge(pmd_t pmd) 1146 { 1147 if (radix_enabled()) 1148 return radix__pmd_mkhuge(pmd); 1149 return hash__pmd_mkhuge(pmd); 1150 } 1151 1152 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 1153 extern int pmdp_set_access_flags(struct vm_area_struct *vma, 1154 unsigned long address, pmd_t *pmdp, 1155 pmd_t entry, int dirty); 1156 1157 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 1158 extern int pmdp_test_and_clear_young(struct vm_area_struct *vma, 1159 unsigned long address, pmd_t *pmdp); 1160 1161 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 1162 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 1163 unsigned long addr, pmd_t *pmdp) 1164 { 1165 if (radix_enabled()) 1166 return radix__pmdp_huge_get_and_clear(mm, addr, pmdp); 1167 return hash__pmdp_huge_get_and_clear(mm, addr, pmdp); 1168 } 1169 1170 static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, 1171 unsigned long address, pmd_t *pmdp) 1172 { 1173 if (radix_enabled()) 1174 return radix__pmdp_collapse_flush(vma, address, pmdp); 1175 return hash__pmdp_collapse_flush(vma, address, pmdp); 1176 } 1177 #define pmdp_collapse_flush pmdp_collapse_flush 1178 1179 #define __HAVE_ARCH_PGTABLE_DEPOSIT 1180 static inline void pgtable_trans_huge_deposit(struct mm_struct *mm, 1181 pmd_t *pmdp, pgtable_t pgtable) 1182 { 1183 if (radix_enabled()) 1184 return radix__pgtable_trans_huge_deposit(mm, pmdp, pgtable); 1185 return hash__pgtable_trans_huge_deposit(mm, pmdp, pgtable); 1186 } 1187 1188 #define __HAVE_ARCH_PGTABLE_WITHDRAW 1189 static inline pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, 1190 pmd_t *pmdp) 1191 { 1192 if (radix_enabled()) 1193 return radix__pgtable_trans_huge_withdraw(mm, pmdp); 1194 return hash__pgtable_trans_huge_withdraw(mm, pmdp); 1195 } 1196 1197 #define __HAVE_ARCH_PMDP_INVALIDATE 1198 extern pmd_t pmdp_invalidate(struct vm_area_struct *vma, unsigned long address, 1199 pmd_t *pmdp); 1200 1201 #define pmd_move_must_withdraw pmd_move_must_withdraw 1202 struct spinlock; 1203 static inline int pmd_move_must_withdraw(struct spinlock *new_pmd_ptl, 1204 struct spinlock *old_pmd_ptl, 1205 struct vm_area_struct *vma) 1206 { 1207 if (radix_enabled()) 1208 return false; 1209 /* 1210 * Archs like ppc64 use pgtable to store per pmd 1211 * specific information. So when we switch the pmd, 1212 * we should also withdraw and deposit the pgtable 1213 */ 1214 return true; 1215 } 1216 1217 1218 #define arch_needs_pgtable_deposit arch_needs_pgtable_deposit 1219 static inline bool arch_needs_pgtable_deposit(void) 1220 { 1221 if (radix_enabled()) 1222 return false; 1223 return true; 1224 } 1225 extern void serialize_against_pte_lookup(struct mm_struct *mm); 1226 1227 1228 static inline pmd_t pmd_mkdevmap(pmd_t pmd) 1229 { 1230 return __pmd(pmd_val(pmd) | (_PAGE_PTE | _PAGE_DEVMAP)); 1231 } 1232 1233 static inline int pmd_devmap(pmd_t pmd) 1234 { 1235 return pte_devmap(pmd_pte(pmd)); 1236 } 1237 1238 static inline int pud_devmap(pud_t pud) 1239 { 1240 return 0; 1241 } 1242 1243 static inline int pgd_devmap(pgd_t pgd) 1244 { 1245 return 0; 1246 } 1247 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1248 1249 static inline const int pud_pfn(pud_t pud) 1250 { 1251 /* 1252 * Currently all calls to pud_pfn() are gated around a pud_devmap() 1253 * check so this should never be used. If it grows another user we 1254 * want to know about it. 1255 */ 1256 BUILD_BUG(); 1257 return 0; 1258 } 1259 1260 #endif /* __ASSEMBLY__ */ 1261 #endif /* _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ */ 1262