1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * xHCI host controller driver PCI Bus Glue. 4 * 5 * Copyright (C) 2008 Intel Corp. 6 * 7 * Author: Sarah Sharp 8 * Some code borrowed from the Linux EHCI driver. 9 */ 10 11 #include <linux/pci.h> 12 #include <linux/slab.h> 13 #include <linux/module.h> 14 #include <linux/acpi.h> 15 16 #include "xhci.h" 17 #include "xhci-trace.h" 18 19 #define SSIC_PORT_NUM 2 20 #define SSIC_PORT_CFG2 0x880c 21 #define SSIC_PORT_CFG2_OFFSET 0x30 22 #define PROG_DONE (1 << 30) 23 #define SSIC_PORT_UNUSED (1 << 31) 24 25 /* Device for a quirk */ 26 #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73 27 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000 28 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009 0x1009 29 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400 30 31 #define PCI_VENDOR_ID_ETRON 0x1b6f 32 #define PCI_DEVICE_ID_EJ168 0x7023 33 34 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31 35 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31 36 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI 0x9cb1 37 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5 38 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f 39 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f 40 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8 41 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8 42 #define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8 43 #define PCI_DEVICE_ID_INTEL_DNV_XHCI 0x19d0 44 45 #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI 0x1142 46 47 static const char hcd_name[] = "xhci_hcd"; 48 49 static struct hc_driver __read_mostly xhci_pci_hc_driver; 50 51 static int xhci_pci_setup(struct usb_hcd *hcd); 52 53 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = { 54 .reset = xhci_pci_setup, 55 }; 56 57 /* called after powerup, by probe or system-pm "wakeup" */ 58 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev) 59 { 60 /* 61 * TODO: Implement finding debug ports later. 62 * TODO: see if there are any quirks that need to be added to handle 63 * new extended capabilities. 64 */ 65 66 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */ 67 if (!pci_set_mwi(pdev)) 68 xhci_dbg(xhci, "MWI active\n"); 69 70 xhci_dbg(xhci, "Finished xhci_pci_reinit\n"); 71 return 0; 72 } 73 74 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci) 75 { 76 struct pci_dev *pdev = to_pci_dev(dev); 77 78 /* Look for vendor-specific quirks */ 79 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 80 (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK || 81 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) { 82 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 83 pdev->revision == 0x0) { 84 xhci->quirks |= XHCI_RESET_EP_QUIRK; 85 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 86 "QUIRK: Fresco Logic xHC needs configure" 87 " endpoint cmd after reset endpoint"); 88 } 89 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 90 pdev->revision == 0x4) { 91 xhci->quirks |= XHCI_SLOW_SUSPEND; 92 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 93 "QUIRK: Fresco Logic xHC revision %u" 94 "must be suspended extra slowly", 95 pdev->revision); 96 } 97 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK) 98 xhci->quirks |= XHCI_BROKEN_STREAMS; 99 /* Fresco Logic confirms: all revisions of this chip do not 100 * support MSI, even though some of them claim to in their PCI 101 * capabilities. 102 */ 103 xhci->quirks |= XHCI_BROKEN_MSI; 104 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 105 "QUIRK: Fresco Logic revision %u " 106 "has broken MSI implementation", 107 pdev->revision); 108 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 109 } 110 111 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 112 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009) 113 xhci->quirks |= XHCI_BROKEN_STREAMS; 114 115 if (pdev->vendor == PCI_VENDOR_ID_NEC) 116 xhci->quirks |= XHCI_NEC_HOST; 117 118 if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96) 119 xhci->quirks |= XHCI_AMD_0x96_HOST; 120 121 /* AMD PLL quirk */ 122 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info()) 123 xhci->quirks |= XHCI_AMD_PLL_FIX; 124 125 if (pdev->vendor == PCI_VENDOR_ID_AMD) 126 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 127 128 if (pdev->vendor == PCI_VENDOR_ID_INTEL) { 129 xhci->quirks |= XHCI_LPM_SUPPORT; 130 xhci->quirks |= XHCI_INTEL_HOST; 131 xhci->quirks |= XHCI_AVOID_BEI; 132 } 133 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 134 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) { 135 xhci->quirks |= XHCI_EP_LIMIT_QUIRK; 136 xhci->limit_active_eps = 64; 137 xhci->quirks |= XHCI_SW_BW_CHECKING; 138 /* 139 * PPT desktop boards DH77EB and DH77DF will power back on after 140 * a few seconds of being shutdown. The fix for this is to 141 * switch the ports from xHCI to EHCI on shutdown. We can't use 142 * DMI information to find those particular boards (since each 143 * vendor will change the board name), so we have to key off all 144 * PPT chipsets. 145 */ 146 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 147 } 148 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 149 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI || 150 pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) { 151 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 152 xhci->quirks |= XHCI_SPURIOUS_WAKEUP; 153 } 154 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 155 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 156 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI || 157 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 158 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI || 159 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI || 160 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI || 161 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI)) { 162 xhci->quirks |= XHCI_PME_STUCK_QUIRK; 163 } 164 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 165 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) { 166 xhci->quirks |= XHCI_SSIC_PORT_UNUSED; 167 } 168 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 169 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 170 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI || 171 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI)) 172 xhci->quirks |= XHCI_MISSING_CAS; 173 174 if (pdev->vendor == PCI_VENDOR_ID_ETRON && 175 pdev->device == PCI_DEVICE_ID_EJ168) { 176 xhci->quirks |= XHCI_RESET_ON_RESUME; 177 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 178 xhci->quirks |= XHCI_BROKEN_STREAMS; 179 } 180 if (pdev->vendor == PCI_VENDOR_ID_RENESAS && 181 pdev->device == 0x0014) 182 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 183 if (pdev->vendor == PCI_VENDOR_ID_RENESAS && 184 pdev->device == 0x0015) 185 xhci->quirks |= XHCI_RESET_ON_RESUME; 186 if (pdev->vendor == PCI_VENDOR_ID_VIA) 187 xhci->quirks |= XHCI_RESET_ON_RESUME; 188 189 /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */ 190 if (pdev->vendor == PCI_VENDOR_ID_VIA && 191 pdev->device == 0x3432) 192 xhci->quirks |= XHCI_BROKEN_STREAMS; 193 194 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 195 pdev->device == 0x1042) 196 xhci->quirks |= XHCI_BROKEN_STREAMS; 197 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 198 pdev->device == 0x1142) 199 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 200 201 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 202 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) 203 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL; 204 205 if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241) 206 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7; 207 208 if (xhci->quirks & XHCI_RESET_ON_RESUME) 209 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 210 "QUIRK: Resetting on resume"); 211 } 212 213 #ifdef CONFIG_ACPI 214 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) 215 { 216 static const guid_t intel_dsm_guid = 217 GUID_INIT(0xac340cb7, 0xe901, 0x45bf, 218 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23); 219 union acpi_object *obj; 220 221 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1, 222 NULL); 223 ACPI_FREE(obj); 224 } 225 #else 226 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { } 227 #endif /* CONFIG_ACPI */ 228 229 /* called during probe() after chip reset completes */ 230 static int xhci_pci_setup(struct usb_hcd *hcd) 231 { 232 struct xhci_hcd *xhci; 233 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 234 int retval; 235 236 xhci = hcd_to_xhci(hcd); 237 if (!xhci->sbrn) 238 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn); 239 240 /* imod_interval is the interrupt moderation value in nanoseconds. */ 241 xhci->imod_interval = 40000; 242 243 retval = xhci_gen_setup(hcd, xhci_pci_quirks); 244 if (retval) 245 return retval; 246 247 if (!usb_hcd_is_primary_hcd(hcd)) 248 return 0; 249 250 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn); 251 252 /* Find any debug ports */ 253 return xhci_pci_reinit(xhci, pdev); 254 } 255 256 /* 257 * We need to register our own PCI probe function (instead of the USB core's 258 * function) in order to create a second roothub under xHCI. 259 */ 260 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) 261 { 262 int retval; 263 struct xhci_hcd *xhci; 264 struct hc_driver *driver; 265 struct usb_hcd *hcd; 266 267 driver = (struct hc_driver *)id->driver_data; 268 269 /* For some HW implementation, a XHCI reset is just not enough... */ 270 if (usb_xhci_needs_pci_reset(dev)) { 271 dev_info(&dev->dev, "Resetting\n"); 272 if (pci_reset_function_locked(dev)) 273 dev_warn(&dev->dev, "Reset failed"); 274 } 275 276 /* Prevent runtime suspending between USB-2 and USB-3 initialization */ 277 pm_runtime_get_noresume(&dev->dev); 278 279 /* Register the USB 2.0 roothub. 280 * FIXME: USB core must know to register the USB 2.0 roothub first. 281 * This is sort of silly, because we could just set the HCD driver flags 282 * to say USB 2.0, but I'm not sure what the implications would be in 283 * the other parts of the HCD code. 284 */ 285 retval = usb_hcd_pci_probe(dev, id); 286 287 if (retval) 288 goto put_runtime_pm; 289 290 /* USB 2.0 roothub is stored in the PCI device now. */ 291 hcd = dev_get_drvdata(&dev->dev); 292 xhci = hcd_to_xhci(hcd); 293 xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev, 294 pci_name(dev), hcd); 295 if (!xhci->shared_hcd) { 296 retval = -ENOMEM; 297 goto dealloc_usb2_hcd; 298 } 299 300 retval = usb_add_hcd(xhci->shared_hcd, dev->irq, 301 IRQF_SHARED); 302 if (retval) 303 goto put_usb3_hcd; 304 /* Roothub already marked as USB 3.0 speed */ 305 306 if (!(xhci->quirks & XHCI_BROKEN_STREAMS) && 307 HCC_MAX_PSA(xhci->hcc_params) >= 4) 308 xhci->shared_hcd->can_do_streams = 1; 309 310 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 311 xhci_pme_acpi_rtd3_enable(dev); 312 313 /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */ 314 pm_runtime_put_noidle(&dev->dev); 315 316 return 0; 317 318 put_usb3_hcd: 319 usb_put_hcd(xhci->shared_hcd); 320 dealloc_usb2_hcd: 321 usb_hcd_pci_remove(dev); 322 put_runtime_pm: 323 pm_runtime_put_noidle(&dev->dev); 324 return retval; 325 } 326 327 static void xhci_pci_remove(struct pci_dev *dev) 328 { 329 struct xhci_hcd *xhci; 330 331 xhci = hcd_to_xhci(pci_get_drvdata(dev)); 332 xhci->xhc_state |= XHCI_STATE_REMOVING; 333 if (xhci->shared_hcd) { 334 usb_remove_hcd(xhci->shared_hcd); 335 usb_put_hcd(xhci->shared_hcd); 336 } 337 338 /* Workaround for spurious wakeups at shutdown with HSW */ 339 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) 340 pci_set_power_state(dev, PCI_D3hot); 341 342 usb_hcd_pci_remove(dev); 343 } 344 345 #ifdef CONFIG_PM 346 /* 347 * In some Intel xHCI controllers, in order to get D3 working, 348 * through a vendor specific SSIC CONFIG register at offset 0x883c, 349 * SSIC PORT need to be marked as "unused" before putting xHCI 350 * into D3. After D3 exit, the SSIC port need to be marked as "used". 351 * Without this change, xHCI might not enter D3 state. 352 */ 353 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend) 354 { 355 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 356 u32 val; 357 void __iomem *reg; 358 int i; 359 360 for (i = 0; i < SSIC_PORT_NUM; i++) { 361 reg = (void __iomem *) xhci->cap_regs + 362 SSIC_PORT_CFG2 + 363 i * SSIC_PORT_CFG2_OFFSET; 364 365 /* Notify SSIC that SSIC profile programming is not done. */ 366 val = readl(reg) & ~PROG_DONE; 367 writel(val, reg); 368 369 /* Mark SSIC port as unused(suspend) or used(resume) */ 370 val = readl(reg); 371 if (suspend) 372 val |= SSIC_PORT_UNUSED; 373 else 374 val &= ~SSIC_PORT_UNUSED; 375 writel(val, reg); 376 377 /* Notify SSIC that SSIC profile programming is done */ 378 val = readl(reg) | PROG_DONE; 379 writel(val, reg); 380 readl(reg); 381 } 382 } 383 384 /* 385 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear 386 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4 387 */ 388 static void xhci_pme_quirk(struct usb_hcd *hcd) 389 { 390 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 391 void __iomem *reg; 392 u32 val; 393 394 reg = (void __iomem *) xhci->cap_regs + 0x80a4; 395 val = readl(reg); 396 writel(val | BIT(28), reg); 397 readl(reg); 398 } 399 400 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) 401 { 402 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 403 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 404 int ret; 405 406 /* 407 * Systems with the TI redriver that loses port status change events 408 * need to have the registers polled during D3, so avoid D3cold. 409 */ 410 if (xhci->quirks & XHCI_COMP_MODE_QUIRK) 411 pci_d3cold_disable(pdev); 412 413 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 414 xhci_pme_quirk(hcd); 415 416 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) 417 xhci_ssic_port_unused_quirk(hcd, true); 418 419 ret = xhci_suspend(xhci, do_wakeup); 420 if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED)) 421 xhci_ssic_port_unused_quirk(hcd, false); 422 423 return ret; 424 } 425 426 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated) 427 { 428 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 429 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 430 int retval = 0; 431 432 /* The BIOS on systems with the Intel Panther Point chipset may or may 433 * not support xHCI natively. That means that during system resume, it 434 * may switch the ports back to EHCI so that users can use their 435 * keyboard to select a kernel from GRUB after resume from hibernate. 436 * 437 * The BIOS is supposed to remember whether the OS had xHCI ports 438 * enabled before resume, and switch the ports back to xHCI when the 439 * BIOS/OS semaphore is written, but we all know we can't trust BIOS 440 * writers. 441 * 442 * Unconditionally switch the ports back to xHCI after a system resume. 443 * It should not matter whether the EHCI or xHCI controller is 444 * resumed first. It's enough to do the switchover in xHCI because 445 * USB core won't notice anything as the hub driver doesn't start 446 * running again until after all the devices (including both EHCI and 447 * xHCI host controllers) have been resumed. 448 */ 449 450 if (pdev->vendor == PCI_VENDOR_ID_INTEL) 451 usb_enable_intel_xhci_ports(pdev); 452 453 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) 454 xhci_ssic_port_unused_quirk(hcd, false); 455 456 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 457 xhci_pme_quirk(hcd); 458 459 retval = xhci_resume(xhci, hibernated); 460 return retval; 461 } 462 #endif /* CONFIG_PM */ 463 464 /*-------------------------------------------------------------------------*/ 465 466 /* PCI driver selection metadata; PCI hotplugging uses this */ 467 static const struct pci_device_id pci_ids[] = { { 468 /* handle any USB 3.0 xHCI controller */ 469 PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0), 470 .driver_data = (unsigned long) &xhci_pci_hc_driver, 471 }, 472 { /* end: all zeroes */ } 473 }; 474 MODULE_DEVICE_TABLE(pci, pci_ids); 475 476 /* pci driver glue; this is a "new style" PCI driver module */ 477 static struct pci_driver xhci_pci_driver = { 478 .name = (char *) hcd_name, 479 .id_table = pci_ids, 480 481 .probe = xhci_pci_probe, 482 .remove = xhci_pci_remove, 483 /* suspend and resume implemented later */ 484 485 .shutdown = usb_hcd_pci_shutdown, 486 #ifdef CONFIG_PM 487 .driver = { 488 .pm = &usb_hcd_pci_pm_ops 489 }, 490 #endif 491 }; 492 493 static int __init xhci_pci_init(void) 494 { 495 xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides); 496 #ifdef CONFIG_PM 497 xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend; 498 xhci_pci_hc_driver.pci_resume = xhci_pci_resume; 499 #endif 500 return pci_register_driver(&xhci_pci_driver); 501 } 502 module_init(xhci_pci_init); 503 504 static void __exit xhci_pci_exit(void) 505 { 506 pci_unregister_driver(&xhci_pci_driver); 507 } 508 module_exit(xhci_pci_exit); 509 510 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver"); 511 MODULE_LICENSE("GPL"); 512