1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) STMicroelectronics SA 2017 4 * 5 * Authors: Philippe Cornu <philippe.cornu@st.com> 6 * Yannick Fertre <yannick.fertre@st.com> 7 */ 8 9 #include <drm/drmP.h> 10 #include <drm/drm_mipi_dsi.h> 11 #include <drm/drm_panel.h> 12 #include <linux/backlight.h> 13 #include <linux/gpio/consumer.h> 14 #include <linux/regulator/consumer.h> 15 #include <video/mipi_display.h> 16 17 #define DRV_NAME "orisetech_otm8009a" 18 19 #define OTM8009A_BACKLIGHT_DEFAULT 240 20 #define OTM8009A_BACKLIGHT_MAX 255 21 22 /* Manufacturer Command Set */ 23 #define MCS_ADRSFT 0x0000 /* Address Shift Function */ 24 #define MCS_PANSET 0xB3A6 /* Panel Type Setting */ 25 #define MCS_SD_CTRL 0xC0A2 /* Source Driver Timing Setting */ 26 #define MCS_P_DRV_M 0xC0B4 /* Panel Driving Mode */ 27 #define MCS_OSC_ADJ 0xC181 /* Oscillator Adjustment for Idle/Normal mode */ 28 #define MCS_RGB_VID_SET 0xC1A1 /* RGB Video Mode Setting */ 29 #define MCS_SD_PCH_CTRL 0xC480 /* Source Driver Precharge Control */ 30 #define MCS_NO_DOC1 0xC48A /* Command not documented */ 31 #define MCS_PWR_CTRL1 0xC580 /* Power Control Setting 1 */ 32 #define MCS_PWR_CTRL2 0xC590 /* Power Control Setting 2 for Normal Mode */ 33 #define MCS_PWR_CTRL4 0xC5B0 /* Power Control Setting 4 for DC Voltage */ 34 #define MCS_PANCTRLSET1 0xCB80 /* Panel Control Setting 1 */ 35 #define MCS_PANCTRLSET2 0xCB90 /* Panel Control Setting 2 */ 36 #define MCS_PANCTRLSET3 0xCBA0 /* Panel Control Setting 3 */ 37 #define MCS_PANCTRLSET4 0xCBB0 /* Panel Control Setting 4 */ 38 #define MCS_PANCTRLSET5 0xCBC0 /* Panel Control Setting 5 */ 39 #define MCS_PANCTRLSET6 0xCBD0 /* Panel Control Setting 6 */ 40 #define MCS_PANCTRLSET7 0xCBE0 /* Panel Control Setting 7 */ 41 #define MCS_PANCTRLSET8 0xCBF0 /* Panel Control Setting 8 */ 42 #define MCS_PANU2D1 0xCC80 /* Panel U2D Setting 1 */ 43 #define MCS_PANU2D2 0xCC90 /* Panel U2D Setting 2 */ 44 #define MCS_PANU2D3 0xCCA0 /* Panel U2D Setting 3 */ 45 #define MCS_PAND2U1 0xCCB0 /* Panel D2U Setting 1 */ 46 #define MCS_PAND2U2 0xCCC0 /* Panel D2U Setting 2 */ 47 #define MCS_PAND2U3 0xCCD0 /* Panel D2U Setting 3 */ 48 #define MCS_GOAVST 0xCE80 /* GOA VST Setting */ 49 #define MCS_GOACLKA1 0xCEA0 /* GOA CLKA1 Setting */ 50 #define MCS_GOACLKA3 0xCEB0 /* GOA CLKA3 Setting */ 51 #define MCS_GOAECLK 0xCFC0 /* GOA ECLK Setting */ 52 #define MCS_NO_DOC2 0xCFD0 /* Command not documented */ 53 #define MCS_GVDDSET 0xD800 /* GVDD/NGVDD */ 54 #define MCS_VCOMDC 0xD900 /* VCOM Voltage Setting */ 55 #define MCS_GMCT2_2P 0xE100 /* Gamma Correction 2.2+ Setting */ 56 #define MCS_GMCT2_2N 0xE200 /* Gamma Correction 2.2- Setting */ 57 #define MCS_NO_DOC3 0xF5B6 /* Command not documented */ 58 #define MCS_CMD2_ENA1 0xFF00 /* Enable Access Command2 "CMD2" */ 59 #define MCS_CMD2_ENA2 0xFF80 /* Enable Access Orise Command2 */ 60 61 struct otm8009a { 62 struct device *dev; 63 struct drm_panel panel; 64 struct backlight_device *bl_dev; 65 struct gpio_desc *reset_gpio; 66 struct regulator *supply; 67 bool prepared; 68 bool enabled; 69 }; 70 71 static const struct drm_display_mode default_mode = { 72 .clock = 32729, 73 .hdisplay = 480, 74 .hsync_start = 480 + 120, 75 .hsync_end = 480 + 120 + 63, 76 .htotal = 480 + 120 + 63 + 120, 77 .vdisplay = 800, 78 .vsync_start = 800 + 12, 79 .vsync_end = 800 + 12 + 12, 80 .vtotal = 800 + 12 + 12 + 12, 81 .vrefresh = 50, 82 .flags = 0, 83 .width_mm = 52, 84 .height_mm = 86, 85 }; 86 87 static inline struct otm8009a *panel_to_otm8009a(struct drm_panel *panel) 88 { 89 return container_of(panel, struct otm8009a, panel); 90 } 91 92 static void otm8009a_dcs_write_buf(struct otm8009a *ctx, const void *data, 93 size_t len) 94 { 95 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); 96 97 if (mipi_dsi_dcs_write_buffer(dsi, data, len) < 0) 98 DRM_WARN("mipi dsi dcs write buffer failed\n"); 99 } 100 101 #define dcs_write_seq(ctx, seq...) \ 102 ({ \ 103 static const u8 d[] = { seq }; \ 104 otm8009a_dcs_write_buf(ctx, d, ARRAY_SIZE(d)); \ 105 }) 106 107 #define dcs_write_cmd_at(ctx, cmd, seq...) \ 108 ({ \ 109 dcs_write_seq(ctx, MCS_ADRSFT, (cmd) & 0xFF); \ 110 dcs_write_seq(ctx, (cmd) >> 8, seq); \ 111 }) 112 113 static int otm8009a_init_sequence(struct otm8009a *ctx) 114 { 115 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); 116 int ret; 117 118 /* Enter CMD2 */ 119 dcs_write_cmd_at(ctx, MCS_CMD2_ENA1, 0x80, 0x09, 0x01); 120 121 /* Enter Orise Command2 */ 122 dcs_write_cmd_at(ctx, MCS_CMD2_ENA2, 0x80, 0x09); 123 124 dcs_write_cmd_at(ctx, MCS_SD_PCH_CTRL, 0x30); 125 mdelay(10); 126 127 dcs_write_cmd_at(ctx, MCS_NO_DOC1, 0x40); 128 mdelay(10); 129 130 dcs_write_cmd_at(ctx, MCS_PWR_CTRL4 + 1, 0xA9); 131 dcs_write_cmd_at(ctx, MCS_PWR_CTRL2 + 1, 0x34); 132 dcs_write_cmd_at(ctx, MCS_P_DRV_M, 0x50); 133 dcs_write_cmd_at(ctx, MCS_VCOMDC, 0x4E); 134 dcs_write_cmd_at(ctx, MCS_OSC_ADJ, 0x66); /* 65Hz */ 135 dcs_write_cmd_at(ctx, MCS_PWR_CTRL2 + 2, 0x01); 136 dcs_write_cmd_at(ctx, MCS_PWR_CTRL2 + 5, 0x34); 137 dcs_write_cmd_at(ctx, MCS_PWR_CTRL2 + 4, 0x33); 138 dcs_write_cmd_at(ctx, MCS_GVDDSET, 0x79, 0x79); 139 dcs_write_cmd_at(ctx, MCS_SD_CTRL + 1, 0x1B); 140 dcs_write_cmd_at(ctx, MCS_PWR_CTRL1 + 2, 0x83); 141 dcs_write_cmd_at(ctx, MCS_SD_PCH_CTRL + 1, 0x83); 142 dcs_write_cmd_at(ctx, MCS_RGB_VID_SET, 0x0E); 143 dcs_write_cmd_at(ctx, MCS_PANSET, 0x00, 0x01); 144 145 dcs_write_cmd_at(ctx, MCS_GOAVST, 0x85, 0x01, 0x00, 0x84, 0x01, 0x00); 146 dcs_write_cmd_at(ctx, MCS_GOACLKA1, 0x18, 0x04, 0x03, 0x39, 0x00, 0x00, 147 0x00, 0x18, 0x03, 0x03, 0x3A, 0x00, 0x00, 0x00); 148 dcs_write_cmd_at(ctx, MCS_GOACLKA3, 0x18, 0x02, 0x03, 0x3B, 0x00, 0x00, 149 0x00, 0x18, 0x01, 0x03, 0x3C, 0x00, 0x00, 0x00); 150 dcs_write_cmd_at(ctx, MCS_GOAECLK, 0x01, 0x01, 0x20, 0x20, 0x00, 0x00, 151 0x01, 0x02, 0x00, 0x00); 152 153 dcs_write_cmd_at(ctx, MCS_NO_DOC2, 0x00); 154 155 dcs_write_cmd_at(ctx, MCS_PANCTRLSET1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); 156 dcs_write_cmd_at(ctx, MCS_PANCTRLSET2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 157 0, 0, 0, 0, 0); 158 dcs_write_cmd_at(ctx, MCS_PANCTRLSET3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 159 0, 0, 0, 0, 0); 160 dcs_write_cmd_at(ctx, MCS_PANCTRLSET4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); 161 dcs_write_cmd_at(ctx, MCS_PANCTRLSET5, 0, 4, 4, 4, 4, 4, 0, 0, 0, 0, 162 0, 0, 0, 0, 0); 163 dcs_write_cmd_at(ctx, MCS_PANCTRLSET6, 0, 0, 0, 0, 0, 0, 4, 4, 4, 4, 164 4, 0, 0, 0, 0); 165 dcs_write_cmd_at(ctx, MCS_PANCTRLSET7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); 166 dcs_write_cmd_at(ctx, MCS_PANCTRLSET8, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 167 0xFF, 0xFF, 0xFF, 0xFF, 0xFF); 168 169 dcs_write_cmd_at(ctx, MCS_PANU2D1, 0x00, 0x26, 0x09, 0x0B, 0x01, 0x25, 170 0x00, 0x00, 0x00, 0x00); 171 dcs_write_cmd_at(ctx, MCS_PANU2D2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 172 0x00, 0x00, 0x00, 0x00, 0x00, 0x26, 0x0A, 0x0C, 0x02); 173 dcs_write_cmd_at(ctx, MCS_PANU2D3, 0x25, 0x00, 0x00, 0x00, 0x00, 0x00, 174 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); 175 dcs_write_cmd_at(ctx, MCS_PAND2U1, 0x00, 0x25, 0x0C, 0x0A, 0x02, 0x26, 176 0x00, 0x00, 0x00, 0x00); 177 dcs_write_cmd_at(ctx, MCS_PAND2U2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 178 0x00, 0x00, 0x00, 0x00, 0x00, 0x25, 0x0B, 0x09, 0x01); 179 dcs_write_cmd_at(ctx, MCS_PAND2U3, 0x26, 0x00, 0x00, 0x00, 0x00, 0x00, 180 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); 181 182 dcs_write_cmd_at(ctx, MCS_PWR_CTRL1 + 1, 0x66); 183 184 dcs_write_cmd_at(ctx, MCS_NO_DOC3, 0x06); 185 186 dcs_write_cmd_at(ctx, MCS_GMCT2_2P, 0x00, 0x09, 0x0F, 0x0E, 0x07, 0x10, 187 0x0B, 0x0A, 0x04, 0x07, 0x0B, 0x08, 0x0F, 0x10, 0x0A, 188 0x01); 189 dcs_write_cmd_at(ctx, MCS_GMCT2_2N, 0x00, 0x09, 0x0F, 0x0E, 0x07, 0x10, 190 0x0B, 0x0A, 0x04, 0x07, 0x0B, 0x08, 0x0F, 0x10, 0x0A, 191 0x01); 192 193 /* Exit CMD2 */ 194 dcs_write_cmd_at(ctx, MCS_CMD2_ENA1, 0xFF, 0xFF, 0xFF); 195 196 ret = mipi_dsi_dcs_nop(dsi); 197 if (ret) 198 return ret; 199 200 ret = mipi_dsi_dcs_exit_sleep_mode(dsi); 201 if (ret) 202 return ret; 203 204 /* Wait for sleep out exit */ 205 mdelay(120); 206 207 /* Default portrait 480x800 rgb24 */ 208 dcs_write_seq(ctx, MIPI_DCS_SET_ADDRESS_MODE, 0x00); 209 210 ret = mipi_dsi_dcs_set_column_address(dsi, 0, 211 default_mode.hdisplay - 1); 212 if (ret) 213 return ret; 214 215 ret = mipi_dsi_dcs_set_page_address(dsi, 0, default_mode.vdisplay - 1); 216 if (ret) 217 return ret; 218 219 /* See otm8009a driver documentation for pixel format descriptions */ 220 ret = mipi_dsi_dcs_set_pixel_format(dsi, MIPI_DCS_PIXEL_FMT_24BIT | 221 MIPI_DCS_PIXEL_FMT_24BIT << 4); 222 if (ret) 223 return ret; 224 225 /* Disable CABC feature */ 226 dcs_write_seq(ctx, MIPI_DCS_WRITE_POWER_SAVE, 0x00); 227 228 ret = mipi_dsi_dcs_set_display_on(dsi); 229 if (ret) 230 return ret; 231 232 ret = mipi_dsi_dcs_nop(dsi); 233 if (ret) 234 return ret; 235 236 /* Send Command GRAM memory write (no parameters) */ 237 dcs_write_seq(ctx, MIPI_DCS_WRITE_MEMORY_START); 238 239 return 0; 240 } 241 242 static int otm8009a_disable(struct drm_panel *panel) 243 { 244 struct otm8009a *ctx = panel_to_otm8009a(panel); 245 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); 246 int ret; 247 248 if (!ctx->enabled) 249 return 0; /* This is not an issue so we return 0 here */ 250 251 /* Power off the backlight. Note: end-user still controls brightness */ 252 ctx->bl_dev->props.power = FB_BLANK_POWERDOWN; 253 ret = backlight_update_status(ctx->bl_dev); 254 if (ret) 255 return ret; 256 257 ret = mipi_dsi_dcs_set_display_off(dsi); 258 if (ret) 259 return ret; 260 261 ret = mipi_dsi_dcs_enter_sleep_mode(dsi); 262 if (ret) 263 return ret; 264 265 msleep(120); 266 267 ctx->enabled = false; 268 269 return 0; 270 } 271 272 static int otm8009a_unprepare(struct drm_panel *panel) 273 { 274 struct otm8009a *ctx = panel_to_otm8009a(panel); 275 276 if (!ctx->prepared) 277 return 0; 278 279 if (ctx->reset_gpio) { 280 gpiod_set_value_cansleep(ctx->reset_gpio, 1); 281 msleep(20); 282 } 283 284 regulator_disable(ctx->supply); 285 286 ctx->prepared = false; 287 288 return 0; 289 } 290 291 static int otm8009a_prepare(struct drm_panel *panel) 292 { 293 struct otm8009a *ctx = panel_to_otm8009a(panel); 294 int ret; 295 296 if (ctx->prepared) 297 return 0; 298 299 ret = regulator_enable(ctx->supply); 300 if (ret < 0) { 301 DRM_ERROR("failed to enable supply: %d\n", ret); 302 return ret; 303 } 304 305 if (ctx->reset_gpio) { 306 gpiod_set_value_cansleep(ctx->reset_gpio, 0); 307 gpiod_set_value_cansleep(ctx->reset_gpio, 1); 308 msleep(20); 309 gpiod_set_value_cansleep(ctx->reset_gpio, 0); 310 msleep(100); 311 } 312 313 ret = otm8009a_init_sequence(ctx); 314 if (ret) 315 return ret; 316 317 ctx->prepared = true; 318 319 /* 320 * Power on the backlight. Note: end-user still controls brightness 321 * Note: ctx->prepared must be true before updating the backlight. 322 */ 323 ctx->bl_dev->props.power = FB_BLANK_UNBLANK; 324 backlight_update_status(ctx->bl_dev); 325 326 return 0; 327 } 328 329 static int otm8009a_enable(struct drm_panel *panel) 330 { 331 struct otm8009a *ctx = panel_to_otm8009a(panel); 332 333 ctx->enabled = true; 334 335 return 0; 336 } 337 338 static int otm8009a_get_modes(struct drm_panel *panel) 339 { 340 struct drm_display_mode *mode; 341 342 mode = drm_mode_duplicate(panel->drm, &default_mode); 343 if (!mode) { 344 DRM_ERROR("failed to add mode %ux%ux@%u\n", 345 default_mode.hdisplay, default_mode.vdisplay, 346 default_mode.vrefresh); 347 return -ENOMEM; 348 } 349 350 drm_mode_set_name(mode); 351 352 mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED; 353 drm_mode_probed_add(panel->connector, mode); 354 355 panel->connector->display_info.width_mm = mode->width_mm; 356 panel->connector->display_info.height_mm = mode->height_mm; 357 358 return 1; 359 } 360 361 static const struct drm_panel_funcs otm8009a_drm_funcs = { 362 .disable = otm8009a_disable, 363 .unprepare = otm8009a_unprepare, 364 .prepare = otm8009a_prepare, 365 .enable = otm8009a_enable, 366 .get_modes = otm8009a_get_modes, 367 }; 368 369 /* 370 * DSI-BASED BACKLIGHT 371 */ 372 373 static int otm8009a_backlight_update_status(struct backlight_device *bd) 374 { 375 struct otm8009a *ctx = bl_get_data(bd); 376 u8 data[2]; 377 378 if (!ctx->prepared) { 379 DRM_DEBUG("lcd not ready yet for setting its backlight!\n"); 380 return -ENXIO; 381 } 382 383 if (bd->props.power <= FB_BLANK_NORMAL) { 384 /* Power on the backlight with the requested brightness 385 * Note We can not use mipi_dsi_dcs_set_display_brightness() 386 * as otm8009a driver support only 8-bit brightness (1 param). 387 */ 388 data[0] = MIPI_DCS_SET_DISPLAY_BRIGHTNESS; 389 data[1] = bd->props.brightness; 390 otm8009a_dcs_write_buf(ctx, data, ARRAY_SIZE(data)); 391 392 /* set Brightness Control & Backlight on */ 393 data[1] = 0x24; 394 395 } else { 396 /* Power off the backlight: set Brightness Control & Bl off */ 397 data[1] = 0; 398 } 399 400 /* Update Brightness Control & Backlight */ 401 data[0] = MIPI_DCS_WRITE_CONTROL_DISPLAY; 402 otm8009a_dcs_write_buf(ctx, data, ARRAY_SIZE(data)); 403 404 return 0; 405 } 406 407 static const struct backlight_ops otm8009a_backlight_ops = { 408 .update_status = otm8009a_backlight_update_status, 409 }; 410 411 static int otm8009a_probe(struct mipi_dsi_device *dsi) 412 { 413 struct device *dev = &dsi->dev; 414 struct otm8009a *ctx; 415 int ret; 416 417 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 418 if (!ctx) 419 return -ENOMEM; 420 421 ctx->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 422 if (IS_ERR(ctx->reset_gpio)) { 423 dev_err(dev, "cannot get reset-gpio\n"); 424 return PTR_ERR(ctx->reset_gpio); 425 } 426 427 ctx->supply = devm_regulator_get(dev, "power"); 428 if (IS_ERR(ctx->supply)) { 429 ret = PTR_ERR(ctx->supply); 430 dev_err(dev, "failed to request regulator: %d\n", ret); 431 return ret; 432 } 433 434 mipi_dsi_set_drvdata(dsi, ctx); 435 436 ctx->dev = dev; 437 438 dsi->lanes = 2; 439 dsi->format = MIPI_DSI_FMT_RGB888; 440 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 441 MIPI_DSI_MODE_LPM; 442 443 drm_panel_init(&ctx->panel); 444 ctx->panel.dev = dev; 445 ctx->panel.funcs = &otm8009a_drm_funcs; 446 447 ctx->bl_dev = backlight_device_register(DRV_NAME "_backlight", dev, ctx, 448 &otm8009a_backlight_ops, NULL); 449 if (IS_ERR(ctx->bl_dev)) { 450 dev_err(dev, "failed to register backlight device\n"); 451 return PTR_ERR(ctx->bl_dev); 452 } 453 454 ctx->bl_dev->props.max_brightness = OTM8009A_BACKLIGHT_MAX; 455 ctx->bl_dev->props.brightness = OTM8009A_BACKLIGHT_DEFAULT; 456 ctx->bl_dev->props.power = FB_BLANK_POWERDOWN; 457 ctx->bl_dev->props.type = BACKLIGHT_RAW; 458 459 drm_panel_add(&ctx->panel); 460 461 ret = mipi_dsi_attach(dsi); 462 if (ret < 0) { 463 dev_err(dev, "mipi_dsi_attach failed. Is host ready?\n"); 464 drm_panel_remove(&ctx->panel); 465 backlight_device_unregister(ctx->bl_dev); 466 return ret; 467 } 468 469 DRM_INFO(DRV_NAME "_panel %ux%u@%u %ubpp dsi %udl - ready\n", 470 default_mode.hdisplay, default_mode.vdisplay, 471 default_mode.vrefresh, 472 mipi_dsi_pixel_format_to_bpp(dsi->format), dsi->lanes); 473 474 return 0; 475 } 476 477 static int otm8009a_remove(struct mipi_dsi_device *dsi) 478 { 479 struct otm8009a *ctx = mipi_dsi_get_drvdata(dsi); 480 481 mipi_dsi_detach(dsi); 482 drm_panel_remove(&ctx->panel); 483 484 backlight_device_unregister(ctx->bl_dev); 485 486 return 0; 487 } 488 489 static const struct of_device_id orisetech_otm8009a_of_match[] = { 490 { .compatible = "orisetech,otm8009a" }, 491 { } 492 }; 493 MODULE_DEVICE_TABLE(of, orisetech_otm8009a_of_match); 494 495 static struct mipi_dsi_driver orisetech_otm8009a_driver = { 496 .probe = otm8009a_probe, 497 .remove = otm8009a_remove, 498 .driver = { 499 .name = DRV_NAME "_panel", 500 .of_match_table = orisetech_otm8009a_of_match, 501 }, 502 }; 503 module_mipi_dsi_driver(orisetech_otm8009a_driver); 504 505 MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>"); 506 MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>"); 507 MODULE_DESCRIPTION("DRM driver for Orise Tech OTM8009A MIPI DSI panel"); 508 MODULE_LICENSE("GPL v2"); 509