1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/ktime.h> 29 #include <linux/pagemap.h> 30 #include <drm/drmP.h> 31 #include <drm/amdgpu_drm.h> 32 #include "amdgpu.h" 33 34 void amdgpu_gem_object_free(struct drm_gem_object *gobj) 35 { 36 struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj); 37 38 if (robj) { 39 amdgpu_mn_unregister(robj); 40 amdgpu_bo_unref(&robj); 41 } 42 } 43 44 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, 45 int alignment, u32 initial_domain, 46 u64 flags, enum ttm_bo_type type, 47 struct reservation_object *resv, 48 struct drm_gem_object **obj) 49 { 50 struct amdgpu_bo *bo; 51 int r; 52 53 *obj = NULL; 54 /* At least align on page size */ 55 if (alignment < PAGE_SIZE) { 56 alignment = PAGE_SIZE; 57 } 58 59 r = amdgpu_bo_create(adev, size, alignment, initial_domain, 60 flags, type, resv, &bo); 61 if (r) { 62 DRM_DEBUG("Failed to allocate GEM object (%ld, %d, %u, %d)\n", 63 size, initial_domain, alignment, r); 64 return r; 65 } 66 *obj = &bo->gem_base; 67 68 return 0; 69 } 70 71 void amdgpu_gem_force_release(struct amdgpu_device *adev) 72 { 73 struct drm_device *ddev = adev->ddev; 74 struct drm_file *file; 75 76 mutex_lock(&ddev->filelist_mutex); 77 78 list_for_each_entry(file, &ddev->filelist, lhead) { 79 struct drm_gem_object *gobj; 80 int handle; 81 82 WARN_ONCE(1, "Still active user space clients!\n"); 83 spin_lock(&file->table_lock); 84 idr_for_each_entry(&file->object_idr, gobj, handle) { 85 WARN_ONCE(1, "And also active allocations!\n"); 86 drm_gem_object_put_unlocked(gobj); 87 } 88 idr_destroy(&file->object_idr); 89 spin_unlock(&file->table_lock); 90 } 91 92 mutex_unlock(&ddev->filelist_mutex); 93 } 94 95 /* 96 * Call from drm_gem_handle_create which appear in both new and open ioctl 97 * case. 98 */ 99 int amdgpu_gem_object_open(struct drm_gem_object *obj, 100 struct drm_file *file_priv) 101 { 102 struct amdgpu_bo *abo = gem_to_amdgpu_bo(obj); 103 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 104 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 105 struct amdgpu_vm *vm = &fpriv->vm; 106 struct amdgpu_bo_va *bo_va; 107 struct mm_struct *mm; 108 int r; 109 110 mm = amdgpu_ttm_tt_get_usermm(abo->tbo.ttm); 111 if (mm && mm != current->mm) 112 return -EPERM; 113 114 if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID && 115 abo->tbo.resv != vm->root.base.bo->tbo.resv) 116 return -EPERM; 117 118 r = amdgpu_bo_reserve(abo, false); 119 if (r) 120 return r; 121 122 bo_va = amdgpu_vm_bo_find(vm, abo); 123 if (!bo_va) { 124 bo_va = amdgpu_vm_bo_add(adev, vm, abo); 125 } else { 126 ++bo_va->ref_count; 127 } 128 amdgpu_bo_unreserve(abo); 129 return 0; 130 } 131 132 void amdgpu_gem_object_close(struct drm_gem_object *obj, 133 struct drm_file *file_priv) 134 { 135 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); 136 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 137 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 138 struct amdgpu_vm *vm = &fpriv->vm; 139 140 struct amdgpu_bo_list_entry vm_pd; 141 struct list_head list, duplicates; 142 struct ttm_validate_buffer tv; 143 struct ww_acquire_ctx ticket; 144 struct amdgpu_bo_va *bo_va; 145 int r; 146 147 INIT_LIST_HEAD(&list); 148 INIT_LIST_HEAD(&duplicates); 149 150 tv.bo = &bo->tbo; 151 tv.shared = true; 152 list_add(&tv.head, &list); 153 154 amdgpu_vm_get_pd_bo(vm, &list, &vm_pd); 155 156 r = ttm_eu_reserve_buffers(&ticket, &list, false, &duplicates); 157 if (r) { 158 dev_err(adev->dev, "leaking bo va because " 159 "we fail to reserve bo (%d)\n", r); 160 return; 161 } 162 bo_va = amdgpu_vm_bo_find(vm, bo); 163 if (bo_va && --bo_va->ref_count == 0) { 164 amdgpu_vm_bo_rmv(adev, bo_va); 165 166 if (amdgpu_vm_ready(vm)) { 167 struct dma_fence *fence = NULL; 168 169 r = amdgpu_vm_clear_freed(adev, vm, &fence); 170 if (unlikely(r)) { 171 dev_err(adev->dev, "failed to clear page " 172 "tables on GEM object close (%d)\n", r); 173 } 174 175 if (fence) { 176 amdgpu_bo_fence(bo, fence, true); 177 dma_fence_put(fence); 178 } 179 } 180 } 181 ttm_eu_backoff_reservation(&ticket, &list); 182 } 183 184 /* 185 * GEM ioctls. 186 */ 187 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, 188 struct drm_file *filp) 189 { 190 struct amdgpu_device *adev = dev->dev_private; 191 struct amdgpu_fpriv *fpriv = filp->driver_priv; 192 struct amdgpu_vm *vm = &fpriv->vm; 193 union drm_amdgpu_gem_create *args = data; 194 uint64_t flags = args->in.domain_flags; 195 uint64_t size = args->in.bo_size; 196 struct reservation_object *resv = NULL; 197 struct drm_gem_object *gobj; 198 uint32_t handle; 199 int r; 200 201 /* reject invalid gem flags */ 202 if (flags & ~(AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | 203 AMDGPU_GEM_CREATE_NO_CPU_ACCESS | 204 AMDGPU_GEM_CREATE_CPU_GTT_USWC | 205 AMDGPU_GEM_CREATE_VRAM_CLEARED | 206 AMDGPU_GEM_CREATE_VM_ALWAYS_VALID | 207 AMDGPU_GEM_CREATE_EXPLICIT_SYNC)) 208 209 return -EINVAL; 210 211 /* reject invalid gem domains */ 212 if (args->in.domains & ~(AMDGPU_GEM_DOMAIN_CPU | 213 AMDGPU_GEM_DOMAIN_GTT | 214 AMDGPU_GEM_DOMAIN_VRAM | 215 AMDGPU_GEM_DOMAIN_GDS | 216 AMDGPU_GEM_DOMAIN_GWS | 217 AMDGPU_GEM_DOMAIN_OA)) 218 return -EINVAL; 219 220 /* create a gem object to contain this object in */ 221 if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS | 222 AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) { 223 flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS; 224 if (args->in.domains == AMDGPU_GEM_DOMAIN_GDS) 225 size = size << AMDGPU_GDS_SHIFT; 226 else if (args->in.domains == AMDGPU_GEM_DOMAIN_GWS) 227 size = size << AMDGPU_GWS_SHIFT; 228 else if (args->in.domains == AMDGPU_GEM_DOMAIN_OA) 229 size = size << AMDGPU_OA_SHIFT; 230 else 231 return -EINVAL; 232 } 233 size = roundup(size, PAGE_SIZE); 234 235 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { 236 r = amdgpu_bo_reserve(vm->root.base.bo, false); 237 if (r) 238 return r; 239 240 resv = vm->root.base.bo->tbo.resv; 241 } 242 243 r = amdgpu_gem_object_create(adev, size, args->in.alignment, 244 (u32)(0xffffffff & args->in.domains), 245 flags, false, resv, &gobj); 246 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { 247 if (!r) { 248 struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj); 249 250 abo->parent = amdgpu_bo_ref(vm->root.base.bo); 251 } 252 amdgpu_bo_unreserve(vm->root.base.bo); 253 } 254 if (r) 255 return r; 256 257 r = drm_gem_handle_create(filp, gobj, &handle); 258 /* drop reference from allocate - handle holds it now */ 259 drm_gem_object_put_unlocked(gobj); 260 if (r) 261 return r; 262 263 memset(args, 0, sizeof(*args)); 264 args->out.handle = handle; 265 return 0; 266 } 267 268 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, 269 struct drm_file *filp) 270 { 271 struct ttm_operation_ctx ctx = { true, false }; 272 struct amdgpu_device *adev = dev->dev_private; 273 struct drm_amdgpu_gem_userptr *args = data; 274 struct drm_gem_object *gobj; 275 struct amdgpu_bo *bo; 276 uint32_t handle; 277 int r; 278 279 if (offset_in_page(args->addr | args->size)) 280 return -EINVAL; 281 282 /* reject unknown flag values */ 283 if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY | 284 AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE | 285 AMDGPU_GEM_USERPTR_REGISTER)) 286 return -EINVAL; 287 288 if (!(args->flags & AMDGPU_GEM_USERPTR_READONLY) && 289 !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) { 290 291 /* if we want to write to it we must install a MMU notifier */ 292 return -EACCES; 293 } 294 295 /* create a gem object to contain this object in */ 296 r = amdgpu_gem_object_create(adev, args->size, 0, AMDGPU_GEM_DOMAIN_CPU, 297 0, 0, NULL, &gobj); 298 if (r) 299 return r; 300 301 bo = gem_to_amdgpu_bo(gobj); 302 bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT; 303 bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT; 304 r = amdgpu_ttm_tt_set_userptr(bo->tbo.ttm, args->addr, args->flags); 305 if (r) 306 goto release_object; 307 308 if (args->flags & AMDGPU_GEM_USERPTR_REGISTER) { 309 r = amdgpu_mn_register(bo, args->addr); 310 if (r) 311 goto release_object; 312 } 313 314 if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) { 315 r = amdgpu_ttm_tt_get_user_pages(bo->tbo.ttm, 316 bo->tbo.ttm->pages); 317 if (r) 318 goto release_object; 319 320 r = amdgpu_bo_reserve(bo, true); 321 if (r) 322 goto free_pages; 323 324 amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT); 325 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 326 amdgpu_bo_unreserve(bo); 327 if (r) 328 goto free_pages; 329 } 330 331 r = drm_gem_handle_create(filp, gobj, &handle); 332 /* drop reference from allocate - handle holds it now */ 333 drm_gem_object_put_unlocked(gobj); 334 if (r) 335 return r; 336 337 args->handle = handle; 338 return 0; 339 340 free_pages: 341 release_pages(bo->tbo.ttm->pages, bo->tbo.ttm->num_pages); 342 343 release_object: 344 drm_gem_object_put_unlocked(gobj); 345 346 return r; 347 } 348 349 int amdgpu_mode_dumb_mmap(struct drm_file *filp, 350 struct drm_device *dev, 351 uint32_t handle, uint64_t *offset_p) 352 { 353 struct drm_gem_object *gobj; 354 struct amdgpu_bo *robj; 355 356 gobj = drm_gem_object_lookup(filp, handle); 357 if (gobj == NULL) { 358 return -ENOENT; 359 } 360 robj = gem_to_amdgpu_bo(gobj); 361 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm) || 362 (robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) { 363 drm_gem_object_put_unlocked(gobj); 364 return -EPERM; 365 } 366 *offset_p = amdgpu_bo_mmap_offset(robj); 367 drm_gem_object_put_unlocked(gobj); 368 return 0; 369 } 370 371 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, 372 struct drm_file *filp) 373 { 374 union drm_amdgpu_gem_mmap *args = data; 375 uint32_t handle = args->in.handle; 376 memset(args, 0, sizeof(*args)); 377 return amdgpu_mode_dumb_mmap(filp, dev, handle, &args->out.addr_ptr); 378 } 379 380 /** 381 * amdgpu_gem_timeout - calculate jiffies timeout from absolute value 382 * 383 * @timeout_ns: timeout in ns 384 * 385 * Calculate the timeout in jiffies from an absolute timeout in ns. 386 */ 387 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns) 388 { 389 unsigned long timeout_jiffies; 390 ktime_t timeout; 391 392 /* clamp timeout if it's to large */ 393 if (((int64_t)timeout_ns) < 0) 394 return MAX_SCHEDULE_TIMEOUT; 395 396 timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get()); 397 if (ktime_to_ns(timeout) < 0) 398 return 0; 399 400 timeout_jiffies = nsecs_to_jiffies(ktime_to_ns(timeout)); 401 /* clamp timeout to avoid unsigned-> signed overflow */ 402 if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT ) 403 return MAX_SCHEDULE_TIMEOUT - 1; 404 405 return timeout_jiffies; 406 } 407 408 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 409 struct drm_file *filp) 410 { 411 union drm_amdgpu_gem_wait_idle *args = data; 412 struct drm_gem_object *gobj; 413 struct amdgpu_bo *robj; 414 uint32_t handle = args->in.handle; 415 unsigned long timeout = amdgpu_gem_timeout(args->in.timeout); 416 int r = 0; 417 long ret; 418 419 gobj = drm_gem_object_lookup(filp, handle); 420 if (gobj == NULL) { 421 return -ENOENT; 422 } 423 robj = gem_to_amdgpu_bo(gobj); 424 ret = reservation_object_wait_timeout_rcu(robj->tbo.resv, true, true, 425 timeout); 426 427 /* ret == 0 means not signaled, 428 * ret > 0 means signaled 429 * ret < 0 means interrupted before timeout 430 */ 431 if (ret >= 0) { 432 memset(args, 0, sizeof(*args)); 433 args->out.status = (ret == 0); 434 } else 435 r = ret; 436 437 drm_gem_object_put_unlocked(gobj); 438 return r; 439 } 440 441 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, 442 struct drm_file *filp) 443 { 444 struct drm_amdgpu_gem_metadata *args = data; 445 struct drm_gem_object *gobj; 446 struct amdgpu_bo *robj; 447 int r = -1; 448 449 DRM_DEBUG("%d \n", args->handle); 450 gobj = drm_gem_object_lookup(filp, args->handle); 451 if (gobj == NULL) 452 return -ENOENT; 453 robj = gem_to_amdgpu_bo(gobj); 454 455 r = amdgpu_bo_reserve(robj, false); 456 if (unlikely(r != 0)) 457 goto out; 458 459 if (args->op == AMDGPU_GEM_METADATA_OP_GET_METADATA) { 460 amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info); 461 r = amdgpu_bo_get_metadata(robj, args->data.data, 462 sizeof(args->data.data), 463 &args->data.data_size_bytes, 464 &args->data.flags); 465 } else if (args->op == AMDGPU_GEM_METADATA_OP_SET_METADATA) { 466 if (args->data.data_size_bytes > sizeof(args->data.data)) { 467 r = -EINVAL; 468 goto unreserve; 469 } 470 r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info); 471 if (!r) 472 r = amdgpu_bo_set_metadata(robj, args->data.data, 473 args->data.data_size_bytes, 474 args->data.flags); 475 } 476 477 unreserve: 478 amdgpu_bo_unreserve(robj); 479 out: 480 drm_gem_object_put_unlocked(gobj); 481 return r; 482 } 483 484 /** 485 * amdgpu_gem_va_update_vm -update the bo_va in its VM 486 * 487 * @adev: amdgpu_device pointer 488 * @vm: vm to update 489 * @bo_va: bo_va to update 490 * @list: validation list 491 * @operation: map, unmap or clear 492 * 493 * Update the bo_va directly after setting its address. Errors are not 494 * vital here, so they are not reported back to userspace. 495 */ 496 static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev, 497 struct amdgpu_vm *vm, 498 struct amdgpu_bo_va *bo_va, 499 struct list_head *list, 500 uint32_t operation) 501 { 502 int r; 503 504 if (!amdgpu_vm_ready(vm)) 505 return; 506 507 r = amdgpu_vm_clear_freed(adev, vm, NULL); 508 if (r) 509 goto error; 510 511 if (operation == AMDGPU_VA_OP_MAP || 512 operation == AMDGPU_VA_OP_REPLACE) { 513 r = amdgpu_vm_bo_update(adev, bo_va, false); 514 if (r) 515 goto error; 516 } 517 518 r = amdgpu_vm_update_directories(adev, vm); 519 520 error: 521 if (r && r != -ERESTARTSYS) 522 DRM_ERROR("Couldn't update BO_VA (%d)\n", r); 523 } 524 525 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, 526 struct drm_file *filp) 527 { 528 const uint32_t valid_flags = AMDGPU_VM_DELAY_UPDATE | 529 AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE | 530 AMDGPU_VM_PAGE_EXECUTABLE | AMDGPU_VM_MTYPE_MASK; 531 const uint32_t prt_flags = AMDGPU_VM_DELAY_UPDATE | 532 AMDGPU_VM_PAGE_PRT; 533 534 struct drm_amdgpu_gem_va *args = data; 535 struct drm_gem_object *gobj; 536 struct amdgpu_device *adev = dev->dev_private; 537 struct amdgpu_fpriv *fpriv = filp->driver_priv; 538 struct amdgpu_bo *abo; 539 struct amdgpu_bo_va *bo_va; 540 struct amdgpu_bo_list_entry vm_pd; 541 struct ttm_validate_buffer tv; 542 struct ww_acquire_ctx ticket; 543 struct list_head list, duplicates; 544 uint64_t va_flags; 545 int r = 0; 546 547 if (args->va_address < AMDGPU_VA_RESERVED_SIZE) { 548 dev_dbg(&dev->pdev->dev, 549 "va_address 0x%LX is in reserved area 0x%LX\n", 550 args->va_address, AMDGPU_VA_RESERVED_SIZE); 551 return -EINVAL; 552 } 553 554 if (args->va_address >= AMDGPU_VA_HOLE_START && 555 args->va_address < AMDGPU_VA_HOLE_END) { 556 dev_dbg(&dev->pdev->dev, 557 "va_address 0x%LX is in VA hole 0x%LX-0x%LX\n", 558 args->va_address, AMDGPU_VA_HOLE_START, 559 AMDGPU_VA_HOLE_END); 560 return -EINVAL; 561 } 562 563 args->va_address &= AMDGPU_VA_HOLE_MASK; 564 565 if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) { 566 dev_dbg(&dev->pdev->dev, "invalid flags combination 0x%08X\n", 567 args->flags); 568 return -EINVAL; 569 } 570 571 switch (args->operation) { 572 case AMDGPU_VA_OP_MAP: 573 case AMDGPU_VA_OP_UNMAP: 574 case AMDGPU_VA_OP_CLEAR: 575 case AMDGPU_VA_OP_REPLACE: 576 break; 577 default: 578 dev_dbg(&dev->pdev->dev, "unsupported operation %d\n", 579 args->operation); 580 return -EINVAL; 581 } 582 583 INIT_LIST_HEAD(&list); 584 INIT_LIST_HEAD(&duplicates); 585 if ((args->operation != AMDGPU_VA_OP_CLEAR) && 586 !(args->flags & AMDGPU_VM_PAGE_PRT)) { 587 gobj = drm_gem_object_lookup(filp, args->handle); 588 if (gobj == NULL) 589 return -ENOENT; 590 abo = gem_to_amdgpu_bo(gobj); 591 tv.bo = &abo->tbo; 592 tv.shared = false; 593 list_add(&tv.head, &list); 594 } else { 595 gobj = NULL; 596 abo = NULL; 597 } 598 599 amdgpu_vm_get_pd_bo(&fpriv->vm, &list, &vm_pd); 600 601 r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates); 602 if (r) 603 goto error_unref; 604 605 if (abo) { 606 bo_va = amdgpu_vm_bo_find(&fpriv->vm, abo); 607 if (!bo_va) { 608 r = -ENOENT; 609 goto error_backoff; 610 } 611 } else if (args->operation != AMDGPU_VA_OP_CLEAR) { 612 bo_va = fpriv->prt_va; 613 } else { 614 bo_va = NULL; 615 } 616 617 switch (args->operation) { 618 case AMDGPU_VA_OP_MAP: 619 r = amdgpu_vm_alloc_pts(adev, bo_va->base.vm, args->va_address, 620 args->map_size); 621 if (r) 622 goto error_backoff; 623 624 va_flags = amdgpu_gmc_get_pte_flags(adev, args->flags); 625 r = amdgpu_vm_bo_map(adev, bo_va, args->va_address, 626 args->offset_in_bo, args->map_size, 627 va_flags); 628 break; 629 case AMDGPU_VA_OP_UNMAP: 630 r = amdgpu_vm_bo_unmap(adev, bo_va, args->va_address); 631 break; 632 633 case AMDGPU_VA_OP_CLEAR: 634 r = amdgpu_vm_bo_clear_mappings(adev, &fpriv->vm, 635 args->va_address, 636 args->map_size); 637 break; 638 case AMDGPU_VA_OP_REPLACE: 639 r = amdgpu_vm_alloc_pts(adev, bo_va->base.vm, args->va_address, 640 args->map_size); 641 if (r) 642 goto error_backoff; 643 644 va_flags = amdgpu_gmc_get_pte_flags(adev, args->flags); 645 r = amdgpu_vm_bo_replace_map(adev, bo_va, args->va_address, 646 args->offset_in_bo, args->map_size, 647 va_flags); 648 break; 649 default: 650 break; 651 } 652 if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) && !amdgpu_vm_debug) 653 amdgpu_gem_va_update_vm(adev, &fpriv->vm, bo_va, &list, 654 args->operation); 655 656 error_backoff: 657 ttm_eu_backoff_reservation(&ticket, &list); 658 659 error_unref: 660 drm_gem_object_put_unlocked(gobj); 661 return r; 662 } 663 664 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, 665 struct drm_file *filp) 666 { 667 struct amdgpu_device *adev = dev->dev_private; 668 struct drm_amdgpu_gem_op *args = data; 669 struct drm_gem_object *gobj; 670 struct amdgpu_bo *robj; 671 int r; 672 673 gobj = drm_gem_object_lookup(filp, args->handle); 674 if (gobj == NULL) { 675 return -ENOENT; 676 } 677 robj = gem_to_amdgpu_bo(gobj); 678 679 r = amdgpu_bo_reserve(robj, false); 680 if (unlikely(r)) 681 goto out; 682 683 switch (args->op) { 684 case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: { 685 struct drm_amdgpu_gem_create_in info; 686 void __user *out = u64_to_user_ptr(args->value); 687 688 info.bo_size = robj->gem_base.size; 689 info.alignment = robj->tbo.mem.page_alignment << PAGE_SHIFT; 690 info.domains = robj->preferred_domains; 691 info.domain_flags = robj->flags; 692 amdgpu_bo_unreserve(robj); 693 if (copy_to_user(out, &info, sizeof(info))) 694 r = -EFAULT; 695 break; 696 } 697 case AMDGPU_GEM_OP_SET_PLACEMENT: 698 if (robj->prime_shared_count && (args->value & AMDGPU_GEM_DOMAIN_VRAM)) { 699 r = -EINVAL; 700 amdgpu_bo_unreserve(robj); 701 break; 702 } 703 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm)) { 704 r = -EPERM; 705 amdgpu_bo_unreserve(robj); 706 break; 707 } 708 robj->preferred_domains = args->value & (AMDGPU_GEM_DOMAIN_VRAM | 709 AMDGPU_GEM_DOMAIN_GTT | 710 AMDGPU_GEM_DOMAIN_CPU); 711 robj->allowed_domains = robj->preferred_domains; 712 if (robj->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM) 713 robj->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT; 714 715 if (robj->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) 716 amdgpu_vm_bo_invalidate(adev, robj, true); 717 718 amdgpu_bo_unreserve(robj); 719 break; 720 default: 721 amdgpu_bo_unreserve(robj); 722 r = -EINVAL; 723 } 724 725 out: 726 drm_gem_object_put_unlocked(gobj); 727 return r; 728 } 729 730 int amdgpu_mode_dumb_create(struct drm_file *file_priv, 731 struct drm_device *dev, 732 struct drm_mode_create_dumb *args) 733 { 734 struct amdgpu_device *adev = dev->dev_private; 735 struct drm_gem_object *gobj; 736 uint32_t handle; 737 int r; 738 739 args->pitch = amdgpu_align_pitch(adev, args->width, 740 DIV_ROUND_UP(args->bpp, 8), 0); 741 args->size = (u64)args->pitch * args->height; 742 args->size = ALIGN(args->size, PAGE_SIZE); 743 744 r = amdgpu_gem_object_create(adev, args->size, 0, 745 AMDGPU_GEM_DOMAIN_VRAM, 746 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, 747 false, NULL, &gobj); 748 if (r) 749 return -ENOMEM; 750 751 r = drm_gem_handle_create(file_priv, gobj, &handle); 752 /* drop reference from allocate - handle holds it now */ 753 drm_gem_object_put_unlocked(gobj); 754 if (r) { 755 return r; 756 } 757 args->handle = handle; 758 return 0; 759 } 760 761 #if defined(CONFIG_DEBUG_FS) 762 static int amdgpu_debugfs_gem_bo_info(int id, void *ptr, void *data) 763 { 764 struct drm_gem_object *gobj = ptr; 765 struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj); 766 struct seq_file *m = data; 767 768 unsigned domain; 769 const char *placement; 770 unsigned pin_count; 771 uint64_t offset; 772 773 domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type); 774 switch (domain) { 775 case AMDGPU_GEM_DOMAIN_VRAM: 776 placement = "VRAM"; 777 break; 778 case AMDGPU_GEM_DOMAIN_GTT: 779 placement = " GTT"; 780 break; 781 case AMDGPU_GEM_DOMAIN_CPU: 782 default: 783 placement = " CPU"; 784 break; 785 } 786 seq_printf(m, "\t0x%08x: %12ld byte %s", 787 id, amdgpu_bo_size(bo), placement); 788 789 offset = READ_ONCE(bo->tbo.mem.start); 790 if (offset != AMDGPU_BO_INVALID_OFFSET) 791 seq_printf(m, " @ 0x%010Lx", offset); 792 793 pin_count = READ_ONCE(bo->pin_count); 794 if (pin_count) 795 seq_printf(m, " pin count %d", pin_count); 796 seq_printf(m, "\n"); 797 798 return 0; 799 } 800 801 static int amdgpu_debugfs_gem_info(struct seq_file *m, void *data) 802 { 803 struct drm_info_node *node = (struct drm_info_node *)m->private; 804 struct drm_device *dev = node->minor->dev; 805 struct drm_file *file; 806 int r; 807 808 r = mutex_lock_interruptible(&dev->filelist_mutex); 809 if (r) 810 return r; 811 812 list_for_each_entry(file, &dev->filelist, lhead) { 813 struct task_struct *task; 814 815 /* 816 * Although we have a valid reference on file->pid, that does 817 * not guarantee that the task_struct who called get_pid() is 818 * still alive (e.g. get_pid(current) => fork() => exit()). 819 * Therefore, we need to protect this ->comm access using RCU. 820 */ 821 rcu_read_lock(); 822 task = pid_task(file->pid, PIDTYPE_PID); 823 seq_printf(m, "pid %8d command %s:\n", pid_nr(file->pid), 824 task ? task->comm : "<unknown>"); 825 rcu_read_unlock(); 826 827 spin_lock(&file->table_lock); 828 idr_for_each(&file->object_idr, amdgpu_debugfs_gem_bo_info, m); 829 spin_unlock(&file->table_lock); 830 } 831 832 mutex_unlock(&dev->filelist_mutex); 833 return 0; 834 } 835 836 static const struct drm_info_list amdgpu_debugfs_gem_list[] = { 837 {"amdgpu_gem_info", &amdgpu_debugfs_gem_info, 0, NULL}, 838 }; 839 #endif 840 841 int amdgpu_debugfs_gem_init(struct amdgpu_device *adev) 842 { 843 #if defined(CONFIG_DEBUG_FS) 844 return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_gem_list, 1); 845 #endif 846 return 0; 847 } 848