1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "reg_helper.h" 27 #include "dce_audio.h" 28 #include "dce/dce_11_0_d.h" 29 #include "dce/dce_11_0_sh_mask.h" 30 31 #define DCE_AUD(audio)\ 32 container_of(audio, struct dce_audio, base) 33 34 #define CTX \ 35 aud->base.ctx 36 #define DC_LOGGER \ 37 aud->base.ctx->logger 38 #define REG(reg)\ 39 (aud->regs->reg) 40 41 #undef FN 42 #define FN(reg_name, field_name) \ 43 aud->shifts->field_name, aud->masks->field_name 44 45 #define IX_REG(reg)\ 46 ix ## reg 47 48 #define AZ_REG_READ(reg_name) \ 49 read_indirect_azalia_reg(audio, IX_REG(reg_name)) 50 51 #define AZ_REG_WRITE(reg_name, value) \ 52 write_indirect_azalia_reg(audio, IX_REG(reg_name), value) 53 54 static void write_indirect_azalia_reg(struct audio *audio, 55 uint32_t reg_index, 56 uint32_t reg_data) 57 { 58 struct dce_audio *aud = DCE_AUD(audio); 59 60 /* AZALIA_F0_CODEC_ENDPOINT_INDEX endpoint index */ 61 REG_SET(AZALIA_F0_CODEC_ENDPOINT_INDEX, 0, 62 AZALIA_ENDPOINT_REG_INDEX, reg_index); 63 64 /* AZALIA_F0_CODEC_ENDPOINT_DATA endpoint data */ 65 REG_SET(AZALIA_F0_CODEC_ENDPOINT_DATA, 0, 66 AZALIA_ENDPOINT_REG_DATA, reg_data); 67 68 DC_LOG_HW_AUDIO("AUDIO:write_indirect_azalia_reg: index: %u data: %u\n", 69 reg_index, reg_data); 70 } 71 72 static uint32_t read_indirect_azalia_reg(struct audio *audio, uint32_t reg_index) 73 { 74 struct dce_audio *aud = DCE_AUD(audio); 75 76 uint32_t value = 0; 77 78 /* AZALIA_F0_CODEC_ENDPOINT_INDEX endpoint index */ 79 REG_SET(AZALIA_F0_CODEC_ENDPOINT_INDEX, 0, 80 AZALIA_ENDPOINT_REG_INDEX, reg_index); 81 82 /* AZALIA_F0_CODEC_ENDPOINT_DATA endpoint data */ 83 value = REG_READ(AZALIA_F0_CODEC_ENDPOINT_DATA); 84 85 DC_LOG_HW_AUDIO("AUDIO:read_indirect_azalia_reg: index: %u data: %u\n", 86 reg_index, value); 87 88 return value; 89 } 90 91 static bool is_audio_format_supported( 92 const struct audio_info *audio_info, 93 enum audio_format_code audio_format_code, 94 uint32_t *format_index) 95 { 96 uint32_t index; 97 uint32_t max_channe_index = 0; 98 bool found = false; 99 100 if (audio_info == NULL) 101 return found; 102 103 /* pass through whole array */ 104 for (index = 0; index < audio_info->mode_count; index++) { 105 if (audio_info->modes[index].format_code == audio_format_code) { 106 if (found) { 107 /* format has multiply entries, choose one with 108 * highst number of channels */ 109 if (audio_info->modes[index].channel_count > 110 audio_info->modes[max_channe_index].channel_count) { 111 max_channe_index = index; 112 } 113 } else { 114 /* format found, save it's index */ 115 found = true; 116 max_channe_index = index; 117 } 118 } 119 } 120 121 /* return index */ 122 if (found && format_index != NULL) 123 *format_index = max_channe_index; 124 125 return found; 126 } 127 128 /*For HDMI, calculate if specified sample rates can fit into a given timing */ 129 static void check_audio_bandwidth_hdmi( 130 const struct audio_crtc_info *crtc_info, 131 uint32_t channel_count, 132 union audio_sample_rates *sample_rates) 133 { 134 uint32_t samples; 135 uint32_t h_blank; 136 bool limit_freq_to_48_khz = false; 137 bool limit_freq_to_88_2_khz = false; 138 bool limit_freq_to_96_khz = false; 139 bool limit_freq_to_174_4_khz = false; 140 141 /* For two channels supported return whatever sink support,unmodified*/ 142 if (channel_count > 2) { 143 144 /* Based on HDMI spec 1.3 Table 7.5 */ 145 if ((crtc_info->requested_pixel_clock <= 27000) && 146 (crtc_info->v_active <= 576) && 147 !(crtc_info->interlaced) && 148 !(crtc_info->pixel_repetition == 2 || 149 crtc_info->pixel_repetition == 4)) { 150 limit_freq_to_48_khz = true; 151 152 } else if ((crtc_info->requested_pixel_clock <= 27000) && 153 (crtc_info->v_active <= 576) && 154 (crtc_info->interlaced) && 155 (crtc_info->pixel_repetition == 2)) { 156 limit_freq_to_88_2_khz = true; 157 158 } else if ((crtc_info->requested_pixel_clock <= 54000) && 159 (crtc_info->v_active <= 576) && 160 !(crtc_info->interlaced)) { 161 limit_freq_to_174_4_khz = true; 162 } 163 } 164 165 /* Also do some calculation for the available Audio Bandwidth for the 166 * 8 ch (i.e. for the Layout 1 => ch > 2) 167 */ 168 h_blank = crtc_info->h_total - crtc_info->h_active; 169 170 if (crtc_info->pixel_repetition) 171 h_blank *= crtc_info->pixel_repetition; 172 173 /*based on HDMI spec 1.3 Table 7.5 */ 174 h_blank -= 58; 175 /*for Control Period */ 176 h_blank -= 16; 177 178 samples = h_blank * 10; 179 /* Number of Audio Packets (multiplied by 10) per Line (for 8 ch number 180 * of Audio samples per line multiplied by 10 - Layout 1) 181 */ 182 samples /= 32; 183 samples *= crtc_info->v_active; 184 /*Number of samples multiplied by 10, per second */ 185 samples *= crtc_info->refresh_rate; 186 /*Number of Audio samples per second */ 187 samples /= 10; 188 189 /* @todo do it after deep color is implemented 190 * 8xx - deep color bandwidth scaling 191 * Extra bandwidth is avaliable in deep color b/c link runs faster than 192 * pixel rate. This has the effect of allowing more tmds characters to 193 * be transmitted during blank 194 */ 195 196 switch (crtc_info->color_depth) { 197 case COLOR_DEPTH_888: 198 samples *= 4; 199 break; 200 case COLOR_DEPTH_101010: 201 samples *= 5; 202 break; 203 case COLOR_DEPTH_121212: 204 samples *= 6; 205 break; 206 default: 207 samples *= 4; 208 break; 209 } 210 211 samples /= 4; 212 213 /*check limitation*/ 214 if (samples < 88200) 215 limit_freq_to_48_khz = true; 216 else if (samples < 96000) 217 limit_freq_to_88_2_khz = true; 218 else if (samples < 176400) 219 limit_freq_to_96_khz = true; 220 else if (samples < 192000) 221 limit_freq_to_174_4_khz = true; 222 223 if (sample_rates != NULL) { 224 /* limit frequencies */ 225 if (limit_freq_to_174_4_khz) 226 sample_rates->rate.RATE_192 = 0; 227 228 if (limit_freq_to_96_khz) { 229 sample_rates->rate.RATE_192 = 0; 230 sample_rates->rate.RATE_176_4 = 0; 231 } 232 if (limit_freq_to_88_2_khz) { 233 sample_rates->rate.RATE_192 = 0; 234 sample_rates->rate.RATE_176_4 = 0; 235 sample_rates->rate.RATE_96 = 0; 236 } 237 if (limit_freq_to_48_khz) { 238 sample_rates->rate.RATE_192 = 0; 239 sample_rates->rate.RATE_176_4 = 0; 240 sample_rates->rate.RATE_96 = 0; 241 sample_rates->rate.RATE_88_2 = 0; 242 } 243 } 244 } 245 246 /*For DP SST, calculate if specified sample rates can fit into a given timing */ 247 static void check_audio_bandwidth_dpsst( 248 const struct audio_crtc_info *crtc_info, 249 uint32_t channel_count, 250 union audio_sample_rates *sample_rates) 251 { 252 /* do nothing */ 253 } 254 255 /*For DP MST, calculate if specified sample rates can fit into a given timing */ 256 static void check_audio_bandwidth_dpmst( 257 const struct audio_crtc_info *crtc_info, 258 uint32_t channel_count, 259 union audio_sample_rates *sample_rates) 260 { 261 /* do nothing */ 262 } 263 264 static void check_audio_bandwidth( 265 const struct audio_crtc_info *crtc_info, 266 uint32_t channel_count, 267 enum signal_type signal, 268 union audio_sample_rates *sample_rates) 269 { 270 switch (signal) { 271 case SIGNAL_TYPE_HDMI_TYPE_A: 272 check_audio_bandwidth_hdmi( 273 crtc_info, channel_count, sample_rates); 274 break; 275 case SIGNAL_TYPE_EDP: 276 case SIGNAL_TYPE_DISPLAY_PORT: 277 check_audio_bandwidth_dpsst( 278 crtc_info, channel_count, sample_rates); 279 break; 280 case SIGNAL_TYPE_DISPLAY_PORT_MST: 281 check_audio_bandwidth_dpmst( 282 crtc_info, channel_count, sample_rates); 283 break; 284 default: 285 break; 286 } 287 } 288 289 /* expose/not expose HBR capability to Audio driver */ 290 static void set_high_bit_rate_capable( 291 struct audio *audio, 292 bool capable) 293 { 294 uint32_t value = 0; 295 296 /* set high bit rate audio capable*/ 297 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR); 298 299 set_reg_field_value(value, capable, 300 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR, 301 HBR_CAPABLE); 302 303 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR, value); 304 } 305 306 /* set video latency in in ms/2+1 */ 307 static void set_video_latency( 308 struct audio *audio, 309 int latency_in_ms) 310 { 311 uint32_t value = 0; 312 313 if ((latency_in_ms < 0) || (latency_in_ms > 255)) 314 return; 315 316 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC); 317 318 set_reg_field_value(value, latency_in_ms, 319 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 320 VIDEO_LIPSYNC); 321 322 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 323 value); 324 } 325 326 /* set audio latency in in ms/2+1 */ 327 static void set_audio_latency( 328 struct audio *audio, 329 int latency_in_ms) 330 { 331 uint32_t value = 0; 332 333 if (latency_in_ms < 0) 334 latency_in_ms = 0; 335 336 if (latency_in_ms > 255) 337 latency_in_ms = 255; 338 339 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC); 340 341 set_reg_field_value(value, latency_in_ms, 342 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 343 AUDIO_LIPSYNC); 344 345 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 346 value); 347 } 348 349 void dce_aud_az_enable(struct audio *audio) 350 { 351 struct dce_audio *aud = DCE_AUD(audio); 352 uint32_t value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL); 353 354 set_reg_field_value(value, 1, 355 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 356 CLOCK_GATING_DISABLE); 357 set_reg_field_value(value, 1, 358 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 359 AUDIO_ENABLED); 360 361 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); 362 set_reg_field_value(value, 0, 363 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 364 CLOCK_GATING_DISABLE); 365 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); 366 367 DC_LOG_HW_AUDIO("\n\t========= AUDIO:dce_aud_az_enable: index: %u data: 0x%x\n", 368 audio->inst, value); 369 } 370 371 void dce_aud_az_disable(struct audio *audio) 372 { 373 uint32_t value; 374 struct dce_audio *aud = DCE_AUD(audio); 375 376 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL); 377 set_reg_field_value(value, 1, 378 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 379 CLOCK_GATING_DISABLE); 380 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); 381 382 set_reg_field_value(value, 0, 383 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 384 AUDIO_ENABLED); 385 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); 386 387 set_reg_field_value(value, 0, 388 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 389 CLOCK_GATING_DISABLE); 390 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); 391 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL); 392 DC_LOG_HW_AUDIO("\n\t========= AUDIO:dce_aud_az_disable: index: %u data: 0x%x\n", 393 audio->inst, value); 394 } 395 396 void dce_aud_az_configure( 397 struct audio *audio, 398 enum signal_type signal, 399 const struct audio_crtc_info *crtc_info, 400 const struct audio_info *audio_info) 401 { 402 struct dce_audio *aud = DCE_AUD(audio); 403 404 uint32_t speakers = audio_info->flags.info.ALLSPEAKERS; 405 uint32_t value; 406 uint32_t field = 0; 407 enum audio_format_code audio_format_code; 408 uint32_t format_index; 409 uint32_t index; 410 bool is_ac3_supported = false; 411 union audio_sample_rates sample_rate; 412 uint32_t strlen = 0; 413 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL); 414 set_reg_field_value(value, 1, 415 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 416 CLOCK_GATING_DISABLE); 417 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); 418 419 /* Speaker Allocation */ 420 /* 421 uint32_t value; 422 uint32_t field = 0;*/ 423 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER); 424 425 set_reg_field_value(value, 426 speakers, 427 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 428 SPEAKER_ALLOCATION); 429 430 /* LFE_PLAYBACK_LEVEL = LFEPBL 431 * LFEPBL = 0 : Unknown or refer to other information 432 * LFEPBL = 1 : 0dB playback 433 * LFEPBL = 2 : +10dB playback 434 * LFE_BL = 3 : Reserved 435 */ 436 set_reg_field_value(value, 437 0, 438 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 439 LFE_PLAYBACK_LEVEL); 440 /* todo: according to reg spec LFE_PLAYBACK_LEVEL is read only. 441 * why are we writing to it? DCE8 does not write this */ 442 443 444 set_reg_field_value(value, 445 0, 446 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 447 HDMI_CONNECTION); 448 449 set_reg_field_value(value, 450 0, 451 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 452 DP_CONNECTION); 453 454 field = get_reg_field_value(value, 455 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 456 EXTRA_CONNECTION_INFO); 457 458 field &= ~0x1; 459 460 set_reg_field_value(value, 461 field, 462 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 463 EXTRA_CONNECTION_INFO); 464 465 /* set audio for output signal */ 466 switch (signal) { 467 case SIGNAL_TYPE_HDMI_TYPE_A: 468 set_reg_field_value(value, 469 1, 470 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 471 HDMI_CONNECTION); 472 473 break; 474 475 case SIGNAL_TYPE_EDP: 476 case SIGNAL_TYPE_DISPLAY_PORT: 477 case SIGNAL_TYPE_DISPLAY_PORT_MST: 478 set_reg_field_value(value, 479 1, 480 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 481 DP_CONNECTION); 482 break; 483 default: 484 BREAK_TO_DEBUGGER(); 485 break; 486 } 487 488 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, value); 489 490 /* Audio Descriptors */ 491 /* pass through all formats */ 492 for (format_index = 0; format_index < AUDIO_FORMAT_CODE_COUNT; 493 format_index++) { 494 audio_format_code = 495 (AUDIO_FORMAT_CODE_FIRST + format_index); 496 497 /* those are unsupported, skip programming */ 498 if (audio_format_code == AUDIO_FORMAT_CODE_1BITAUDIO || 499 audio_format_code == AUDIO_FORMAT_CODE_DST) 500 continue; 501 502 value = 0; 503 504 /* check if supported */ 505 if (is_audio_format_supported( 506 audio_info, audio_format_code, &index)) { 507 const struct audio_mode *audio_mode = 508 &audio_info->modes[index]; 509 union audio_sample_rates sample_rates = 510 audio_mode->sample_rates; 511 uint8_t byte2 = audio_mode->max_bit_rate; 512 513 /* adjust specific properties */ 514 switch (audio_format_code) { 515 case AUDIO_FORMAT_CODE_LINEARPCM: { 516 check_audio_bandwidth( 517 crtc_info, 518 audio_mode->channel_count, 519 signal, 520 &sample_rates); 521 522 byte2 = audio_mode->sample_size; 523 524 set_reg_field_value(value, 525 sample_rates.all, 526 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 527 SUPPORTED_FREQUENCIES_STEREO); 528 } 529 break; 530 case AUDIO_FORMAT_CODE_AC3: 531 is_ac3_supported = true; 532 break; 533 case AUDIO_FORMAT_CODE_DOLBYDIGITALPLUS: 534 case AUDIO_FORMAT_CODE_DTS_HD: 535 case AUDIO_FORMAT_CODE_MAT_MLP: 536 case AUDIO_FORMAT_CODE_DST: 537 case AUDIO_FORMAT_CODE_WMAPRO: 538 byte2 = audio_mode->vendor_specific; 539 break; 540 default: 541 break; 542 } 543 544 /* fill audio format data */ 545 set_reg_field_value(value, 546 audio_mode->channel_count - 1, 547 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 548 MAX_CHANNELS); 549 550 set_reg_field_value(value, 551 sample_rates.all, 552 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 553 SUPPORTED_FREQUENCIES); 554 555 set_reg_field_value(value, 556 byte2, 557 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 558 DESCRIPTOR_BYTE_2); 559 } /* if */ 560 561 AZ_REG_WRITE( 562 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 + format_index, 563 value); 564 } /* for */ 565 566 if (is_ac3_supported) 567 /* todo: this reg global. why program global register? */ 568 REG_WRITE(AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS, 569 0x05); 570 571 /* check for 192khz/8-Ch support for HBR requirements */ 572 sample_rate.all = 0; 573 sample_rate.rate.RATE_192 = 1; 574 575 check_audio_bandwidth( 576 crtc_info, 577 8, 578 signal, 579 &sample_rate); 580 581 set_high_bit_rate_capable(audio, sample_rate.rate.RATE_192); 582 583 /* Audio and Video Lipsync */ 584 set_video_latency(audio, audio_info->video_latency); 585 set_audio_latency(audio, audio_info->audio_latency); 586 587 value = 0; 588 set_reg_field_value(value, audio_info->manufacture_id, 589 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0, 590 MANUFACTURER_ID); 591 592 set_reg_field_value(value, audio_info->product_id, 593 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0, 594 PRODUCT_ID); 595 596 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0, 597 value); 598 599 value = 0; 600 601 /*get display name string length */ 602 while (audio_info->display_name[strlen++] != '\0') { 603 if (strlen >= 604 MAX_HW_AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS) 605 break; 606 } 607 set_reg_field_value(value, strlen, 608 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1, 609 SINK_DESCRIPTION_LEN); 610 611 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1, 612 value); 613 614 /* 615 *write the port ID: 616 *PORT_ID0 = display index 617 *PORT_ID1 = 16bit BDF 618 *(format MSB->LSB: 8bit Bus, 5bit Device, 3bit Function) 619 */ 620 621 value = 0; 622 623 set_reg_field_value(value, audio_info->port_id[0], 624 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2, 625 PORT_ID0); 626 627 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2, value); 628 629 value = 0; 630 set_reg_field_value(value, audio_info->port_id[1], 631 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3, 632 PORT_ID1); 633 634 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3, value); 635 636 /*write the 18 char monitor string */ 637 638 value = 0; 639 set_reg_field_value(value, audio_info->display_name[0], 640 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4, 641 DESCRIPTION0); 642 643 set_reg_field_value(value, audio_info->display_name[1], 644 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4, 645 DESCRIPTION1); 646 647 set_reg_field_value(value, audio_info->display_name[2], 648 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4, 649 DESCRIPTION2); 650 651 set_reg_field_value(value, audio_info->display_name[3], 652 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4, 653 DESCRIPTION3); 654 655 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4, value); 656 657 value = 0; 658 set_reg_field_value(value, audio_info->display_name[4], 659 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5, 660 DESCRIPTION4); 661 662 set_reg_field_value(value, audio_info->display_name[5], 663 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5, 664 DESCRIPTION5); 665 666 set_reg_field_value(value, audio_info->display_name[6], 667 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5, 668 DESCRIPTION6); 669 670 set_reg_field_value(value, audio_info->display_name[7], 671 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5, 672 DESCRIPTION7); 673 674 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5, value); 675 676 value = 0; 677 set_reg_field_value(value, audio_info->display_name[8], 678 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6, 679 DESCRIPTION8); 680 681 set_reg_field_value(value, audio_info->display_name[9], 682 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6, 683 DESCRIPTION9); 684 685 set_reg_field_value(value, audio_info->display_name[10], 686 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6, 687 DESCRIPTION10); 688 689 set_reg_field_value(value, audio_info->display_name[11], 690 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6, 691 DESCRIPTION11); 692 693 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6, value); 694 695 value = 0; 696 set_reg_field_value(value, audio_info->display_name[12], 697 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7, 698 DESCRIPTION12); 699 700 set_reg_field_value(value, audio_info->display_name[13], 701 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7, 702 DESCRIPTION13); 703 704 set_reg_field_value(value, audio_info->display_name[14], 705 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7, 706 DESCRIPTION14); 707 708 set_reg_field_value(value, audio_info->display_name[15], 709 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7, 710 DESCRIPTION15); 711 712 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7, value); 713 714 value = 0; 715 set_reg_field_value(value, audio_info->display_name[16], 716 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8, 717 DESCRIPTION16); 718 719 set_reg_field_value(value, audio_info->display_name[17], 720 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8, 721 DESCRIPTION17); 722 723 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8, value); 724 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL); 725 set_reg_field_value(value, 0, 726 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 727 CLOCK_GATING_DISABLE); 728 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); 729 } 730 731 /* 732 * todo: wall clk related functionality probably belong to clock_src. 733 */ 734 735 /* search pixel clock value for Azalia HDMI Audio */ 736 static void get_azalia_clock_info_hdmi( 737 uint32_t crtc_pixel_clock_in_khz, 738 uint32_t actual_pixel_clock_in_khz, 739 struct azalia_clock_info *azalia_clock_info) 740 { 741 /* audio_dto_phase= 24 * 10,000; 742 * 24MHz in [100Hz] units */ 743 azalia_clock_info->audio_dto_phase = 744 24 * 10000; 745 746 /* audio_dto_module = PCLKFrequency * 10,000; 747 * [khz] -> [100Hz] */ 748 azalia_clock_info->audio_dto_module = 749 actual_pixel_clock_in_khz * 10; 750 } 751 752 static void get_azalia_clock_info_dp( 753 uint32_t requested_pixel_clock_in_khz, 754 const struct audio_pll_info *pll_info, 755 struct azalia_clock_info *azalia_clock_info) 756 { 757 /* Reported dpDtoSourceClockInkhz value for 758 * DCE8 already adjusted for SS, do not need any 759 * adjustment here anymore 760 */ 761 762 /*audio_dto_phase = 24 * 10,000; 763 * 24MHz in [100Hz] units */ 764 azalia_clock_info->audio_dto_phase = 24 * 10000; 765 766 /*audio_dto_module = dpDtoSourceClockInkhz * 10,000; 767 * [khz] ->[100Hz] */ 768 azalia_clock_info->audio_dto_module = 769 pll_info->dp_dto_source_clock_in_khz * 10; 770 } 771 772 void dce_aud_wall_dto_setup( 773 struct audio *audio, 774 enum signal_type signal, 775 const struct audio_crtc_info *crtc_info, 776 const struct audio_pll_info *pll_info) 777 { 778 struct dce_audio *aud = DCE_AUD(audio); 779 780 struct azalia_clock_info clock_info = { 0 }; 781 782 if (dc_is_hdmi_signal(signal)) { 783 uint32_t src_sel; 784 785 /*DTO0 Programming goal: 786 -generate 24MHz, 128*Fs from 24MHz 787 -use DTO0 when an active HDMI port is connected 788 (optionally a DP is connected) */ 789 790 /* calculate DTO settings */ 791 get_azalia_clock_info_hdmi( 792 crtc_info->requested_pixel_clock, 793 crtc_info->calculated_pixel_clock, 794 &clock_info); 795 796 DC_LOG_HW_AUDIO("\n%s:Input::requested_pixel_clock = %d"\ 797 "calculated_pixel_clock =%d\n"\ 798 "audio_dto_module = %d audio_dto_phase =%d \n\n", __func__,\ 799 crtc_info->requested_pixel_clock,\ 800 crtc_info->calculated_pixel_clock,\ 801 clock_info.audio_dto_module,\ 802 clock_info.audio_dto_phase); 803 804 /* On TN/SI, Program DTO source select and DTO select before 805 programming DTO modulo and DTO phase. These bits must be 806 programmed first, otherwise there will be no HDMI audio at boot 807 up. This is a HW sequence change (different from old ASICs). 808 Caution when changing this programming sequence. 809 810 HDMI enabled, using DTO0 811 program master CRTC for DTO0 */ 812 src_sel = pll_info->dto_source - DTO_SOURCE_ID0; 813 REG_UPDATE_2(DCCG_AUDIO_DTO_SOURCE, 814 DCCG_AUDIO_DTO0_SOURCE_SEL, src_sel, 815 DCCG_AUDIO_DTO_SEL, 0); 816 817 /* module */ 818 REG_UPDATE(DCCG_AUDIO_DTO0_MODULE, 819 DCCG_AUDIO_DTO0_MODULE, clock_info.audio_dto_module); 820 821 /* phase */ 822 REG_UPDATE(DCCG_AUDIO_DTO0_PHASE, 823 DCCG_AUDIO_DTO0_PHASE, clock_info.audio_dto_phase); 824 } else { 825 /*DTO1 Programming goal: 826 -generate 24MHz, 512*Fs, 128*Fs from 24MHz 827 -default is to used DTO1, and switch to DTO0 when an audio 828 master HDMI port is connected 829 -use as default for DP 830 831 calculate DTO settings */ 832 get_azalia_clock_info_dp( 833 crtc_info->requested_pixel_clock, 834 pll_info, 835 &clock_info); 836 837 /* Program DTO select before programming DTO modulo and DTO 838 phase. default to use DTO1 */ 839 840 REG_UPDATE(DCCG_AUDIO_DTO_SOURCE, 841 DCCG_AUDIO_DTO_SEL, 1); 842 843 REG_UPDATE(DCCG_AUDIO_DTO_SOURCE, 844 DCCG_AUDIO_DTO_SEL, 1); 845 /* DCCG_AUDIO_DTO2_USE_512FBR_DTO, 1) 846 * Select 512fs for DP TODO: web register definition 847 * does not match register header file 848 * DCE11 version it's commented out while DCE8 it's set to 1 849 */ 850 851 /* module */ 852 REG_UPDATE(DCCG_AUDIO_DTO1_MODULE, 853 DCCG_AUDIO_DTO1_MODULE, clock_info.audio_dto_module); 854 855 /* phase */ 856 REG_UPDATE(DCCG_AUDIO_DTO1_PHASE, 857 DCCG_AUDIO_DTO1_PHASE, clock_info.audio_dto_phase); 858 859 REG_UPDATE(DCCG_AUDIO_DTO_SOURCE, 860 DCCG_AUDIO_DTO2_USE_512FBR_DTO, 1); 861 862 } 863 } 864 865 static bool dce_aud_endpoint_valid(struct audio *audio) 866 { 867 uint32_t value; 868 uint32_t port_connectivity; 869 870 value = AZ_REG_READ( 871 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT); 872 873 port_connectivity = get_reg_field_value(value, 874 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT, 875 PORT_CONNECTIVITY); 876 877 return !(port_connectivity == 1); 878 } 879 880 /* initialize HW state */ 881 void dce_aud_hw_init( 882 struct audio *audio) 883 { 884 uint32_t value; 885 struct dce_audio *aud = DCE_AUD(audio); 886 887 /* we only need to program the following registers once, so we only do 888 it for the inst 0*/ 889 if (audio->inst != 0) 890 return; 891 892 /* Suport R5 - 32khz 893 * Suport R6 - 44.1khz 894 * Suport R7 - 48khz 895 */ 896 /*disable clock gating before write to endpoint register*/ 897 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL); 898 set_reg_field_value(value, 1, 899 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 900 CLOCK_GATING_DISABLE); 901 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); 902 REG_UPDATE(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES, 903 AUDIO_RATE_CAPABILITIES, 0x70); 904 905 /*Keep alive bit to verify HW block in BU. */ 906 REG_UPDATE_2(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES, 907 CLKSTOP, 1, 908 EPSS, 1); 909 set_reg_field_value(value, 0, 910 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 911 CLOCK_GATING_DISABLE); 912 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); 913 } 914 915 static const struct audio_funcs funcs = { 916 .endpoint_valid = dce_aud_endpoint_valid, 917 .hw_init = dce_aud_hw_init, 918 .wall_dto_setup = dce_aud_wall_dto_setup, 919 .az_enable = dce_aud_az_enable, 920 .az_disable = dce_aud_az_disable, 921 .az_configure = dce_aud_az_configure, 922 .destroy = dce_aud_destroy, 923 }; 924 925 void dce_aud_destroy(struct audio **audio) 926 { 927 struct dce_audio *aud = DCE_AUD(*audio); 928 929 kfree(aud); 930 *audio = NULL; 931 } 932 933 struct audio *dce_audio_create( 934 struct dc_context *ctx, 935 unsigned int inst, 936 const struct dce_audio_registers *reg, 937 const struct dce_audio_shift *shifts, 938 const struct dce_aduio_mask *masks 939 ) 940 { 941 struct dce_audio *audio = kzalloc(sizeof(*audio), GFP_KERNEL); 942 943 if (audio == NULL) { 944 ASSERT_CRITICAL(audio); 945 return NULL; 946 } 947 948 audio->base.ctx = ctx; 949 audio->base.inst = inst; 950 audio->base.funcs = &funcs; 951 952 audio->regs = reg; 953 audio->shifts = shifts; 954 audio->masks = masks; 955 956 return &audio->base; 957 } 958 959