1 /******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2016 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 *******************************************************************************/ 28 29 #include <linux/pci.h> 30 #include <linux/delay.h> 31 #include <linux/sched.h> 32 33 #include "ixgbe.h" 34 #include "ixgbe_phy.h" 35 36 #define IXGBE_82598_MAX_TX_QUEUES 32 37 #define IXGBE_82598_MAX_RX_QUEUES 64 38 #define IXGBE_82598_RAR_ENTRIES 16 39 #define IXGBE_82598_MC_TBL_SIZE 128 40 #define IXGBE_82598_VFT_TBL_SIZE 128 41 #define IXGBE_82598_RX_PB_SIZE 512 42 43 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw, 44 ixgbe_link_speed speed, 45 bool autoneg_wait_to_complete); 46 static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset, 47 u8 *eeprom_data); 48 49 /** 50 * ixgbe_set_pcie_completion_timeout - set pci-e completion timeout 51 * @hw: pointer to the HW structure 52 * 53 * The defaults for 82598 should be in the range of 50us to 50ms, 54 * however the hardware default for these parts is 500us to 1ms which is less 55 * than the 10ms recommended by the pci-e spec. To address this we need to 56 * increase the value to either 10ms to 250ms for capability version 1 config, 57 * or 16ms to 55ms for version 2. 58 **/ 59 static void ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw) 60 { 61 u32 gcr = IXGBE_READ_REG(hw, IXGBE_GCR); 62 u16 pcie_devctl2; 63 64 if (ixgbe_removed(hw->hw_addr)) 65 return; 66 67 /* only take action if timeout value is defaulted to 0 */ 68 if (gcr & IXGBE_GCR_CMPL_TMOUT_MASK) 69 goto out; 70 71 /* 72 * if capababilities version is type 1 we can write the 73 * timeout of 10ms to 250ms through the GCR register 74 */ 75 if (!(gcr & IXGBE_GCR_CAP_VER2)) { 76 gcr |= IXGBE_GCR_CMPL_TMOUT_10ms; 77 goto out; 78 } 79 80 /* 81 * for version 2 capabilities we need to write the config space 82 * directly in order to set the completion timeout value for 83 * 16ms to 55ms 84 */ 85 pcie_devctl2 = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_CONTROL2); 86 pcie_devctl2 |= IXGBE_PCI_DEVICE_CONTROL2_16ms; 87 ixgbe_write_pci_cfg_word(hw, IXGBE_PCI_DEVICE_CONTROL2, pcie_devctl2); 88 out: 89 /* disable completion timeout resend */ 90 gcr &= ~IXGBE_GCR_CMPL_TMOUT_RESEND; 91 IXGBE_WRITE_REG(hw, IXGBE_GCR, gcr); 92 } 93 94 static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw) 95 { 96 struct ixgbe_mac_info *mac = &hw->mac; 97 98 /* Call PHY identify routine to get the phy type */ 99 ixgbe_identify_phy_generic(hw); 100 101 mac->mcft_size = IXGBE_82598_MC_TBL_SIZE; 102 mac->vft_size = IXGBE_82598_VFT_TBL_SIZE; 103 mac->num_rar_entries = IXGBE_82598_RAR_ENTRIES; 104 mac->rx_pb_size = IXGBE_82598_RX_PB_SIZE; 105 mac->max_rx_queues = IXGBE_82598_MAX_RX_QUEUES; 106 mac->max_tx_queues = IXGBE_82598_MAX_TX_QUEUES; 107 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw); 108 109 return 0; 110 } 111 112 /** 113 * ixgbe_init_phy_ops_82598 - PHY/SFP specific init 114 * @hw: pointer to hardware structure 115 * 116 * Initialize any function pointers that were not able to be 117 * set during get_invariants because the PHY/SFP type was 118 * not known. Perform the SFP init if necessary. 119 * 120 **/ 121 static s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw) 122 { 123 struct ixgbe_mac_info *mac = &hw->mac; 124 struct ixgbe_phy_info *phy = &hw->phy; 125 s32 ret_val; 126 u16 list_offset, data_offset; 127 128 /* Identify the PHY */ 129 phy->ops.identify(hw); 130 131 /* Overwrite the link function pointers if copper PHY */ 132 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) { 133 mac->ops.setup_link = &ixgbe_setup_copper_link_82598; 134 mac->ops.get_link_capabilities = 135 &ixgbe_get_copper_link_capabilities_generic; 136 } 137 138 switch (hw->phy.type) { 139 case ixgbe_phy_tn: 140 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx; 141 phy->ops.check_link = &ixgbe_check_phy_link_tnx; 142 break; 143 case ixgbe_phy_nl: 144 phy->ops.reset = &ixgbe_reset_phy_nl; 145 146 /* Call SFP+ identify routine to get the SFP+ module type */ 147 ret_val = phy->ops.identify_sfp(hw); 148 if (ret_val) 149 return ret_val; 150 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) 151 return IXGBE_ERR_SFP_NOT_SUPPORTED; 152 153 /* Check to see if SFP+ module is supported */ 154 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, 155 &list_offset, 156 &data_offset); 157 if (ret_val) 158 return IXGBE_ERR_SFP_NOT_SUPPORTED; 159 break; 160 default: 161 break; 162 } 163 164 return 0; 165 } 166 167 /** 168 * ixgbe_start_hw_82598 - Prepare hardware for Tx/Rx 169 * @hw: pointer to hardware structure 170 * 171 * Starts the hardware using the generic start_hw function. 172 * Disables relaxed ordering for archs other than SPARC 173 * Then set pcie completion timeout 174 * 175 **/ 176 static s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw) 177 { 178 s32 ret_val; 179 180 ret_val = ixgbe_start_hw_generic(hw); 181 if (ret_val) 182 return ret_val; 183 184 /* set the completion timeout for interface */ 185 ixgbe_set_pcie_completion_timeout(hw); 186 187 return 0; 188 } 189 190 /** 191 * ixgbe_get_link_capabilities_82598 - Determines link capabilities 192 * @hw: pointer to hardware structure 193 * @speed: pointer to link speed 194 * @autoneg: boolean auto-negotiation value 195 * 196 * Determines the link capabilities by reading the AUTOC register. 197 **/ 198 static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw, 199 ixgbe_link_speed *speed, 200 bool *autoneg) 201 { 202 u32 autoc = 0; 203 204 /* 205 * Determine link capabilities based on the stored value of AUTOC, 206 * which represents EEPROM defaults. If AUTOC value has not been 207 * stored, use the current register value. 208 */ 209 if (hw->mac.orig_link_settings_stored) 210 autoc = hw->mac.orig_autoc; 211 else 212 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 213 214 switch (autoc & IXGBE_AUTOC_LMS_MASK) { 215 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 216 *speed = IXGBE_LINK_SPEED_1GB_FULL; 217 *autoneg = false; 218 break; 219 220 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 221 *speed = IXGBE_LINK_SPEED_10GB_FULL; 222 *autoneg = false; 223 break; 224 225 case IXGBE_AUTOC_LMS_1G_AN: 226 *speed = IXGBE_LINK_SPEED_1GB_FULL; 227 *autoneg = true; 228 break; 229 230 case IXGBE_AUTOC_LMS_KX4_AN: 231 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN: 232 *speed = IXGBE_LINK_SPEED_UNKNOWN; 233 if (autoc & IXGBE_AUTOC_KX4_SUPP) 234 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 235 if (autoc & IXGBE_AUTOC_KX_SUPP) 236 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 237 *autoneg = true; 238 break; 239 240 default: 241 return IXGBE_ERR_LINK_SETUP; 242 } 243 244 return 0; 245 } 246 247 /** 248 * ixgbe_get_media_type_82598 - Determines media type 249 * @hw: pointer to hardware structure 250 * 251 * Returns the media type (fiber, copper, backplane) 252 **/ 253 static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw) 254 { 255 /* Detect if there is a copper PHY attached. */ 256 switch (hw->phy.type) { 257 case ixgbe_phy_cu_unknown: 258 case ixgbe_phy_tn: 259 return ixgbe_media_type_copper; 260 261 default: 262 break; 263 } 264 265 /* Media type for I82598 is based on device ID */ 266 switch (hw->device_id) { 267 case IXGBE_DEV_ID_82598: 268 case IXGBE_DEV_ID_82598_BX: 269 /* Default device ID is mezzanine card KX/KX4 */ 270 return ixgbe_media_type_backplane; 271 272 case IXGBE_DEV_ID_82598AF_DUAL_PORT: 273 case IXGBE_DEV_ID_82598AF_SINGLE_PORT: 274 case IXGBE_DEV_ID_82598_DA_DUAL_PORT: 275 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: 276 case IXGBE_DEV_ID_82598EB_XF_LR: 277 case IXGBE_DEV_ID_82598EB_SFP_LOM: 278 return ixgbe_media_type_fiber; 279 280 case IXGBE_DEV_ID_82598EB_CX4: 281 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT: 282 return ixgbe_media_type_cx4; 283 284 case IXGBE_DEV_ID_82598AT: 285 case IXGBE_DEV_ID_82598AT2: 286 return ixgbe_media_type_copper; 287 288 default: 289 return ixgbe_media_type_unknown; 290 } 291 } 292 293 /** 294 * ixgbe_fc_enable_82598 - Enable flow control 295 * @hw: pointer to hardware structure 296 * 297 * Enable flow control according to the current settings. 298 **/ 299 static s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw) 300 { 301 u32 fctrl_reg; 302 u32 rmcs_reg; 303 u32 reg; 304 u32 fcrtl, fcrth; 305 u32 link_speed = 0; 306 int i; 307 bool link_up; 308 309 /* Validate the water mark configuration */ 310 if (!hw->fc.pause_time) 311 return IXGBE_ERR_INVALID_LINK_SETTINGS; 312 313 /* Low water mark of zero causes XOFF floods */ 314 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 315 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && 316 hw->fc.high_water[i]) { 317 if (!hw->fc.low_water[i] || 318 hw->fc.low_water[i] >= hw->fc.high_water[i]) { 319 hw_dbg(hw, "Invalid water mark configuration\n"); 320 return IXGBE_ERR_INVALID_LINK_SETTINGS; 321 } 322 } 323 } 324 325 /* 326 * On 82598 having Rx FC on causes resets while doing 1G 327 * so if it's on turn it off once we know link_speed. For 328 * more details see 82598 Specification update. 329 */ 330 hw->mac.ops.check_link(hw, &link_speed, &link_up, false); 331 if (link_up && link_speed == IXGBE_LINK_SPEED_1GB_FULL) { 332 switch (hw->fc.requested_mode) { 333 case ixgbe_fc_full: 334 hw->fc.requested_mode = ixgbe_fc_tx_pause; 335 break; 336 case ixgbe_fc_rx_pause: 337 hw->fc.requested_mode = ixgbe_fc_none; 338 break; 339 default: 340 /* no change */ 341 break; 342 } 343 } 344 345 /* Negotiate the fc mode to use */ 346 hw->mac.ops.fc_autoneg(hw); 347 348 /* Disable any previous flow control settings */ 349 fctrl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL); 350 fctrl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE); 351 352 rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS); 353 rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X); 354 355 /* 356 * The possible values of fc.current_mode are: 357 * 0: Flow control is completely disabled 358 * 1: Rx flow control is enabled (we can receive pause frames, 359 * but not send pause frames). 360 * 2: Tx flow control is enabled (we can send pause frames but 361 * we do not support receiving pause frames). 362 * 3: Both Rx and Tx flow control (symmetric) are enabled. 363 * other: Invalid. 364 */ 365 switch (hw->fc.current_mode) { 366 case ixgbe_fc_none: 367 /* 368 * Flow control is disabled by software override or autoneg. 369 * The code below will actually disable it in the HW. 370 */ 371 break; 372 case ixgbe_fc_rx_pause: 373 /* 374 * Rx Flow control is enabled and Tx Flow control is 375 * disabled by software override. Since there really 376 * isn't a way to advertise that we are capable of RX 377 * Pause ONLY, we will advertise that we support both 378 * symmetric and asymmetric Rx PAUSE. Later, we will 379 * disable the adapter's ability to send PAUSE frames. 380 */ 381 fctrl_reg |= IXGBE_FCTRL_RFCE; 382 break; 383 case ixgbe_fc_tx_pause: 384 /* 385 * Tx Flow control is enabled, and Rx Flow control is 386 * disabled by software override. 387 */ 388 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X; 389 break; 390 case ixgbe_fc_full: 391 /* Flow control (both Rx and Tx) is enabled by SW override. */ 392 fctrl_reg |= IXGBE_FCTRL_RFCE; 393 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X; 394 break; 395 default: 396 hw_dbg(hw, "Flow control param set incorrectly\n"); 397 return IXGBE_ERR_CONFIG; 398 } 399 400 /* Set 802.3x based flow control settings. */ 401 fctrl_reg |= IXGBE_FCTRL_DPF; 402 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg); 403 IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg); 404 405 /* Set up and enable Rx high/low water mark thresholds, enable XON. */ 406 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 407 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && 408 hw->fc.high_water[i]) { 409 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE; 410 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN; 411 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), fcrtl); 412 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), fcrth); 413 } else { 414 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), 0); 415 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), 0); 416 } 417 418 } 419 420 /* Configure pause time (2 TCs per register) */ 421 reg = hw->fc.pause_time * 0x00010001; 422 for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++) 423 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); 424 425 /* Configure flow control refresh threshold value */ 426 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); 427 428 return 0; 429 } 430 431 /** 432 * ixgbe_start_mac_link_82598 - Configures MAC link settings 433 * @hw: pointer to hardware structure 434 * @autoneg_wait_to_complete: true when waiting for completion is needed 435 * 436 * Configures link settings based on values in the ixgbe_hw struct. 437 * Restarts the link. Performs autonegotiation if needed. 438 **/ 439 static s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw, 440 bool autoneg_wait_to_complete) 441 { 442 u32 autoc_reg; 443 u32 links_reg; 444 u32 i; 445 s32 status = 0; 446 447 /* Restart link */ 448 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 449 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 450 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 451 452 /* Only poll for autoneg to complete if specified to do so */ 453 if (autoneg_wait_to_complete) { 454 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) == 455 IXGBE_AUTOC_LMS_KX4_AN || 456 (autoc_reg & IXGBE_AUTOC_LMS_MASK) == 457 IXGBE_AUTOC_LMS_KX4_AN_1G_AN) { 458 links_reg = 0; /* Just in case Autoneg time = 0 */ 459 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { 460 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 461 if (links_reg & IXGBE_LINKS_KX_AN_COMP) 462 break; 463 msleep(100); 464 } 465 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { 466 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE; 467 hw_dbg(hw, "Autonegotiation did not complete.\n"); 468 } 469 } 470 } 471 472 /* Add delay to filter out noises during initial link setup */ 473 msleep(50); 474 475 return status; 476 } 477 478 /** 479 * ixgbe_validate_link_ready - Function looks for phy link 480 * @hw: pointer to hardware structure 481 * 482 * Function indicates success when phy link is available. If phy is not ready 483 * within 5 seconds of MAC indicating link, the function returns error. 484 **/ 485 static s32 ixgbe_validate_link_ready(struct ixgbe_hw *hw) 486 { 487 u32 timeout; 488 u16 an_reg; 489 490 if (hw->device_id != IXGBE_DEV_ID_82598AT2) 491 return 0; 492 493 for (timeout = 0; 494 timeout < IXGBE_VALIDATE_LINK_READY_TIMEOUT; timeout++) { 495 hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN, &an_reg); 496 497 if ((an_reg & MDIO_AN_STAT1_COMPLETE) && 498 (an_reg & MDIO_STAT1_LSTATUS)) 499 break; 500 501 msleep(100); 502 } 503 504 if (timeout == IXGBE_VALIDATE_LINK_READY_TIMEOUT) { 505 hw_dbg(hw, "Link was indicated but link is down\n"); 506 return IXGBE_ERR_LINK_SETUP; 507 } 508 509 return 0; 510 } 511 512 /** 513 * ixgbe_check_mac_link_82598 - Get link/speed status 514 * @hw: pointer to hardware structure 515 * @speed: pointer to link speed 516 * @link_up: true is link is up, false otherwise 517 * @link_up_wait_to_complete: bool used to wait for link up or not 518 * 519 * Reads the links register to determine if link is up and the current speed 520 **/ 521 static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, 522 ixgbe_link_speed *speed, bool *link_up, 523 bool link_up_wait_to_complete) 524 { 525 u32 links_reg; 526 u32 i; 527 u16 link_reg, adapt_comp_reg; 528 529 /* 530 * SERDES PHY requires us to read link status from register 0xC79F. 531 * Bit 0 set indicates link is up/ready; clear indicates link down. 532 * 0xC00C is read to check that the XAUI lanes are active. Bit 0 533 * clear indicates active; set indicates inactive. 534 */ 535 if (hw->phy.type == ixgbe_phy_nl) { 536 hw->phy.ops.read_reg(hw, 0xC79F, MDIO_MMD_PMAPMD, &link_reg); 537 hw->phy.ops.read_reg(hw, 0xC79F, MDIO_MMD_PMAPMD, &link_reg); 538 hw->phy.ops.read_reg(hw, 0xC00C, MDIO_MMD_PMAPMD, 539 &adapt_comp_reg); 540 if (link_up_wait_to_complete) { 541 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { 542 if ((link_reg & 1) && 543 ((adapt_comp_reg & 1) == 0)) { 544 *link_up = true; 545 break; 546 } else { 547 *link_up = false; 548 } 549 msleep(100); 550 hw->phy.ops.read_reg(hw, 0xC79F, 551 MDIO_MMD_PMAPMD, 552 &link_reg); 553 hw->phy.ops.read_reg(hw, 0xC00C, 554 MDIO_MMD_PMAPMD, 555 &adapt_comp_reg); 556 } 557 } else { 558 if ((link_reg & 1) && ((adapt_comp_reg & 1) == 0)) 559 *link_up = true; 560 else 561 *link_up = false; 562 } 563 564 if (!*link_up) 565 return 0; 566 } 567 568 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 569 if (link_up_wait_to_complete) { 570 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { 571 if (links_reg & IXGBE_LINKS_UP) { 572 *link_up = true; 573 break; 574 } else { 575 *link_up = false; 576 } 577 msleep(100); 578 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 579 } 580 } else { 581 if (links_reg & IXGBE_LINKS_UP) 582 *link_up = true; 583 else 584 *link_up = false; 585 } 586 587 if (links_reg & IXGBE_LINKS_SPEED) 588 *speed = IXGBE_LINK_SPEED_10GB_FULL; 589 else 590 *speed = IXGBE_LINK_SPEED_1GB_FULL; 591 592 if ((hw->device_id == IXGBE_DEV_ID_82598AT2) && *link_up && 593 (ixgbe_validate_link_ready(hw) != 0)) 594 *link_up = false; 595 596 return 0; 597 } 598 599 /** 600 * ixgbe_setup_mac_link_82598 - Set MAC link speed 601 * @hw: pointer to hardware structure 602 * @speed: new link speed 603 * @autoneg_wait_to_complete: true when waiting for completion is needed 604 * 605 * Set the link speed in the AUTOC register and restarts link. 606 **/ 607 static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw, 608 ixgbe_link_speed speed, 609 bool autoneg_wait_to_complete) 610 { 611 bool autoneg = false; 612 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN; 613 u32 curr_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 614 u32 autoc = curr_autoc; 615 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK; 616 617 /* Check to see if speed passed in is supported. */ 618 ixgbe_get_link_capabilities_82598(hw, &link_capabilities, &autoneg); 619 speed &= link_capabilities; 620 621 if (speed == IXGBE_LINK_SPEED_UNKNOWN) 622 return IXGBE_ERR_LINK_SETUP; 623 624 /* Set KX4/KX support according to speed requested */ 625 else if (link_mode == IXGBE_AUTOC_LMS_KX4_AN || 626 link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) { 627 autoc &= ~IXGBE_AUTOC_KX4_KX_SUPP_MASK; 628 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 629 autoc |= IXGBE_AUTOC_KX4_SUPP; 630 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 631 autoc |= IXGBE_AUTOC_KX_SUPP; 632 if (autoc != curr_autoc) 633 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc); 634 } 635 636 /* Setup and restart the link based on the new values in 637 * ixgbe_hw This will write the AUTOC register based on the new 638 * stored values 639 */ 640 return ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete); 641 } 642 643 644 /** 645 * ixgbe_setup_copper_link_82598 - Set the PHY autoneg advertised field 646 * @hw: pointer to hardware structure 647 * @speed: new link speed 648 * @autoneg_wait_to_complete: true if waiting is needed to complete 649 * 650 * Sets the link speed in the AUTOC register in the MAC and restarts link. 651 **/ 652 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw, 653 ixgbe_link_speed speed, 654 bool autoneg_wait_to_complete) 655 { 656 s32 status; 657 658 /* Setup the PHY according to input speed */ 659 status = hw->phy.ops.setup_link_speed(hw, speed, 660 autoneg_wait_to_complete); 661 /* Set up MAC */ 662 ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete); 663 664 return status; 665 } 666 667 /** 668 * ixgbe_reset_hw_82598 - Performs hardware reset 669 * @hw: pointer to hardware structure 670 * 671 * Resets the hardware by resetting the transmit and receive units, masks and 672 * clears all interrupts, performing a PHY reset, and performing a link (MAC) 673 * reset. 674 **/ 675 static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw) 676 { 677 s32 status; 678 s32 phy_status = 0; 679 u32 ctrl; 680 u32 gheccr; 681 u32 i; 682 u32 autoc; 683 u8 analog_val; 684 685 /* Call adapter stop to disable tx/rx and clear interrupts */ 686 status = hw->mac.ops.stop_adapter(hw); 687 if (status) 688 return status; 689 690 /* 691 * Power up the Atlas Tx lanes if they are currently powered down. 692 * Atlas Tx lanes are powered down for MAC loopback tests, but 693 * they are not automatically restored on reset. 694 */ 695 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val); 696 if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) { 697 /* Enable Tx Atlas so packets can be transmitted again */ 698 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, 699 &analog_val); 700 analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN; 701 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, 702 analog_val); 703 704 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, 705 &analog_val); 706 analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL; 707 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, 708 analog_val); 709 710 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, 711 &analog_val); 712 analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL; 713 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, 714 analog_val); 715 716 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, 717 &analog_val); 718 analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL; 719 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, 720 analog_val); 721 } 722 723 /* Reset PHY */ 724 if (hw->phy.reset_disable == false) { 725 /* PHY ops must be identified and initialized prior to reset */ 726 727 /* Init PHY and function pointers, perform SFP setup */ 728 phy_status = hw->phy.ops.init(hw); 729 if (phy_status == IXGBE_ERR_SFP_NOT_SUPPORTED) 730 return phy_status; 731 if (phy_status == IXGBE_ERR_SFP_NOT_PRESENT) 732 goto mac_reset_top; 733 734 hw->phy.ops.reset(hw); 735 } 736 737 mac_reset_top: 738 /* 739 * Issue global reset to the MAC. This needs to be a SW reset. 740 * If link reset is used, it might reset the MAC when mng is using it 741 */ 742 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL) | IXGBE_CTRL_RST; 743 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 744 IXGBE_WRITE_FLUSH(hw); 745 usleep_range(1000, 1200); 746 747 /* Poll for reset bit to self-clear indicating reset is complete */ 748 for (i = 0; i < 10; i++) { 749 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 750 if (!(ctrl & IXGBE_CTRL_RST)) 751 break; 752 udelay(1); 753 } 754 if (ctrl & IXGBE_CTRL_RST) { 755 status = IXGBE_ERR_RESET_FAILED; 756 hw_dbg(hw, "Reset polling failed to complete.\n"); 757 } 758 759 msleep(50); 760 761 /* 762 * Double resets are required for recovery from certain error 763 * conditions. Between resets, it is necessary to stall to allow time 764 * for any pending HW events to complete. 765 */ 766 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 767 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 768 goto mac_reset_top; 769 } 770 771 gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR); 772 gheccr &= ~(BIT(21) | BIT(18) | BIT(9) | BIT(6)); 773 IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr); 774 775 /* 776 * Store the original AUTOC value if it has not been 777 * stored off yet. Otherwise restore the stored original 778 * AUTOC value since the reset operation sets back to deaults. 779 */ 780 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 781 if (hw->mac.orig_link_settings_stored == false) { 782 hw->mac.orig_autoc = autoc; 783 hw->mac.orig_link_settings_stored = true; 784 } else if (autoc != hw->mac.orig_autoc) { 785 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc); 786 } 787 788 /* Store the permanent mac address */ 789 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 790 791 /* 792 * Store MAC address from RAR0, clear receive address registers, and 793 * clear the multicast table 794 */ 795 hw->mac.ops.init_rx_addrs(hw); 796 797 if (phy_status) 798 status = phy_status; 799 800 return status; 801 } 802 803 /** 804 * ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address 805 * @hw: pointer to hardware struct 806 * @rar: receive address register index to associate with a VMDq index 807 * @vmdq: VMDq set index 808 **/ 809 static s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 810 { 811 u32 rar_high; 812 u32 rar_entries = hw->mac.num_rar_entries; 813 814 /* Make sure we are using a valid rar index range */ 815 if (rar >= rar_entries) { 816 hw_dbg(hw, "RAR index %d is out of range.\n", rar); 817 return IXGBE_ERR_INVALID_ARGUMENT; 818 } 819 820 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); 821 rar_high &= ~IXGBE_RAH_VIND_MASK; 822 rar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK); 823 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high); 824 return 0; 825 } 826 827 /** 828 * ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address 829 * @hw: pointer to hardware struct 830 * @rar: receive address register index to associate with a VMDq index 831 * @vmdq: VMDq clear index (not used in 82598, but elsewhere) 832 **/ 833 static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 834 { 835 u32 rar_high; 836 u32 rar_entries = hw->mac.num_rar_entries; 837 838 839 /* Make sure we are using a valid rar index range */ 840 if (rar >= rar_entries) { 841 hw_dbg(hw, "RAR index %d is out of range.\n", rar); 842 return IXGBE_ERR_INVALID_ARGUMENT; 843 } 844 845 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); 846 if (rar_high & IXGBE_RAH_VIND_MASK) { 847 rar_high &= ~IXGBE_RAH_VIND_MASK; 848 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high); 849 } 850 851 return 0; 852 } 853 854 /** 855 * ixgbe_set_vfta_82598 - Set VLAN filter table 856 * @hw: pointer to hardware structure 857 * @vlan: VLAN id to write to VLAN filter 858 * @vind: VMDq output index that maps queue to VLAN id in VFTA 859 * @vlan_on: boolean flag to turn on/off VLAN in VFTA 860 * @vlvf_bypass: boolean flag - unused 861 * 862 * Turn on/off specified VLAN in the VLAN filter table. 863 **/ 864 static s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind, 865 bool vlan_on, bool vlvf_bypass) 866 { 867 u32 regindex; 868 u32 bitindex; 869 u32 bits; 870 u32 vftabyte; 871 872 if (vlan > 4095) 873 return IXGBE_ERR_PARAM; 874 875 /* Determine 32-bit word position in array */ 876 regindex = (vlan >> 5) & 0x7F; /* upper seven bits */ 877 878 /* Determine the location of the (VMD) queue index */ 879 vftabyte = ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */ 880 bitindex = (vlan & 0x7) << 2; /* lower 3 bits indicate nibble */ 881 882 /* Set the nibble for VMD queue index */ 883 bits = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex)); 884 bits &= (~(0x0F << bitindex)); 885 bits |= (vind << bitindex); 886 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex), bits); 887 888 /* Determine the location of the bit for this VLAN id */ 889 bitindex = vlan & 0x1F; /* lower five bits */ 890 891 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex)); 892 if (vlan_on) 893 /* Turn on this VLAN id */ 894 bits |= BIT(bitindex); 895 else 896 /* Turn off this VLAN id */ 897 bits &= ~BIT(bitindex); 898 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits); 899 900 return 0; 901 } 902 903 /** 904 * ixgbe_clear_vfta_82598 - Clear VLAN filter table 905 * @hw: pointer to hardware structure 906 * 907 * Clears the VLAN filer table, and the VMDq index associated with the filter 908 **/ 909 static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw) 910 { 911 u32 offset; 912 u32 vlanbyte; 913 914 for (offset = 0; offset < hw->mac.vft_size; offset++) 915 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); 916 917 for (vlanbyte = 0; vlanbyte < 4; vlanbyte++) 918 for (offset = 0; offset < hw->mac.vft_size; offset++) 919 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset), 920 0); 921 922 return 0; 923 } 924 925 /** 926 * ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register 927 * @hw: pointer to hardware structure 928 * @reg: analog register to read 929 * @val: read value 930 * 931 * Performs read operation to Atlas analog register specified. 932 **/ 933 static s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val) 934 { 935 u32 atlas_ctl; 936 937 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, 938 IXGBE_ATLASCTL_WRITE_CMD | (reg << 8)); 939 IXGBE_WRITE_FLUSH(hw); 940 udelay(10); 941 atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL); 942 *val = (u8)atlas_ctl; 943 944 return 0; 945 } 946 947 /** 948 * ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register 949 * @hw: pointer to hardware structure 950 * @reg: atlas register to write 951 * @val: value to write 952 * 953 * Performs write operation to Atlas analog register specified. 954 **/ 955 static s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val) 956 { 957 u32 atlas_ctl; 958 959 atlas_ctl = (reg << 8) | val; 960 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl); 961 IXGBE_WRITE_FLUSH(hw); 962 udelay(10); 963 964 return 0; 965 } 966 967 /** 968 * ixgbe_read_i2c_phy_82598 - Reads 8 bit word over I2C interface. 969 * @hw: pointer to hardware structure 970 * @dev_addr: address to read from 971 * @byte_offset: byte offset to read from dev_addr 972 * @eeprom_data: value read 973 * 974 * Performs 8 byte read operation to SFP module's data over I2C interface. 975 **/ 976 static s32 ixgbe_read_i2c_phy_82598(struct ixgbe_hw *hw, u8 dev_addr, 977 u8 byte_offset, u8 *eeprom_data) 978 { 979 s32 status = 0; 980 u16 sfp_addr = 0; 981 u16 sfp_data = 0; 982 u16 sfp_stat = 0; 983 u16 gssr; 984 u32 i; 985 986 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 987 gssr = IXGBE_GSSR_PHY1_SM; 988 else 989 gssr = IXGBE_GSSR_PHY0_SM; 990 991 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != 0) 992 return IXGBE_ERR_SWFW_SYNC; 993 994 if (hw->phy.type == ixgbe_phy_nl) { 995 /* 996 * phy SDA/SCL registers are at addresses 0xC30A to 997 * 0xC30D. These registers are used to talk to the SFP+ 998 * module's EEPROM through the SDA/SCL (I2C) interface. 999 */ 1000 sfp_addr = (dev_addr << 8) + byte_offset; 1001 sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK); 1002 hw->phy.ops.write_reg_mdi(hw, 1003 IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR, 1004 MDIO_MMD_PMAPMD, 1005 sfp_addr); 1006 1007 /* Poll status */ 1008 for (i = 0; i < 100; i++) { 1009 hw->phy.ops.read_reg_mdi(hw, 1010 IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT, 1011 MDIO_MMD_PMAPMD, 1012 &sfp_stat); 1013 sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK; 1014 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS) 1015 break; 1016 usleep_range(10000, 20000); 1017 } 1018 1019 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) { 1020 hw_dbg(hw, "EEPROM read did not pass.\n"); 1021 status = IXGBE_ERR_SFP_NOT_PRESENT; 1022 goto out; 1023 } 1024 1025 /* Read data */ 1026 hw->phy.ops.read_reg_mdi(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA, 1027 MDIO_MMD_PMAPMD, &sfp_data); 1028 1029 *eeprom_data = (u8)(sfp_data >> 8); 1030 } else { 1031 status = IXGBE_ERR_PHY; 1032 } 1033 1034 out: 1035 hw->mac.ops.release_swfw_sync(hw, gssr); 1036 return status; 1037 } 1038 1039 /** 1040 * ixgbe_read_i2c_eeprom_82598 - Reads 8 bit word over I2C interface. 1041 * @hw: pointer to hardware structure 1042 * @byte_offset: EEPROM byte offset to read 1043 * @eeprom_data: value read 1044 * 1045 * Performs 8 byte read operation to SFP module's EEPROM over I2C interface. 1046 **/ 1047 static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset, 1048 u8 *eeprom_data) 1049 { 1050 return ixgbe_read_i2c_phy_82598(hw, IXGBE_I2C_EEPROM_DEV_ADDR, 1051 byte_offset, eeprom_data); 1052 } 1053 1054 /** 1055 * ixgbe_read_i2c_sff8472_82598 - Reads 8 bit word over I2C interface. 1056 * @hw: pointer to hardware structure 1057 * @byte_offset: byte offset at address 0xA2 1058 * @sff8472_data: value read 1059 * 1060 * Performs 8 byte read operation to SFP module's SFF-8472 data over I2C 1061 **/ 1062 static s32 ixgbe_read_i2c_sff8472_82598(struct ixgbe_hw *hw, u8 byte_offset, 1063 u8 *sff8472_data) 1064 { 1065 return ixgbe_read_i2c_phy_82598(hw, IXGBE_I2C_EEPROM_DEV_ADDR2, 1066 byte_offset, sff8472_data); 1067 } 1068 1069 /** 1070 * ixgbe_set_lan_id_multi_port_pcie_82598 - Set LAN id for PCIe multiple 1071 * port devices. 1072 * @hw: pointer to the HW structure 1073 * 1074 * Calls common function and corrects issue with some single port devices 1075 * that enable LAN1 but not LAN0. 1076 **/ 1077 static void ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw) 1078 { 1079 struct ixgbe_bus_info *bus = &hw->bus; 1080 u16 pci_gen = 0; 1081 u16 pci_ctrl2 = 0; 1082 1083 ixgbe_set_lan_id_multi_port_pcie(hw); 1084 1085 /* check if LAN0 is disabled */ 1086 hw->eeprom.ops.read(hw, IXGBE_PCIE_GENERAL_PTR, &pci_gen); 1087 if ((pci_gen != 0) && (pci_gen != 0xFFFF)) { 1088 1089 hw->eeprom.ops.read(hw, pci_gen + IXGBE_PCIE_CTRL2, &pci_ctrl2); 1090 1091 /* if LAN0 is completely disabled force function to 0 */ 1092 if ((pci_ctrl2 & IXGBE_PCIE_CTRL2_LAN_DISABLE) && 1093 !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DISABLE_SELECT) && 1094 !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DUMMY_ENABLE)) { 1095 1096 bus->func = 0; 1097 } 1098 } 1099 } 1100 1101 /** 1102 * ixgbe_set_rxpba_82598 - Initialize RX packet buffer 1103 * @hw: pointer to hardware structure 1104 * @num_pb: number of packet buffers to allocate 1105 * @headroom: reserve n KB of headroom 1106 * @strategy: packet buffer allocation strategy 1107 **/ 1108 static void ixgbe_set_rxpba_82598(struct ixgbe_hw *hw, int num_pb, 1109 u32 headroom, int strategy) 1110 { 1111 u32 rxpktsize = IXGBE_RXPBSIZE_64KB; 1112 u8 i = 0; 1113 1114 if (!num_pb) 1115 return; 1116 1117 /* Setup Rx packet buffer sizes */ 1118 switch (strategy) { 1119 case PBA_STRATEGY_WEIGHTED: 1120 /* Setup the first four at 80KB */ 1121 rxpktsize = IXGBE_RXPBSIZE_80KB; 1122 for (; i < 4; i++) 1123 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); 1124 /* Setup the last four at 48KB...don't re-init i */ 1125 rxpktsize = IXGBE_RXPBSIZE_48KB; 1126 /* Fall Through */ 1127 case PBA_STRATEGY_EQUAL: 1128 default: 1129 /* Divide the remaining Rx packet buffer evenly among the TCs */ 1130 for (; i < IXGBE_MAX_PACKET_BUFFERS; i++) 1131 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); 1132 break; 1133 } 1134 1135 /* Setup Tx packet buffer sizes */ 1136 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) 1137 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), IXGBE_TXPBSIZE_40KB); 1138 } 1139 1140 static const struct ixgbe_mac_operations mac_ops_82598 = { 1141 .init_hw = &ixgbe_init_hw_generic, 1142 .reset_hw = &ixgbe_reset_hw_82598, 1143 .start_hw = &ixgbe_start_hw_82598, 1144 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic, 1145 .get_media_type = &ixgbe_get_media_type_82598, 1146 .enable_rx_dma = &ixgbe_enable_rx_dma_generic, 1147 .get_mac_addr = &ixgbe_get_mac_addr_generic, 1148 .stop_adapter = &ixgbe_stop_adapter_generic, 1149 .get_bus_info = &ixgbe_get_bus_info_generic, 1150 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie_82598, 1151 .read_analog_reg8 = &ixgbe_read_analog_reg8_82598, 1152 .write_analog_reg8 = &ixgbe_write_analog_reg8_82598, 1153 .setup_link = &ixgbe_setup_mac_link_82598, 1154 .set_rxpba = &ixgbe_set_rxpba_82598, 1155 .check_link = &ixgbe_check_mac_link_82598, 1156 .get_link_capabilities = &ixgbe_get_link_capabilities_82598, 1157 .led_on = &ixgbe_led_on_generic, 1158 .led_off = &ixgbe_led_off_generic, 1159 .init_led_link_act = ixgbe_init_led_link_act_generic, 1160 .blink_led_start = &ixgbe_blink_led_start_generic, 1161 .blink_led_stop = &ixgbe_blink_led_stop_generic, 1162 .set_rar = &ixgbe_set_rar_generic, 1163 .clear_rar = &ixgbe_clear_rar_generic, 1164 .set_vmdq = &ixgbe_set_vmdq_82598, 1165 .clear_vmdq = &ixgbe_clear_vmdq_82598, 1166 .init_rx_addrs = &ixgbe_init_rx_addrs_generic, 1167 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic, 1168 .enable_mc = &ixgbe_enable_mc_generic, 1169 .disable_mc = &ixgbe_disable_mc_generic, 1170 .clear_vfta = &ixgbe_clear_vfta_82598, 1171 .set_vfta = &ixgbe_set_vfta_82598, 1172 .fc_enable = &ixgbe_fc_enable_82598, 1173 .setup_fc = ixgbe_setup_fc_generic, 1174 .fc_autoneg = ixgbe_fc_autoneg, 1175 .set_fw_drv_ver = NULL, 1176 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync, 1177 .release_swfw_sync = &ixgbe_release_swfw_sync, 1178 .init_swfw_sync = NULL, 1179 .get_thermal_sensor_data = NULL, 1180 .init_thermal_sensor_thresh = NULL, 1181 .prot_autoc_read = &prot_autoc_read_generic, 1182 .prot_autoc_write = &prot_autoc_write_generic, 1183 .enable_rx = &ixgbe_enable_rx_generic, 1184 .disable_rx = &ixgbe_disable_rx_generic, 1185 }; 1186 1187 static const struct ixgbe_eeprom_operations eeprom_ops_82598 = { 1188 .init_params = &ixgbe_init_eeprom_params_generic, 1189 .read = &ixgbe_read_eerd_generic, 1190 .write = &ixgbe_write_eeprom_generic, 1191 .write_buffer = &ixgbe_write_eeprom_buffer_bit_bang_generic, 1192 .read_buffer = &ixgbe_read_eerd_buffer_generic, 1193 .calc_checksum = &ixgbe_calc_eeprom_checksum_generic, 1194 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic, 1195 .update_checksum = &ixgbe_update_eeprom_checksum_generic, 1196 }; 1197 1198 static const struct ixgbe_phy_operations phy_ops_82598 = { 1199 .identify = &ixgbe_identify_phy_generic, 1200 .identify_sfp = &ixgbe_identify_module_generic, 1201 .init = &ixgbe_init_phy_ops_82598, 1202 .reset = &ixgbe_reset_phy_generic, 1203 .read_reg = &ixgbe_read_phy_reg_generic, 1204 .write_reg = &ixgbe_write_phy_reg_generic, 1205 .read_reg_mdi = &ixgbe_read_phy_reg_mdi, 1206 .write_reg_mdi = &ixgbe_write_phy_reg_mdi, 1207 .setup_link = &ixgbe_setup_phy_link_generic, 1208 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic, 1209 .read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_82598, 1210 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_82598, 1211 .check_overtemp = &ixgbe_tn_check_overtemp, 1212 }; 1213 1214 const struct ixgbe_info ixgbe_82598_info = { 1215 .mac = ixgbe_mac_82598EB, 1216 .get_invariants = &ixgbe_get_invariants_82598, 1217 .mac_ops = &mac_ops_82598, 1218 .eeprom_ops = &eeprom_ops_82598, 1219 .phy_ops = &phy_ops_82598, 1220 .mvals = ixgbe_mvals_8259X, 1221 }; 1222