1 /* 2 * OMAP DPLL clock support 3 * 4 * Copyright (C) 2013 Texas Instruments, Inc. 5 * 6 * Tero Kristo <t-kristo@ti.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 13 * kind, whether express or implied; without even the implied warranty 14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 */ 17 18 #include <linux/clk.h> 19 #include <linux/clk-provider.h> 20 #include <linux/slab.h> 21 #include <linux/err.h> 22 #include <linux/of.h> 23 #include <linux/of_address.h> 24 #include <linux/clk/ti.h> 25 #include "clock.h" 26 27 #undef pr_fmt 28 #define pr_fmt(fmt) "%s: " fmt, __func__ 29 30 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \ 31 defined(CONFIG_SOC_DRA7XX) 32 static const struct clk_ops dpll_m4xen_ck_ops = { 33 .enable = &omap3_noncore_dpll_enable, 34 .disable = &omap3_noncore_dpll_disable, 35 .recalc_rate = &omap4_dpll_regm4xen_recalc, 36 .round_rate = &omap4_dpll_regm4xen_round_rate, 37 .set_rate = &omap3_noncore_dpll_set_rate, 38 .set_parent = &omap3_noncore_dpll_set_parent, 39 .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent, 40 .determine_rate = &omap4_dpll_regm4xen_determine_rate, 41 .get_parent = &omap2_init_dpll_parent, 42 }; 43 #else 44 static const struct clk_ops dpll_m4xen_ck_ops = {}; 45 #endif 46 47 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) || \ 48 defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX) || \ 49 defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX) 50 static const struct clk_ops dpll_core_ck_ops = { 51 .recalc_rate = &omap3_dpll_recalc, 52 .get_parent = &omap2_init_dpll_parent, 53 }; 54 55 static const struct clk_ops dpll_ck_ops = { 56 .enable = &omap3_noncore_dpll_enable, 57 .disable = &omap3_noncore_dpll_disable, 58 .recalc_rate = &omap3_dpll_recalc, 59 .round_rate = &omap2_dpll_round_rate, 60 .set_rate = &omap3_noncore_dpll_set_rate, 61 .set_parent = &omap3_noncore_dpll_set_parent, 62 .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent, 63 .determine_rate = &omap3_noncore_dpll_determine_rate, 64 .get_parent = &omap2_init_dpll_parent, 65 }; 66 67 static const struct clk_ops dpll_no_gate_ck_ops = { 68 .recalc_rate = &omap3_dpll_recalc, 69 .get_parent = &omap2_init_dpll_parent, 70 .round_rate = &omap2_dpll_round_rate, 71 .set_rate = &omap3_noncore_dpll_set_rate, 72 .set_parent = &omap3_noncore_dpll_set_parent, 73 .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent, 74 .determine_rate = &omap3_noncore_dpll_determine_rate, 75 }; 76 #else 77 static const struct clk_ops dpll_core_ck_ops = {}; 78 static const struct clk_ops dpll_ck_ops = {}; 79 static const struct clk_ops dpll_no_gate_ck_ops = {}; 80 const struct clk_hw_omap_ops clkhwops_omap3_dpll = {}; 81 #endif 82 83 #ifdef CONFIG_ARCH_OMAP2 84 static const struct clk_ops omap2_dpll_core_ck_ops = { 85 .get_parent = &omap2_init_dpll_parent, 86 .recalc_rate = &omap2_dpllcore_recalc, 87 .round_rate = &omap2_dpll_round_rate, 88 .set_rate = &omap2_reprogram_dpllcore, 89 }; 90 #else 91 static const struct clk_ops omap2_dpll_core_ck_ops = {}; 92 #endif 93 94 #ifdef CONFIG_ARCH_OMAP3 95 static const struct clk_ops omap3_dpll_core_ck_ops = { 96 .get_parent = &omap2_init_dpll_parent, 97 .recalc_rate = &omap3_dpll_recalc, 98 .round_rate = &omap2_dpll_round_rate, 99 }; 100 #else 101 static const struct clk_ops omap3_dpll_core_ck_ops = {}; 102 #endif 103 104 #ifdef CONFIG_ARCH_OMAP3 105 static const struct clk_ops omap3_dpll_ck_ops = { 106 .enable = &omap3_noncore_dpll_enable, 107 .disable = &omap3_noncore_dpll_disable, 108 .get_parent = &omap2_init_dpll_parent, 109 .recalc_rate = &omap3_dpll_recalc, 110 .set_rate = &omap3_noncore_dpll_set_rate, 111 .set_parent = &omap3_noncore_dpll_set_parent, 112 .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent, 113 .determine_rate = &omap3_noncore_dpll_determine_rate, 114 .round_rate = &omap2_dpll_round_rate, 115 }; 116 117 static const struct clk_ops omap3_dpll5_ck_ops = { 118 .enable = &omap3_noncore_dpll_enable, 119 .disable = &omap3_noncore_dpll_disable, 120 .get_parent = &omap2_init_dpll_parent, 121 .recalc_rate = &omap3_dpll_recalc, 122 .set_rate = &omap3_dpll5_set_rate, 123 .set_parent = &omap3_noncore_dpll_set_parent, 124 .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent, 125 .determine_rate = &omap3_noncore_dpll_determine_rate, 126 .round_rate = &omap2_dpll_round_rate, 127 }; 128 129 static const struct clk_ops omap3_dpll_per_ck_ops = { 130 .enable = &omap3_noncore_dpll_enable, 131 .disable = &omap3_noncore_dpll_disable, 132 .get_parent = &omap2_init_dpll_parent, 133 .recalc_rate = &omap3_dpll_recalc, 134 .set_rate = &omap3_dpll4_set_rate, 135 .set_parent = &omap3_noncore_dpll_set_parent, 136 .set_rate_and_parent = &omap3_dpll4_set_rate_and_parent, 137 .determine_rate = &omap3_noncore_dpll_determine_rate, 138 .round_rate = &omap2_dpll_round_rate, 139 }; 140 #endif 141 142 static const struct clk_ops dpll_x2_ck_ops = { 143 .recalc_rate = &omap3_clkoutx2_recalc, 144 }; 145 146 /** 147 * _register_dpll - low level registration of a DPLL clock 148 * @hw: hardware clock definition for the clock 149 * @node: device node for the clock 150 * 151 * Finalizes DPLL registration process. In case a failure (clk-ref or 152 * clk-bypass is missing), the clock is added to retry list and 153 * the initialization is retried on later stage. 154 */ 155 static void __init _register_dpll(void *user, 156 struct device_node *node) 157 { 158 struct clk_hw *hw = user; 159 struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw); 160 struct dpll_data *dd = clk_hw->dpll_data; 161 struct clk *clk; 162 163 clk = of_clk_get(node, 0); 164 if (IS_ERR(clk)) { 165 pr_debug("clk-ref missing for %s, retry later\n", 166 node->name); 167 if (!ti_clk_retry_init(node, hw, _register_dpll)) 168 return; 169 170 goto cleanup; 171 } 172 173 dd->clk_ref = __clk_get_hw(clk); 174 175 clk = of_clk_get(node, 1); 176 177 if (IS_ERR(clk)) { 178 pr_debug("clk-bypass missing for %s, retry later\n", 179 node->name); 180 if (!ti_clk_retry_init(node, hw, _register_dpll)) 181 return; 182 183 goto cleanup; 184 } 185 186 dd->clk_bypass = __clk_get_hw(clk); 187 188 /* register the clock */ 189 clk = ti_clk_register(NULL, &clk_hw->hw, node->name); 190 191 if (!IS_ERR(clk)) { 192 omap2_init_clk_hw_omap_clocks(&clk_hw->hw); 193 of_clk_add_provider(node, of_clk_src_simple_get, clk); 194 kfree(clk_hw->hw.init->parent_names); 195 kfree(clk_hw->hw.init); 196 return; 197 } 198 199 cleanup: 200 kfree(clk_hw->dpll_data); 201 kfree(clk_hw->hw.init->parent_names); 202 kfree(clk_hw->hw.init); 203 kfree(clk_hw); 204 } 205 206 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_ATAGS) 207 void _get_reg(u8 module, u16 offset, struct clk_omap_reg *reg) 208 { 209 reg->index = module; 210 reg->offset = offset; 211 } 212 213 struct clk *ti_clk_register_dpll(struct ti_clk *setup) 214 { 215 struct clk_hw_omap *clk_hw; 216 struct clk_init_data init = { NULL }; 217 struct dpll_data *dd; 218 struct clk *clk; 219 struct ti_clk_dpll *dpll; 220 const struct clk_ops *ops = &omap3_dpll_ck_ops; 221 struct clk *clk_ref; 222 struct clk *clk_bypass; 223 224 dpll = setup->data; 225 226 if (dpll->num_parents < 2) 227 return ERR_PTR(-EINVAL); 228 229 clk_ref = clk_get_sys(NULL, dpll->parents[0]); 230 clk_bypass = clk_get_sys(NULL, dpll->parents[1]); 231 232 if (IS_ERR_OR_NULL(clk_ref) || IS_ERR_OR_NULL(clk_bypass)) 233 return ERR_PTR(-EAGAIN); 234 235 dd = kzalloc(sizeof(*dd), GFP_KERNEL); 236 clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL); 237 if (!dd || !clk_hw) { 238 clk = ERR_PTR(-ENOMEM); 239 goto cleanup; 240 } 241 242 clk_hw->dpll_data = dd; 243 clk_hw->ops = &clkhwops_omap3_dpll; 244 clk_hw->hw.init = &init; 245 246 init.name = setup->name; 247 init.ops = ops; 248 249 init.num_parents = dpll->num_parents; 250 init.parent_names = dpll->parents; 251 252 _get_reg(dpll->module, dpll->control_reg, &dd->control_reg); 253 _get_reg(dpll->module, dpll->idlest_reg, &dd->idlest_reg); 254 _get_reg(dpll->module, dpll->mult_div1_reg, &dd->mult_div1_reg); 255 _get_reg(dpll->module, dpll->autoidle_reg, &dd->autoidle_reg); 256 257 dd->modes = dpll->modes; 258 dd->div1_mask = dpll->div1_mask; 259 dd->idlest_mask = dpll->idlest_mask; 260 dd->mult_mask = dpll->mult_mask; 261 dd->autoidle_mask = dpll->autoidle_mask; 262 dd->enable_mask = dpll->enable_mask; 263 dd->sddiv_mask = dpll->sddiv_mask; 264 dd->dco_mask = dpll->dco_mask; 265 dd->max_divider = dpll->max_divider; 266 dd->min_divider = dpll->min_divider; 267 dd->max_multiplier = dpll->max_multiplier; 268 dd->auto_recal_bit = dpll->auto_recal_bit; 269 dd->recal_en_bit = dpll->recal_en_bit; 270 dd->recal_st_bit = dpll->recal_st_bit; 271 272 dd->clk_ref = __clk_get_hw(clk_ref); 273 dd->clk_bypass = __clk_get_hw(clk_bypass); 274 275 if (dpll->flags & CLKF_CORE) 276 ops = &omap3_dpll_core_ck_ops; 277 278 if (dpll->flags & CLKF_PER) 279 ops = &omap3_dpll_per_ck_ops; 280 281 if (dpll->flags & CLKF_J_TYPE) 282 dd->flags |= DPLL_J_TYPE; 283 284 clk = ti_clk_register(NULL, &clk_hw->hw, setup->name); 285 286 if (!IS_ERR(clk)) 287 return clk; 288 289 cleanup: 290 kfree(dd); 291 kfree(clk_hw); 292 return clk; 293 } 294 #endif 295 296 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \ 297 defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM33XX) || \ 298 defined(CONFIG_SOC_AM43XX) 299 /** 300 * _register_dpll_x2 - Registers a DPLLx2 clock 301 * @node: device node for this clock 302 * @ops: clk_ops for this clock 303 * @hw_ops: clk_hw_ops for this clock 304 * 305 * Initializes a DPLL x 2 clock from device tree data. 306 */ 307 static void _register_dpll_x2(struct device_node *node, 308 const struct clk_ops *ops, 309 const struct clk_hw_omap_ops *hw_ops) 310 { 311 struct clk *clk; 312 struct clk_init_data init = { NULL }; 313 struct clk_hw_omap *clk_hw; 314 const char *name = node->name; 315 const char *parent_name; 316 317 parent_name = of_clk_get_parent_name(node, 0); 318 if (!parent_name) { 319 pr_err("%s must have parent\n", node->name); 320 return; 321 } 322 323 clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL); 324 if (!clk_hw) 325 return; 326 327 clk_hw->ops = hw_ops; 328 clk_hw->hw.init = &init; 329 330 init.name = name; 331 init.ops = ops; 332 init.parent_names = &parent_name; 333 init.num_parents = 1; 334 335 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \ 336 defined(CONFIG_SOC_DRA7XX) 337 if (hw_ops == &clkhwops_omap4_dpllmx) { 338 int ret; 339 340 /* Check if register defined, if not, drop hw-ops */ 341 ret = of_property_count_elems_of_size(node, "reg", 1); 342 if (ret <= 0) { 343 clk_hw->ops = NULL; 344 } else if (ti_clk_get_reg_addr(node, 0, &clk_hw->clksel_reg)) { 345 kfree(clk_hw); 346 return; 347 } 348 } 349 #endif 350 351 /* register the clock */ 352 clk = ti_clk_register(NULL, &clk_hw->hw, name); 353 354 if (IS_ERR(clk)) { 355 kfree(clk_hw); 356 } else { 357 omap2_init_clk_hw_omap_clocks(&clk_hw->hw); 358 of_clk_add_provider(node, of_clk_src_simple_get, clk); 359 } 360 } 361 #endif 362 363 /** 364 * of_ti_dpll_setup - Setup function for OMAP DPLL clocks 365 * @node: device node containing the DPLL info 366 * @ops: ops for the DPLL 367 * @ddt: DPLL data template to use 368 * 369 * Initializes a DPLL clock from device tree data. 370 */ 371 static void __init of_ti_dpll_setup(struct device_node *node, 372 const struct clk_ops *ops, 373 const struct dpll_data *ddt) 374 { 375 struct clk_hw_omap *clk_hw = NULL; 376 struct clk_init_data *init = NULL; 377 const char **parent_names = NULL; 378 struct dpll_data *dd = NULL; 379 u8 dpll_mode = 0; 380 381 dd = kzalloc(sizeof(*dd), GFP_KERNEL); 382 clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL); 383 init = kzalloc(sizeof(*init), GFP_KERNEL); 384 if (!dd || !clk_hw || !init) 385 goto cleanup; 386 387 memcpy(dd, ddt, sizeof(*dd)); 388 389 clk_hw->dpll_data = dd; 390 clk_hw->ops = &clkhwops_omap3_dpll; 391 clk_hw->hw.init = init; 392 393 init->name = node->name; 394 init->ops = ops; 395 396 init->num_parents = of_clk_get_parent_count(node); 397 if (!init->num_parents) { 398 pr_err("%s must have parent(s)\n", node->name); 399 goto cleanup; 400 } 401 402 parent_names = kzalloc(sizeof(char *) * init->num_parents, GFP_KERNEL); 403 if (!parent_names) 404 goto cleanup; 405 406 of_clk_parent_fill(node, parent_names, init->num_parents); 407 408 init->parent_names = parent_names; 409 410 if (ti_clk_get_reg_addr(node, 0, &dd->control_reg)) 411 goto cleanup; 412 413 /* 414 * Special case for OMAP2 DPLL, register order is different due to 415 * missing idlest_reg, also clkhwops is different. Detected from 416 * missing idlest_mask. 417 */ 418 if (!dd->idlest_mask) { 419 if (ti_clk_get_reg_addr(node, 1, &dd->mult_div1_reg)) 420 goto cleanup; 421 #ifdef CONFIG_ARCH_OMAP2 422 clk_hw->ops = &clkhwops_omap2xxx_dpll; 423 omap2xxx_clkt_dpllcore_init(&clk_hw->hw); 424 #endif 425 } else { 426 if (ti_clk_get_reg_addr(node, 1, &dd->idlest_reg)) 427 goto cleanup; 428 429 if (ti_clk_get_reg_addr(node, 2, &dd->mult_div1_reg)) 430 goto cleanup; 431 } 432 433 if (dd->autoidle_mask) { 434 if (ti_clk_get_reg_addr(node, 3, &dd->autoidle_reg)) 435 goto cleanup; 436 } 437 438 if (of_property_read_bool(node, "ti,low-power-stop")) 439 dpll_mode |= 1 << DPLL_LOW_POWER_STOP; 440 441 if (of_property_read_bool(node, "ti,low-power-bypass")) 442 dpll_mode |= 1 << DPLL_LOW_POWER_BYPASS; 443 444 if (of_property_read_bool(node, "ti,lock")) 445 dpll_mode |= 1 << DPLL_LOCKED; 446 447 if (dpll_mode) 448 dd->modes = dpll_mode; 449 450 _register_dpll(&clk_hw->hw, node); 451 return; 452 453 cleanup: 454 kfree(dd); 455 kfree(parent_names); 456 kfree(init); 457 kfree(clk_hw); 458 } 459 460 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \ 461 defined(CONFIG_SOC_DRA7XX) 462 static void __init of_ti_omap4_dpll_x2_setup(struct device_node *node) 463 { 464 _register_dpll_x2(node, &dpll_x2_ck_ops, &clkhwops_omap4_dpllmx); 465 } 466 CLK_OF_DECLARE(ti_omap4_dpll_x2_clock, "ti,omap4-dpll-x2-clock", 467 of_ti_omap4_dpll_x2_setup); 468 #endif 469 470 #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX) 471 static void __init of_ti_am3_dpll_x2_setup(struct device_node *node) 472 { 473 _register_dpll_x2(node, &dpll_x2_ck_ops, NULL); 474 } 475 CLK_OF_DECLARE(ti_am3_dpll_x2_clock, "ti,am3-dpll-x2-clock", 476 of_ti_am3_dpll_x2_setup); 477 #endif 478 479 #ifdef CONFIG_ARCH_OMAP3 480 static void __init of_ti_omap3_dpll_setup(struct device_node *node) 481 { 482 const struct dpll_data dd = { 483 .idlest_mask = 0x1, 484 .enable_mask = 0x7, 485 .autoidle_mask = 0x7, 486 .mult_mask = 0x7ff << 8, 487 .div1_mask = 0x7f, 488 .max_multiplier = 2047, 489 .max_divider = 128, 490 .min_divider = 1, 491 .freqsel_mask = 0xf0, 492 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 493 }; 494 495 if ((of_machine_is_compatible("ti,omap3630") || 496 of_machine_is_compatible("ti,omap36xx")) && 497 !strcmp(node->name, "dpll5_ck")) 498 of_ti_dpll_setup(node, &omap3_dpll5_ck_ops, &dd); 499 else 500 of_ti_dpll_setup(node, &omap3_dpll_ck_ops, &dd); 501 } 502 CLK_OF_DECLARE(ti_omap3_dpll_clock, "ti,omap3-dpll-clock", 503 of_ti_omap3_dpll_setup); 504 505 static void __init of_ti_omap3_core_dpll_setup(struct device_node *node) 506 { 507 const struct dpll_data dd = { 508 .idlest_mask = 0x1, 509 .enable_mask = 0x7, 510 .autoidle_mask = 0x7, 511 .mult_mask = 0x7ff << 16, 512 .div1_mask = 0x7f << 8, 513 .max_multiplier = 2047, 514 .max_divider = 128, 515 .min_divider = 1, 516 .freqsel_mask = 0xf0, 517 }; 518 519 of_ti_dpll_setup(node, &omap3_dpll_core_ck_ops, &dd); 520 } 521 CLK_OF_DECLARE(ti_omap3_core_dpll_clock, "ti,omap3-dpll-core-clock", 522 of_ti_omap3_core_dpll_setup); 523 524 static void __init of_ti_omap3_per_dpll_setup(struct device_node *node) 525 { 526 const struct dpll_data dd = { 527 .idlest_mask = 0x1 << 1, 528 .enable_mask = 0x7 << 16, 529 .autoidle_mask = 0x7 << 3, 530 .mult_mask = 0x7ff << 8, 531 .div1_mask = 0x7f, 532 .max_multiplier = 2047, 533 .max_divider = 128, 534 .min_divider = 1, 535 .freqsel_mask = 0xf00000, 536 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), 537 }; 538 539 of_ti_dpll_setup(node, &omap3_dpll_per_ck_ops, &dd); 540 } 541 CLK_OF_DECLARE(ti_omap3_per_dpll_clock, "ti,omap3-dpll-per-clock", 542 of_ti_omap3_per_dpll_setup); 543 544 static void __init of_ti_omap3_per_jtype_dpll_setup(struct device_node *node) 545 { 546 const struct dpll_data dd = { 547 .idlest_mask = 0x1 << 1, 548 .enable_mask = 0x7 << 16, 549 .autoidle_mask = 0x7 << 3, 550 .mult_mask = 0xfff << 8, 551 .div1_mask = 0x7f, 552 .max_multiplier = 4095, 553 .max_divider = 128, 554 .min_divider = 1, 555 .sddiv_mask = 0xff << 24, 556 .dco_mask = 0xe << 20, 557 .flags = DPLL_J_TYPE, 558 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), 559 }; 560 561 of_ti_dpll_setup(node, &omap3_dpll_per_ck_ops, &dd); 562 } 563 CLK_OF_DECLARE(ti_omap3_per_jtype_dpll_clock, "ti,omap3-dpll-per-j-type-clock", 564 of_ti_omap3_per_jtype_dpll_setup); 565 #endif 566 567 static void __init of_ti_omap4_dpll_setup(struct device_node *node) 568 { 569 const struct dpll_data dd = { 570 .idlest_mask = 0x1, 571 .enable_mask = 0x7, 572 .autoidle_mask = 0x7, 573 .mult_mask = 0x7ff << 8, 574 .div1_mask = 0x7f, 575 .max_multiplier = 2047, 576 .max_divider = 128, 577 .min_divider = 1, 578 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 579 }; 580 581 of_ti_dpll_setup(node, &dpll_ck_ops, &dd); 582 } 583 CLK_OF_DECLARE(ti_omap4_dpll_clock, "ti,omap4-dpll-clock", 584 of_ti_omap4_dpll_setup); 585 586 static void __init of_ti_omap5_mpu_dpll_setup(struct device_node *node) 587 { 588 const struct dpll_data dd = { 589 .idlest_mask = 0x1, 590 .enable_mask = 0x7, 591 .autoidle_mask = 0x7, 592 .mult_mask = 0x7ff << 8, 593 .div1_mask = 0x7f, 594 .max_multiplier = 2047, 595 .max_divider = 128, 596 .dcc_mask = BIT(22), 597 .dcc_rate = 1400000000, /* DCC beyond 1.4GHz */ 598 .min_divider = 1, 599 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 600 }; 601 602 of_ti_dpll_setup(node, &dpll_ck_ops, &dd); 603 } 604 CLK_OF_DECLARE(of_ti_omap5_mpu_dpll_clock, "ti,omap5-mpu-dpll-clock", 605 of_ti_omap5_mpu_dpll_setup); 606 607 static void __init of_ti_omap4_core_dpll_setup(struct device_node *node) 608 { 609 const struct dpll_data dd = { 610 .idlest_mask = 0x1, 611 .enable_mask = 0x7, 612 .autoidle_mask = 0x7, 613 .mult_mask = 0x7ff << 8, 614 .div1_mask = 0x7f, 615 .max_multiplier = 2047, 616 .max_divider = 128, 617 .min_divider = 1, 618 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 619 }; 620 621 of_ti_dpll_setup(node, &dpll_core_ck_ops, &dd); 622 } 623 CLK_OF_DECLARE(ti_omap4_core_dpll_clock, "ti,omap4-dpll-core-clock", 624 of_ti_omap4_core_dpll_setup); 625 626 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \ 627 defined(CONFIG_SOC_DRA7XX) 628 static void __init of_ti_omap4_m4xen_dpll_setup(struct device_node *node) 629 { 630 const struct dpll_data dd = { 631 .idlest_mask = 0x1, 632 .enable_mask = 0x7, 633 .autoidle_mask = 0x7, 634 .mult_mask = 0x7ff << 8, 635 .div1_mask = 0x7f, 636 .max_multiplier = 2047, 637 .max_divider = 128, 638 .min_divider = 1, 639 .m4xen_mask = 0x800, 640 .lpmode_mask = 1 << 10, 641 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 642 }; 643 644 of_ti_dpll_setup(node, &dpll_m4xen_ck_ops, &dd); 645 } 646 CLK_OF_DECLARE(ti_omap4_m4xen_dpll_clock, "ti,omap4-dpll-m4xen-clock", 647 of_ti_omap4_m4xen_dpll_setup); 648 649 static void __init of_ti_omap4_jtype_dpll_setup(struct device_node *node) 650 { 651 const struct dpll_data dd = { 652 .idlest_mask = 0x1, 653 .enable_mask = 0x7, 654 .autoidle_mask = 0x7, 655 .mult_mask = 0xfff << 8, 656 .div1_mask = 0xff, 657 .max_multiplier = 4095, 658 .max_divider = 256, 659 .min_divider = 1, 660 .sddiv_mask = 0xff << 24, 661 .flags = DPLL_J_TYPE, 662 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 663 }; 664 665 of_ti_dpll_setup(node, &dpll_m4xen_ck_ops, &dd); 666 } 667 CLK_OF_DECLARE(ti_omap4_jtype_dpll_clock, "ti,omap4-dpll-j-type-clock", 668 of_ti_omap4_jtype_dpll_setup); 669 #endif 670 671 static void __init of_ti_am3_no_gate_dpll_setup(struct device_node *node) 672 { 673 const struct dpll_data dd = { 674 .idlest_mask = 0x1, 675 .enable_mask = 0x7, 676 .mult_mask = 0x7ff << 8, 677 .div1_mask = 0x7f, 678 .max_multiplier = 2047, 679 .max_divider = 128, 680 .min_divider = 1, 681 .max_rate = 1000000000, 682 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 683 }; 684 685 of_ti_dpll_setup(node, &dpll_no_gate_ck_ops, &dd); 686 } 687 CLK_OF_DECLARE(ti_am3_no_gate_dpll_clock, "ti,am3-dpll-no-gate-clock", 688 of_ti_am3_no_gate_dpll_setup); 689 690 static void __init of_ti_am3_jtype_dpll_setup(struct device_node *node) 691 { 692 const struct dpll_data dd = { 693 .idlest_mask = 0x1, 694 .enable_mask = 0x7, 695 .mult_mask = 0x7ff << 8, 696 .div1_mask = 0x7f, 697 .max_multiplier = 4095, 698 .max_divider = 256, 699 .min_divider = 2, 700 .flags = DPLL_J_TYPE, 701 .max_rate = 2000000000, 702 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 703 }; 704 705 of_ti_dpll_setup(node, &dpll_ck_ops, &dd); 706 } 707 CLK_OF_DECLARE(ti_am3_jtype_dpll_clock, "ti,am3-dpll-j-type-clock", 708 of_ti_am3_jtype_dpll_setup); 709 710 static void __init of_ti_am3_no_gate_jtype_dpll_setup(struct device_node *node) 711 { 712 const struct dpll_data dd = { 713 .idlest_mask = 0x1, 714 .enable_mask = 0x7, 715 .mult_mask = 0x7ff << 8, 716 .div1_mask = 0x7f, 717 .max_multiplier = 2047, 718 .max_divider = 128, 719 .min_divider = 1, 720 .max_rate = 2000000000, 721 .flags = DPLL_J_TYPE, 722 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 723 }; 724 725 of_ti_dpll_setup(node, &dpll_no_gate_ck_ops, &dd); 726 } 727 CLK_OF_DECLARE(ti_am3_no_gate_jtype_dpll_clock, 728 "ti,am3-dpll-no-gate-j-type-clock", 729 of_ti_am3_no_gate_jtype_dpll_setup); 730 731 static void __init of_ti_am3_dpll_setup(struct device_node *node) 732 { 733 const struct dpll_data dd = { 734 .idlest_mask = 0x1, 735 .enable_mask = 0x7, 736 .mult_mask = 0x7ff << 8, 737 .div1_mask = 0x7f, 738 .max_multiplier = 2047, 739 .max_divider = 128, 740 .min_divider = 1, 741 .max_rate = 1000000000, 742 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 743 }; 744 745 of_ti_dpll_setup(node, &dpll_ck_ops, &dd); 746 } 747 CLK_OF_DECLARE(ti_am3_dpll_clock, "ti,am3-dpll-clock", of_ti_am3_dpll_setup); 748 749 static void __init of_ti_am3_core_dpll_setup(struct device_node *node) 750 { 751 const struct dpll_data dd = { 752 .idlest_mask = 0x1, 753 .enable_mask = 0x7, 754 .mult_mask = 0x7ff << 8, 755 .div1_mask = 0x7f, 756 .max_multiplier = 2047, 757 .max_divider = 128, 758 .min_divider = 1, 759 .max_rate = 1000000000, 760 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 761 }; 762 763 of_ti_dpll_setup(node, &dpll_core_ck_ops, &dd); 764 } 765 CLK_OF_DECLARE(ti_am3_core_dpll_clock, "ti,am3-dpll-core-clock", 766 of_ti_am3_core_dpll_setup); 767 768 static void __init of_ti_omap2_core_dpll_setup(struct device_node *node) 769 { 770 const struct dpll_data dd = { 771 .enable_mask = 0x3, 772 .mult_mask = 0x3ff << 12, 773 .div1_mask = 0xf << 8, 774 .max_divider = 16, 775 .min_divider = 1, 776 }; 777 778 of_ti_dpll_setup(node, &omap2_dpll_core_ck_ops, &dd); 779 } 780 CLK_OF_DECLARE(ti_omap2_core_dpll_clock, "ti,omap2-dpll-core-clock", 781 of_ti_omap2_core_dpll_setup); 782