1 /* 2 * Copyright 2017, Nicholas Piggin, IBM Corporation 3 * Licensed under GPLv2. 4 */ 5 6 #define pr_fmt(fmt) "dt-cpu-ftrs: " fmt 7 8 #include <linux/export.h> 9 #include <linux/init.h> 10 #include <linux/jump_label.h> 11 #include <linux/libfdt.h> 12 #include <linux/memblock.h> 13 #include <linux/printk.h> 14 #include <linux/sched.h> 15 #include <linux/string.h> 16 #include <linux/threads.h> 17 18 #include <asm/cputable.h> 19 #include <asm/dt_cpu_ftrs.h> 20 #include <asm/mmu.h> 21 #include <asm/oprofile_impl.h> 22 #include <asm/prom.h> 23 #include <asm/setup.h> 24 25 26 /* Device-tree visible constants follow */ 27 #define ISA_V2_07B 2070 28 #define ISA_V3_0B 3000 29 30 #define USABLE_PR (1U << 0) 31 #define USABLE_OS (1U << 1) 32 #define USABLE_HV (1U << 2) 33 34 #define HV_SUPPORT_HFSCR (1U << 0) 35 #define OS_SUPPORT_FSCR (1U << 0) 36 37 /* For parsing, we define all bits set as "NONE" case */ 38 #define HV_SUPPORT_NONE 0xffffffffU 39 #define OS_SUPPORT_NONE 0xffffffffU 40 41 struct dt_cpu_feature { 42 const char *name; 43 uint32_t isa; 44 uint32_t usable_privilege; 45 uint32_t hv_support; 46 uint32_t os_support; 47 uint32_t hfscr_bit_nr; 48 uint32_t fscr_bit_nr; 49 uint32_t hwcap_bit_nr; 50 /* fdt parsing */ 51 unsigned long node; 52 int enabled; 53 int disabled; 54 }; 55 56 #define CPU_FTRS_BASE \ 57 (CPU_FTR_USE_TB | \ 58 CPU_FTR_LWSYNC | \ 59 CPU_FTR_FPU_UNAVAILABLE |\ 60 CPU_FTR_NODSISRALIGN |\ 61 CPU_FTR_NOEXECUTE |\ 62 CPU_FTR_COHERENT_ICACHE | \ 63 CPU_FTR_STCX_CHECKS_ADDRESS |\ 64 CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ 65 CPU_FTR_DAWR | \ 66 CPU_FTR_ARCH_206 |\ 67 CPU_FTR_ARCH_207S) 68 69 #define MMU_FTRS_HASH_BASE (MMU_FTRS_POWER8) 70 71 #define COMMON_USER_BASE (PPC_FEATURE_32 | PPC_FEATURE_64 | \ 72 PPC_FEATURE_ARCH_2_06 |\ 73 PPC_FEATURE_ICACHE_SNOOP) 74 #define COMMON_USER2_BASE (PPC_FEATURE2_ARCH_2_07 | \ 75 PPC_FEATURE2_ISEL) 76 /* 77 * Set up the base CPU 78 */ 79 80 extern long __machine_check_early_realmode_p8(struct pt_regs *regs); 81 extern long __machine_check_early_realmode_p9(struct pt_regs *regs); 82 83 static int hv_mode; 84 85 static struct { 86 u64 lpcr; 87 u64 hfscr; 88 u64 fscr; 89 } system_registers; 90 91 static void (*init_pmu_registers)(void); 92 93 static void __restore_cpu_cpufeatures(void) 94 { 95 /* 96 * LPCR is restored by the power on engine already. It can be changed 97 * after early init e.g., by radix enable, and we have no unified API 98 * for saving and restoring such SPRs. 99 * 100 * This ->restore hook should really be removed from idle and register 101 * restore moved directly into the idle restore code, because this code 102 * doesn't know how idle is implemented or what it needs restored here. 103 * 104 * The best we can do to accommodate secondary boot and idle restore 105 * for now is "or" LPCR with existing. 106 */ 107 108 mtspr(SPRN_LPCR, system_registers.lpcr | mfspr(SPRN_LPCR)); 109 if (hv_mode) { 110 mtspr(SPRN_LPID, 0); 111 mtspr(SPRN_HFSCR, system_registers.hfscr); 112 } 113 mtspr(SPRN_FSCR, system_registers.fscr); 114 115 if (init_pmu_registers) 116 init_pmu_registers(); 117 } 118 119 static char dt_cpu_name[64]; 120 121 static struct cpu_spec __initdata base_cpu_spec = { 122 .cpu_name = NULL, 123 .cpu_features = CPU_FTRS_BASE, 124 .cpu_user_features = COMMON_USER_BASE, 125 .cpu_user_features2 = COMMON_USER2_BASE, 126 .mmu_features = 0, 127 .icache_bsize = 32, /* minimum block size, fixed by */ 128 .dcache_bsize = 32, /* cache info init. */ 129 .num_pmcs = 0, 130 .pmc_type = PPC_PMC_DEFAULT, 131 .oprofile_cpu_type = NULL, 132 .oprofile_type = PPC_OPROFILE_INVALID, 133 .cpu_setup = NULL, 134 .cpu_restore = __restore_cpu_cpufeatures, 135 .machine_check_early = NULL, 136 .platform = NULL, 137 }; 138 139 static void __init cpufeatures_setup_cpu(void) 140 { 141 set_cur_cpu_spec(&base_cpu_spec); 142 143 cur_cpu_spec->pvr_mask = -1; 144 cur_cpu_spec->pvr_value = mfspr(SPRN_PVR); 145 146 /* Initialize the base environment -- clear FSCR/HFSCR. */ 147 hv_mode = !!(mfmsr() & MSR_HV); 148 if (hv_mode) { 149 /* CPU_FTR_HVMODE is used early in PACA setup */ 150 cur_cpu_spec->cpu_features |= CPU_FTR_HVMODE; 151 mtspr(SPRN_HFSCR, 0); 152 } 153 mtspr(SPRN_FSCR, 0); 154 155 /* 156 * LPCR does not get cleared, to match behaviour with secondaries 157 * in __restore_cpu_cpufeatures. Once the idle code is fixed, this 158 * could clear LPCR too. 159 */ 160 } 161 162 static int __init feat_try_enable_unknown(struct dt_cpu_feature *f) 163 { 164 if (f->hv_support == HV_SUPPORT_NONE) { 165 } else if (f->hv_support & HV_SUPPORT_HFSCR) { 166 u64 hfscr = mfspr(SPRN_HFSCR); 167 hfscr |= 1UL << f->hfscr_bit_nr; 168 mtspr(SPRN_HFSCR, hfscr); 169 } else { 170 /* Does not have a known recipe */ 171 return 0; 172 } 173 174 if (f->os_support == OS_SUPPORT_NONE) { 175 } else if (f->os_support & OS_SUPPORT_FSCR) { 176 u64 fscr = mfspr(SPRN_FSCR); 177 fscr |= 1UL << f->fscr_bit_nr; 178 mtspr(SPRN_FSCR, fscr); 179 } else { 180 /* Does not have a known recipe */ 181 return 0; 182 } 183 184 if ((f->usable_privilege & USABLE_PR) && (f->hwcap_bit_nr != -1)) { 185 uint32_t word = f->hwcap_bit_nr / 32; 186 uint32_t bit = f->hwcap_bit_nr % 32; 187 188 if (word == 0) 189 cur_cpu_spec->cpu_user_features |= 1U << bit; 190 else if (word == 1) 191 cur_cpu_spec->cpu_user_features2 |= 1U << bit; 192 else 193 pr_err("%s could not advertise to user (no hwcap bits)\n", f->name); 194 } 195 196 return 1; 197 } 198 199 static int __init feat_enable(struct dt_cpu_feature *f) 200 { 201 if (f->hv_support != HV_SUPPORT_NONE) { 202 if (f->hfscr_bit_nr != -1) { 203 u64 hfscr = mfspr(SPRN_HFSCR); 204 hfscr |= 1UL << f->hfscr_bit_nr; 205 mtspr(SPRN_HFSCR, hfscr); 206 } 207 } 208 209 if (f->os_support != OS_SUPPORT_NONE) { 210 if (f->fscr_bit_nr != -1) { 211 u64 fscr = mfspr(SPRN_FSCR); 212 fscr |= 1UL << f->fscr_bit_nr; 213 mtspr(SPRN_FSCR, fscr); 214 } 215 } 216 217 if ((f->usable_privilege & USABLE_PR) && (f->hwcap_bit_nr != -1)) { 218 uint32_t word = f->hwcap_bit_nr / 32; 219 uint32_t bit = f->hwcap_bit_nr % 32; 220 221 if (word == 0) 222 cur_cpu_spec->cpu_user_features |= 1U << bit; 223 else if (word == 1) 224 cur_cpu_spec->cpu_user_features2 |= 1U << bit; 225 else 226 pr_err("CPU feature: %s could not advertise to user (no hwcap bits)\n", f->name); 227 } 228 229 return 1; 230 } 231 232 static int __init feat_disable(struct dt_cpu_feature *f) 233 { 234 return 0; 235 } 236 237 static int __init feat_enable_hv(struct dt_cpu_feature *f) 238 { 239 u64 lpcr; 240 241 if (!hv_mode) { 242 pr_err("CPU feature hypervisor present in device tree but HV mode not enabled in the CPU. Ignoring.\n"); 243 return 0; 244 } 245 246 mtspr(SPRN_LPID, 0); 247 248 lpcr = mfspr(SPRN_LPCR); 249 lpcr &= ~LPCR_LPES0; /* HV external interrupts */ 250 mtspr(SPRN_LPCR, lpcr); 251 252 cur_cpu_spec->cpu_features |= CPU_FTR_HVMODE; 253 254 return 1; 255 } 256 257 static int __init feat_enable_le(struct dt_cpu_feature *f) 258 { 259 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_TRUE_LE; 260 return 1; 261 } 262 263 static int __init feat_enable_smt(struct dt_cpu_feature *f) 264 { 265 cur_cpu_spec->cpu_features |= CPU_FTR_SMT; 266 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_SMT; 267 return 1; 268 } 269 270 static int __init feat_enable_idle_nap(struct dt_cpu_feature *f) 271 { 272 u64 lpcr; 273 274 /* Set PECE wakeup modes for ISA 207 */ 275 lpcr = mfspr(SPRN_LPCR); 276 lpcr |= LPCR_PECE0; 277 lpcr |= LPCR_PECE1; 278 lpcr |= LPCR_PECE2; 279 mtspr(SPRN_LPCR, lpcr); 280 281 return 1; 282 } 283 284 static int __init feat_enable_align_dsisr(struct dt_cpu_feature *f) 285 { 286 cur_cpu_spec->cpu_features &= ~CPU_FTR_NODSISRALIGN; 287 288 return 1; 289 } 290 291 static int __init feat_enable_idle_stop(struct dt_cpu_feature *f) 292 { 293 u64 lpcr; 294 295 /* Set PECE wakeup modes for ISAv3.0B */ 296 lpcr = mfspr(SPRN_LPCR); 297 lpcr |= LPCR_PECE0; 298 lpcr |= LPCR_PECE1; 299 lpcr |= LPCR_PECE2; 300 mtspr(SPRN_LPCR, lpcr); 301 302 return 1; 303 } 304 305 static int __init feat_enable_mmu_hash(struct dt_cpu_feature *f) 306 { 307 u64 lpcr; 308 309 lpcr = mfspr(SPRN_LPCR); 310 lpcr &= ~LPCR_ISL; 311 312 /* VRMASD */ 313 lpcr |= LPCR_VPM0; 314 lpcr &= ~LPCR_VPM1; 315 lpcr |= 0x10UL << LPCR_VRMASD_SH; /* L=1 LP=00 */ 316 mtspr(SPRN_LPCR, lpcr); 317 318 cur_cpu_spec->mmu_features |= MMU_FTRS_HASH_BASE; 319 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_HAS_MMU; 320 321 return 1; 322 } 323 324 static int __init feat_enable_mmu_hash_v3(struct dt_cpu_feature *f) 325 { 326 u64 lpcr; 327 328 lpcr = mfspr(SPRN_LPCR); 329 lpcr &= ~LPCR_ISL; 330 mtspr(SPRN_LPCR, lpcr); 331 332 cur_cpu_spec->mmu_features |= MMU_FTRS_HASH_BASE; 333 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_HAS_MMU; 334 335 return 1; 336 } 337 338 339 static int __init feat_enable_mmu_radix(struct dt_cpu_feature *f) 340 { 341 #ifdef CONFIG_PPC_RADIX_MMU 342 cur_cpu_spec->mmu_features |= MMU_FTR_TYPE_RADIX; 343 cur_cpu_spec->mmu_features |= MMU_FTRS_HASH_BASE; 344 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_HAS_MMU; 345 346 return 1; 347 #endif 348 return 0; 349 } 350 351 static int __init feat_enable_dscr(struct dt_cpu_feature *f) 352 { 353 u64 lpcr; 354 355 feat_enable(f); 356 357 lpcr = mfspr(SPRN_LPCR); 358 lpcr &= ~LPCR_DPFD; 359 lpcr |= (4UL << LPCR_DPFD_SH); 360 mtspr(SPRN_LPCR, lpcr); 361 362 return 1; 363 } 364 365 static void hfscr_pmu_enable(void) 366 { 367 u64 hfscr = mfspr(SPRN_HFSCR); 368 hfscr |= PPC_BIT(60); 369 mtspr(SPRN_HFSCR, hfscr); 370 } 371 372 static void init_pmu_power8(void) 373 { 374 if (hv_mode) { 375 mtspr(SPRN_MMCRC, 0); 376 mtspr(SPRN_MMCRH, 0); 377 } 378 379 mtspr(SPRN_MMCRA, 0); 380 mtspr(SPRN_MMCR0, 0); 381 mtspr(SPRN_MMCR1, 0); 382 mtspr(SPRN_MMCR2, 0); 383 mtspr(SPRN_MMCRS, 0); 384 } 385 386 static int __init feat_enable_mce_power8(struct dt_cpu_feature *f) 387 { 388 cur_cpu_spec->platform = "power8"; 389 cur_cpu_spec->machine_check_early = __machine_check_early_realmode_p8; 390 391 return 1; 392 } 393 394 static int __init feat_enable_pmu_power8(struct dt_cpu_feature *f) 395 { 396 hfscr_pmu_enable(); 397 398 init_pmu_power8(); 399 init_pmu_registers = init_pmu_power8; 400 401 cur_cpu_spec->cpu_features |= CPU_FTR_MMCRA; 402 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_PSERIES_PERFMON_COMPAT; 403 if (pvr_version_is(PVR_POWER8E)) 404 cur_cpu_spec->cpu_features |= CPU_FTR_PMAO_BUG; 405 406 cur_cpu_spec->num_pmcs = 6; 407 cur_cpu_spec->pmc_type = PPC_PMC_IBM; 408 cur_cpu_spec->oprofile_cpu_type = "ppc64/power8"; 409 410 return 1; 411 } 412 413 static void init_pmu_power9(void) 414 { 415 if (hv_mode) 416 mtspr(SPRN_MMCRC, 0); 417 418 mtspr(SPRN_MMCRA, 0); 419 mtspr(SPRN_MMCR0, 0); 420 mtspr(SPRN_MMCR1, 0); 421 mtspr(SPRN_MMCR2, 0); 422 } 423 424 static int __init feat_enable_mce_power9(struct dt_cpu_feature *f) 425 { 426 cur_cpu_spec->platform = "power9"; 427 cur_cpu_spec->machine_check_early = __machine_check_early_realmode_p9; 428 429 return 1; 430 } 431 432 static int __init feat_enable_pmu_power9(struct dt_cpu_feature *f) 433 { 434 hfscr_pmu_enable(); 435 436 init_pmu_power9(); 437 init_pmu_registers = init_pmu_power9; 438 439 cur_cpu_spec->cpu_features |= CPU_FTR_MMCRA; 440 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_PSERIES_PERFMON_COMPAT; 441 442 cur_cpu_spec->num_pmcs = 6; 443 cur_cpu_spec->pmc_type = PPC_PMC_IBM; 444 cur_cpu_spec->oprofile_cpu_type = "ppc64/power9"; 445 446 return 1; 447 } 448 449 static int __init feat_enable_tm(struct dt_cpu_feature *f) 450 { 451 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 452 feat_enable(f); 453 cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_HTM_NOSC; 454 return 1; 455 #endif 456 return 0; 457 } 458 459 static int __init feat_enable_fp(struct dt_cpu_feature *f) 460 { 461 feat_enable(f); 462 cur_cpu_spec->cpu_features &= ~CPU_FTR_FPU_UNAVAILABLE; 463 464 return 1; 465 } 466 467 static int __init feat_enable_vector(struct dt_cpu_feature *f) 468 { 469 #ifdef CONFIG_ALTIVEC 470 feat_enable(f); 471 cur_cpu_spec->cpu_features |= CPU_FTR_ALTIVEC; 472 cur_cpu_spec->cpu_features |= CPU_FTR_VMX_COPY; 473 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_HAS_ALTIVEC; 474 475 return 1; 476 #endif 477 return 0; 478 } 479 480 static int __init feat_enable_vsx(struct dt_cpu_feature *f) 481 { 482 #ifdef CONFIG_VSX 483 feat_enable(f); 484 cur_cpu_spec->cpu_features |= CPU_FTR_VSX; 485 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_HAS_VSX; 486 487 return 1; 488 #endif 489 return 0; 490 } 491 492 static int __init feat_enable_purr(struct dt_cpu_feature *f) 493 { 494 cur_cpu_spec->cpu_features |= CPU_FTR_PURR | CPU_FTR_SPURR; 495 496 return 1; 497 } 498 499 static int __init feat_enable_ebb(struct dt_cpu_feature *f) 500 { 501 /* 502 * PPC_FEATURE2_EBB is enabled in PMU init code because it has 503 * historically been related to the PMU facility. This may have 504 * to be decoupled if EBB becomes more generic. For now, follow 505 * existing convention. 506 */ 507 f->hwcap_bit_nr = -1; 508 feat_enable(f); 509 510 return 1; 511 } 512 513 static int __init feat_enable_dbell(struct dt_cpu_feature *f) 514 { 515 u64 lpcr; 516 517 /* P9 has an HFSCR for privileged state */ 518 feat_enable(f); 519 520 cur_cpu_spec->cpu_features |= CPU_FTR_DBELL; 521 522 lpcr = mfspr(SPRN_LPCR); 523 lpcr |= LPCR_PECEDH; /* hyp doorbell wakeup */ 524 mtspr(SPRN_LPCR, lpcr); 525 526 return 1; 527 } 528 529 static int __init feat_enable_hvi(struct dt_cpu_feature *f) 530 { 531 u64 lpcr; 532 533 /* 534 * POWER9 XIVE interrupts including in OPAL XICS compatibility 535 * are always delivered as hypervisor virtualization interrupts (HVI) 536 * rather than EE. 537 * 538 * However LPES0 is not set here, in the chance that an EE does get 539 * delivered to the host somehow, the EE handler would not expect it 540 * to be delivered in LPES0 mode (e.g., using SRR[01]). This could 541 * happen if there is a bug in interrupt controller code, or IC is 542 * misconfigured in systemsim. 543 */ 544 545 lpcr = mfspr(SPRN_LPCR); 546 lpcr |= LPCR_HVICE; /* enable hvi interrupts */ 547 lpcr |= LPCR_HEIC; /* disable ee interrupts when MSR_HV */ 548 lpcr |= LPCR_PECE_HVEE; /* hvi can wake from stop */ 549 mtspr(SPRN_LPCR, lpcr); 550 551 return 1; 552 } 553 554 static int __init feat_enable_large_ci(struct dt_cpu_feature *f) 555 { 556 cur_cpu_spec->mmu_features |= MMU_FTR_CI_LARGE_PAGE; 557 558 return 1; 559 } 560 561 struct dt_cpu_feature_match { 562 const char *name; 563 int (*enable)(struct dt_cpu_feature *f); 564 u64 cpu_ftr_bit_mask; 565 }; 566 567 static struct dt_cpu_feature_match __initdata 568 dt_cpu_feature_match_table[] = { 569 {"hypervisor", feat_enable_hv, 0}, 570 {"big-endian", feat_enable, 0}, 571 {"little-endian", feat_enable_le, CPU_FTR_REAL_LE}, 572 {"smt", feat_enable_smt, 0}, 573 {"interrupt-facilities", feat_enable, 0}, 574 {"timer-facilities", feat_enable, 0}, 575 {"timer-facilities-v3", feat_enable, 0}, 576 {"debug-facilities", feat_enable, 0}, 577 {"come-from-address-register", feat_enable, CPU_FTR_CFAR}, 578 {"branch-tracing", feat_enable, 0}, 579 {"floating-point", feat_enable_fp, 0}, 580 {"vector", feat_enable_vector, 0}, 581 {"vector-scalar", feat_enable_vsx, 0}, 582 {"vector-scalar-v3", feat_enable, 0}, 583 {"decimal-floating-point", feat_enable, 0}, 584 {"decimal-integer", feat_enable, 0}, 585 {"quadword-load-store", feat_enable, 0}, 586 {"vector-crypto", feat_enable, 0}, 587 {"mmu-hash", feat_enable_mmu_hash, 0}, 588 {"mmu-radix", feat_enable_mmu_radix, 0}, 589 {"mmu-hash-v3", feat_enable_mmu_hash_v3, 0}, 590 {"virtual-page-class-key-protection", feat_enable, 0}, 591 {"transactional-memory", feat_enable_tm, CPU_FTR_TM}, 592 {"transactional-memory-v3", feat_enable_tm, 0}, 593 {"idle-nap", feat_enable_idle_nap, 0}, 594 {"alignment-interrupt-dsisr", feat_enable_align_dsisr, 0}, 595 {"idle-stop", feat_enable_idle_stop, 0}, 596 {"machine-check-power8", feat_enable_mce_power8, 0}, 597 {"performance-monitor-power8", feat_enable_pmu_power8, 0}, 598 {"data-stream-control-register", feat_enable_dscr, CPU_FTR_DSCR}, 599 {"event-based-branch", feat_enable_ebb, 0}, 600 {"target-address-register", feat_enable, 0}, 601 {"branch-history-rolling-buffer", feat_enable, 0}, 602 {"control-register", feat_enable, CPU_FTR_CTRL}, 603 {"processor-control-facility", feat_enable_dbell, CPU_FTR_DBELL}, 604 {"processor-control-facility-v3", feat_enable_dbell, CPU_FTR_DBELL}, 605 {"processor-utilization-of-resources-register", feat_enable_purr, 0}, 606 {"no-execute", feat_enable, 0}, 607 {"strong-access-ordering", feat_enable, CPU_FTR_SAO}, 608 {"cache-inhibited-large-page", feat_enable_large_ci, 0}, 609 {"coprocessor-icswx", feat_enable, 0}, 610 {"hypervisor-virtualization-interrupt", feat_enable_hvi, 0}, 611 {"program-priority-register", feat_enable, CPU_FTR_HAS_PPR}, 612 {"wait", feat_enable, 0}, 613 {"atomic-memory-operations", feat_enable, 0}, 614 {"branch-v3", feat_enable, 0}, 615 {"copy-paste", feat_enable, 0}, 616 {"decimal-floating-point-v3", feat_enable, 0}, 617 {"decimal-integer-v3", feat_enable, 0}, 618 {"fixed-point-v3", feat_enable, 0}, 619 {"floating-point-v3", feat_enable, 0}, 620 {"group-start-register", feat_enable, 0}, 621 {"pc-relative-addressing", feat_enable, 0}, 622 {"machine-check-power9", feat_enable_mce_power9, 0}, 623 {"performance-monitor-power9", feat_enable_pmu_power9, 0}, 624 {"event-based-branch-v3", feat_enable, 0}, 625 {"random-number-generator", feat_enable, 0}, 626 {"system-call-vectored", feat_disable, 0}, 627 {"trace-interrupt-v3", feat_enable, 0}, 628 {"vector-v3", feat_enable, 0}, 629 {"vector-binary128", feat_enable, 0}, 630 {"vector-binary16", feat_enable, 0}, 631 {"wait-v3", feat_enable, 0}, 632 }; 633 634 static bool __initdata using_dt_cpu_ftrs; 635 static bool __initdata enable_unknown = true; 636 637 static int __init dt_cpu_ftrs_parse(char *str) 638 { 639 if (!str) 640 return 0; 641 642 if (!strcmp(str, "off")) 643 using_dt_cpu_ftrs = false; 644 else if (!strcmp(str, "known")) 645 enable_unknown = false; 646 else 647 return 1; 648 649 return 0; 650 } 651 early_param("dt_cpu_ftrs", dt_cpu_ftrs_parse); 652 653 static void __init cpufeatures_setup_start(u32 isa) 654 { 655 pr_info("setup for ISA %d\n", isa); 656 657 if (isa >= 3000) { 658 cur_cpu_spec->cpu_features |= CPU_FTR_ARCH_300; 659 cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_ARCH_3_00; 660 } 661 } 662 663 static bool __init cpufeatures_process_feature(struct dt_cpu_feature *f) 664 { 665 const struct dt_cpu_feature_match *m; 666 bool known = false; 667 int i; 668 669 for (i = 0; i < ARRAY_SIZE(dt_cpu_feature_match_table); i++) { 670 m = &dt_cpu_feature_match_table[i]; 671 if (!strcmp(f->name, m->name)) { 672 known = true; 673 if (m->enable(f)) 674 break; 675 676 pr_info("not enabling: %s (disabled or unsupported by kernel)\n", 677 f->name); 678 return false; 679 } 680 } 681 682 if (!known && enable_unknown) { 683 if (!feat_try_enable_unknown(f)) { 684 pr_info("not enabling: %s (unknown and unsupported by kernel)\n", 685 f->name); 686 return false; 687 } 688 } 689 690 if (m->cpu_ftr_bit_mask) 691 cur_cpu_spec->cpu_features |= m->cpu_ftr_bit_mask; 692 693 if (known) 694 pr_debug("enabling: %s\n", f->name); 695 else 696 pr_debug("enabling: %s (unknown)\n", f->name); 697 698 return true; 699 } 700 701 static __init void cpufeatures_cpu_quirks(void) 702 { 703 int version = mfspr(SPRN_PVR); 704 705 /* 706 * Not all quirks can be derived from the cpufeatures device tree. 707 */ 708 if ((version & 0xffffff00) == 0x004e0100) 709 cur_cpu_spec->cpu_features |= CPU_FTR_POWER9_DD1; 710 else if ((version & 0xffffefff) == 0x004e0201) 711 cur_cpu_spec->cpu_features |= CPU_FTR_POWER9_DD2_1; 712 713 if ((version & 0xffff0000) == 0x004e0000) 714 cur_cpu_spec->cpu_features |= CPU_FTR_P9_TLBIE_BUG; 715 } 716 717 static void __init cpufeatures_setup_finished(void) 718 { 719 cpufeatures_cpu_quirks(); 720 721 if (hv_mode && !(cur_cpu_spec->cpu_features & CPU_FTR_HVMODE)) { 722 pr_err("hypervisor not present in device tree but HV mode is enabled in the CPU. Enabling.\n"); 723 cur_cpu_spec->cpu_features |= CPU_FTR_HVMODE; 724 } 725 726 /* Make sure powerpc_base_platform is non-NULL */ 727 powerpc_base_platform = cur_cpu_spec->platform; 728 729 system_registers.lpcr = mfspr(SPRN_LPCR); 730 system_registers.hfscr = mfspr(SPRN_HFSCR); 731 system_registers.fscr = mfspr(SPRN_FSCR); 732 733 pr_info("final cpu/mmu features = 0x%016lx 0x%08x\n", 734 cur_cpu_spec->cpu_features, cur_cpu_spec->mmu_features); 735 } 736 737 static int __init disabled_on_cmdline(void) 738 { 739 unsigned long root, chosen; 740 const char *p; 741 742 root = of_get_flat_dt_root(); 743 chosen = of_get_flat_dt_subnode_by_name(root, "chosen"); 744 if (chosen == -FDT_ERR_NOTFOUND) 745 return false; 746 747 p = of_get_flat_dt_prop(chosen, "bootargs", NULL); 748 if (!p) 749 return false; 750 751 if (strstr(p, "dt_cpu_ftrs=off")) 752 return true; 753 754 return false; 755 } 756 757 static int __init fdt_find_cpu_features(unsigned long node, const char *uname, 758 int depth, void *data) 759 { 760 if (of_flat_dt_is_compatible(node, "ibm,powerpc-cpu-features") 761 && of_get_flat_dt_prop(node, "isa", NULL)) 762 return 1; 763 764 return 0; 765 } 766 767 bool __init dt_cpu_ftrs_in_use(void) 768 { 769 return using_dt_cpu_ftrs; 770 } 771 772 bool __init dt_cpu_ftrs_init(void *fdt) 773 { 774 using_dt_cpu_ftrs = false; 775 776 /* Setup and verify the FDT, if it fails we just bail */ 777 if (!early_init_dt_verify(fdt)) 778 return false; 779 780 if (!of_scan_flat_dt(fdt_find_cpu_features, NULL)) 781 return false; 782 783 if (disabled_on_cmdline()) 784 return false; 785 786 cpufeatures_setup_cpu(); 787 788 using_dt_cpu_ftrs = true; 789 return true; 790 } 791 792 static int nr_dt_cpu_features; 793 static struct dt_cpu_feature *dt_cpu_features; 794 795 static int __init process_cpufeatures_node(unsigned long node, 796 const char *uname, int i) 797 { 798 const __be32 *prop; 799 struct dt_cpu_feature *f; 800 int len; 801 802 f = &dt_cpu_features[i]; 803 memset(f, 0, sizeof(struct dt_cpu_feature)); 804 805 f->node = node; 806 807 f->name = uname; 808 809 prop = of_get_flat_dt_prop(node, "isa", &len); 810 if (!prop) { 811 pr_warn("%s: missing isa property\n", uname); 812 return 0; 813 } 814 f->isa = be32_to_cpup(prop); 815 816 prop = of_get_flat_dt_prop(node, "usable-privilege", &len); 817 if (!prop) { 818 pr_warn("%s: missing usable-privilege property", uname); 819 return 0; 820 } 821 f->usable_privilege = be32_to_cpup(prop); 822 823 prop = of_get_flat_dt_prop(node, "hv-support", &len); 824 if (prop) 825 f->hv_support = be32_to_cpup(prop); 826 else 827 f->hv_support = HV_SUPPORT_NONE; 828 829 prop = of_get_flat_dt_prop(node, "os-support", &len); 830 if (prop) 831 f->os_support = be32_to_cpup(prop); 832 else 833 f->os_support = OS_SUPPORT_NONE; 834 835 prop = of_get_flat_dt_prop(node, "hfscr-bit-nr", &len); 836 if (prop) 837 f->hfscr_bit_nr = be32_to_cpup(prop); 838 else 839 f->hfscr_bit_nr = -1; 840 prop = of_get_flat_dt_prop(node, "fscr-bit-nr", &len); 841 if (prop) 842 f->fscr_bit_nr = be32_to_cpup(prop); 843 else 844 f->fscr_bit_nr = -1; 845 prop = of_get_flat_dt_prop(node, "hwcap-bit-nr", &len); 846 if (prop) 847 f->hwcap_bit_nr = be32_to_cpup(prop); 848 else 849 f->hwcap_bit_nr = -1; 850 851 if (f->usable_privilege & USABLE_HV) { 852 if (!(mfmsr() & MSR_HV)) { 853 pr_warn("%s: HV feature passed to guest\n", uname); 854 return 0; 855 } 856 857 if (f->hv_support == HV_SUPPORT_NONE && f->hfscr_bit_nr != -1) { 858 pr_warn("%s: unwanted hfscr_bit_nr\n", uname); 859 return 0; 860 } 861 862 if (f->hv_support == HV_SUPPORT_HFSCR) { 863 if (f->hfscr_bit_nr == -1) { 864 pr_warn("%s: missing hfscr_bit_nr\n", uname); 865 return 0; 866 } 867 } 868 } else { 869 if (f->hv_support != HV_SUPPORT_NONE || f->hfscr_bit_nr != -1) { 870 pr_warn("%s: unwanted hv_support/hfscr_bit_nr\n", uname); 871 return 0; 872 } 873 } 874 875 if (f->usable_privilege & USABLE_OS) { 876 if (f->os_support == OS_SUPPORT_NONE && f->fscr_bit_nr != -1) { 877 pr_warn("%s: unwanted fscr_bit_nr\n", uname); 878 return 0; 879 } 880 881 if (f->os_support == OS_SUPPORT_FSCR) { 882 if (f->fscr_bit_nr == -1) { 883 pr_warn("%s: missing fscr_bit_nr\n", uname); 884 return 0; 885 } 886 } 887 } else { 888 if (f->os_support != OS_SUPPORT_NONE || f->fscr_bit_nr != -1) { 889 pr_warn("%s: unwanted os_support/fscr_bit_nr\n", uname); 890 return 0; 891 } 892 } 893 894 if (!(f->usable_privilege & USABLE_PR)) { 895 if (f->hwcap_bit_nr != -1) { 896 pr_warn("%s: unwanted hwcap_bit_nr\n", uname); 897 return 0; 898 } 899 } 900 901 /* Do all the independent features in the first pass */ 902 if (!of_get_flat_dt_prop(node, "dependencies", &len)) { 903 if (cpufeatures_process_feature(f)) 904 f->enabled = 1; 905 else 906 f->disabled = 1; 907 } 908 909 return 0; 910 } 911 912 static void __init cpufeatures_deps_enable(struct dt_cpu_feature *f) 913 { 914 const __be32 *prop; 915 int len; 916 int nr_deps; 917 int i; 918 919 if (f->enabled || f->disabled) 920 return; 921 922 prop = of_get_flat_dt_prop(f->node, "dependencies", &len); 923 if (!prop) { 924 pr_warn("%s: missing dependencies property", f->name); 925 return; 926 } 927 928 nr_deps = len / sizeof(int); 929 930 for (i = 0; i < nr_deps; i++) { 931 unsigned long phandle = be32_to_cpu(prop[i]); 932 int j; 933 934 for (j = 0; j < nr_dt_cpu_features; j++) { 935 struct dt_cpu_feature *d = &dt_cpu_features[j]; 936 937 if (of_get_flat_dt_phandle(d->node) == phandle) { 938 cpufeatures_deps_enable(d); 939 if (d->disabled) { 940 f->disabled = 1; 941 return; 942 } 943 } 944 } 945 } 946 947 if (cpufeatures_process_feature(f)) 948 f->enabled = 1; 949 else 950 f->disabled = 1; 951 } 952 953 static int __init scan_cpufeatures_subnodes(unsigned long node, 954 const char *uname, 955 void *data) 956 { 957 int *count = data; 958 959 process_cpufeatures_node(node, uname, *count); 960 961 (*count)++; 962 963 return 0; 964 } 965 966 static int __init count_cpufeatures_subnodes(unsigned long node, 967 const char *uname, 968 void *data) 969 { 970 int *count = data; 971 972 (*count)++; 973 974 return 0; 975 } 976 977 static int __init dt_cpu_ftrs_scan_callback(unsigned long node, const char 978 *uname, int depth, void *data) 979 { 980 const __be32 *prop; 981 int count, i; 982 u32 isa; 983 984 /* We are scanning "ibm,powerpc-cpu-features" nodes only */ 985 if (!of_flat_dt_is_compatible(node, "ibm,powerpc-cpu-features")) 986 return 0; 987 988 prop = of_get_flat_dt_prop(node, "isa", NULL); 989 if (!prop) 990 /* We checked before, "can't happen" */ 991 return 0; 992 993 isa = be32_to_cpup(prop); 994 995 /* Count and allocate space for cpu features */ 996 of_scan_flat_dt_subnodes(node, count_cpufeatures_subnodes, 997 &nr_dt_cpu_features); 998 dt_cpu_features = __va( 999 memblock_alloc(sizeof(struct dt_cpu_feature)* 1000 nr_dt_cpu_features, PAGE_SIZE)); 1001 1002 cpufeatures_setup_start(isa); 1003 1004 /* Scan nodes into dt_cpu_features and enable those without deps */ 1005 count = 0; 1006 of_scan_flat_dt_subnodes(node, scan_cpufeatures_subnodes, &count); 1007 1008 /* Recursive enable remaining features with dependencies */ 1009 for (i = 0; i < nr_dt_cpu_features; i++) { 1010 struct dt_cpu_feature *f = &dt_cpu_features[i]; 1011 1012 cpufeatures_deps_enable(f); 1013 } 1014 1015 prop = of_get_flat_dt_prop(node, "display-name", NULL); 1016 if (prop && strlen((char *)prop) != 0) { 1017 strlcpy(dt_cpu_name, (char *)prop, sizeof(dt_cpu_name)); 1018 cur_cpu_spec->cpu_name = dt_cpu_name; 1019 } 1020 1021 cpufeatures_setup_finished(); 1022 1023 memblock_free(__pa(dt_cpu_features), 1024 sizeof(struct dt_cpu_feature)*nr_dt_cpu_features); 1025 1026 return 0; 1027 } 1028 1029 void __init dt_cpu_ftrs_scan(void) 1030 { 1031 if (!using_dt_cpu_ftrs) 1032 return; 1033 1034 of_scan_flat_dt(dt_cpu_ftrs_scan_callback, NULL); 1035 } 1036