1 /* 2 * Copyright (c) 2017 Intel Corporation. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License version 6 * 2 as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #ifndef __IPU3_CIO2_H 15 #define __IPU3_CIO2_H 16 17 #define CIO2_NAME "ipu3-cio2" 18 #define CIO2_DEVICE_NAME "Intel IPU3 CIO2" 19 #define CIO2_ENTITY_NAME "ipu3-csi2" 20 #define CIO2_PCI_ID 0x9d32 21 #define CIO2_PCI_BAR 0 22 #define CIO2_DMA_MASK DMA_BIT_MASK(39) 23 #define CIO2_IMAGE_MAX_WIDTH 4224 24 #define CIO2_IMAGE_MAX_LENGTH 3136 25 26 #define CIO2_IMAGE_MAX_WIDTH 4224 27 #define CIO2_IMAGE_MAX_LENGTH 3136 28 29 /* 32MB = 8xFBPT_entry */ 30 #define CIO2_MAX_LOPS 8 31 #define CIO2_MAX_BUFFERS (PAGE_SIZE / 16 / CIO2_MAX_LOPS) 32 33 #define CIO2_PAD_SINK 0 34 #define CIO2_PAD_SOURCE 1 35 #define CIO2_PADS 2 36 37 #define CIO2_NUM_DMA_CHAN 20 38 #define CIO2_NUM_PORTS 4 /* DPHYs */ 39 40 /* 1 for each sensor */ 41 #define CIO2_QUEUES CIO2_NUM_PORTS 42 43 /* Register and bit field definitions */ 44 #define CIO2_REG_PIPE_BASE(n) ((n) * 0x0400) /* n = 0..3 */ 45 #define CIO2_REG_CSIRX_BASE 0x000 46 #define CIO2_REG_MIPIBE_BASE 0x100 47 #define CIO2_REG_PIXELGEN_BAS 0x200 48 #define CIO2_REG_IRQCTRL_BASE 0x300 49 #define CIO2_REG_GPREG_BASE 0x1000 50 51 /* base register: CIO2_REG_PIPE_BASE(pipe) * CIO2_REG_CSIRX_BASE */ 52 #define CIO2_REG_CSIRX_ENABLE (CIO2_REG_CSIRX_BASE + 0x0) 53 #define CIO2_REG_CSIRX_NOF_ENABLED_LANES (CIO2_REG_CSIRX_BASE + 0x4) 54 #define CIO2_REG_CSIRX_SP_IF_CONFIG (CIO2_REG_CSIRX_BASE + 0x10) 55 #define CIO2_REG_CSIRX_LP_IF_CONFIG (CIO2_REG_CSIRX_BASE + 0x14) 56 #define CIO2_CSIRX_IF_CONFIG_FILTEROUT 0x00 57 #define CIO2_CSIRX_IF_CONFIG_FILTEROUT_VC_INACTIVE 0x01 58 #define CIO2_CSIRX_IF_CONFIG_PASS 0x02 59 #define CIO2_CSIRX_IF_CONFIG_FLAG_ERROR BIT(2) 60 #define CIO2_REG_CSIRX_STATUS (CIO2_REG_CSIRX_BASE + 0x18) 61 #define CIO2_REG_CSIRX_STATUS_DLANE_HS (CIO2_REG_CSIRX_BASE + 0x1c) 62 #define CIO2_CSIRX_STATUS_DLANE_HS_MASK 0xff 63 #define CIO2_REG_CSIRX_STATUS_DLANE_LP (CIO2_REG_CSIRX_BASE + 0x20) 64 #define CIO2_CSIRX_STATUS_DLANE_LP_MASK 0xffffff 65 /* Termination enable and settle in 0.0625ns units, lane=0..3 or -1 for clock */ 66 #define CIO2_REG_CSIRX_DLY_CNT_TERMEN(lane) \ 67 (CIO2_REG_CSIRX_BASE + 0x2c + 8 * (lane)) 68 #define CIO2_REG_CSIRX_DLY_CNT_SETTLE(lane) \ 69 (CIO2_REG_CSIRX_BASE + 0x30 + 8 * (lane)) 70 /* base register: CIO2_REG_PIPE_BASE(pipe) * CIO2_REG_MIPIBE_BASE */ 71 #define CIO2_REG_MIPIBE_ENABLE (CIO2_REG_MIPIBE_BASE + 0x0) 72 #define CIO2_REG_MIPIBE_STATUS (CIO2_REG_MIPIBE_BASE + 0x4) 73 #define CIO2_REG_MIPIBE_COMP_FORMAT(vc) \ 74 (CIO2_REG_MIPIBE_BASE + 0x8 + 0x4 * (vc)) 75 #define CIO2_REG_MIPIBE_FORCE_RAW8 (CIO2_REG_MIPIBE_BASE + 0x20) 76 #define CIO2_REG_MIPIBE_FORCE_RAW8_ENABLE BIT(0) 77 #define CIO2_REG_MIPIBE_FORCE_RAW8_USE_TYPEID BIT(1) 78 #define CIO2_REG_MIPIBE_FORCE_RAW8_TYPEID_SHIFT 2 79 80 #define CIO2_REG_MIPIBE_IRQ_STATUS (CIO2_REG_MIPIBE_BASE + 0x24) 81 #define CIO2_REG_MIPIBE_IRQ_CLEAR (CIO2_REG_MIPIBE_BASE + 0x28) 82 #define CIO2_REG_MIPIBE_GLOBAL_LUT_DISREGARD (CIO2_REG_MIPIBE_BASE + 0x68) 83 #define CIO2_MIPIBE_GLOBAL_LUT_DISREGARD 1 84 #define CIO2_REG_MIPIBE_PKT_STALL_STATUS (CIO2_REG_MIPIBE_BASE + 0x6c) 85 #define CIO2_REG_MIPIBE_PARSE_GSP_THROUGH_LP_LUT_REG_IDX \ 86 (CIO2_REG_MIPIBE_BASE + 0x70) 87 #define CIO2_REG_MIPIBE_SP_LUT_ENTRY(vc) \ 88 (CIO2_REG_MIPIBE_BASE + 0x74 + 4 * (vc)) 89 #define CIO2_REG_MIPIBE_LP_LUT_ENTRY(m) /* m = 0..15 */ \ 90 (CIO2_REG_MIPIBE_BASE + 0x84 + 4 * (m)) 91 #define CIO2_MIPIBE_LP_LUT_ENTRY_DISREGARD 1 92 #define CIO2_MIPIBE_LP_LUT_ENTRY_SID_SHIFT 1 93 #define CIO2_MIPIBE_LP_LUT_ENTRY_VC_SHIFT 5 94 #define CIO2_MIPIBE_LP_LUT_ENTRY_FORMAT_TYPE_SHIFT 7 95 96 /* base register: CIO2_REG_PIPE_BASE(pipe) * CIO2_REG_IRQCTRL_BASE */ 97 /* IRQ registers are 18-bit wide, see cio2_irq_error for bit definitions */ 98 #define CIO2_REG_IRQCTRL_EDGE (CIO2_REG_IRQCTRL_BASE + 0x00) 99 #define CIO2_REG_IRQCTRL_MASK (CIO2_REG_IRQCTRL_BASE + 0x04) 100 #define CIO2_REG_IRQCTRL_STATUS (CIO2_REG_IRQCTRL_BASE + 0x08) 101 #define CIO2_REG_IRQCTRL_CLEAR (CIO2_REG_IRQCTRL_BASE + 0x0c) 102 #define CIO2_REG_IRQCTRL_ENABLE (CIO2_REG_IRQCTRL_BASE + 0x10) 103 #define CIO2_REG_IRQCTRL_LEVEL_NOT_PULSE (CIO2_REG_IRQCTRL_BASE + 0x14) 104 105 #define CIO2_REG_GPREG_SRST (CIO2_REG_GPREG_BASE + 0x0) 106 #define CIO2_GPREG_SRST_ALL 0xffff /* Reset all */ 107 #define CIO2_REG_FB_HPLL_FREQ (CIO2_REG_GPREG_BASE + 0x08) 108 #define CIO2_REG_ISCLK_RATIO (CIO2_REG_GPREG_BASE + 0xc) 109 110 #define CIO2_REG_CGC 0x1400 111 #define CIO2_CGC_CSI2_TGE BIT(0) 112 #define CIO2_CGC_PRIM_TGE BIT(1) 113 #define CIO2_CGC_SIDE_TGE BIT(2) 114 #define CIO2_CGC_XOSC_TGE BIT(3) 115 #define CIO2_CGC_MPLL_SHUTDOWN_EN BIT(4) 116 #define CIO2_CGC_D3I3_TGE BIT(5) 117 #define CIO2_CGC_CSI2_INTERFRAME_TGE BIT(6) 118 #define CIO2_CGC_CSI2_PORT_DCGE BIT(8) 119 #define CIO2_CGC_CSI2_DCGE BIT(9) 120 #define CIO2_CGC_SIDE_DCGE BIT(10) 121 #define CIO2_CGC_PRIM_DCGE BIT(11) 122 #define CIO2_CGC_ROSC_DCGE BIT(12) 123 #define CIO2_CGC_XOSC_DCGE BIT(13) 124 #define CIO2_CGC_FLIS_DCGE BIT(14) 125 #define CIO2_CGC_CLKGATE_HOLDOFF_SHIFT 20 126 #define CIO2_CGC_CSI_CLKGATE_HOLDOFF_SHIFT 24 127 #define CIO2_REG_D0I3C 0x1408 128 #define CIO2_D0I3C_I3 BIT(2) /* Set D0I3 */ 129 #define CIO2_D0I3C_RR BIT(3) /* Restore? */ 130 #define CIO2_REG_SWRESET 0x140c 131 #define CIO2_SWRESET_SWRESET 1 132 #define CIO2_REG_SENSOR_ACTIVE 0x1410 133 #define CIO2_REG_INT_STS 0x1414 134 #define CIO2_REG_INT_STS_EXT_OE 0x1418 135 #define CIO2_INT_EXT_OE_DMAOE_SHIFT 0 136 #define CIO2_INT_EXT_OE_DMAOE_MASK 0x7ffff 137 #define CIO2_INT_EXT_OE_OES_SHIFT 24 138 #define CIO2_INT_EXT_OE_OES_MASK (0xf << CIO2_INT_EXT_OE_OES_SHIFT) 139 #define CIO2_REG_INT_EN 0x1420 140 #define CIO2_REG_INT_EN_IRQ (1 << 24) 141 #define CIO2_REG_INT_EN_IOS(dma) (1 << (((dma) >> 1) + 12)) 142 /* 143 * Interrupt on completion bit, Eg. DMA 0-3 maps to bit 0-3, 144 * DMA4 & DMA5 map to bit 4 ... DMA18 & DMA19 map to bit 11 Et cetera 145 */ 146 #define CIO2_INT_IOC(dma) (1 << ((dma) < 4 ? (dma) : ((dma) >> 1) + 2)) 147 #define CIO2_INT_IOC_SHIFT 0 148 #define CIO2_INT_IOC_MASK (0x7ff << CIO2_INT_IOC_SHIFT) 149 #define CIO2_INT_IOS_IOLN(dma) (1 << (((dma) >> 1) + 12)) 150 #define CIO2_INT_IOS_IOLN_SHIFT 12 151 #define CIO2_INT_IOS_IOLN_MASK (0x3ff << CIO2_INT_IOS_IOLN_SHIFT) 152 #define CIO2_INT_IOIE BIT(22) 153 #define CIO2_INT_IOOE BIT(23) 154 #define CIO2_INT_IOIRQ BIT(24) 155 #define CIO2_REG_INT_EN_EXT_OE 0x1424 156 #define CIO2_REG_DMA_DBG 0x1448 157 #define CIO2_REG_DMA_DBG_DMA_INDEX_SHIFT 0 158 #define CIO2_REG_PBM_ARB_CTRL 0x1460 159 #define CIO2_PBM_ARB_CTRL_LANES_DIV 0 /* 4-4-2-2 lanes */ 160 #define CIO2_PBM_ARB_CTRL_LANES_DIV_SHIFT 0 161 #define CIO2_PBM_ARB_CTRL_LE_EN BIT(7) 162 #define CIO2_PBM_ARB_CTRL_PLL_POST_SHTDN 2 163 #define CIO2_PBM_ARB_CTRL_PLL_POST_SHTDN_SHIFT 8 164 #define CIO2_PBM_ARB_CTRL_PLL_AHD_WK_UP 480 165 #define CIO2_PBM_ARB_CTRL_PLL_AHD_WK_UP_SHIFT 16 166 #define CIO2_REG_PBM_WMCTRL1 0x1464 167 #define CIO2_PBM_WMCTRL1_MIN_2CK_SHIFT 0 168 #define CIO2_PBM_WMCTRL1_MID1_2CK_SHIFT 8 169 #define CIO2_PBM_WMCTRL1_MID2_2CK_SHIFT 16 170 #define CIO2_PBM_WMCTRL1_TS_COUNT_DISABLE BIT(31) 171 #define CIO2_PBM_WMCTRL1_MIN_2CK (4 << CIO2_PBM_WMCTRL1_MIN_2CK_SHIFT) 172 #define CIO2_PBM_WMCTRL1_MID1_2CK (16 << CIO2_PBM_WMCTRL1_MID1_2CK_SHIFT) 173 #define CIO2_PBM_WMCTRL1_MID2_2CK (21 << CIO2_PBM_WMCTRL1_MID2_2CK_SHIFT) 174 #define CIO2_REG_PBM_WMCTRL2 0x1468 175 #define CIO2_PBM_WMCTRL2_HWM_2CK 40 176 #define CIO2_PBM_WMCTRL2_HWM_2CK_SHIFT 0 177 #define CIO2_PBM_WMCTRL2_LWM_2CK 22 178 #define CIO2_PBM_WMCTRL2_LWM_2CK_SHIFT 8 179 #define CIO2_PBM_WMCTRL2_OBFFWM_2CK 2 180 #define CIO2_PBM_WMCTRL2_OBFFWM_2CK_SHIFT 16 181 #define CIO2_PBM_WMCTRL2_TRANSDYN 1 182 #define CIO2_PBM_WMCTRL2_TRANSDYN_SHIFT 24 183 #define CIO2_PBM_WMCTRL2_DYNWMEN BIT(28) 184 #define CIO2_PBM_WMCTRL2_OBFF_MEM_EN BIT(29) 185 #define CIO2_PBM_WMCTRL2_OBFF_CPU_EN BIT(30) 186 #define CIO2_PBM_WMCTRL2_DRAINNOW BIT(31) 187 #define CIO2_REG_PBM_TS_COUNT 0x146c 188 #define CIO2_REG_PBM_FOPN_ABORT 0x1474 189 /* below n = 0..3 */ 190 #define CIO2_PBM_FOPN_ABORT(n) (0x1 << 8 * (n)) 191 #define CIO2_PBM_FOPN_FORCE_ABORT(n) (0x2 << 8 * (n)) 192 #define CIO2_PBM_FOPN_FRAMEOPEN(n) (0x8 << 8 * (n)) 193 #define CIO2_REG_LTRCTRL 0x1480 194 #define CIO2_LTRCTRL_LTRDYNEN BIT(16) 195 #define CIO2_LTRCTRL_LTRSTABLETIME_SHIFT 8 196 #define CIO2_LTRCTRL_LTRSTABLETIME_MASK 0xff 197 #define CIO2_LTRCTRL_LTRSEL1S3 BIT(7) 198 #define CIO2_LTRCTRL_LTRSEL1S2 BIT(6) 199 #define CIO2_LTRCTRL_LTRSEL1S1 BIT(5) 200 #define CIO2_LTRCTRL_LTRSEL1S0 BIT(4) 201 #define CIO2_LTRCTRL_LTRSEL2S3 BIT(3) 202 #define CIO2_LTRCTRL_LTRSEL2S2 BIT(2) 203 #define CIO2_LTRCTRL_LTRSEL2S1 BIT(1) 204 #define CIO2_LTRCTRL_LTRSEL2S0 BIT(0) 205 #define CIO2_REG_LTRVAL23 0x1484 206 #define CIO2_REG_LTRVAL01 0x1488 207 #define CIO2_LTRVAL02_VAL_SHIFT 0 208 #define CIO2_LTRVAL02_SCALE_SHIFT 10 209 #define CIO2_LTRVAL13_VAL_SHIFT 16 210 #define CIO2_LTRVAL13_SCALE_SHIFT 26 211 212 #define CIO2_LTRVAL0_VAL 175 213 /* Value times 1024 ns */ 214 #define CIO2_LTRVAL0_SCALE 2 215 #define CIO2_LTRVAL1_VAL 90 216 #define CIO2_LTRVAL1_SCALE 2 217 #define CIO2_LTRVAL2_VAL 90 218 #define CIO2_LTRVAL2_SCALE 2 219 #define CIO2_LTRVAL3_VAL 90 220 #define CIO2_LTRVAL3_SCALE 2 221 222 #define CIO2_REG_CDMABA(n) (0x1500 + 0x10 * (n)) /* n = 0..19 */ 223 #define CIO2_REG_CDMARI(n) (0x1504 + 0x10 * (n)) 224 #define CIO2_CDMARI_FBPT_RP_SHIFT 0 225 #define CIO2_CDMARI_FBPT_RP_MASK 0xff 226 #define CIO2_REG_CDMAC0(n) (0x1508 + 0x10 * (n)) 227 #define CIO2_CDMAC0_FBPT_LEN_SHIFT 0 228 #define CIO2_CDMAC0_FBPT_WIDTH_SHIFT 8 229 #define CIO2_CDMAC0_FBPT_NS BIT(25) 230 #define CIO2_CDMAC0_DMA_INTR_ON_FS BIT(26) 231 #define CIO2_CDMAC0_DMA_INTR_ON_FE BIT(27) 232 #define CIO2_CDMAC0_FBPT_UPDATE_FIFO_FULL BIT(28) 233 #define CIO2_CDMAC0_FBPT_FIFO_FULL_FIX_DIS BIT(29) 234 #define CIO2_CDMAC0_DMA_EN BIT(30) 235 #define CIO2_CDMAC0_DMA_HALTED BIT(31) 236 #define CIO2_REG_CDMAC1(n) (0x150c + 0x10 * (n)) 237 #define CIO2_CDMAC1_LINENUMINT_SHIFT 0 238 #define CIO2_CDMAC1_LINENUMUPDATE_SHIFT 16 239 /* n = 0..3 */ 240 #define CIO2_REG_PXM_PXF_FMT_CFG0(n) (0x1700 + 0x30 * (n)) 241 #define CIO2_PXM_PXF_FMT_CFG_SID0_SHIFT 0 242 #define CIO2_PXM_PXF_FMT_CFG_SID1_SHIFT 16 243 #define CIO2_PXM_PXF_FMT_CFG_PCK_64B (0 << 0) 244 #define CIO2_PXM_PXF_FMT_CFG_PCK_32B (1 << 0) 245 #define CIO2_PXM_PXF_FMT_CFG_BPP_08 (0 << 2) 246 #define CIO2_PXM_PXF_FMT_CFG_BPP_10 (1 << 2) 247 #define CIO2_PXM_PXF_FMT_CFG_BPP_12 (2 << 2) 248 #define CIO2_PXM_PXF_FMT_CFG_BPP_14 (3 << 2) 249 #define CIO2_PXM_PXF_FMT_CFG_SPEC_4PPC (0 << 4) 250 #define CIO2_PXM_PXF_FMT_CFG_SPEC_3PPC_RGBA (1 << 4) 251 #define CIO2_PXM_PXF_FMT_CFG_SPEC_3PPC_ARGB (2 << 4) 252 #define CIO2_PXM_PXF_FMT_CFG_SPEC_PLANAR2 (3 << 4) 253 #define CIO2_PXM_PXF_FMT_CFG_SPEC_PLANAR3 (4 << 4) 254 #define CIO2_PXM_PXF_FMT_CFG_SPEC_NV16 (5 << 4) 255 #define CIO2_PXM_PXF_FMT_CFG_PSWAP4_1ST_AB (1 << 7) 256 #define CIO2_PXM_PXF_FMT_CFG_PSWAP4_1ST_CD (1 << 8) 257 #define CIO2_PXM_PXF_FMT_CFG_PSWAP4_2ND_AC (1 << 9) 258 #define CIO2_PXM_PXF_FMT_CFG_PSWAP4_2ND_BD (1 << 10) 259 #define CIO2_REG_INT_STS_EXT_IE 0x17e4 260 #define CIO2_REG_INT_EN_EXT_IE 0x17e8 261 #define CIO2_INT_EXT_IE_ECC_RE(n) (0x01 << (8 * (n))) 262 #define CIO2_INT_EXT_IE_DPHY_NR(n) (0x02 << (8 * (n))) 263 #define CIO2_INT_EXT_IE_ECC_NR(n) (0x04 << (8 * (n))) 264 #define CIO2_INT_EXT_IE_CRCERR(n) (0x08 << (8 * (n))) 265 #define CIO2_INT_EXT_IE_INTERFRAMEDATA(n) (0x10 << (8 * (n))) 266 #define CIO2_INT_EXT_IE_PKT2SHORT(n) (0x20 << (8 * (n))) 267 #define CIO2_INT_EXT_IE_PKT2LONG(n) (0x40 << (8 * (n))) 268 #define CIO2_INT_EXT_IE_IRQ(n) (0x80 << (8 * (n))) 269 #define CIO2_REG_PXM_FRF_CFG(n) (0x1720 + 0x30 * (n)) 270 #define CIO2_PXM_FRF_CFG_FNSEL BIT(0) 271 #define CIO2_PXM_FRF_CFG_FN_RST BIT(1) 272 #define CIO2_PXM_FRF_CFG_ABORT BIT(2) 273 #define CIO2_PXM_FRF_CFG_CRC_TH_SHIFT 3 274 #define CIO2_PXM_FRF_CFG_MSK_ECC_DPHY_NR BIT(8) 275 #define CIO2_PXM_FRF_CFG_MSK_ECC_RE BIT(9) 276 #define CIO2_PXM_FRF_CFG_MSK_ECC_DPHY_NE BIT(10) 277 #define CIO2_PXM_FRF_CFG_EVEN_ODD_MODE_SHIFT 11 278 #define CIO2_PXM_FRF_CFG_MASK_CRC_THRES BIT(13) 279 #define CIO2_PXM_FRF_CFG_MASK_CSI_ACCEPT BIT(14) 280 #define CIO2_PXM_FRF_CFG_CIOHC_FS_MODE BIT(15) 281 #define CIO2_PXM_FRF_CFG_CIOHC_FRST_FRM_SHIFT 16 282 #define CIO2_REG_PXM_SID2BID0(n) (0x1724 + 0x30 * (n)) 283 #define CIO2_FB_HPLL_FREQ 0x2 284 #define CIO2_ISCLK_RATIO 0xc 285 286 #define CIO2_IRQCTRL_MASK 0x3ffff 287 288 #define CIO2_INT_EN_EXT_OE_MASK 0x8f0fffff 289 290 #define CIO2_CGC_CLKGATE_HOLDOFF 3 291 #define CIO2_CGC_CSI_CLKGATE_HOLDOFF 5 292 293 #define CIO2_PXM_FRF_CFG_CRC_TH 16 294 295 #define CIO2_INT_EN_EXT_IE_MASK 0xffffffff 296 297 #define CIO2_DMA_CHAN 0 298 299 #define CIO2_CSIRX_DLY_CNT_CLANE_IDX -1 300 301 #define CIO2_CSIRX_DLY_CNT_TERMEN_CLANE_A 0 302 #define CIO2_CSIRX_DLY_CNT_TERMEN_CLANE_B 0 303 #define CIO2_CSIRX_DLY_CNT_SETTLE_CLANE_A 95 304 #define CIO2_CSIRX_DLY_CNT_SETTLE_CLANE_B -8 305 306 #define CIO2_CSIRX_DLY_CNT_TERMEN_DLANE_A 0 307 #define CIO2_CSIRX_DLY_CNT_TERMEN_DLANE_B 0 308 #define CIO2_CSIRX_DLY_CNT_SETTLE_DLANE_A 85 309 #define CIO2_CSIRX_DLY_CNT_SETTLE_DLANE_B -2 310 311 #define CIO2_CSIRX_DLY_CNT_TERMEN_DEFAULT 0x4 312 #define CIO2_CSIRX_DLY_CNT_SETTLE_DEFAULT 0x570 313 314 #define CIO2_PMCSR_OFFSET 4 315 #define CIO2_PMCSR_D0D3_SHIFT 2 316 #define CIO2_PMCSR_D3 0x3 317 318 struct cio2_csi2_timing { 319 s32 clk_termen; 320 s32 clk_settle; 321 s32 dat_termen; 322 s32 dat_settle; 323 }; 324 325 struct cio2_buffer { 326 struct vb2_v4l2_buffer vbb; 327 u32 *lop[CIO2_MAX_LOPS]; 328 dma_addr_t lop_bus_addr[CIO2_MAX_LOPS]; 329 unsigned int offset; 330 }; 331 332 struct csi2_bus_info { 333 u32 port; 334 u32 lanes; 335 }; 336 337 struct cio2_queue { 338 /* mutex to be used by vb2_queue */ 339 struct mutex lock; 340 struct media_pipeline pipe; 341 struct csi2_bus_info csi2; 342 struct v4l2_subdev *sensor; 343 void __iomem *csi_rx_base; 344 345 /* Subdev, /dev/v4l-subdevX */ 346 struct v4l2_subdev subdev; 347 struct media_pad subdev_pads[CIO2_PADS]; 348 struct v4l2_mbus_framefmt subdev_fmt; 349 atomic_t frame_sequence; 350 351 /* Video device, /dev/videoX */ 352 struct video_device vdev; 353 struct media_pad vdev_pad; 354 struct v4l2_pix_format_mplane format; 355 struct vb2_queue vbq; 356 357 /* Buffer queue handling */ 358 struct cio2_fbpt_entry *fbpt; /* Frame buffer pointer table */ 359 dma_addr_t fbpt_bus_addr; 360 struct cio2_buffer *bufs[CIO2_MAX_BUFFERS]; 361 unsigned int bufs_first; /* Index of the first used entry */ 362 unsigned int bufs_next; /* Index of the first unused entry */ 363 atomic_t bufs_queued; 364 }; 365 366 struct cio2_device { 367 struct pci_dev *pci_dev; 368 void __iomem *base; 369 struct v4l2_device v4l2_dev; 370 struct cio2_queue queue[CIO2_QUEUES]; 371 struct cio2_queue *cur_queue; 372 /* mutex to be used by video_device */ 373 struct mutex lock; 374 375 bool streaming; 376 struct v4l2_async_notifier notifier; 377 struct media_device media_dev; 378 379 /* 380 * Safety net to catch DMA fetch ahead 381 * when reaching the end of LOP 382 */ 383 void *dummy_page; 384 /* DMA handle of dummy_page */ 385 dma_addr_t dummy_page_bus_addr; 386 /* single List of Pointers (LOP) page */ 387 u32 *dummy_lop; 388 /* DMA handle of dummy_lop */ 389 dma_addr_t dummy_lop_bus_addr; 390 }; 391 392 /**************** Virtual channel ****************/ 393 /* 394 * This should come from sensor driver. No 395 * driver interface nor requirement yet. 396 */ 397 #define SENSOR_VIR_CH_DFLT 0 398 399 /**************** FBPT operations ****************/ 400 #define CIO2_FBPT_SIZE (CIO2_MAX_BUFFERS * CIO2_MAX_LOPS * \ 401 sizeof(struct cio2_fbpt_entry)) 402 403 #define CIO2_FBPT_SUBENTRY_UNIT 4 404 #define CIO2_PAGE_SIZE 4096 405 406 /* cio2 fbpt first_entry ctrl status */ 407 #define CIO2_FBPT_CTRL_VALID BIT(0) 408 #define CIO2_FBPT_CTRL_IOC BIT(1) 409 #define CIO2_FBPT_CTRL_IOS BIT(2) 410 #define CIO2_FBPT_CTRL_SUCCXFAIL BIT(3) 411 #define CIO2_FBPT_CTRL_CMPLCODE_SHIFT 4 412 413 /* 414 * Frame Buffer Pointer Table(FBPT) entry 415 * each entry describe an output buffer and consists of 416 * several sub-entries 417 */ 418 struct __packed cio2_fbpt_entry { 419 union { 420 struct __packed { 421 u32 ctrl; /* status ctrl */ 422 u16 cur_line_num; /* current line # written to DDR */ 423 u16 frame_num; /* updated by DMA upon FE */ 424 u32 first_page_offset; /* offset for 1st page in LOP */ 425 } first_entry; 426 /* Second entry per buffer */ 427 struct __packed { 428 u32 timestamp; 429 u32 num_of_bytes; 430 /* the number of bytes for write on last page */ 431 u16 last_page_available_bytes; 432 /* the number of pages allocated for this buf */ 433 u16 num_of_pages; 434 } second_entry; 435 }; 436 u32 lop_page_addr; /* Points to list of pointers (LOP) table */ 437 }; 438 439 static inline struct cio2_queue *file_to_cio2_queue(struct file *file) 440 { 441 return container_of(video_devdata(file), struct cio2_queue, vdev); 442 } 443 444 static inline struct cio2_queue *vb2q_to_cio2_queue(struct vb2_queue *vq) 445 { 446 return container_of(vq, struct cio2_queue, vbq); 447 } 448 449 #endif 450