1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * linux/arch/x86_64/entry.S 4 * 5 * Copyright (C) 1991, 1992 Linus Torvalds 6 * Copyright (C) 2000, 2001, 2002 Andi Kleen SuSE Labs 7 * Copyright (C) 2000 Pavel Machek <pavel@suse.cz> 8 * 9 * entry.S contains the system-call and fault low-level handling routines. 10 * 11 * Some of this is documented in Documentation/x86/entry_64.txt 12 * 13 * A note on terminology: 14 * - iret frame: Architecture defined interrupt frame from SS to RIP 15 * at the top of the kernel process stack. 16 * 17 * Some macro usage: 18 * - ENTRY/END: Define functions in the symbol table. 19 * - TRACE_IRQ_*: Trace hardirq state for lock debugging. 20 * - idtentry: Define exception entry points. 21 */ 22#include <linux/linkage.h> 23#include <asm/segment.h> 24#include <asm/cache.h> 25#include <asm/errno.h> 26#include <asm/asm-offsets.h> 27#include <asm/msr.h> 28#include <asm/unistd.h> 29#include <asm/thread_info.h> 30#include <asm/hw_irq.h> 31#include <asm/page_types.h> 32#include <asm/irqflags.h> 33#include <asm/paravirt.h> 34#include <asm/percpu.h> 35#include <asm/asm.h> 36#include <asm/smap.h> 37#include <asm/pgtable_types.h> 38#include <asm/export.h> 39#include <asm/frame.h> 40#include <asm/nospec-branch.h> 41#include <linux/err.h> 42 43#include "calling.h" 44 45.code64 46.section .entry.text, "ax" 47 48#ifdef CONFIG_PARAVIRT 49ENTRY(native_usergs_sysret64) 50 UNWIND_HINT_EMPTY 51 swapgs 52 sysretq 53END(native_usergs_sysret64) 54#endif /* CONFIG_PARAVIRT */ 55 56.macro TRACE_IRQS_FLAGS flags:req 57#ifdef CONFIG_TRACE_IRQFLAGS 58 bt $9, \flags /* interrupts off? */ 59 jnc 1f 60 TRACE_IRQS_ON 611: 62#endif 63.endm 64 65.macro TRACE_IRQS_IRETQ 66 TRACE_IRQS_FLAGS EFLAGS(%rsp) 67.endm 68 69/* 70 * When dynamic function tracer is enabled it will add a breakpoint 71 * to all locations that it is about to modify, sync CPUs, update 72 * all the code, sync CPUs, then remove the breakpoints. In this time 73 * if lockdep is enabled, it might jump back into the debug handler 74 * outside the updating of the IST protection. (TRACE_IRQS_ON/OFF). 75 * 76 * We need to change the IDT table before calling TRACE_IRQS_ON/OFF to 77 * make sure the stack pointer does not get reset back to the top 78 * of the debug stack, and instead just reuses the current stack. 79 */ 80#if defined(CONFIG_DYNAMIC_FTRACE) && defined(CONFIG_TRACE_IRQFLAGS) 81 82.macro TRACE_IRQS_OFF_DEBUG 83 call debug_stack_set_zero 84 TRACE_IRQS_OFF 85 call debug_stack_reset 86.endm 87 88.macro TRACE_IRQS_ON_DEBUG 89 call debug_stack_set_zero 90 TRACE_IRQS_ON 91 call debug_stack_reset 92.endm 93 94.macro TRACE_IRQS_IRETQ_DEBUG 95 bt $9, EFLAGS(%rsp) /* interrupts off? */ 96 jnc 1f 97 TRACE_IRQS_ON_DEBUG 981: 99.endm 100 101#else 102# define TRACE_IRQS_OFF_DEBUG TRACE_IRQS_OFF 103# define TRACE_IRQS_ON_DEBUG TRACE_IRQS_ON 104# define TRACE_IRQS_IRETQ_DEBUG TRACE_IRQS_IRETQ 105#endif 106 107/* 108 * 64-bit SYSCALL instruction entry. Up to 6 arguments in registers. 109 * 110 * This is the only entry point used for 64-bit system calls. The 111 * hardware interface is reasonably well designed and the register to 112 * argument mapping Linux uses fits well with the registers that are 113 * available when SYSCALL is used. 114 * 115 * SYSCALL instructions can be found inlined in libc implementations as 116 * well as some other programs and libraries. There are also a handful 117 * of SYSCALL instructions in the vDSO used, for example, as a 118 * clock_gettimeofday fallback. 119 * 120 * 64-bit SYSCALL saves rip to rcx, clears rflags.RF, then saves rflags to r11, 121 * then loads new ss, cs, and rip from previously programmed MSRs. 122 * rflags gets masked by a value from another MSR (so CLD and CLAC 123 * are not needed). SYSCALL does not save anything on the stack 124 * and does not change rsp. 125 * 126 * Registers on entry: 127 * rax system call number 128 * rcx return address 129 * r11 saved rflags (note: r11 is callee-clobbered register in C ABI) 130 * rdi arg0 131 * rsi arg1 132 * rdx arg2 133 * r10 arg3 (needs to be moved to rcx to conform to C ABI) 134 * r8 arg4 135 * r9 arg5 136 * (note: r12-r15, rbp, rbx are callee-preserved in C ABI) 137 * 138 * Only called from user space. 139 * 140 * When user can change pt_regs->foo always force IRET. That is because 141 * it deals with uncanonical addresses better. SYSRET has trouble 142 * with them due to bugs in both AMD and Intel CPUs. 143 */ 144 145 .pushsection .entry_trampoline, "ax" 146 147/* 148 * The code in here gets remapped into cpu_entry_area's trampoline. This means 149 * that the assembler and linker have the wrong idea as to where this code 150 * lives (and, in fact, it's mapped more than once, so it's not even at a 151 * fixed address). So we can't reference any symbols outside the entry 152 * trampoline and expect it to work. 153 * 154 * Instead, we carefully abuse %rip-relative addressing. 155 * _entry_trampoline(%rip) refers to the start of the remapped) entry 156 * trampoline. We can thus find cpu_entry_area with this macro: 157 */ 158 159#define CPU_ENTRY_AREA \ 160 _entry_trampoline - CPU_ENTRY_AREA_entry_trampoline(%rip) 161 162/* The top word of the SYSENTER stack is hot and is usable as scratch space. */ 163#define RSP_SCRATCH CPU_ENTRY_AREA_entry_stack + \ 164 SIZEOF_entry_stack - 8 + CPU_ENTRY_AREA 165 166ENTRY(entry_SYSCALL_64_trampoline) 167 UNWIND_HINT_EMPTY 168 swapgs 169 170 /* Stash the user RSP. */ 171 movq %rsp, RSP_SCRATCH 172 173 /* Note: using %rsp as a scratch reg. */ 174 SWITCH_TO_KERNEL_CR3 scratch_reg=%rsp 175 176 /* Load the top of the task stack into RSP */ 177 movq CPU_ENTRY_AREA_tss + TSS_sp1 + CPU_ENTRY_AREA, %rsp 178 179 /* Start building the simulated IRET frame. */ 180 pushq $__USER_DS /* pt_regs->ss */ 181 pushq RSP_SCRATCH /* pt_regs->sp */ 182 pushq %r11 /* pt_regs->flags */ 183 pushq $__USER_CS /* pt_regs->cs */ 184 pushq %rcx /* pt_regs->ip */ 185 186 /* 187 * x86 lacks a near absolute jump, and we can't jump to the real 188 * entry text with a relative jump. We could push the target 189 * address and then use retq, but this destroys the pipeline on 190 * many CPUs (wasting over 20 cycles on Sandy Bridge). Instead, 191 * spill RDI and restore it in a second-stage trampoline. 192 */ 193 pushq %rdi 194 movq $entry_SYSCALL_64_stage2, %rdi 195 JMP_NOSPEC %rdi 196END(entry_SYSCALL_64_trampoline) 197 198 .popsection 199 200ENTRY(entry_SYSCALL_64_stage2) 201 UNWIND_HINT_EMPTY 202 popq %rdi 203 jmp entry_SYSCALL_64_after_hwframe 204END(entry_SYSCALL_64_stage2) 205 206ENTRY(entry_SYSCALL_64) 207 UNWIND_HINT_EMPTY 208 /* 209 * Interrupts are off on entry. 210 * We do not frame this tiny irq-off block with TRACE_IRQS_OFF/ON, 211 * it is too small to ever cause noticeable irq latency. 212 */ 213 214 swapgs 215 /* 216 * This path is only taken when PAGE_TABLE_ISOLATION is disabled so it 217 * is not required to switch CR3. 218 */ 219 movq %rsp, PER_CPU_VAR(rsp_scratch) 220 movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp 221 222 /* Construct struct pt_regs on stack */ 223 pushq $__USER_DS /* pt_regs->ss */ 224 pushq PER_CPU_VAR(rsp_scratch) /* pt_regs->sp */ 225 pushq %r11 /* pt_regs->flags */ 226 pushq $__USER_CS /* pt_regs->cs */ 227 pushq %rcx /* pt_regs->ip */ 228GLOBAL(entry_SYSCALL_64_after_hwframe) 229 pushq %rax /* pt_regs->orig_ax */ 230 231 PUSH_AND_CLEAR_REGS rax=$-ENOSYS 232 233 TRACE_IRQS_OFF 234 235 /* IRQs are off. */ 236 movq %rsp, %rdi 237 call do_syscall_64 /* returns with IRQs disabled */ 238 239 TRACE_IRQS_IRETQ /* we're about to change IF */ 240 241 /* 242 * Try to use SYSRET instead of IRET if we're returning to 243 * a completely clean 64-bit userspace context. If we're not, 244 * go to the slow exit path. 245 */ 246 movq RCX(%rsp), %rcx 247 movq RIP(%rsp), %r11 248 249 cmpq %rcx, %r11 /* SYSRET requires RCX == RIP */ 250 jne swapgs_restore_regs_and_return_to_usermode 251 252 /* 253 * On Intel CPUs, SYSRET with non-canonical RCX/RIP will #GP 254 * in kernel space. This essentially lets the user take over 255 * the kernel, since userspace controls RSP. 256 * 257 * If width of "canonical tail" ever becomes variable, this will need 258 * to be updated to remain correct on both old and new CPUs. 259 * 260 * Change top bits to match most significant bit (47th or 56th bit 261 * depending on paging mode) in the address. 262 */ 263 shl $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx 264 sar $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx 265 266 /* If this changed %rcx, it was not canonical */ 267 cmpq %rcx, %r11 268 jne swapgs_restore_regs_and_return_to_usermode 269 270 cmpq $__USER_CS, CS(%rsp) /* CS must match SYSRET */ 271 jne swapgs_restore_regs_and_return_to_usermode 272 273 movq R11(%rsp), %r11 274 cmpq %r11, EFLAGS(%rsp) /* R11 == RFLAGS */ 275 jne swapgs_restore_regs_and_return_to_usermode 276 277 /* 278 * SYSCALL clears RF when it saves RFLAGS in R11 and SYSRET cannot 279 * restore RF properly. If the slowpath sets it for whatever reason, we 280 * need to restore it correctly. 281 * 282 * SYSRET can restore TF, but unlike IRET, restoring TF results in a 283 * trap from userspace immediately after SYSRET. This would cause an 284 * infinite loop whenever #DB happens with register state that satisfies 285 * the opportunistic SYSRET conditions. For example, single-stepping 286 * this user code: 287 * 288 * movq $stuck_here, %rcx 289 * pushfq 290 * popq %r11 291 * stuck_here: 292 * 293 * would never get past 'stuck_here'. 294 */ 295 testq $(X86_EFLAGS_RF|X86_EFLAGS_TF), %r11 296 jnz swapgs_restore_regs_and_return_to_usermode 297 298 /* nothing to check for RSP */ 299 300 cmpq $__USER_DS, SS(%rsp) /* SS must match SYSRET */ 301 jne swapgs_restore_regs_and_return_to_usermode 302 303 /* 304 * We win! This label is here just for ease of understanding 305 * perf profiles. Nothing jumps here. 306 */ 307syscall_return_via_sysret: 308 /* rcx and r11 are already restored (see code above) */ 309 UNWIND_HINT_EMPTY 310 POP_REGS pop_rdi=0 skip_r11rcx=1 311 312 /* 313 * Now all regs are restored except RSP and RDI. 314 * Save old stack pointer and switch to trampoline stack. 315 */ 316 movq %rsp, %rdi 317 movq PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %rsp 318 319 pushq RSP-RDI(%rdi) /* RSP */ 320 pushq (%rdi) /* RDI */ 321 322 /* 323 * We are on the trampoline stack. All regs except RDI are live. 324 * We can do future final exit work right here. 325 */ 326 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi 327 328 popq %rdi 329 popq %rsp 330 USERGS_SYSRET64 331END(entry_SYSCALL_64) 332 333/* 334 * %rdi: prev task 335 * %rsi: next task 336 */ 337ENTRY(__switch_to_asm) 338 UNWIND_HINT_FUNC 339 /* 340 * Save callee-saved registers 341 * This must match the order in inactive_task_frame 342 */ 343 pushq %rbp 344 pushq %rbx 345 pushq %r12 346 pushq %r13 347 pushq %r14 348 pushq %r15 349 350 /* switch stack */ 351 movq %rsp, TASK_threadsp(%rdi) 352 movq TASK_threadsp(%rsi), %rsp 353 354#ifdef CONFIG_CC_STACKPROTECTOR 355 movq TASK_stack_canary(%rsi), %rbx 356 movq %rbx, PER_CPU_VAR(irq_stack_union)+stack_canary_offset 357#endif 358 359#ifdef CONFIG_RETPOLINE 360 /* 361 * When switching from a shallower to a deeper call stack 362 * the RSB may either underflow or use entries populated 363 * with userspace addresses. On CPUs where those concerns 364 * exist, overwrite the RSB with entries which capture 365 * speculative execution to prevent attack. 366 */ 367 /* Clobbers %rbx */ 368 FILL_RETURN_BUFFER RSB_CLEAR_LOOPS, X86_FEATURE_RSB_CTXSW 369#endif 370 371 /* restore callee-saved registers */ 372 popq %r15 373 popq %r14 374 popq %r13 375 popq %r12 376 popq %rbx 377 popq %rbp 378 379 jmp __switch_to 380END(__switch_to_asm) 381 382/* 383 * A newly forked process directly context switches into this address. 384 * 385 * rax: prev task we switched from 386 * rbx: kernel thread func (NULL for user thread) 387 * r12: kernel thread arg 388 */ 389ENTRY(ret_from_fork) 390 UNWIND_HINT_EMPTY 391 movq %rax, %rdi 392 call schedule_tail /* rdi: 'prev' task parameter */ 393 394 testq %rbx, %rbx /* from kernel_thread? */ 395 jnz 1f /* kernel threads are uncommon */ 396 3972: 398 UNWIND_HINT_REGS 399 movq %rsp, %rdi 400 call syscall_return_slowpath /* returns with IRQs disabled */ 401 TRACE_IRQS_ON /* user mode is traced as IRQS on */ 402 jmp swapgs_restore_regs_and_return_to_usermode 403 4041: 405 /* kernel thread */ 406 movq %r12, %rdi 407 CALL_NOSPEC %rbx 408 /* 409 * A kernel thread is allowed to return here after successfully 410 * calling do_execve(). Exit to userspace to complete the execve() 411 * syscall. 412 */ 413 movq $0, RAX(%rsp) 414 jmp 2b 415END(ret_from_fork) 416 417/* 418 * Build the entry stubs with some assembler magic. 419 * We pack 1 stub into every 8-byte block. 420 */ 421 .align 8 422ENTRY(irq_entries_start) 423 vector=FIRST_EXTERNAL_VECTOR 424 .rept (FIRST_SYSTEM_VECTOR - FIRST_EXTERNAL_VECTOR) 425 UNWIND_HINT_IRET_REGS 426 pushq $(~vector+0x80) /* Note: always in signed byte range */ 427 jmp common_interrupt 428 .align 8 429 vector=vector+1 430 .endr 431END(irq_entries_start) 432 433.macro DEBUG_ENTRY_ASSERT_IRQS_OFF 434#ifdef CONFIG_DEBUG_ENTRY 435 pushq %rax 436 SAVE_FLAGS(CLBR_RAX) 437 testl $X86_EFLAGS_IF, %eax 438 jz .Lokay_\@ 439 ud2 440.Lokay_\@: 441 popq %rax 442#endif 443.endm 444 445/* 446 * Enters the IRQ stack if we're not already using it. NMI-safe. Clobbers 447 * flags and puts old RSP into old_rsp, and leaves all other GPRs alone. 448 * Requires kernel GSBASE. 449 * 450 * The invariant is that, if irq_count != -1, then the IRQ stack is in use. 451 */ 452.macro ENTER_IRQ_STACK regs=1 old_rsp 453 DEBUG_ENTRY_ASSERT_IRQS_OFF 454 movq %rsp, \old_rsp 455 456 .if \regs 457 UNWIND_HINT_REGS base=\old_rsp 458 .endif 459 460 incl PER_CPU_VAR(irq_count) 461 jnz .Lirq_stack_push_old_rsp_\@ 462 463 /* 464 * Right now, if we just incremented irq_count to zero, we've 465 * claimed the IRQ stack but we haven't switched to it yet. 466 * 467 * If anything is added that can interrupt us here without using IST, 468 * it must be *extremely* careful to limit its stack usage. This 469 * could include kprobes and a hypothetical future IST-less #DB 470 * handler. 471 * 472 * The OOPS unwinder relies on the word at the top of the IRQ 473 * stack linking back to the previous RSP for the entire time we're 474 * on the IRQ stack. For this to work reliably, we need to write 475 * it before we actually move ourselves to the IRQ stack. 476 */ 477 478 movq \old_rsp, PER_CPU_VAR(irq_stack_union + IRQ_STACK_SIZE - 8) 479 movq PER_CPU_VAR(irq_stack_ptr), %rsp 480 481#ifdef CONFIG_DEBUG_ENTRY 482 /* 483 * If the first movq above becomes wrong due to IRQ stack layout 484 * changes, the only way we'll notice is if we try to unwind right 485 * here. Assert that we set up the stack right to catch this type 486 * of bug quickly. 487 */ 488 cmpq -8(%rsp), \old_rsp 489 je .Lirq_stack_okay\@ 490 ud2 491 .Lirq_stack_okay\@: 492#endif 493 494.Lirq_stack_push_old_rsp_\@: 495 pushq \old_rsp 496 497 .if \regs 498 UNWIND_HINT_REGS indirect=1 499 .endif 500.endm 501 502/* 503 * Undoes ENTER_IRQ_STACK. 504 */ 505.macro LEAVE_IRQ_STACK regs=1 506 DEBUG_ENTRY_ASSERT_IRQS_OFF 507 /* We need to be off the IRQ stack before decrementing irq_count. */ 508 popq %rsp 509 510 .if \regs 511 UNWIND_HINT_REGS 512 .endif 513 514 /* 515 * As in ENTER_IRQ_STACK, irq_count == 0, we are still claiming 516 * the irq stack but we're not on it. 517 */ 518 519 decl PER_CPU_VAR(irq_count) 520.endm 521 522/* 523 * Interrupt entry/exit. 524 * 525 * Interrupt entry points save only callee clobbered registers in fast path. 526 * 527 * Entry runs with interrupts off. 528 */ 529 530/* 0(%rsp): ~(interrupt number) */ 531 .macro interrupt func 532 cld 533 534 testb $3, CS-ORIG_RAX(%rsp) 535 jz 1f 536 SWAPGS 537 call switch_to_thread_stack 5381: 539 540 PUSH_AND_CLEAR_REGS 541 ENCODE_FRAME_POINTER 542 543 testb $3, CS(%rsp) 544 jz 1f 545 546 /* 547 * IRQ from user mode. 548 * 549 * We need to tell lockdep that IRQs are off. We can't do this until 550 * we fix gsbase, and we should do it before enter_from_user_mode 551 * (which can take locks). Since TRACE_IRQS_OFF idempotent, 552 * the simplest way to handle it is to just call it twice if 553 * we enter from user mode. There's no reason to optimize this since 554 * TRACE_IRQS_OFF is a no-op if lockdep is off. 555 */ 556 TRACE_IRQS_OFF 557 558 CALL_enter_from_user_mode 559 5601: 561 ENTER_IRQ_STACK old_rsp=%rdi 562 /* We entered an interrupt context - irqs are off: */ 563 TRACE_IRQS_OFF 564 565 call \func /* rdi points to pt_regs */ 566 .endm 567 568 /* 569 * The interrupt stubs push (~vector+0x80) onto the stack and 570 * then jump to common_interrupt. 571 */ 572 .p2align CONFIG_X86_L1_CACHE_SHIFT 573common_interrupt: 574 ASM_CLAC 575 addq $-0x80, (%rsp) /* Adjust vector to [-256, -1] range */ 576 interrupt do_IRQ 577 /* 0(%rsp): old RSP */ 578ret_from_intr: 579 DISABLE_INTERRUPTS(CLBR_ANY) 580 TRACE_IRQS_OFF 581 582 LEAVE_IRQ_STACK 583 584 testb $3, CS(%rsp) 585 jz retint_kernel 586 587 /* Interrupt came from user space */ 588GLOBAL(retint_user) 589 mov %rsp,%rdi 590 call prepare_exit_to_usermode 591 TRACE_IRQS_IRETQ 592 593GLOBAL(swapgs_restore_regs_and_return_to_usermode) 594#ifdef CONFIG_DEBUG_ENTRY 595 /* Assert that pt_regs indicates user mode. */ 596 testb $3, CS(%rsp) 597 jnz 1f 598 ud2 5991: 600#endif 601 POP_REGS pop_rdi=0 602 603 /* 604 * The stack is now user RDI, orig_ax, RIP, CS, EFLAGS, RSP, SS. 605 * Save old stack pointer and switch to trampoline stack. 606 */ 607 movq %rsp, %rdi 608 movq PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %rsp 609 610 /* Copy the IRET frame to the trampoline stack. */ 611 pushq 6*8(%rdi) /* SS */ 612 pushq 5*8(%rdi) /* RSP */ 613 pushq 4*8(%rdi) /* EFLAGS */ 614 pushq 3*8(%rdi) /* CS */ 615 pushq 2*8(%rdi) /* RIP */ 616 617 /* Push user RDI on the trampoline stack. */ 618 pushq (%rdi) 619 620 /* 621 * We are on the trampoline stack. All regs except RDI are live. 622 * We can do future final exit work right here. 623 */ 624 625 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi 626 627 /* Restore RDI. */ 628 popq %rdi 629 SWAPGS 630 INTERRUPT_RETURN 631 632 633/* Returning to kernel space */ 634retint_kernel: 635#ifdef CONFIG_PREEMPT 636 /* Interrupts are off */ 637 /* Check if we need preemption */ 638 bt $9, EFLAGS(%rsp) /* were interrupts off? */ 639 jnc 1f 6400: cmpl $0, PER_CPU_VAR(__preempt_count) 641 jnz 1f 642 call preempt_schedule_irq 643 jmp 0b 6441: 645#endif 646 /* 647 * The iretq could re-enable interrupts: 648 */ 649 TRACE_IRQS_IRETQ 650 651GLOBAL(restore_regs_and_return_to_kernel) 652#ifdef CONFIG_DEBUG_ENTRY 653 /* Assert that pt_regs indicates kernel mode. */ 654 testb $3, CS(%rsp) 655 jz 1f 656 ud2 6571: 658#endif 659 POP_REGS 660 addq $8, %rsp /* skip regs->orig_ax */ 661 /* 662 * ARCH_HAS_MEMBARRIER_SYNC_CORE rely on IRET core serialization 663 * when returning from IPI handler. 664 */ 665 INTERRUPT_RETURN 666 667ENTRY(native_iret) 668 UNWIND_HINT_IRET_REGS 669 /* 670 * Are we returning to a stack segment from the LDT? Note: in 671 * 64-bit mode SS:RSP on the exception stack is always valid. 672 */ 673#ifdef CONFIG_X86_ESPFIX64 674 testb $4, (SS-RIP)(%rsp) 675 jnz native_irq_return_ldt 676#endif 677 678.global native_irq_return_iret 679native_irq_return_iret: 680 /* 681 * This may fault. Non-paranoid faults on return to userspace are 682 * handled by fixup_bad_iret. These include #SS, #GP, and #NP. 683 * Double-faults due to espfix64 are handled in do_double_fault. 684 * Other faults here are fatal. 685 */ 686 iretq 687 688#ifdef CONFIG_X86_ESPFIX64 689native_irq_return_ldt: 690 /* 691 * We are running with user GSBASE. All GPRs contain their user 692 * values. We have a percpu ESPFIX stack that is eight slots 693 * long (see ESPFIX_STACK_SIZE). espfix_waddr points to the bottom 694 * of the ESPFIX stack. 695 * 696 * We clobber RAX and RDI in this code. We stash RDI on the 697 * normal stack and RAX on the ESPFIX stack. 698 * 699 * The ESPFIX stack layout we set up looks like this: 700 * 701 * --- top of ESPFIX stack --- 702 * SS 703 * RSP 704 * RFLAGS 705 * CS 706 * RIP <-- RSP points here when we're done 707 * RAX <-- espfix_waddr points here 708 * --- bottom of ESPFIX stack --- 709 */ 710 711 pushq %rdi /* Stash user RDI */ 712 SWAPGS /* to kernel GS */ 713 SWITCH_TO_KERNEL_CR3 scratch_reg=%rdi /* to kernel CR3 */ 714 715 movq PER_CPU_VAR(espfix_waddr), %rdi 716 movq %rax, (0*8)(%rdi) /* user RAX */ 717 movq (1*8)(%rsp), %rax /* user RIP */ 718 movq %rax, (1*8)(%rdi) 719 movq (2*8)(%rsp), %rax /* user CS */ 720 movq %rax, (2*8)(%rdi) 721 movq (3*8)(%rsp), %rax /* user RFLAGS */ 722 movq %rax, (3*8)(%rdi) 723 movq (5*8)(%rsp), %rax /* user SS */ 724 movq %rax, (5*8)(%rdi) 725 movq (4*8)(%rsp), %rax /* user RSP */ 726 movq %rax, (4*8)(%rdi) 727 /* Now RAX == RSP. */ 728 729 andl $0xffff0000, %eax /* RAX = (RSP & 0xffff0000) */ 730 731 /* 732 * espfix_stack[31:16] == 0. The page tables are set up such that 733 * (espfix_stack | (X & 0xffff0000)) points to a read-only alias of 734 * espfix_waddr for any X. That is, there are 65536 RO aliases of 735 * the same page. Set up RSP so that RSP[31:16] contains the 736 * respective 16 bits of the /userspace/ RSP and RSP nonetheless 737 * still points to an RO alias of the ESPFIX stack. 738 */ 739 orq PER_CPU_VAR(espfix_stack), %rax 740 741 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi 742 SWAPGS /* to user GS */ 743 popq %rdi /* Restore user RDI */ 744 745 movq %rax, %rsp 746 UNWIND_HINT_IRET_REGS offset=8 747 748 /* 749 * At this point, we cannot write to the stack any more, but we can 750 * still read. 751 */ 752 popq %rax /* Restore user RAX */ 753 754 /* 755 * RSP now points to an ordinary IRET frame, except that the page 756 * is read-only and RSP[31:16] are preloaded with the userspace 757 * values. We can now IRET back to userspace. 758 */ 759 jmp native_irq_return_iret 760#endif 761END(common_interrupt) 762 763/* 764 * APIC interrupts. 765 */ 766.macro apicinterrupt3 num sym do_sym 767ENTRY(\sym) 768 UNWIND_HINT_IRET_REGS 769 ASM_CLAC 770 pushq $~(\num) 771.Lcommon_\sym: 772 interrupt \do_sym 773 jmp ret_from_intr 774END(\sym) 775.endm 776 777/* Make sure APIC interrupt handlers end up in the irqentry section: */ 778#define PUSH_SECTION_IRQENTRY .pushsection .irqentry.text, "ax" 779#define POP_SECTION_IRQENTRY .popsection 780 781.macro apicinterrupt num sym do_sym 782PUSH_SECTION_IRQENTRY 783apicinterrupt3 \num \sym \do_sym 784POP_SECTION_IRQENTRY 785.endm 786 787#ifdef CONFIG_SMP 788apicinterrupt3 IRQ_MOVE_CLEANUP_VECTOR irq_move_cleanup_interrupt smp_irq_move_cleanup_interrupt 789apicinterrupt3 REBOOT_VECTOR reboot_interrupt smp_reboot_interrupt 790#endif 791 792#ifdef CONFIG_X86_UV 793apicinterrupt3 UV_BAU_MESSAGE uv_bau_message_intr1 uv_bau_message_interrupt 794#endif 795 796apicinterrupt LOCAL_TIMER_VECTOR apic_timer_interrupt smp_apic_timer_interrupt 797apicinterrupt X86_PLATFORM_IPI_VECTOR x86_platform_ipi smp_x86_platform_ipi 798 799#ifdef CONFIG_HAVE_KVM 800apicinterrupt3 POSTED_INTR_VECTOR kvm_posted_intr_ipi smp_kvm_posted_intr_ipi 801apicinterrupt3 POSTED_INTR_WAKEUP_VECTOR kvm_posted_intr_wakeup_ipi smp_kvm_posted_intr_wakeup_ipi 802apicinterrupt3 POSTED_INTR_NESTED_VECTOR kvm_posted_intr_nested_ipi smp_kvm_posted_intr_nested_ipi 803#endif 804 805#ifdef CONFIG_X86_MCE_THRESHOLD 806apicinterrupt THRESHOLD_APIC_VECTOR threshold_interrupt smp_threshold_interrupt 807#endif 808 809#ifdef CONFIG_X86_MCE_AMD 810apicinterrupt DEFERRED_ERROR_VECTOR deferred_error_interrupt smp_deferred_error_interrupt 811#endif 812 813#ifdef CONFIG_X86_THERMAL_VECTOR 814apicinterrupt THERMAL_APIC_VECTOR thermal_interrupt smp_thermal_interrupt 815#endif 816 817#ifdef CONFIG_SMP 818apicinterrupt CALL_FUNCTION_SINGLE_VECTOR call_function_single_interrupt smp_call_function_single_interrupt 819apicinterrupt CALL_FUNCTION_VECTOR call_function_interrupt smp_call_function_interrupt 820apicinterrupt RESCHEDULE_VECTOR reschedule_interrupt smp_reschedule_interrupt 821#endif 822 823apicinterrupt ERROR_APIC_VECTOR error_interrupt smp_error_interrupt 824apicinterrupt SPURIOUS_APIC_VECTOR spurious_interrupt smp_spurious_interrupt 825 826#ifdef CONFIG_IRQ_WORK 827apicinterrupt IRQ_WORK_VECTOR irq_work_interrupt smp_irq_work_interrupt 828#endif 829 830/* 831 * Exception entry points. 832 */ 833#define CPU_TSS_IST(x) PER_CPU_VAR(cpu_tss_rw) + (TSS_ist + ((x) - 1) * 8) 834 835/* 836 * Switch to the thread stack. This is called with the IRET frame and 837 * orig_ax on the stack. (That is, RDI..R12 are not on the stack and 838 * space has not been allocated for them.) 839 */ 840ENTRY(switch_to_thread_stack) 841 UNWIND_HINT_FUNC 842 843 pushq %rdi 844 /* Need to switch before accessing the thread stack. */ 845 SWITCH_TO_KERNEL_CR3 scratch_reg=%rdi 846 movq %rsp, %rdi 847 movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp 848 UNWIND_HINT sp_offset=16 sp_reg=ORC_REG_DI 849 850 pushq 7*8(%rdi) /* regs->ss */ 851 pushq 6*8(%rdi) /* regs->rsp */ 852 pushq 5*8(%rdi) /* regs->eflags */ 853 pushq 4*8(%rdi) /* regs->cs */ 854 pushq 3*8(%rdi) /* regs->ip */ 855 pushq 2*8(%rdi) /* regs->orig_ax */ 856 pushq 8(%rdi) /* return address */ 857 UNWIND_HINT_FUNC 858 859 movq (%rdi), %rdi 860 ret 861END(switch_to_thread_stack) 862 863.macro idtentry sym do_sym has_error_code:req paranoid=0 shift_ist=-1 864ENTRY(\sym) 865 UNWIND_HINT_IRET_REGS offset=\has_error_code*8 866 867 /* Sanity check */ 868 .if \shift_ist != -1 && \paranoid == 0 869 .error "using shift_ist requires paranoid=1" 870 .endif 871 872 ASM_CLAC 873 874 .if \has_error_code == 0 875 pushq $-1 /* ORIG_RAX: no syscall to restart */ 876 .endif 877 878 /* Save all registers in pt_regs */ 879 PUSH_AND_CLEAR_REGS 880 ENCODE_FRAME_POINTER 881 882 .if \paranoid < 2 883 testb $3, CS(%rsp) /* If coming from userspace, switch stacks */ 884 jnz .Lfrom_usermode_switch_stack_\@ 885 .endif 886 887 .if \paranoid 888 call paranoid_entry 889 .else 890 call error_entry 891 .endif 892 UNWIND_HINT_REGS 893 /* returned flag: ebx=0: need swapgs on exit, ebx=1: don't need it */ 894 895 .if \paranoid 896 .if \shift_ist != -1 897 TRACE_IRQS_OFF_DEBUG /* reload IDT in case of recursion */ 898 .else 899 TRACE_IRQS_OFF 900 .endif 901 .endif 902 903 movq %rsp, %rdi /* pt_regs pointer */ 904 905 .if \has_error_code 906 movq ORIG_RAX(%rsp), %rsi /* get error code */ 907 movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */ 908 .else 909 xorl %esi, %esi /* no error code */ 910 .endif 911 912 .if \shift_ist != -1 913 subq $EXCEPTION_STKSZ, CPU_TSS_IST(\shift_ist) 914 .endif 915 916 call \do_sym 917 918 .if \shift_ist != -1 919 addq $EXCEPTION_STKSZ, CPU_TSS_IST(\shift_ist) 920 .endif 921 922 /* these procedures expect "no swapgs" flag in ebx */ 923 .if \paranoid 924 jmp paranoid_exit 925 .else 926 jmp error_exit 927 .endif 928 929 .if \paranoid < 2 930 /* 931 * Entry from userspace. Switch stacks and treat it 932 * as a normal entry. This means that paranoid handlers 933 * run in real process context if user_mode(regs). 934 */ 935.Lfrom_usermode_switch_stack_\@: 936 call error_entry 937 938 movq %rsp, %rdi /* pt_regs pointer */ 939 940 .if \has_error_code 941 movq ORIG_RAX(%rsp), %rsi /* get error code */ 942 movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */ 943 .else 944 xorl %esi, %esi /* no error code */ 945 .endif 946 947 call \do_sym 948 949 jmp error_exit /* %ebx: no swapgs flag */ 950 .endif 951END(\sym) 952.endm 953 954idtentry divide_error do_divide_error has_error_code=0 955idtentry overflow do_overflow has_error_code=0 956idtentry bounds do_bounds has_error_code=0 957idtentry invalid_op do_invalid_op has_error_code=0 958idtentry device_not_available do_device_not_available has_error_code=0 959idtentry double_fault do_double_fault has_error_code=1 paranoid=2 960idtentry coprocessor_segment_overrun do_coprocessor_segment_overrun has_error_code=0 961idtentry invalid_TSS do_invalid_TSS has_error_code=1 962idtentry segment_not_present do_segment_not_present has_error_code=1 963idtentry spurious_interrupt_bug do_spurious_interrupt_bug has_error_code=0 964idtentry coprocessor_error do_coprocessor_error has_error_code=0 965idtentry alignment_check do_alignment_check has_error_code=1 966idtentry simd_coprocessor_error do_simd_coprocessor_error has_error_code=0 967 968 969 /* 970 * Reload gs selector with exception handling 971 * edi: new selector 972 */ 973ENTRY(native_load_gs_index) 974 FRAME_BEGIN 975 pushfq 976 DISABLE_INTERRUPTS(CLBR_ANY & ~CLBR_RDI) 977 TRACE_IRQS_OFF 978 SWAPGS 979.Lgs_change: 980 movl %edi, %gs 9812: ALTERNATIVE "", "mfence", X86_BUG_SWAPGS_FENCE 982 SWAPGS 983 TRACE_IRQS_FLAGS (%rsp) 984 popfq 985 FRAME_END 986 ret 987ENDPROC(native_load_gs_index) 988EXPORT_SYMBOL(native_load_gs_index) 989 990 _ASM_EXTABLE(.Lgs_change, bad_gs) 991 .section .fixup, "ax" 992 /* running with kernelgs */ 993bad_gs: 994 SWAPGS /* switch back to user gs */ 995.macro ZAP_GS 996 /* This can't be a string because the preprocessor needs to see it. */ 997 movl $__USER_DS, %eax 998 movl %eax, %gs 999.endm 1000 ALTERNATIVE "", "ZAP_GS", X86_BUG_NULL_SEG 1001 xorl %eax, %eax 1002 movl %eax, %gs 1003 jmp 2b 1004 .previous 1005 1006/* Call softirq on interrupt stack. Interrupts are off. */ 1007ENTRY(do_softirq_own_stack) 1008 pushq %rbp 1009 mov %rsp, %rbp 1010 ENTER_IRQ_STACK regs=0 old_rsp=%r11 1011 call __do_softirq 1012 LEAVE_IRQ_STACK regs=0 1013 leaveq 1014 ret 1015ENDPROC(do_softirq_own_stack) 1016 1017#ifdef CONFIG_XEN 1018idtentry hypervisor_callback xen_do_hypervisor_callback has_error_code=0 1019 1020/* 1021 * A note on the "critical region" in our callback handler. 1022 * We want to avoid stacking callback handlers due to events occurring 1023 * during handling of the last event. To do this, we keep events disabled 1024 * until we've done all processing. HOWEVER, we must enable events before 1025 * popping the stack frame (can't be done atomically) and so it would still 1026 * be possible to get enough handler activations to overflow the stack. 1027 * Although unlikely, bugs of that kind are hard to track down, so we'd 1028 * like to avoid the possibility. 1029 * So, on entry to the handler we detect whether we interrupted an 1030 * existing activation in its critical region -- if so, we pop the current 1031 * activation and restart the handler using the previous one. 1032 */ 1033ENTRY(xen_do_hypervisor_callback) /* do_hypervisor_callback(struct *pt_regs) */ 1034 1035/* 1036 * Since we don't modify %rdi, evtchn_do_upall(struct *pt_regs) will 1037 * see the correct pointer to the pt_regs 1038 */ 1039 UNWIND_HINT_FUNC 1040 movq %rdi, %rsp /* we don't return, adjust the stack frame */ 1041 UNWIND_HINT_REGS 1042 1043 ENTER_IRQ_STACK old_rsp=%r10 1044 call xen_evtchn_do_upcall 1045 LEAVE_IRQ_STACK 1046 1047#ifndef CONFIG_PREEMPT 1048 call xen_maybe_preempt_hcall 1049#endif 1050 jmp error_exit 1051END(xen_do_hypervisor_callback) 1052 1053/* 1054 * Hypervisor uses this for application faults while it executes. 1055 * We get here for two reasons: 1056 * 1. Fault while reloading DS, ES, FS or GS 1057 * 2. Fault while executing IRET 1058 * Category 1 we do not need to fix up as Xen has already reloaded all segment 1059 * registers that could be reloaded and zeroed the others. 1060 * Category 2 we fix up by killing the current process. We cannot use the 1061 * normal Linux return path in this case because if we use the IRET hypercall 1062 * to pop the stack frame we end up in an infinite loop of failsafe callbacks. 1063 * We distinguish between categories by comparing each saved segment register 1064 * with its current contents: any discrepancy means we in category 1. 1065 */ 1066ENTRY(xen_failsafe_callback) 1067 UNWIND_HINT_EMPTY 1068 movl %ds, %ecx 1069 cmpw %cx, 0x10(%rsp) 1070 jne 1f 1071 movl %es, %ecx 1072 cmpw %cx, 0x18(%rsp) 1073 jne 1f 1074 movl %fs, %ecx 1075 cmpw %cx, 0x20(%rsp) 1076 jne 1f 1077 movl %gs, %ecx 1078 cmpw %cx, 0x28(%rsp) 1079 jne 1f 1080 /* All segments match their saved values => Category 2 (Bad IRET). */ 1081 movq (%rsp), %rcx 1082 movq 8(%rsp), %r11 1083 addq $0x30, %rsp 1084 pushq $0 /* RIP */ 1085 UNWIND_HINT_IRET_REGS offset=8 1086 jmp general_protection 10871: /* Segment mismatch => Category 1 (Bad segment). Retry the IRET. */ 1088 movq (%rsp), %rcx 1089 movq 8(%rsp), %r11 1090 addq $0x30, %rsp 1091 UNWIND_HINT_IRET_REGS 1092 pushq $-1 /* orig_ax = -1 => not a system call */ 1093 PUSH_AND_CLEAR_REGS 1094 ENCODE_FRAME_POINTER 1095 jmp error_exit 1096END(xen_failsafe_callback) 1097 1098apicinterrupt3 HYPERVISOR_CALLBACK_VECTOR \ 1099 xen_hvm_callback_vector xen_evtchn_do_upcall 1100 1101#endif /* CONFIG_XEN */ 1102 1103#if IS_ENABLED(CONFIG_HYPERV) 1104apicinterrupt3 HYPERVISOR_CALLBACK_VECTOR \ 1105 hyperv_callback_vector hyperv_vector_handler 1106 1107apicinterrupt3 HYPERV_REENLIGHTENMENT_VECTOR \ 1108 hyperv_reenlightenment_vector hyperv_reenlightenment_intr 1109#endif /* CONFIG_HYPERV */ 1110 1111idtentry debug do_debug has_error_code=0 paranoid=1 shift_ist=DEBUG_STACK 1112idtentry int3 do_int3 has_error_code=0 paranoid=1 shift_ist=DEBUG_STACK 1113idtentry stack_segment do_stack_segment has_error_code=1 1114 1115#ifdef CONFIG_XEN 1116idtentry xennmi do_nmi has_error_code=0 1117idtentry xendebug do_debug has_error_code=0 1118idtentry xenint3 do_int3 has_error_code=0 1119#endif 1120 1121idtentry general_protection do_general_protection has_error_code=1 1122idtentry page_fault do_page_fault has_error_code=1 1123 1124#ifdef CONFIG_KVM_GUEST 1125idtentry async_page_fault do_async_page_fault has_error_code=1 1126#endif 1127 1128#ifdef CONFIG_X86_MCE 1129idtentry machine_check do_mce has_error_code=0 paranoid=1 1130#endif 1131 1132/* 1133 * Switch gs if needed. 1134 * Use slow, but surefire "are we in kernel?" check. 1135 * Return: ebx=0: need swapgs on exit, ebx=1: otherwise 1136 */ 1137ENTRY(paranoid_entry) 1138 UNWIND_HINT_FUNC 1139 cld 1140 movl $1, %ebx 1141 movl $MSR_GS_BASE, %ecx 1142 rdmsr 1143 testl %edx, %edx 1144 js 1f /* negative -> in kernel */ 1145 SWAPGS 1146 xorl %ebx, %ebx 1147 11481: 1149 SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg=%rax save_reg=%r14 1150 1151 ret 1152END(paranoid_entry) 1153 1154/* 1155 * "Paranoid" exit path from exception stack. This is invoked 1156 * only on return from non-NMI IST interrupts that came 1157 * from kernel space. 1158 * 1159 * We may be returning to very strange contexts (e.g. very early 1160 * in syscall entry), so checking for preemption here would 1161 * be complicated. Fortunately, we there's no good reason 1162 * to try to handle preemption here. 1163 * 1164 * On entry, ebx is "no swapgs" flag (1: don't need swapgs, 0: need it) 1165 */ 1166ENTRY(paranoid_exit) 1167 UNWIND_HINT_REGS 1168 DISABLE_INTERRUPTS(CLBR_ANY) 1169 TRACE_IRQS_OFF_DEBUG 1170 testl %ebx, %ebx /* swapgs needed? */ 1171 jnz .Lparanoid_exit_no_swapgs 1172 TRACE_IRQS_IRETQ 1173 RESTORE_CR3 scratch_reg=%rbx save_reg=%r14 1174 SWAPGS_UNSAFE_STACK 1175 jmp .Lparanoid_exit_restore 1176.Lparanoid_exit_no_swapgs: 1177 TRACE_IRQS_IRETQ_DEBUG 1178 RESTORE_CR3 scratch_reg=%rbx save_reg=%r14 1179.Lparanoid_exit_restore: 1180 jmp restore_regs_and_return_to_kernel 1181END(paranoid_exit) 1182 1183/* 1184 * Switch gs if needed. 1185 * Return: EBX=0: came from user mode; EBX=1: otherwise 1186 */ 1187ENTRY(error_entry) 1188 UNWIND_HINT_REGS offset=8 1189 cld 1190 testb $3, CS+8(%rsp) 1191 jz .Lerror_kernelspace 1192 1193 /* 1194 * We entered from user mode or we're pretending to have entered 1195 * from user mode due to an IRET fault. 1196 */ 1197 SWAPGS 1198 /* We have user CR3. Change to kernel CR3. */ 1199 SWITCH_TO_KERNEL_CR3 scratch_reg=%rax 1200 1201.Lerror_entry_from_usermode_after_swapgs: 1202 /* Put us onto the real thread stack. */ 1203 popq %r12 /* save return addr in %12 */ 1204 movq %rsp, %rdi /* arg0 = pt_regs pointer */ 1205 call sync_regs 1206 movq %rax, %rsp /* switch stack */ 1207 ENCODE_FRAME_POINTER 1208 pushq %r12 1209 1210 /* 1211 * We need to tell lockdep that IRQs are off. We can't do this until 1212 * we fix gsbase, and we should do it before enter_from_user_mode 1213 * (which can take locks). 1214 */ 1215 TRACE_IRQS_OFF 1216 CALL_enter_from_user_mode 1217 ret 1218 1219.Lerror_entry_done: 1220 TRACE_IRQS_OFF 1221 ret 1222 1223 /* 1224 * There are two places in the kernel that can potentially fault with 1225 * usergs. Handle them here. B stepping K8s sometimes report a 1226 * truncated RIP for IRET exceptions returning to compat mode. Check 1227 * for these here too. 1228 */ 1229.Lerror_kernelspace: 1230 incl %ebx 1231 leaq native_irq_return_iret(%rip), %rcx 1232 cmpq %rcx, RIP+8(%rsp) 1233 je .Lerror_bad_iret 1234 movl %ecx, %eax /* zero extend */ 1235 cmpq %rax, RIP+8(%rsp) 1236 je .Lbstep_iret 1237 cmpq $.Lgs_change, RIP+8(%rsp) 1238 jne .Lerror_entry_done 1239 1240 /* 1241 * hack: .Lgs_change can fail with user gsbase. If this happens, fix up 1242 * gsbase and proceed. We'll fix up the exception and land in 1243 * .Lgs_change's error handler with kernel gsbase. 1244 */ 1245 SWAPGS 1246 SWITCH_TO_KERNEL_CR3 scratch_reg=%rax 1247 jmp .Lerror_entry_done 1248 1249.Lbstep_iret: 1250 /* Fix truncated RIP */ 1251 movq %rcx, RIP+8(%rsp) 1252 /* fall through */ 1253 1254.Lerror_bad_iret: 1255 /* 1256 * We came from an IRET to user mode, so we have user 1257 * gsbase and CR3. Switch to kernel gsbase and CR3: 1258 */ 1259 SWAPGS 1260 SWITCH_TO_KERNEL_CR3 scratch_reg=%rax 1261 1262 /* 1263 * Pretend that the exception came from user mode: set up pt_regs 1264 * as if we faulted immediately after IRET and clear EBX so that 1265 * error_exit knows that we will be returning to user mode. 1266 */ 1267 mov %rsp, %rdi 1268 call fixup_bad_iret 1269 mov %rax, %rsp 1270 decl %ebx 1271 jmp .Lerror_entry_from_usermode_after_swapgs 1272END(error_entry) 1273 1274 1275/* 1276 * On entry, EBX is a "return to kernel mode" flag: 1277 * 1: already in kernel mode, don't need SWAPGS 1278 * 0: user gsbase is loaded, we need SWAPGS and standard preparation for return to usermode 1279 */ 1280ENTRY(error_exit) 1281 UNWIND_HINT_REGS 1282 DISABLE_INTERRUPTS(CLBR_ANY) 1283 TRACE_IRQS_OFF 1284 testl %ebx, %ebx 1285 jnz retint_kernel 1286 jmp retint_user 1287END(error_exit) 1288 1289/* 1290 * Runs on exception stack. Xen PV does not go through this path at all, 1291 * so we can use real assembly here. 1292 * 1293 * Registers: 1294 * %r14: Used to save/restore the CR3 of the interrupted context 1295 * when PAGE_TABLE_ISOLATION is in use. Do not clobber. 1296 */ 1297ENTRY(nmi) 1298 UNWIND_HINT_IRET_REGS 1299 1300 /* 1301 * We allow breakpoints in NMIs. If a breakpoint occurs, then 1302 * the iretq it performs will take us out of NMI context. 1303 * This means that we can have nested NMIs where the next 1304 * NMI is using the top of the stack of the previous NMI. We 1305 * can't let it execute because the nested NMI will corrupt the 1306 * stack of the previous NMI. NMI handlers are not re-entrant 1307 * anyway. 1308 * 1309 * To handle this case we do the following: 1310 * Check the a special location on the stack that contains 1311 * a variable that is set when NMIs are executing. 1312 * The interrupted task's stack is also checked to see if it 1313 * is an NMI stack. 1314 * If the variable is not set and the stack is not the NMI 1315 * stack then: 1316 * o Set the special variable on the stack 1317 * o Copy the interrupt frame into an "outermost" location on the 1318 * stack 1319 * o Copy the interrupt frame into an "iret" location on the stack 1320 * o Continue processing the NMI 1321 * If the variable is set or the previous stack is the NMI stack: 1322 * o Modify the "iret" location to jump to the repeat_nmi 1323 * o return back to the first NMI 1324 * 1325 * Now on exit of the first NMI, we first clear the stack variable 1326 * The NMI stack will tell any nested NMIs at that point that it is 1327 * nested. Then we pop the stack normally with iret, and if there was 1328 * a nested NMI that updated the copy interrupt stack frame, a 1329 * jump will be made to the repeat_nmi code that will handle the second 1330 * NMI. 1331 * 1332 * However, espfix prevents us from directly returning to userspace 1333 * with a single IRET instruction. Similarly, IRET to user mode 1334 * can fault. We therefore handle NMIs from user space like 1335 * other IST entries. 1336 */ 1337 1338 ASM_CLAC 1339 1340 /* Use %rdx as our temp variable throughout */ 1341 pushq %rdx 1342 1343 testb $3, CS-RIP+8(%rsp) 1344 jz .Lnmi_from_kernel 1345 1346 /* 1347 * NMI from user mode. We need to run on the thread stack, but we 1348 * can't go through the normal entry paths: NMIs are masked, and 1349 * we don't want to enable interrupts, because then we'll end 1350 * up in an awkward situation in which IRQs are on but NMIs 1351 * are off. 1352 * 1353 * We also must not push anything to the stack before switching 1354 * stacks lest we corrupt the "NMI executing" variable. 1355 */ 1356 1357 swapgs 1358 cld 1359 SWITCH_TO_KERNEL_CR3 scratch_reg=%rdx 1360 movq %rsp, %rdx 1361 movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp 1362 UNWIND_HINT_IRET_REGS base=%rdx offset=8 1363 pushq 5*8(%rdx) /* pt_regs->ss */ 1364 pushq 4*8(%rdx) /* pt_regs->rsp */ 1365 pushq 3*8(%rdx) /* pt_regs->flags */ 1366 pushq 2*8(%rdx) /* pt_regs->cs */ 1367 pushq 1*8(%rdx) /* pt_regs->rip */ 1368 UNWIND_HINT_IRET_REGS 1369 pushq $-1 /* pt_regs->orig_ax */ 1370 PUSH_AND_CLEAR_REGS rdx=(%rdx) 1371 ENCODE_FRAME_POINTER 1372 1373 /* 1374 * At this point we no longer need to worry about stack damage 1375 * due to nesting -- we're on the normal thread stack and we're 1376 * done with the NMI stack. 1377 */ 1378 1379 movq %rsp, %rdi 1380 movq $-1, %rsi 1381 call do_nmi 1382 1383 /* 1384 * Return back to user mode. We must *not* do the normal exit 1385 * work, because we don't want to enable interrupts. 1386 */ 1387 jmp swapgs_restore_regs_and_return_to_usermode 1388 1389.Lnmi_from_kernel: 1390 /* 1391 * Here's what our stack frame will look like: 1392 * +---------------------------------------------------------+ 1393 * | original SS | 1394 * | original Return RSP | 1395 * | original RFLAGS | 1396 * | original CS | 1397 * | original RIP | 1398 * +---------------------------------------------------------+ 1399 * | temp storage for rdx | 1400 * +---------------------------------------------------------+ 1401 * | "NMI executing" variable | 1402 * +---------------------------------------------------------+ 1403 * | iret SS } Copied from "outermost" frame | 1404 * | iret Return RSP } on each loop iteration; overwritten | 1405 * | iret RFLAGS } by a nested NMI to force another | 1406 * | iret CS } iteration if needed. | 1407 * | iret RIP } | 1408 * +---------------------------------------------------------+ 1409 * | outermost SS } initialized in first_nmi; | 1410 * | outermost Return RSP } will not be changed before | 1411 * | outermost RFLAGS } NMI processing is done. | 1412 * | outermost CS } Copied to "iret" frame on each | 1413 * | outermost RIP } iteration. | 1414 * +---------------------------------------------------------+ 1415 * | pt_regs | 1416 * +---------------------------------------------------------+ 1417 * 1418 * The "original" frame is used by hardware. Before re-enabling 1419 * NMIs, we need to be done with it, and we need to leave enough 1420 * space for the asm code here. 1421 * 1422 * We return by executing IRET while RSP points to the "iret" frame. 1423 * That will either return for real or it will loop back into NMI 1424 * processing. 1425 * 1426 * The "outermost" frame is copied to the "iret" frame on each 1427 * iteration of the loop, so each iteration starts with the "iret" 1428 * frame pointing to the final return target. 1429 */ 1430 1431 /* 1432 * Determine whether we're a nested NMI. 1433 * 1434 * If we interrupted kernel code between repeat_nmi and 1435 * end_repeat_nmi, then we are a nested NMI. We must not 1436 * modify the "iret" frame because it's being written by 1437 * the outer NMI. That's okay; the outer NMI handler is 1438 * about to about to call do_nmi anyway, so we can just 1439 * resume the outer NMI. 1440 */ 1441 1442 movq $repeat_nmi, %rdx 1443 cmpq 8(%rsp), %rdx 1444 ja 1f 1445 movq $end_repeat_nmi, %rdx 1446 cmpq 8(%rsp), %rdx 1447 ja nested_nmi_out 14481: 1449 1450 /* 1451 * Now check "NMI executing". If it's set, then we're nested. 1452 * This will not detect if we interrupted an outer NMI just 1453 * before IRET. 1454 */ 1455 cmpl $1, -8(%rsp) 1456 je nested_nmi 1457 1458 /* 1459 * Now test if the previous stack was an NMI stack. This covers 1460 * the case where we interrupt an outer NMI after it clears 1461 * "NMI executing" but before IRET. We need to be careful, though: 1462 * there is one case in which RSP could point to the NMI stack 1463 * despite there being no NMI active: naughty userspace controls 1464 * RSP at the very beginning of the SYSCALL targets. We can 1465 * pull a fast one on naughty userspace, though: we program 1466 * SYSCALL to mask DF, so userspace cannot cause DF to be set 1467 * if it controls the kernel's RSP. We set DF before we clear 1468 * "NMI executing". 1469 */ 1470 lea 6*8(%rsp), %rdx 1471 /* Compare the NMI stack (rdx) with the stack we came from (4*8(%rsp)) */ 1472 cmpq %rdx, 4*8(%rsp) 1473 /* If the stack pointer is above the NMI stack, this is a normal NMI */ 1474 ja first_nmi 1475 1476 subq $EXCEPTION_STKSZ, %rdx 1477 cmpq %rdx, 4*8(%rsp) 1478 /* If it is below the NMI stack, it is a normal NMI */ 1479 jb first_nmi 1480 1481 /* Ah, it is within the NMI stack. */ 1482 1483 testb $(X86_EFLAGS_DF >> 8), (3*8 + 1)(%rsp) 1484 jz first_nmi /* RSP was user controlled. */ 1485 1486 /* This is a nested NMI. */ 1487 1488nested_nmi: 1489 /* 1490 * Modify the "iret" frame to point to repeat_nmi, forcing another 1491 * iteration of NMI handling. 1492 */ 1493 subq $8, %rsp 1494 leaq -10*8(%rsp), %rdx 1495 pushq $__KERNEL_DS 1496 pushq %rdx 1497 pushfq 1498 pushq $__KERNEL_CS 1499 pushq $repeat_nmi 1500 1501 /* Put stack back */ 1502 addq $(6*8), %rsp 1503 1504nested_nmi_out: 1505 popq %rdx 1506 1507 /* We are returning to kernel mode, so this cannot result in a fault. */ 1508 iretq 1509 1510first_nmi: 1511 /* Restore rdx. */ 1512 movq (%rsp), %rdx 1513 1514 /* Make room for "NMI executing". */ 1515 pushq $0 1516 1517 /* Leave room for the "iret" frame */ 1518 subq $(5*8), %rsp 1519 1520 /* Copy the "original" frame to the "outermost" frame */ 1521 .rept 5 1522 pushq 11*8(%rsp) 1523 .endr 1524 UNWIND_HINT_IRET_REGS 1525 1526 /* Everything up to here is safe from nested NMIs */ 1527 1528#ifdef CONFIG_DEBUG_ENTRY 1529 /* 1530 * For ease of testing, unmask NMIs right away. Disabled by 1531 * default because IRET is very expensive. 1532 */ 1533 pushq $0 /* SS */ 1534 pushq %rsp /* RSP (minus 8 because of the previous push) */ 1535 addq $8, (%rsp) /* Fix up RSP */ 1536 pushfq /* RFLAGS */ 1537 pushq $__KERNEL_CS /* CS */ 1538 pushq $1f /* RIP */ 1539 iretq /* continues at repeat_nmi below */ 1540 UNWIND_HINT_IRET_REGS 15411: 1542#endif 1543 1544repeat_nmi: 1545 /* 1546 * If there was a nested NMI, the first NMI's iret will return 1547 * here. But NMIs are still enabled and we can take another 1548 * nested NMI. The nested NMI checks the interrupted RIP to see 1549 * if it is between repeat_nmi and end_repeat_nmi, and if so 1550 * it will just return, as we are about to repeat an NMI anyway. 1551 * This makes it safe to copy to the stack frame that a nested 1552 * NMI will update. 1553 * 1554 * RSP is pointing to "outermost RIP". gsbase is unknown, but, if 1555 * we're repeating an NMI, gsbase has the same value that it had on 1556 * the first iteration. paranoid_entry will load the kernel 1557 * gsbase if needed before we call do_nmi. "NMI executing" 1558 * is zero. 1559 */ 1560 movq $1, 10*8(%rsp) /* Set "NMI executing". */ 1561 1562 /* 1563 * Copy the "outermost" frame to the "iret" frame. NMIs that nest 1564 * here must not modify the "iret" frame while we're writing to 1565 * it or it will end up containing garbage. 1566 */ 1567 addq $(10*8), %rsp 1568 .rept 5 1569 pushq -6*8(%rsp) 1570 .endr 1571 subq $(5*8), %rsp 1572end_repeat_nmi: 1573 1574 /* 1575 * Everything below this point can be preempted by a nested NMI. 1576 * If this happens, then the inner NMI will change the "iret" 1577 * frame to point back to repeat_nmi. 1578 */ 1579 pushq $-1 /* ORIG_RAX: no syscall to restart */ 1580 PUSH_AND_CLEAR_REGS 1581 ENCODE_FRAME_POINTER 1582 1583 /* 1584 * Use paranoid_entry to handle SWAPGS, but no need to use paranoid_exit 1585 * as we should not be calling schedule in NMI context. 1586 * Even with normal interrupts enabled. An NMI should not be 1587 * setting NEED_RESCHED or anything that normal interrupts and 1588 * exceptions might do. 1589 */ 1590 call paranoid_entry 1591 UNWIND_HINT_REGS 1592 1593 /* paranoidentry do_nmi, 0; without TRACE_IRQS_OFF */ 1594 movq %rsp, %rdi 1595 movq $-1, %rsi 1596 call do_nmi 1597 1598 RESTORE_CR3 scratch_reg=%r15 save_reg=%r14 1599 1600 testl %ebx, %ebx /* swapgs needed? */ 1601 jnz nmi_restore 1602nmi_swapgs: 1603 SWAPGS_UNSAFE_STACK 1604nmi_restore: 1605 POP_REGS 1606 1607 /* 1608 * Skip orig_ax and the "outermost" frame to point RSP at the "iret" 1609 * at the "iret" frame. 1610 */ 1611 addq $6*8, %rsp 1612 1613 /* 1614 * Clear "NMI executing". Set DF first so that we can easily 1615 * distinguish the remaining code between here and IRET from 1616 * the SYSCALL entry and exit paths. 1617 * 1618 * We arguably should just inspect RIP instead, but I (Andy) wrote 1619 * this code when I had the misapprehension that Xen PV supported 1620 * NMIs, and Xen PV would break that approach. 1621 */ 1622 std 1623 movq $0, 5*8(%rsp) /* clear "NMI executing" */ 1624 1625 /* 1626 * iretq reads the "iret" frame and exits the NMI stack in a 1627 * single instruction. We are returning to kernel mode, so this 1628 * cannot result in a fault. Similarly, we don't need to worry 1629 * about espfix64 on the way back to kernel mode. 1630 */ 1631 iretq 1632END(nmi) 1633 1634ENTRY(ignore_sysret) 1635 UNWIND_HINT_EMPTY 1636 mov $-ENOSYS, %eax 1637 sysret 1638END(ignore_sysret) 1639 1640ENTRY(rewind_stack_do_exit) 1641 UNWIND_HINT_FUNC 1642 /* Prevent any naive code from trying to unwind to our caller. */ 1643 xorl %ebp, %ebp 1644 1645 movq PER_CPU_VAR(cpu_current_top_of_stack), %rax 1646 leaq -PTREGS_SIZE(%rax), %rsp 1647 UNWIND_HINT_FUNC sp_offset=PTREGS_SIZE 1648 1649 call do_exit 1650END(rewind_stack_do_exit) 1651