1/* 2 * DTS File for HiSilicon Hi3798cv200 SoC. 3 * 4 * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd. 5 * 6 * Released under the GPLv2 only. 7 * SPDX-License-Identifier: GPL-2.0 8 */ 9 10#include <dt-bindings/clock/histb-clock.h> 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/phy/phy.h> 14#include <dt-bindings/reset/ti-syscon.h> 15 16/ { 17 compatible = "hisilicon,hi3798cv200"; 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 psci { 23 compatible = "arm,psci-0.2"; 24 method = "smc"; 25 }; 26 27 cpus { 28 #address-cells = <2>; 29 #size-cells = <0>; 30 31 cpu@0 { 32 compatible = "arm,cortex-a53"; 33 device_type = "cpu"; 34 reg = <0x0 0x0>; 35 enable-method = "psci"; 36 }; 37 38 cpu@1 { 39 compatible = "arm,cortex-a53"; 40 device_type = "cpu"; 41 reg = <0x0 0x1>; 42 enable-method = "psci"; 43 }; 44 45 cpu@2 { 46 compatible = "arm,cortex-a53"; 47 device_type = "cpu"; 48 reg = <0x0 0x2>; 49 enable-method = "psci"; 50 }; 51 52 cpu@3 { 53 compatible = "arm,cortex-a53"; 54 device_type = "cpu"; 55 reg = <0x0 0x3>; 56 enable-method = "psci"; 57 }; 58 }; 59 60 gic: interrupt-controller@f1001000 { 61 compatible = "arm,gic-400"; 62 reg = <0x0 0xf1001000 0x0 0x1000>, /* GICD */ 63 <0x0 0xf1002000 0x0 0x100>; /* GICC */ 64 #address-cells = <0>; 65 #interrupt-cells = <3>; 66 interrupt-controller; 67 }; 68 69 timer { 70 compatible = "arm,armv8-timer"; 71 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | 72 IRQ_TYPE_LEVEL_LOW)>, 73 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | 74 IRQ_TYPE_LEVEL_LOW)>, 75 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | 76 IRQ_TYPE_LEVEL_LOW)>, 77 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | 78 IRQ_TYPE_LEVEL_LOW)>; 79 }; 80 81 soc: soc@f0000000 { 82 compatible = "simple-bus"; 83 #address-cells = <1>; 84 #size-cells = <1>; 85 ranges = <0x0 0x0 0xf0000000 0x10000000>; 86 87 crg: clock-reset-controller@8a22000 { 88 compatible = "hisilicon,hi3798cv200-crg", "syscon", "simple-mfd"; 89 reg = <0x8a22000 0x1000>; 90 #clock-cells = <1>; 91 #reset-cells = <2>; 92 93 gmacphyrst: reset-controller { 94 compatible = "ti,syscon-reset"; 95 #reset-cells = <1>; 96 ti,reset-bits = 97 <0xcc 12 0xcc 12 0 0 (ASSERT_CLEAR | 98 DEASSERT_SET|STATUS_NONE)>, 99 <0xcc 13 0xcc 13 0 0 (ASSERT_CLEAR | 100 DEASSERT_SET|STATUS_NONE)>; 101 }; 102 }; 103 104 sysctrl: system-controller@8000000 { 105 compatible = "hisilicon,hi3798cv200-sysctrl", "syscon"; 106 reg = <0x8000000 0x1000>; 107 #clock-cells = <1>; 108 #reset-cells = <2>; 109 }; 110 111 perictrl: peripheral-controller@8a20000 { 112 compatible = "hisilicon,hi3798cv200-perictrl", "syscon", 113 "simple-mfd"; 114 reg = <0x8a20000 0x1000>; 115 #address-cells = <1>; 116 #size-cells = <1>; 117 ranges = <0x0 0x8a20000 0x1000>; 118 119 combphy0: phy@850 { 120 compatible = "hisilicon,hi3798cv200-combphy"; 121 reg = <0x850 0x8>; 122 #phy-cells = <1>; 123 clocks = <&crg HISTB_COMBPHY0_CLK>; 124 resets = <&crg 0x188 4>; 125 assigned-clocks = <&crg HISTB_COMBPHY0_CLK>; 126 assigned-clock-rates = <100000000>; 127 hisilicon,fixed-mode = <PHY_TYPE_USB3>; 128 }; 129 130 combphy1: phy@858 { 131 compatible = "hisilicon,hi3798cv200-combphy"; 132 reg = <0x858 0x8>; 133 #phy-cells = <1>; 134 clocks = <&crg HISTB_COMBPHY1_CLK>; 135 resets = <&crg 0x188 12>; 136 assigned-clocks = <&crg HISTB_COMBPHY1_CLK>; 137 assigned-clock-rates = <100000000>; 138 hisilicon,mode-select-bits = <0x0008 11 (0x3 << 11)>; 139 }; 140 }; 141 142 uart0: serial@8b00000 { 143 compatible = "arm,pl011", "arm,primecell"; 144 reg = <0x8b00000 0x1000>; 145 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 146 clocks = <&sysctrl HISTB_UART0_CLK>; 147 clock-names = "apb_pclk"; 148 status = "disabled"; 149 }; 150 151 uart2: serial@8b02000 { 152 compatible = "arm,pl011", "arm,primecell"; 153 reg = <0x8b02000 0x1000>; 154 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 155 clocks = <&crg HISTB_UART2_CLK>; 156 clock-names = "apb_pclk"; 157 status = "disabled"; 158 }; 159 160 i2c0: i2c@8b10000 { 161 compatible = "hisilicon,hix5hd2-i2c"; 162 reg = <0x8b10000 0x1000>; 163 #address-cells = <1>; 164 #size-cells = <0>; 165 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 166 clock-frequency = <400000>; 167 clocks = <&crg HISTB_I2C0_CLK>; 168 status = "disabled"; 169 }; 170 171 i2c1: i2c@8b11000 { 172 compatible = "hisilicon,hix5hd2-i2c"; 173 reg = <0x8b11000 0x1000>; 174 #address-cells = <1>; 175 #size-cells = <0>; 176 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 177 clock-frequency = <400000>; 178 clocks = <&crg HISTB_I2C1_CLK>; 179 status = "disabled"; 180 }; 181 182 i2c2: i2c@8b12000 { 183 compatible = "hisilicon,hix5hd2-i2c"; 184 reg = <0x8b12000 0x1000>; 185 #address-cells = <1>; 186 #size-cells = <0>; 187 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 188 clock-frequency = <400000>; 189 clocks = <&crg HISTB_I2C2_CLK>; 190 status = "disabled"; 191 }; 192 193 i2c3: i2c@8b13000 { 194 compatible = "hisilicon,hix5hd2-i2c"; 195 reg = <0x8b13000 0x1000>; 196 #address-cells = <1>; 197 #size-cells = <0>; 198 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 199 clock-frequency = <400000>; 200 clocks = <&crg HISTB_I2C3_CLK>; 201 status = "disabled"; 202 }; 203 204 i2c4: i2c@8b14000 { 205 compatible = "hisilicon,hix5hd2-i2c"; 206 reg = <0x8b14000 0x1000>; 207 #address-cells = <1>; 208 #size-cells = <0>; 209 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 210 clock-frequency = <400000>; 211 clocks = <&crg HISTB_I2C4_CLK>; 212 status = "disabled"; 213 }; 214 215 spi0: spi@8b1a000 { 216 compatible = "arm,pl022", "arm,primecell"; 217 reg = <0x8b1a000 0x1000>; 218 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 219 num-cs = <1>; 220 cs-gpios = <&gpio7 1 0>; 221 clocks = <&crg HISTB_SPI0_CLK>; 222 clock-names = "apb_pclk"; 223 #address-cells = <1>; 224 #size-cells = <0>; 225 status = "disabled"; 226 }; 227 228 sd0: mmc@9820000 { 229 compatible = "snps,dw-mshc"; 230 reg = <0x9820000 0x10000>; 231 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 232 clocks = <&crg HISTB_SDIO0_CIU_CLK>, 233 <&crg HISTB_SDIO0_BIU_CLK>; 234 clock-names = "ciu", "biu"; 235 resets = <&crg 0x9c 4>; 236 reset-names = "reset"; 237 status = "disabled"; 238 }; 239 240 emmc: mmc@9830000 { 241 compatible = "snps,dw-mshc"; 242 reg = <0x9830000 0x10000>; 243 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 244 clocks = <&crg HISTB_MMC_CIU_CLK>, 245 <&crg HISTB_MMC_BIU_CLK>; 246 clock-names = "ciu", "biu"; 247 }; 248 249 gpio0: gpio@8b20000 { 250 compatible = "arm,pl061", "arm,primecell"; 251 reg = <0x8b20000 0x1000>; 252 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 253 gpio-controller; 254 #gpio-cells = <2>; 255 interrupt-controller; 256 #interrupt-cells = <2>; 257 clocks = <&crg HISTB_APB_CLK>; 258 clock-names = "apb_pclk"; 259 status = "disabled"; 260 }; 261 262 gpio1: gpio@8b21000 { 263 compatible = "arm,pl061", "arm,primecell"; 264 reg = <0x8b21000 0x1000>; 265 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 266 gpio-controller; 267 #gpio-cells = <2>; 268 interrupt-controller; 269 #interrupt-cells = <2>; 270 clocks = <&crg HISTB_APB_CLK>; 271 clock-names = "apb_pclk"; 272 status = "disabled"; 273 }; 274 275 gpio2: gpio@8b22000 { 276 compatible = "arm,pl061", "arm,primecell"; 277 reg = <0x8b22000 0x1000>; 278 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 279 gpio-controller; 280 #gpio-cells = <2>; 281 interrupt-controller; 282 #interrupt-cells = <2>; 283 clocks = <&crg HISTB_APB_CLK>; 284 clock-names = "apb_pclk"; 285 status = "disabled"; 286 }; 287 288 gpio3: gpio@8b23000 { 289 compatible = "arm,pl061", "arm,primecell"; 290 reg = <0x8b23000 0x1000>; 291 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 292 gpio-controller; 293 #gpio-cells = <2>; 294 interrupt-controller; 295 #interrupt-cells = <2>; 296 clocks = <&crg HISTB_APB_CLK>; 297 clock-names = "apb_pclk"; 298 status = "disabled"; 299 }; 300 301 gpio4: gpio@8b24000 { 302 compatible = "arm,pl061", "arm,primecell"; 303 reg = <0x8b24000 0x1000>; 304 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 305 gpio-controller; 306 #gpio-cells = <2>; 307 interrupt-controller; 308 #interrupt-cells = <2>; 309 clocks = <&crg HISTB_APB_CLK>; 310 clock-names = "apb_pclk"; 311 status = "disabled"; 312 }; 313 314 gpio5: gpio@8004000 { 315 compatible = "arm,pl061", "arm,primecell"; 316 reg = <0x8004000 0x1000>; 317 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 318 gpio-controller; 319 #gpio-cells = <2>; 320 interrupt-controller; 321 #interrupt-cells = <2>; 322 clocks = <&crg HISTB_APB_CLK>; 323 clock-names = "apb_pclk"; 324 status = "disabled"; 325 }; 326 327 gpio6: gpio@8b26000 { 328 compatible = "arm,pl061", "arm,primecell"; 329 reg = <0x8b26000 0x1000>; 330 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 331 gpio-controller; 332 #gpio-cells = <2>; 333 interrupt-controller; 334 #interrupt-cells = <2>; 335 clocks = <&crg HISTB_APB_CLK>; 336 clock-names = "apb_pclk"; 337 status = "disabled"; 338 }; 339 340 gpio7: gpio@8b27000 { 341 compatible = "arm,pl061", "arm,primecell"; 342 reg = <0x8b27000 0x1000>; 343 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 344 gpio-controller; 345 #gpio-cells = <2>; 346 interrupt-controller; 347 #interrupt-cells = <2>; 348 clocks = <&crg HISTB_APB_CLK>; 349 clock-names = "apb_pclk"; 350 status = "disabled"; 351 }; 352 353 gpio8: gpio@8b28000 { 354 compatible = "arm,pl061", "arm,primecell"; 355 reg = <0x8b28000 0x1000>; 356 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 357 gpio-controller; 358 #gpio-cells = <2>; 359 interrupt-controller; 360 #interrupt-cells = <2>; 361 clocks = <&crg HISTB_APB_CLK>; 362 clock-names = "apb_pclk"; 363 status = "disabled"; 364 }; 365 366 gpio9: gpio@8b29000 { 367 compatible = "arm,pl061", "arm,primecell"; 368 reg = <0x8b29000 0x1000>; 369 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 370 gpio-controller; 371 #gpio-cells = <2>; 372 interrupt-controller; 373 #interrupt-cells = <2>; 374 clocks = <&crg HISTB_APB_CLK>; 375 clock-names = "apb_pclk"; 376 status = "disabled"; 377 }; 378 379 gpio10: gpio@8b2a000 { 380 compatible = "arm,pl061", "arm,primecell"; 381 reg = <0x8b2a000 0x1000>; 382 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 383 gpio-controller; 384 #gpio-cells = <2>; 385 interrupt-controller; 386 #interrupt-cells = <2>; 387 clocks = <&crg HISTB_APB_CLK>; 388 clock-names = "apb_pclk"; 389 status = "disabled"; 390 }; 391 392 gpio11: gpio@8b2b000 { 393 compatible = "arm,pl061", "arm,primecell"; 394 reg = <0x8b2b000 0x1000>; 395 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 396 gpio-controller; 397 #gpio-cells = <2>; 398 interrupt-controller; 399 #interrupt-cells = <2>; 400 clocks = <&crg HISTB_APB_CLK>; 401 clock-names = "apb_pclk"; 402 status = "disabled"; 403 }; 404 405 gpio12: gpio@8b2c000 { 406 compatible = "arm,pl061", "arm,primecell"; 407 reg = <0x8b2c000 0x1000>; 408 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 409 gpio-controller; 410 #gpio-cells = <2>; 411 interrupt-controller; 412 #interrupt-cells = <2>; 413 clocks = <&crg HISTB_APB_CLK>; 414 clock-names = "apb_pclk"; 415 status = "disabled"; 416 }; 417 418 gmac0: ethernet@9840000 { 419 compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2"; 420 reg = <0x9840000 0x1000>, 421 <0x984300c 0x4>; 422 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 423 clocks = <&crg HISTB_ETH0_MAC_CLK>, 424 <&crg HISTB_ETH0_MACIF_CLK>; 425 clock-names = "mac_core", "mac_ifc"; 426 resets = <&crg 0xcc 8>, 427 <&crg 0xcc 10>, 428 <&gmacphyrst 0>; 429 reset-names = "mac_core", "mac_ifc", "phy"; 430 status = "disabled"; 431 }; 432 433 gmac1: ethernet@9841000 { 434 compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2"; 435 reg = <0x9841000 0x1000>, 436 <0x9843010 0x4>; 437 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 438 clocks = <&crg HISTB_ETH1_MAC_CLK>, 439 <&crg HISTB_ETH1_MACIF_CLK>; 440 clock-names = "mac_core", "mac_ifc"; 441 resets = <&crg 0xcc 9>, 442 <&crg 0xcc 11>, 443 <&gmacphyrst 1>; 444 reset-names = "mac_core", "mac_ifc", "phy"; 445 status = "disabled"; 446 }; 447 448 ir: ir@8001000 { 449 compatible = "hisilicon,hix5hd2-ir"; 450 reg = <0x8001000 0x1000>; 451 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 452 clocks = <&sysctrl HISTB_IR_CLK>; 453 status = "disabled"; 454 }; 455 456 pcie: pcie@9860000 { 457 compatible = "hisilicon,hi3798cv200-pcie"; 458 reg = <0x9860000 0x1000>, 459 <0x0 0x2000>, 460 <0x2000000 0x01000000>; 461 reg-names = "control", "rc-dbi", "config"; 462 #address-cells = <3>; 463 #size-cells = <2>; 464 device_type = "pci"; 465 bus-range = <0 15>; 466 num-lanes = <1>; 467 ranges = <0x81000000 0x0 0x00000000 0x4f00000 0x0 0x100000 468 0x82000000 0x0 0x3000000 0x3000000 0x0 0x01f00000>; 469 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 470 interrupt-names = "msi"; 471 #interrupt-cells = <1>; 472 interrupt-map-mask = <0 0 0 0>; 473 interrupt-map = <0 0 0 0 &gic 0 131 IRQ_TYPE_LEVEL_HIGH>; 474 clocks = <&crg HISTB_PCIE_AUX_CLK>, 475 <&crg HISTB_PCIE_PIPE_CLK>, 476 <&crg HISTB_PCIE_SYS_CLK>, 477 <&crg HISTB_PCIE_BUS_CLK>; 478 clock-names = "aux", "pipe", "sys", "bus"; 479 resets = <&crg 0x18c 6>, <&crg 0x18c 5>, <&crg 0x18c 4>; 480 reset-names = "soft", "sys", "bus"; 481 phys = <&combphy1 PHY_TYPE_PCIE>; 482 phy-names = "phy"; 483 status = "disabled"; 484 }; 485 }; 486}; 487