1/* 2 * Copyright (c) 2017 Amlogic, Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 5 */ 6 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10 11/ { 12 compatible = "amlogic,meson-axg"; 13 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 reserved-memory { 19 #address-cells = <2>; 20 #size-cells = <2>; 21 ranges; 22 23 /* 16 MiB reserved for Hardware ROM Firmware */ 24 hwrom_reserved: hwrom@0 { 25 reg = <0x0 0x0 0x0 0x1000000>; 26 no-map; 27 }; 28 29 /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */ 30 secmon_reserved: secmon@5000000 { 31 reg = <0x0 0x05000000 0x0 0x300000>; 32 no-map; 33 }; 34 }; 35 36 cpus { 37 #address-cells = <0x2>; 38 #size-cells = <0x0>; 39 40 cpu0: cpu@0 { 41 device_type = "cpu"; 42 compatible = "arm,cortex-a53", "arm,armv8"; 43 reg = <0x0 0x0>; 44 enable-method = "psci"; 45 next-level-cache = <&l2>; 46 }; 47 48 cpu1: cpu@1 { 49 device_type = "cpu"; 50 compatible = "arm,cortex-a53", "arm,armv8"; 51 reg = <0x0 0x1>; 52 enable-method = "psci"; 53 next-level-cache = <&l2>; 54 }; 55 56 cpu2: cpu@2 { 57 device_type = "cpu"; 58 compatible = "arm,cortex-a53", "arm,armv8"; 59 reg = <0x0 0x2>; 60 enable-method = "psci"; 61 next-level-cache = <&l2>; 62 }; 63 64 cpu3: cpu@3 { 65 device_type = "cpu"; 66 compatible = "arm,cortex-a53", "arm,armv8"; 67 reg = <0x0 0x3>; 68 enable-method = "psci"; 69 next-level-cache = <&l2>; 70 }; 71 72 l2: l2-cache0 { 73 compatible = "cache"; 74 }; 75 }; 76 77 arm-pmu { 78 compatible = "arm,cortex-a53-pmu"; 79 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 80 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 83 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 84 }; 85 86 psci { 87 compatible = "arm,psci-1.0"; 88 method = "smc"; 89 }; 90 91 timer { 92 compatible = "arm,armv8-timer"; 93 interrupts = <GIC_PPI 13 94 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 95 <GIC_PPI 14 96 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 97 <GIC_PPI 11 98 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 99 <GIC_PPI 10 100 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 101 }; 102 103 xtal: xtal-clk { 104 compatible = "fixed-clock"; 105 clock-frequency = <24000000>; 106 clock-output-names = "xtal"; 107 #clock-cells = <0>; 108 }; 109 110 soc { 111 compatible = "simple-bus"; 112 #address-cells = <2>; 113 #size-cells = <2>; 114 ranges; 115 116 cbus: bus@ffd00000 { 117 compatible = "simple-bus"; 118 reg = <0x0 0xffd00000 0x0 0x25000>; 119 #address-cells = <2>; 120 #size-cells = <2>; 121 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>; 122 123 uart_A: serial@24000 { 124 compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart"; 125 reg = <0x0 0x24000 0x0 0x14>; 126 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 127 status = "disabled"; 128 }; 129 130 uart_B: serial@23000 { 131 compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart"; 132 reg = <0x0 0x23000 0x0 0x14>; 133 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; 134 status = "disabled"; 135 }; 136 }; 137 138 gic: interrupt-controller@ffc01000 { 139 compatible = "arm,gic-400"; 140 reg = <0x0 0xffc01000 0 0x1000>, 141 <0x0 0xffc02000 0 0x2000>, 142 <0x0 0xffc04000 0 0x2000>, 143 <0x0 0xffc06000 0 0x2000>; 144 interrupt-controller; 145 interrupts = <GIC_PPI 9 146 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 147 #interrupt-cells = <3>; 148 #address-cells = <0>; 149 }; 150 151 mailbox: mailbox@ff63dc00 { 152 compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu"; 153 reg = <0 0xff63dc00 0 0x400>; 154 interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>, 155 <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>, 156 <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>; 157 #mbox-cells = <1>; 158 }; 159 160 sram: sram@fffc0000 { 161 compatible = "amlogic,meson-axg-sram", "mmio-sram"; 162 reg = <0x0 0xfffc0000 0x0 0x20000>; 163 #address-cells = <1>; 164 #size-cells = <1>; 165 ranges = <0 0x0 0xfffc0000 0x20000>; 166 167 cpu_scp_lpri: scp-shmem@0 { 168 compatible = "amlogic,meson-axg-scp-shmem"; 169 reg = <0x13000 0x400>; 170 }; 171 172 cpu_scp_hpri: scp-shmem@200 { 173 compatible = "amlogic,meson-axg-scp-shmem"; 174 reg = <0x13400 0x400>; 175 }; 176 }; 177 178 aobus: bus@ff800000 { 179 compatible = "simple-bus"; 180 reg = <0x0 0xff800000 0x0 0x100000>; 181 #address-cells = <2>; 182 #size-cells = <2>; 183 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; 184 185 uart_AO: serial@3000 { 186 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; 187 reg = <0x0 0x3000 0x0 0x18>; 188 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 189 clocks = <&xtal>, <&xtal>, <&xtal>; 190 clock-names = "xtal", "pclk", "baud"; 191 status = "disabled"; 192 }; 193 194 uart_AO_B: serial@4000 { 195 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; 196 reg = <0x0 0x4000 0x0 0x18>; 197 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 198 clocks = <&xtal>, <&xtal>, <&xtal>; 199 clock-names = "xtal", "pclk", "baud"; 200 status = "disabled"; 201 }; 202 }; 203 }; 204}; 205