1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc.cls 3 * 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #include "dm_services.h" 28 29 30 #include "stream_encoder.h" 31 #include "resource.h" 32 #include "include/irq_service_interface.h" 33 #include "dce120_resource.h" 34 #include "dce112/dce112_resource.h" 35 36 #include "dce110/dce110_resource.h" 37 #include "../virtual/virtual_stream_encoder.h" 38 #include "dce120_timing_generator.h" 39 #include "irq/dce120/irq_service_dce120.h" 40 #include "dce/dce_opp.h" 41 #include "dce/dce_clock_source.h" 42 #include "dce/dce_clocks.h" 43 #include "dce/dce_ipp.h" 44 #include "dce/dce_mem_input.h" 45 46 #include "dce110/dce110_hw_sequencer.h" 47 #include "dce120/dce120_hw_sequencer.h" 48 #include "dce/dce_transform.h" 49 50 #include "dce/dce_audio.h" 51 #include "dce/dce_link_encoder.h" 52 #include "dce/dce_stream_encoder.h" 53 #include "dce/dce_hwseq.h" 54 #include "dce/dce_abm.h" 55 #include "dce/dce_dmcu.h" 56 57 #include "dce/dce_12_0_offset.h" 58 #include "dce/dce_12_0_sh_mask.h" 59 #include "soc15_hw_ip.h" 60 #include "vega10_ip_offset.h" 61 #include "nbio/nbio_6_1_offset.h" 62 #include "reg_helper.h" 63 64 #include "dce100/dce100_resource.h" 65 66 #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL 67 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f 68 #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 69 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f 70 #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 71 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f 72 #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 73 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f 74 #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 75 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f 76 #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 77 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f 78 #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 79 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x270f 80 #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 81 #endif 82 83 enum dce120_clk_src_array_id { 84 DCE120_CLK_SRC_PLL0, 85 DCE120_CLK_SRC_PLL1, 86 DCE120_CLK_SRC_PLL2, 87 DCE120_CLK_SRC_PLL3, 88 DCE120_CLK_SRC_PLL4, 89 DCE120_CLK_SRC_PLL5, 90 91 DCE120_CLK_SRC_TOTAL 92 }; 93 94 static const struct dce110_timing_generator_offsets dce120_tg_offsets[] = { 95 { 96 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 97 }, 98 { 99 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 100 }, 101 { 102 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 103 }, 104 { 105 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 106 }, 107 { 108 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 109 }, 110 { 111 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 112 } 113 }; 114 115 /* begin ********************* 116 * macros to expend register list macro defined in HW object header file */ 117 118 #define BASE_INNER(seg) \ 119 DCE_BASE__INST0_SEG ## seg 120 121 #define NBIO_BASE_INNER(seg) \ 122 NBIF_BASE__INST0_SEG ## seg 123 124 #define NBIO_BASE(seg) \ 125 NBIO_BASE_INNER(seg) 126 127 /* compile time expand base address. */ 128 #define BASE(seg) \ 129 BASE_INNER(seg) 130 131 #define SR(reg_name)\ 132 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 133 mm ## reg_name 134 135 #define SRI(reg_name, block, id)\ 136 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 137 mm ## block ## id ## _ ## reg_name 138 139 /* macros to expend register list macro defined in HW object header file 140 * end *********************/ 141 142 143 static const struct dce_dmcu_registers dmcu_regs = { 144 DMCU_DCE110_COMMON_REG_LIST() 145 }; 146 147 static const struct dce_dmcu_shift dmcu_shift = { 148 DMCU_MASK_SH_LIST_DCE110(__SHIFT) 149 }; 150 151 static const struct dce_dmcu_mask dmcu_mask = { 152 DMCU_MASK_SH_LIST_DCE110(_MASK) 153 }; 154 155 static const struct dce_abm_registers abm_regs = { 156 ABM_DCE110_COMMON_REG_LIST() 157 }; 158 159 static const struct dce_abm_shift abm_shift = { 160 ABM_MASK_SH_LIST_DCE110(__SHIFT) 161 }; 162 163 static const struct dce_abm_mask abm_mask = { 164 ABM_MASK_SH_LIST_DCE110(_MASK) 165 }; 166 167 #define ipp_regs(id)\ 168 [id] = {\ 169 IPP_DCE110_REG_LIST_DCE_BASE(id)\ 170 } 171 172 static const struct dce_ipp_registers ipp_regs[] = { 173 ipp_regs(0), 174 ipp_regs(1), 175 ipp_regs(2), 176 ipp_regs(3), 177 ipp_regs(4), 178 ipp_regs(5) 179 }; 180 181 static const struct dce_ipp_shift ipp_shift = { 182 IPP_DCE120_MASK_SH_LIST_SOC_BASE(__SHIFT) 183 }; 184 185 static const struct dce_ipp_mask ipp_mask = { 186 IPP_DCE120_MASK_SH_LIST_SOC_BASE(_MASK) 187 }; 188 189 #define transform_regs(id)\ 190 [id] = {\ 191 XFM_COMMON_REG_LIST_DCE110(id)\ 192 } 193 194 static const struct dce_transform_registers xfm_regs[] = { 195 transform_regs(0), 196 transform_regs(1), 197 transform_regs(2), 198 transform_regs(3), 199 transform_regs(4), 200 transform_regs(5) 201 }; 202 203 static const struct dce_transform_shift xfm_shift = { 204 XFM_COMMON_MASK_SH_LIST_SOC_BASE(__SHIFT) 205 }; 206 207 static const struct dce_transform_mask xfm_mask = { 208 XFM_COMMON_MASK_SH_LIST_SOC_BASE(_MASK) 209 }; 210 211 #define aux_regs(id)\ 212 [id] = {\ 213 AUX_REG_LIST(id)\ 214 } 215 216 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = { 217 aux_regs(0), 218 aux_regs(1), 219 aux_regs(2), 220 aux_regs(3), 221 aux_regs(4), 222 aux_regs(5) 223 }; 224 225 #define hpd_regs(id)\ 226 [id] = {\ 227 HPD_REG_LIST(id)\ 228 } 229 230 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = { 231 hpd_regs(0), 232 hpd_regs(1), 233 hpd_regs(2), 234 hpd_regs(3), 235 hpd_regs(4), 236 hpd_regs(5) 237 }; 238 239 #define link_regs(id)\ 240 [id] = {\ 241 LE_DCE120_REG_LIST(id), \ 242 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 243 } 244 245 static const struct dce110_link_enc_registers link_enc_regs[] = { 246 link_regs(0), 247 link_regs(1), 248 link_regs(2), 249 link_regs(3), 250 link_regs(4), 251 link_regs(5), 252 link_regs(6), 253 }; 254 255 256 #define stream_enc_regs(id)\ 257 [id] = {\ 258 SE_COMMON_REG_LIST(id),\ 259 .TMDS_CNTL = 0,\ 260 } 261 262 static const struct dce110_stream_enc_registers stream_enc_regs[] = { 263 stream_enc_regs(0), 264 stream_enc_regs(1), 265 stream_enc_regs(2), 266 stream_enc_regs(3), 267 stream_enc_regs(4), 268 stream_enc_regs(5) 269 }; 270 271 static const struct dce_stream_encoder_shift se_shift = { 272 SE_COMMON_MASK_SH_LIST_DCE120(__SHIFT) 273 }; 274 275 static const struct dce_stream_encoder_mask se_mask = { 276 SE_COMMON_MASK_SH_LIST_DCE120(_MASK) 277 }; 278 279 #define opp_regs(id)\ 280 [id] = {\ 281 OPP_DCE_120_REG_LIST(id),\ 282 } 283 284 static const struct dce_opp_registers opp_regs[] = { 285 opp_regs(0), 286 opp_regs(1), 287 opp_regs(2), 288 opp_regs(3), 289 opp_regs(4), 290 opp_regs(5) 291 }; 292 293 static const struct dce_opp_shift opp_shift = { 294 OPP_COMMON_MASK_SH_LIST_DCE_120(__SHIFT) 295 }; 296 297 static const struct dce_opp_mask opp_mask = { 298 OPP_COMMON_MASK_SH_LIST_DCE_120(_MASK) 299 }; 300 301 #define audio_regs(id)\ 302 [id] = {\ 303 AUD_COMMON_REG_LIST(id)\ 304 } 305 306 static const struct dce_audio_registers audio_regs[] = { 307 audio_regs(0), 308 audio_regs(1), 309 audio_regs(2), 310 audio_regs(3), 311 audio_regs(4), 312 audio_regs(5) 313 }; 314 315 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 316 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 317 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 318 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 319 320 static const struct dce_audio_shift audio_shift = { 321 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 322 }; 323 324 static const struct dce_aduio_mask audio_mask = { 325 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 326 }; 327 328 #define clk_src_regs(index, id)\ 329 [index] = {\ 330 CS_COMMON_REG_LIST_DCE_112(id),\ 331 } 332 333 static const struct dce110_clk_src_regs clk_src_regs[] = { 334 clk_src_regs(0, A), 335 clk_src_regs(1, B), 336 clk_src_regs(2, C), 337 clk_src_regs(3, D), 338 clk_src_regs(4, E), 339 clk_src_regs(5, F) 340 }; 341 342 static const struct dce110_clk_src_shift cs_shift = { 343 CS_COMMON_MASK_SH_LIST_DCE_112(__SHIFT) 344 }; 345 346 static const struct dce110_clk_src_mask cs_mask = { 347 CS_COMMON_MASK_SH_LIST_DCE_112(_MASK) 348 }; 349 350 struct output_pixel_processor *dce120_opp_create( 351 struct dc_context *ctx, 352 uint32_t inst) 353 { 354 struct dce110_opp *opp = 355 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); 356 357 if (!opp) 358 return NULL; 359 360 dce110_opp_construct(opp, 361 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 362 return &opp->base; 363 } 364 365 static const struct bios_registers bios_regs = { 366 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 + NBIO_BASE(mmBIOS_SCRATCH_6_BASE_IDX) 367 }; 368 369 static const struct resource_caps res_cap = { 370 .num_timing_generator = 6, 371 .num_audio = 7, 372 .num_stream_encoder = 6, 373 .num_pll = 6, 374 }; 375 376 static const struct dc_debug debug_defaults = { 377 .disable_clock_gate = true, 378 }; 379 380 struct clock_source *dce120_clock_source_create( 381 struct dc_context *ctx, 382 struct dc_bios *bios, 383 enum clock_source_id id, 384 const struct dce110_clk_src_regs *regs, 385 bool dp_clk_src) 386 { 387 struct dce110_clk_src *clk_src = 388 kzalloc(sizeof(*clk_src), GFP_KERNEL); 389 390 if (!clk_src) 391 return NULL; 392 393 if (dce110_clk_src_construct(clk_src, ctx, bios, id, 394 regs, &cs_shift, &cs_mask)) { 395 clk_src->base.dp_clk_src = dp_clk_src; 396 return &clk_src->base; 397 } 398 399 BREAK_TO_DEBUGGER(); 400 return NULL; 401 } 402 403 void dce120_clock_source_destroy(struct clock_source **clk_src) 404 { 405 kfree(TO_DCE110_CLK_SRC(*clk_src)); 406 *clk_src = NULL; 407 } 408 409 410 bool dce120_hw_sequencer_create(struct dc *dc) 411 { 412 /* All registers used by dce11.2 match those in dce11 in offset and 413 * structure 414 */ 415 dce120_hw_sequencer_construct(dc); 416 417 /*TODO Move to separate file and Override what is needed */ 418 419 return true; 420 } 421 422 static struct timing_generator *dce120_timing_generator_create( 423 struct dc_context *ctx, 424 uint32_t instance, 425 const struct dce110_timing_generator_offsets *offsets) 426 { 427 struct dce110_timing_generator *tg110 = 428 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); 429 430 if (!tg110) 431 return NULL; 432 433 dce120_timing_generator_construct(tg110, ctx, instance, offsets); 434 return &tg110->base; 435 } 436 437 static void dce120_transform_destroy(struct transform **xfm) 438 { 439 kfree(TO_DCE_TRANSFORM(*xfm)); 440 *xfm = NULL; 441 } 442 443 static void destruct(struct dce110_resource_pool *pool) 444 { 445 unsigned int i; 446 447 for (i = 0; i < pool->base.pipe_count; i++) { 448 if (pool->base.opps[i] != NULL) 449 dce110_opp_destroy(&pool->base.opps[i]); 450 451 if (pool->base.transforms[i] != NULL) 452 dce120_transform_destroy(&pool->base.transforms[i]); 453 454 if (pool->base.ipps[i] != NULL) 455 dce_ipp_destroy(&pool->base.ipps[i]); 456 457 if (pool->base.mis[i] != NULL) { 458 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); 459 pool->base.mis[i] = NULL; 460 } 461 462 if (pool->base.irqs != NULL) { 463 dal_irq_service_destroy(&pool->base.irqs); 464 } 465 466 if (pool->base.timing_generators[i] != NULL) { 467 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); 468 pool->base.timing_generators[i] = NULL; 469 } 470 } 471 472 for (i = 0; i < pool->base.audio_count; i++) { 473 if (pool->base.audios[i]) 474 dce_aud_destroy(&pool->base.audios[i]); 475 } 476 477 for (i = 0; i < pool->base.stream_enc_count; i++) { 478 if (pool->base.stream_enc[i] != NULL) 479 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); 480 } 481 482 for (i = 0; i < pool->base.clk_src_count; i++) { 483 if (pool->base.clock_sources[i] != NULL) 484 dce120_clock_source_destroy( 485 &pool->base.clock_sources[i]); 486 } 487 488 if (pool->base.dp_clock_source != NULL) 489 dce120_clock_source_destroy(&pool->base.dp_clock_source); 490 491 if (pool->base.abm != NULL) 492 dce_abm_destroy(&pool->base.abm); 493 494 if (pool->base.dmcu != NULL) 495 dce_dmcu_destroy(&pool->base.dmcu); 496 497 if (pool->base.display_clock != NULL) 498 dce_disp_clk_destroy(&pool->base.display_clock); 499 } 500 501 static void read_dce_straps( 502 struct dc_context *ctx, 503 struct resource_straps *straps) 504 { 505 uint32_t reg_val = dm_read_reg_soc15(ctx, mmCC_DC_MISC_STRAPS, 0); 506 507 straps->audio_stream_number = get_reg_field_value(reg_val, 508 CC_DC_MISC_STRAPS, 509 AUDIO_STREAM_NUMBER); 510 straps->hdmi_disable = get_reg_field_value(reg_val, 511 CC_DC_MISC_STRAPS, 512 HDMI_DISABLE); 513 514 reg_val = dm_read_reg_soc15(ctx, mmDC_PINSTRAPS, 0); 515 straps->dc_pinstraps_audio = get_reg_field_value(reg_val, 516 DC_PINSTRAPS, 517 DC_PINSTRAPS_AUDIO); 518 } 519 520 static struct audio *create_audio( 521 struct dc_context *ctx, unsigned int inst) 522 { 523 return dce_audio_create(ctx, inst, 524 &audio_regs[inst], &audio_shift, &audio_mask); 525 } 526 527 static const struct encoder_feature_support link_enc_feature = { 528 .max_hdmi_deep_color = COLOR_DEPTH_121212, 529 .max_hdmi_pixel_clock = 600000, 530 .ycbcr420_supported = true, 531 .flags.bits.IS_HBR2_CAPABLE = true, 532 .flags.bits.IS_HBR3_CAPABLE = true, 533 .flags.bits.IS_TPS3_CAPABLE = true, 534 .flags.bits.IS_TPS4_CAPABLE = true, 535 .flags.bits.IS_YCBCR_CAPABLE = true 536 }; 537 538 static struct link_encoder *dce120_link_encoder_create( 539 const struct encoder_init_data *enc_init_data) 540 { 541 struct dce110_link_encoder *enc110 = 542 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); 543 544 if (!enc110) 545 return NULL; 546 547 dce110_link_encoder_construct(enc110, 548 enc_init_data, 549 &link_enc_feature, 550 &link_enc_regs[enc_init_data->transmitter], 551 &link_enc_aux_regs[enc_init_data->channel - 1], 552 &link_enc_hpd_regs[enc_init_data->hpd_source]); 553 554 return &enc110->base; 555 } 556 557 static struct input_pixel_processor *dce120_ipp_create( 558 struct dc_context *ctx, uint32_t inst) 559 { 560 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); 561 562 if (!ipp) { 563 BREAK_TO_DEBUGGER(); 564 return NULL; 565 } 566 567 dce_ipp_construct(ipp, ctx, inst, 568 &ipp_regs[inst], &ipp_shift, &ipp_mask); 569 return &ipp->base; 570 } 571 572 static struct stream_encoder *dce120_stream_encoder_create( 573 enum engine_id eng_id, 574 struct dc_context *ctx) 575 { 576 struct dce110_stream_encoder *enc110 = 577 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); 578 579 if (!enc110) 580 return NULL; 581 582 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, 583 &stream_enc_regs[eng_id], 584 &se_shift, &se_mask); 585 return &enc110->base; 586 } 587 588 #define SRII(reg_name, block, id)\ 589 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 590 mm ## block ## id ## _ ## reg_name 591 592 static const struct dce_hwseq_registers hwseq_reg = { 593 HWSEQ_DCE120_REG_LIST() 594 }; 595 596 static const struct dce_hwseq_shift hwseq_shift = { 597 HWSEQ_DCE12_MASK_SH_LIST(__SHIFT) 598 }; 599 600 static const struct dce_hwseq_mask hwseq_mask = { 601 HWSEQ_DCE12_MASK_SH_LIST(_MASK) 602 }; 603 604 static struct dce_hwseq *dce120_hwseq_create( 605 struct dc_context *ctx) 606 { 607 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 608 609 if (hws) { 610 hws->ctx = ctx; 611 hws->regs = &hwseq_reg; 612 hws->shifts = &hwseq_shift; 613 hws->masks = &hwseq_mask; 614 } 615 return hws; 616 } 617 618 static const struct resource_create_funcs res_create_funcs = { 619 .read_dce_straps = read_dce_straps, 620 .create_audio = create_audio, 621 .create_stream_encoder = dce120_stream_encoder_create, 622 .create_hwseq = dce120_hwseq_create, 623 }; 624 625 #define mi_inst_regs(id) { MI_DCE12_REG_LIST(id) } 626 static const struct dce_mem_input_registers mi_regs[] = { 627 mi_inst_regs(0), 628 mi_inst_regs(1), 629 mi_inst_regs(2), 630 mi_inst_regs(3), 631 mi_inst_regs(4), 632 mi_inst_regs(5), 633 }; 634 635 static const struct dce_mem_input_shift mi_shifts = { 636 MI_DCE12_MASK_SH_LIST(__SHIFT) 637 }; 638 639 static const struct dce_mem_input_mask mi_masks = { 640 MI_DCE12_MASK_SH_LIST(_MASK) 641 }; 642 643 static struct mem_input *dce120_mem_input_create( 644 struct dc_context *ctx, 645 uint32_t inst) 646 { 647 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), 648 GFP_KERNEL); 649 650 if (!dce_mi) { 651 BREAK_TO_DEBUGGER(); 652 return NULL; 653 } 654 655 dce112_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); 656 return &dce_mi->base; 657 } 658 659 static struct transform *dce120_transform_create( 660 struct dc_context *ctx, 661 uint32_t inst) 662 { 663 struct dce_transform *transform = 664 kzalloc(sizeof(struct dce_transform), GFP_KERNEL); 665 666 if (!transform) 667 return NULL; 668 669 dce_transform_construct(transform, ctx, inst, 670 &xfm_regs[inst], &xfm_shift, &xfm_mask); 671 transform->lb_memory_size = 0x1404; /*5124*/ 672 return &transform->base; 673 } 674 675 static void dce120_destroy_resource_pool(struct resource_pool **pool) 676 { 677 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); 678 679 destruct(dce110_pool); 680 kfree(dce110_pool); 681 *pool = NULL; 682 } 683 684 static const struct resource_funcs dce120_res_pool_funcs = { 685 .destroy = dce120_destroy_resource_pool, 686 .link_enc_create = dce120_link_encoder_create, 687 .validate_guaranteed = dce112_validate_guaranteed, 688 .validate_bandwidth = dce112_validate_bandwidth, 689 .validate_plane = dce100_validate_plane, 690 .add_stream_to_ctx = dce112_add_stream_to_ctx 691 }; 692 693 static void bw_calcs_data_update_from_pplib(struct dc *dc) 694 { 695 struct dm_pp_clock_levels_with_latency eng_clks = {0}; 696 struct dm_pp_clock_levels_with_latency mem_clks = {0}; 697 struct dm_pp_wm_sets_with_clock_ranges clk_ranges = {0}; 698 int i; 699 unsigned int clk; 700 unsigned int latency; 701 702 /*do system clock*/ 703 if (!dm_pp_get_clock_levels_by_type_with_latency( 704 dc->ctx, 705 DM_PP_CLOCK_TYPE_ENGINE_CLK, 706 &eng_clks) || eng_clks.num_levels == 0) { 707 708 eng_clks.num_levels = 8; 709 clk = 300000; 710 711 for (i = 0; i < eng_clks.num_levels; i++) { 712 eng_clks.data[i].clocks_in_khz = clk; 713 clk += 100000; 714 } 715 } 716 717 /* convert all the clock fro kHz to fix point mHz TODO: wloop data */ 718 dc->bw_vbios->high_sclk = bw_frc_to_fixed( 719 eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000); 720 dc->bw_vbios->mid1_sclk = bw_frc_to_fixed( 721 eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000); 722 dc->bw_vbios->mid2_sclk = bw_frc_to_fixed( 723 eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000); 724 dc->bw_vbios->mid3_sclk = bw_frc_to_fixed( 725 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000); 726 dc->bw_vbios->mid4_sclk = bw_frc_to_fixed( 727 eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000); 728 dc->bw_vbios->mid5_sclk = bw_frc_to_fixed( 729 eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000); 730 dc->bw_vbios->mid6_sclk = bw_frc_to_fixed( 731 eng_clks.data[eng_clks.num_levels*6/8].clocks_in_khz, 1000); 732 dc->bw_vbios->low_sclk = bw_frc_to_fixed( 733 eng_clks.data[0].clocks_in_khz, 1000); 734 735 /*do memory clock*/ 736 if (!dm_pp_get_clock_levels_by_type_with_latency( 737 dc->ctx, 738 DM_PP_CLOCK_TYPE_MEMORY_CLK, 739 &mem_clks) || mem_clks.num_levels == 0) { 740 741 mem_clks.num_levels = 3; 742 clk = 250000; 743 latency = 45; 744 745 for (i = 0; i < eng_clks.num_levels; i++) { 746 mem_clks.data[i].clocks_in_khz = clk; 747 mem_clks.data[i].latency_in_us = latency; 748 clk += 500000; 749 latency -= 5; 750 } 751 752 } 753 754 /* we don't need to call PPLIB for validation clock since they 755 * also give us the highest sclk and highest mclk (UMA clock). 756 * ALSO always convert UMA clock (from PPLIB) to YCLK (HW formula): 757 * YCLK = UMACLK*m_memoryTypeMultiplier 758 */ 759 dc->bw_vbios->low_yclk = bw_frc_to_fixed( 760 mem_clks.data[0].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, 1000); 761 dc->bw_vbios->mid_yclk = bw_frc_to_fixed( 762 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, 763 1000); 764 dc->bw_vbios->high_yclk = bw_frc_to_fixed( 765 mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, 766 1000); 767 768 /* Now notify PPLib/SMU about which Watermarks sets they should select 769 * depending on DPM state they are in. And update BW MGR GFX Engine and 770 * Memory clock member variables for Watermarks calculations for each 771 * Watermark Set 772 */ 773 clk_ranges.num_wm_sets = 4; 774 clk_ranges.wm_clk_ranges[0].wm_set_id = WM_SET_A; 775 clk_ranges.wm_clk_ranges[0].wm_min_eng_clk_in_khz = 776 eng_clks.data[0].clocks_in_khz; 777 clk_ranges.wm_clk_ranges[0].wm_max_eng_clk_in_khz = 778 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1; 779 clk_ranges.wm_clk_ranges[0].wm_min_memg_clk_in_khz = 780 mem_clks.data[0].clocks_in_khz; 781 clk_ranges.wm_clk_ranges[0].wm_max_mem_clk_in_khz = 782 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1; 783 784 clk_ranges.wm_clk_ranges[1].wm_set_id = WM_SET_B; 785 clk_ranges.wm_clk_ranges[1].wm_min_eng_clk_in_khz = 786 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz; 787 /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */ 788 clk_ranges.wm_clk_ranges[1].wm_max_eng_clk_in_khz = 5000000; 789 clk_ranges.wm_clk_ranges[1].wm_min_memg_clk_in_khz = 790 mem_clks.data[0].clocks_in_khz; 791 clk_ranges.wm_clk_ranges[1].wm_max_mem_clk_in_khz = 792 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1; 793 794 clk_ranges.wm_clk_ranges[2].wm_set_id = WM_SET_C; 795 clk_ranges.wm_clk_ranges[2].wm_min_eng_clk_in_khz = 796 eng_clks.data[0].clocks_in_khz; 797 clk_ranges.wm_clk_ranges[2].wm_max_eng_clk_in_khz = 798 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1; 799 clk_ranges.wm_clk_ranges[2].wm_min_memg_clk_in_khz = 800 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz; 801 /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */ 802 clk_ranges.wm_clk_ranges[2].wm_max_mem_clk_in_khz = 5000000; 803 804 clk_ranges.wm_clk_ranges[3].wm_set_id = WM_SET_D; 805 clk_ranges.wm_clk_ranges[3].wm_min_eng_clk_in_khz = 806 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz; 807 /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */ 808 clk_ranges.wm_clk_ranges[3].wm_max_eng_clk_in_khz = 5000000; 809 clk_ranges.wm_clk_ranges[3].wm_min_memg_clk_in_khz = 810 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz; 811 /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */ 812 clk_ranges.wm_clk_ranges[3].wm_max_mem_clk_in_khz = 5000000; 813 814 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */ 815 dm_pp_notify_wm_clock_changes(dc->ctx, &clk_ranges); 816 } 817 818 static bool construct( 819 uint8_t num_virtual_links, 820 struct dc *dc, 821 struct dce110_resource_pool *pool) 822 { 823 unsigned int i; 824 struct dc_context *ctx = dc->ctx; 825 struct irq_service_init_data irq_init_data; 826 827 ctx->dc_bios->regs = &bios_regs; 828 829 pool->base.res_cap = &res_cap; 830 pool->base.funcs = &dce120_res_pool_funcs; 831 832 /* TODO: Fill more data from GreenlandAsicCapability.cpp */ 833 pool->base.pipe_count = res_cap.num_timing_generator; 834 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; 835 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 836 837 dc->caps.max_downscale_ratio = 200; 838 dc->caps.i2c_speed_in_khz = 100; 839 dc->caps.max_cursor_size = 128; 840 dc->caps.dual_link_dvi = true; 841 842 dc->debug = debug_defaults; 843 844 /************************************************* 845 * Create resources * 846 *************************************************/ 847 848 pool->base.clock_sources[DCE120_CLK_SRC_PLL0] = 849 dce120_clock_source_create(ctx, ctx->dc_bios, 850 CLOCK_SOURCE_COMBO_PHY_PLL0, 851 &clk_src_regs[0], false); 852 pool->base.clock_sources[DCE120_CLK_SRC_PLL1] = 853 dce120_clock_source_create(ctx, ctx->dc_bios, 854 CLOCK_SOURCE_COMBO_PHY_PLL1, 855 &clk_src_regs[1], false); 856 pool->base.clock_sources[DCE120_CLK_SRC_PLL2] = 857 dce120_clock_source_create(ctx, ctx->dc_bios, 858 CLOCK_SOURCE_COMBO_PHY_PLL2, 859 &clk_src_regs[2], false); 860 pool->base.clock_sources[DCE120_CLK_SRC_PLL3] = 861 dce120_clock_source_create(ctx, ctx->dc_bios, 862 CLOCK_SOURCE_COMBO_PHY_PLL3, 863 &clk_src_regs[3], false); 864 pool->base.clock_sources[DCE120_CLK_SRC_PLL4] = 865 dce120_clock_source_create(ctx, ctx->dc_bios, 866 CLOCK_SOURCE_COMBO_PHY_PLL4, 867 &clk_src_regs[4], false); 868 pool->base.clock_sources[DCE120_CLK_SRC_PLL5] = 869 dce120_clock_source_create(ctx, ctx->dc_bios, 870 CLOCK_SOURCE_COMBO_PHY_PLL5, 871 &clk_src_regs[5], false); 872 pool->base.clk_src_count = DCE120_CLK_SRC_TOTAL; 873 874 pool->base.dp_clock_source = 875 dce120_clock_source_create(ctx, ctx->dc_bios, 876 CLOCK_SOURCE_ID_DP_DTO, 877 &clk_src_regs[0], true); 878 879 for (i = 0; i < pool->base.clk_src_count; i++) { 880 if (pool->base.clock_sources[i] == NULL) { 881 dm_error("DC: failed to create clock sources!\n"); 882 BREAK_TO_DEBUGGER(); 883 goto clk_src_create_fail; 884 } 885 } 886 887 pool->base.display_clock = dce120_disp_clk_create(ctx); 888 if (pool->base.display_clock == NULL) { 889 dm_error("DC: failed to create display clock!\n"); 890 BREAK_TO_DEBUGGER(); 891 goto disp_clk_create_fail; 892 } 893 894 pool->base.dmcu = dce_dmcu_create(ctx, 895 &dmcu_regs, 896 &dmcu_shift, 897 &dmcu_mask); 898 if (pool->base.dmcu == NULL) { 899 dm_error("DC: failed to create dmcu!\n"); 900 BREAK_TO_DEBUGGER(); 901 goto res_create_fail; 902 } 903 904 pool->base.abm = dce_abm_create(ctx, 905 &abm_regs, 906 &abm_shift, 907 &abm_mask); 908 if (pool->base.abm == NULL) { 909 dm_error("DC: failed to create abm!\n"); 910 BREAK_TO_DEBUGGER(); 911 goto res_create_fail; 912 } 913 914 irq_init_data.ctx = dc->ctx; 915 pool->base.irqs = dal_irq_service_dce120_create(&irq_init_data); 916 if (!pool->base.irqs) 917 goto irqs_create_fail; 918 919 for (i = 0; i < pool->base.pipe_count; i++) { 920 pool->base.timing_generators[i] = 921 dce120_timing_generator_create( 922 ctx, 923 i, 924 &dce120_tg_offsets[i]); 925 if (pool->base.timing_generators[i] == NULL) { 926 BREAK_TO_DEBUGGER(); 927 dm_error("DC: failed to create tg!\n"); 928 goto controller_create_fail; 929 } 930 931 pool->base.mis[i] = dce120_mem_input_create(ctx, i); 932 933 if (pool->base.mis[i] == NULL) { 934 BREAK_TO_DEBUGGER(); 935 dm_error( 936 "DC: failed to create memory input!\n"); 937 goto controller_create_fail; 938 } 939 940 pool->base.ipps[i] = dce120_ipp_create(ctx, i); 941 if (pool->base.ipps[i] == NULL) { 942 BREAK_TO_DEBUGGER(); 943 dm_error( 944 "DC: failed to create input pixel processor!\n"); 945 goto controller_create_fail; 946 } 947 948 pool->base.transforms[i] = dce120_transform_create(ctx, i); 949 if (pool->base.transforms[i] == NULL) { 950 BREAK_TO_DEBUGGER(); 951 dm_error( 952 "DC: failed to create transform!\n"); 953 goto res_create_fail; 954 } 955 956 pool->base.opps[i] = dce120_opp_create( 957 ctx, 958 i); 959 if (pool->base.opps[i] == NULL) { 960 BREAK_TO_DEBUGGER(); 961 dm_error( 962 "DC: failed to create output pixel processor!\n"); 963 } 964 } 965 966 if (!resource_construct(num_virtual_links, dc, &pool->base, 967 &res_create_funcs)) 968 goto res_create_fail; 969 970 /* Create hardware sequencer */ 971 if (!dce120_hw_sequencer_create(dc)) 972 goto controller_create_fail; 973 974 dc->caps.max_planes = pool->base.pipe_count; 975 976 bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id); 977 978 bw_calcs_data_update_from_pplib(dc); 979 980 return true; 981 982 irqs_create_fail: 983 controller_create_fail: 984 disp_clk_create_fail: 985 clk_src_create_fail: 986 res_create_fail: 987 988 destruct(pool); 989 990 return false; 991 } 992 993 struct resource_pool *dce120_create_resource_pool( 994 uint8_t num_virtual_links, 995 struct dc *dc) 996 { 997 struct dce110_resource_pool *pool = 998 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 999 1000 if (!pool) 1001 return NULL; 1002 1003 if (construct(num_virtual_links, dc, pool)) 1004 return &pool->base; 1005 1006 BREAK_TO_DEBUGGER(); 1007 return NULL; 1008 } 1009