1/* 2 * Device Tree Source for the r8a77995 SoC 3 * 4 * Copyright (C) 2016 Renesas Electronics Corp. 5 * Copyright (C) 2017 Glider bvba 6 * 7 * This file is licensed under the terms of the GNU General Public License 8 * version 2. This program is licensed "as is" without any warranty of any 9 * kind, whether express or implied. 10 */ 11 12#include <dt-bindings/clock/r8a77995-cpg-mssr.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/power/r8a77995-sysc.h> 15 16/ { 17 compatible = "renesas,r8a77995"; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 psci { 22 compatible = "arm,psci-1.0", "arm,psci-0.2"; 23 method = "smc"; 24 }; 25 26 cpus { 27 #address-cells = <1>; 28 #size-cells = <0>; 29 30 a53_0: cpu@0 { 31 compatible = "arm,cortex-a53", "arm,armv8"; 32 reg = <0x0>; 33 device_type = "cpu"; 34 power-domains = <&sysc R8A77995_PD_CA53_CPU0>; 35 next-level-cache = <&L2_CA53>; 36 enable-method = "psci"; 37 }; 38 39 L2_CA53: cache-controller-1 { 40 compatible = "cache"; 41 power-domains = <&sysc R8A77995_PD_CA53_SCU>; 42 cache-unified; 43 cache-level = <2>; 44 }; 45 }; 46 47 extal_clk: extal { 48 compatible = "fixed-clock"; 49 #clock-cells = <0>; 50 /* This value must be overridden by the board */ 51 clock-frequency = <0>; 52 }; 53 54 /* External CAN clock - to be overridden by boards that provide it */ 55 can_clk: can { 56 compatible = "fixed-clock"; 57 #clock-cells = <0>; 58 clock-frequency = <0>; 59 }; 60 61 pmu_a53 { 62 compatible = "arm,cortex-a53-pmu"; 63 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 64 }; 65 66 scif_clk: scif { 67 compatible = "fixed-clock"; 68 #clock-cells = <0>; 69 clock-frequency = <0>; 70 }; 71 72 soc { 73 compatible = "simple-bus"; 74 interrupt-parent = <&gic>; 75 #address-cells = <2>; 76 #size-cells = <2>; 77 ranges; 78 79 gic: interrupt-controller@f1010000 { 80 compatible = "arm,gic-400"; 81 #interrupt-cells = <3>; 82 #address-cells = <0>; 83 interrupt-controller; 84 reg = <0x0 0xf1010000 0 0x1000>, 85 <0x0 0xf1020000 0 0x20000>, 86 <0x0 0xf1040000 0 0x20000>, 87 <0x0 0xf1060000 0 0x20000>; 88 interrupts = <GIC_PPI 9 89 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; 90 clocks = <&cpg CPG_MOD 408>; 91 clock-names = "clk"; 92 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 93 resets = <&cpg 408>; 94 }; 95 96 rwdt: watchdog@e6020000 { 97 compatible = "renesas,r8a77995-wdt", 98 "renesas,rcar-gen3-wdt"; 99 reg = <0 0xe6020000 0 0x0c>; 100 clocks = <&cpg CPG_MOD 402>; 101 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 102 resets = <&cpg 402>; 103 status = "disabled"; 104 }; 105 106 ipmmu_vi0: mmu@febd0000 { 107 compatible = "renesas,ipmmu-r8a77995"; 108 reg = <0 0xfebd0000 0 0x1000>; 109 renesas,ipmmu-main = <&ipmmu_mm 14>; 110 #iommu-cells = <1>; 111 status = "disabled"; 112 }; 113 114 ipmmu_vp0: mmu@fe990000 { 115 compatible = "renesas,ipmmu-r8a77995"; 116 reg = <0 0xfe990000 0 0x1000>; 117 renesas,ipmmu-main = <&ipmmu_mm 16>; 118 #iommu-cells = <1>; 119 status = "disabled"; 120 }; 121 122 ipmmu_vc0: mmu@fe6b0000 { 123 compatible = "renesas,ipmmu-r8a77995"; 124 reg = <0 0xfe6b0000 0 0x1000>; 125 renesas,ipmmu-main = <&ipmmu_mm 12>; 126 #iommu-cells = <1>; 127 status = "disabled"; 128 }; 129 130 ipmmu_pv0: mmu@fd800000 { 131 compatible = "renesas,ipmmu-r8a77995"; 132 reg = <0 0xfd800000 0 0x1000>; 133 renesas,ipmmu-main = <&ipmmu_mm 6>; 134 #iommu-cells = <1>; 135 status = "disabled"; 136 }; 137 138 ipmmu_hc: mmu@e6570000 { 139 compatible = "renesas,ipmmu-r8a77995"; 140 reg = <0 0xe6570000 0 0x1000>; 141 renesas,ipmmu-main = <&ipmmu_mm 2>; 142 #iommu-cells = <1>; 143 status = "disabled"; 144 }; 145 146 ipmmu_rt: mmu@ffc80000 { 147 compatible = "renesas,ipmmu-r8a77995"; 148 reg = <0 0xffc80000 0 0x1000>; 149 renesas,ipmmu-main = <&ipmmu_mm 10>; 150 #iommu-cells = <1>; 151 status = "disabled"; 152 }; 153 154 ipmmu_mp: mmu@ec670000 { 155 compatible = "renesas,ipmmu-r8a77995"; 156 reg = <0 0xec670000 0 0x1000>; 157 renesas,ipmmu-main = <&ipmmu_mm 4>; 158 #iommu-cells = <1>; 159 status = "disabled"; 160 }; 161 162 ipmmu_ds0: mmu@e6740000 { 163 compatible = "renesas,ipmmu-r8a77995"; 164 reg = <0 0xe6740000 0 0x1000>; 165 renesas,ipmmu-main = <&ipmmu_mm 0>; 166 #iommu-cells = <1>; 167 status = "disabled"; 168 }; 169 170 ipmmu_ds1: mmu@e7740000 { 171 compatible = "renesas,ipmmu-r8a77995"; 172 reg = <0 0xe7740000 0 0x1000>; 173 renesas,ipmmu-main = <&ipmmu_mm 1>; 174 #iommu-cells = <1>; 175 status = "disabled"; 176 }; 177 178 ipmmu_mm: mmu@e67b0000 { 179 compatible = "renesas,ipmmu-r8a77995"; 180 reg = <0 0xe67b0000 0 0x1000>; 181 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 183 #iommu-cells = <1>; 184 status = "disabled"; 185 }; 186 187 188 cpg: clock-controller@e6150000 { 189 compatible = "renesas,r8a77995-cpg-mssr"; 190 reg = <0 0xe6150000 0 0x1000>; 191 clocks = <&extal_clk>; 192 clock-names = "extal"; 193 #clock-cells = <2>; 194 #power-domain-cells = <0>; 195 #reset-cells = <1>; 196 }; 197 198 rst: reset-controller@e6160000 { 199 compatible = "renesas,r8a77995-rst"; 200 reg = <0 0xe6160000 0 0x0200>; 201 }; 202 203 pfc: pin-controller@e6060000 { 204 compatible = "renesas,pfc-r8a77995"; 205 reg = <0 0xe6060000 0 0x508>; 206 }; 207 208 prr: chipid@fff00044 { 209 compatible = "renesas,prr"; 210 reg = <0 0xfff00044 0 4>; 211 }; 212 213 sysc: system-controller@e6180000 { 214 compatible = "renesas,r8a77995-sysc"; 215 reg = <0 0xe6180000 0 0x0400>; 216 #power-domain-cells = <1>; 217 }; 218 219 intc_ex: interrupt-controller@e61c0000 { 220 compatible = "renesas,intc-ex-r8a77995", "renesas,irqc"; 221 #interrupt-cells = <2>; 222 interrupt-controller; 223 reg = <0 0xe61c0000 0 0x200>; 224 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 225 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 226 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH 227 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 228 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 229 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 230 clocks = <&cpg CPG_MOD 407>; 231 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 232 resets = <&cpg 407>; 233 }; 234 235 dmac0: dma-controller@e6700000 { 236 compatible = "renesas,dmac-r8a77995", 237 "renesas,rcar-dmac"; 238 reg = <0 0xe6700000 0 0x10000>; 239 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH 240 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH 241 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH 242 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 243 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 244 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 245 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 246 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 247 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 248 interrupt-names = "error", 249 "ch0", "ch1", "ch2", "ch3", 250 "ch4", "ch5", "ch6", "ch7"; 251 clocks = <&cpg CPG_MOD 219>; 252 clock-names = "fck"; 253 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 254 resets = <&cpg 219>; 255 #dma-cells = <1>; 256 dma-channels = <8>; 257 }; 258 259 dmac1: dma-controller@e7300000 { 260 compatible = "renesas,dmac-r8a77995", 261 "renesas,rcar-dmac"; 262 reg = <0 0xe7300000 0 0x10000>; 263 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 264 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 265 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH 266 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 267 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 268 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 269 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 270 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH 271 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>; 272 interrupt-names = "error", 273 "ch0", "ch1", "ch2", "ch3", 274 "ch4", "ch5", "ch6", "ch7"; 275 clocks = <&cpg CPG_MOD 218>; 276 clock-names = "fck"; 277 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 278 resets = <&cpg 218>; 279 #dma-cells = <1>; 280 dma-channels = <8>; 281 }; 282 283 dmac2: dma-controller@e7310000 { 284 compatible = "renesas,dmac-r8a77995", 285 "renesas,rcar-dmac"; 286 reg = <0 0xe7310000 0 0x10000>; 287 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH 288 GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH 289 GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH 290 GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH 291 GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH 292 GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH 293 GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH 294 GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH 295 GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>; 296 interrupt-names = "error", 297 "ch0", "ch1", "ch2", "ch3", 298 "ch4", "ch5", "ch6", "ch7"; 299 clocks = <&cpg CPG_MOD 217>; 300 clock-names = "fck"; 301 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 302 resets = <&cpg 217>; 303 #dma-cells = <1>; 304 dma-channels = <8>; 305 }; 306 307 gpio0: gpio@e6050000 { 308 compatible = "renesas,gpio-r8a77995", 309 "renesas,rcar-gen3-gpio", 310 "renesas,gpio-rcar"; 311 reg = <0 0xe6050000 0 0x50>; 312 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 313 #gpio-cells = <2>; 314 gpio-controller; 315 gpio-ranges = <&pfc 0 0 9>; 316 #interrupt-cells = <2>; 317 interrupt-controller; 318 clocks = <&cpg CPG_MOD 912>; 319 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 320 resets = <&cpg 912>; 321 }; 322 323 gpio1: gpio@e6051000 { 324 compatible = "renesas,gpio-r8a77995", 325 "renesas,rcar-gen3-gpio", 326 "renesas,gpio-rcar"; 327 reg = <0 0xe6051000 0 0x50>; 328 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 329 #gpio-cells = <2>; 330 gpio-controller; 331 gpio-ranges = <&pfc 0 32 32>; 332 #interrupt-cells = <2>; 333 interrupt-controller; 334 clocks = <&cpg CPG_MOD 911>; 335 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 336 resets = <&cpg 911>; 337 }; 338 339 gpio2: gpio@e6052000 { 340 compatible = "renesas,gpio-r8a77995", 341 "renesas,rcar-gen3-gpio", 342 "renesas,gpio-rcar"; 343 reg = <0 0xe6052000 0 0x50>; 344 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 345 #gpio-cells = <2>; 346 gpio-controller; 347 gpio-ranges = <&pfc 0 64 32>; 348 #interrupt-cells = <2>; 349 interrupt-controller; 350 clocks = <&cpg CPG_MOD 910>; 351 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 352 resets = <&cpg 910>; 353 }; 354 355 gpio3: gpio@e6053000 { 356 compatible = "renesas,gpio-r8a77995", 357 "renesas,rcar-gen3-gpio", 358 "renesas,gpio-rcar"; 359 reg = <0 0xe6053000 0 0x50>; 360 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 361 #gpio-cells = <2>; 362 gpio-controller; 363 gpio-ranges = <&pfc 0 96 10>; 364 #interrupt-cells = <2>; 365 interrupt-controller; 366 clocks = <&cpg CPG_MOD 909>; 367 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 368 resets = <&cpg 909>; 369 }; 370 371 gpio4: gpio@e6054000 { 372 compatible = "renesas,gpio-r8a77995", 373 "renesas,rcar-gen3-gpio", 374 "renesas,gpio-rcar"; 375 reg = <0 0xe6054000 0 0x50>; 376 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 377 #gpio-cells = <2>; 378 gpio-controller; 379 gpio-ranges = <&pfc 0 128 32>; 380 #interrupt-cells = <2>; 381 interrupt-controller; 382 clocks = <&cpg CPG_MOD 908>; 383 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 384 resets = <&cpg 908>; 385 }; 386 387 gpio5: gpio@e6055000 { 388 compatible = "renesas,gpio-r8a77995", 389 "renesas,rcar-gen3-gpio", 390 "renesas,gpio-rcar"; 391 reg = <0 0xe6055000 0 0x50>; 392 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 393 #gpio-cells = <2>; 394 gpio-controller; 395 gpio-ranges = <&pfc 0 160 21>; 396 #interrupt-cells = <2>; 397 interrupt-controller; 398 clocks = <&cpg CPG_MOD 907>; 399 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 400 resets = <&cpg 907>; 401 }; 402 403 gpio6: gpio@e6055400 { 404 compatible = "renesas,gpio-r8a77995", 405 "renesas,rcar-gen3-gpio", 406 "renesas,gpio-rcar"; 407 reg = <0 0xe6055400 0 0x50>; 408 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 409 #gpio-cells = <2>; 410 gpio-controller; 411 gpio-ranges = <&pfc 0 192 14>; 412 #interrupt-cells = <2>; 413 interrupt-controller; 414 clocks = <&cpg CPG_MOD 906>; 415 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 416 resets = <&cpg 906>; 417 }; 418 419 can0: can@e6c30000 { 420 compatible = "renesas,can-r8a77995", 421 "renesas,rcar-gen3-can"; 422 reg = <0 0xe6c30000 0 0x1000>; 423 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 424 clocks = <&cpg CPG_MOD 916>, 425 <&cpg CPG_CORE R8A77995_CLK_CANFD>, 426 <&can_clk>; 427 clock-names = "clkp1", "clkp2", "can_clk"; 428 assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>; 429 assigned-clock-rates = <40000000>; 430 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 431 resets = <&cpg 916>; 432 status = "disabled"; 433 }; 434 435 can1: can@e6c38000 { 436 compatible = "renesas,can-r8a77995", 437 "renesas,rcar-gen3-can"; 438 reg = <0 0xe6c38000 0 0x1000>; 439 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 440 clocks = <&cpg CPG_MOD 915>, 441 <&cpg CPG_CORE R8A77995_CLK_CANFD>, 442 <&can_clk>; 443 clock-names = "clkp1", "clkp2", "can_clk"; 444 assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>; 445 assigned-clock-rates = <40000000>; 446 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 447 resets = <&cpg 915>; 448 status = "disabled"; 449 }; 450 451 canfd: can@e66c0000 { 452 compatible = "renesas,r8a77995-canfd", 453 "renesas,rcar-gen3-canfd"; 454 reg = <0 0xe66c0000 0 0x8000>; 455 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 456 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 457 clocks = <&cpg CPG_MOD 914>, 458 <&cpg CPG_CORE R8A77995_CLK_CANFD>, 459 <&can_clk>; 460 clock-names = "fck", "canfd", "can_clk"; 461 assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>; 462 assigned-clock-rates = <40000000>; 463 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 464 resets = <&cpg 914>; 465 status = "disabled"; 466 467 channel0 { 468 status = "disabled"; 469 }; 470 471 channel1 { 472 status = "disabled"; 473 }; 474 }; 475 476 avb: ethernet@e6800000 { 477 compatible = "renesas,etheravb-r8a77995", 478 "renesas,etheravb-rcar-gen3"; 479 reg = <0 0xe6800000 0 0x800>; 480 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 481 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 482 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 483 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 484 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 485 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 486 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 487 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 488 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 489 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 490 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 491 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 492 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 493 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 494 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 495 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 496 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 497 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 498 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 499 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 500 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 501 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 502 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 503 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 504 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 505 interrupt-names = "ch0", "ch1", "ch2", "ch3", 506 "ch4", "ch5", "ch6", "ch7", 507 "ch8", "ch9", "ch10", "ch11", 508 "ch12", "ch13", "ch14", "ch15", 509 "ch16", "ch17", "ch18", "ch19", 510 "ch20", "ch21", "ch22", "ch23", 511 "ch24"; 512 clocks = <&cpg CPG_MOD 812>; 513 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 514 resets = <&cpg 812>; 515 phy-mode = "rgmii"; 516 iommus = <&ipmmu_ds0 16>; 517 #address-cells = <1>; 518 #size-cells = <0>; 519 status = "disabled"; 520 }; 521 522 scif2: serial@e6e88000 { 523 compatible = "renesas,scif-r8a77995", 524 "renesas,rcar-gen3-scif", "renesas,scif"; 525 reg = <0 0xe6e88000 0 64>; 526 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 527 clocks = <&cpg CPG_MOD 310>, 528 <&cpg CPG_CORE R8A77995_CLK_S3D1C>, 529 <&scif_clk>; 530 clock-names = "fck", "brg_int", "scif_clk"; 531 dmas = <&dmac1 0x13>, <&dmac1 0x12>, 532 <&dmac2 0x13>, <&dmac2 0x12>; 533 dma-names = "tx", "rx", "tx", "rx"; 534 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 535 resets = <&cpg 310>; 536 status = "disabled"; 537 }; 538 539 i2c0: i2c@e6500000 { 540 #address-cells = <1>; 541 #size-cells = <0>; 542 compatible = "renesas,i2c-r8a77995", 543 "renesas,rcar-gen3-i2c"; 544 reg = <0 0xe6500000 0 0x40>; 545 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 546 clocks = <&cpg CPG_MOD 931>; 547 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 548 resets = <&cpg 931>; 549 dmas = <&dmac1 0x91>, <&dmac1 0x90>, 550 <&dmac2 0x91>, <&dmac2 0x90>; 551 dma-names = "tx", "rx", "tx", "rx"; 552 i2c-scl-internal-delay-ns = <6>; 553 status = "disabled"; 554 }; 555 556 i2c1: i2c@e6508000 { 557 #address-cells = <1>; 558 #size-cells = <0>; 559 compatible = "renesas,i2c-r8a77995", 560 "renesas,rcar-gen3-i2c"; 561 reg = <0 0xe6508000 0 0x40>; 562 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 563 clocks = <&cpg CPG_MOD 930>; 564 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 565 resets = <&cpg 930>; 566 dmas = <&dmac1 0x93>, <&dmac1 0x92>, 567 <&dmac2 0x93>, <&dmac2 0x92>; 568 dma-names = "tx", "rx", "tx", "rx"; 569 i2c-scl-internal-delay-ns = <6>; 570 status = "disabled"; 571 }; 572 573 i2c2: i2c@e6510000 { 574 #address-cells = <1>; 575 #size-cells = <0>; 576 compatible = "renesas,i2c-r8a77995", 577 "renesas,rcar-gen3-i2c"; 578 reg = <0 0xe6510000 0 0x40>; 579 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 580 clocks = <&cpg CPG_MOD 929>; 581 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 582 resets = <&cpg 929>; 583 dmas = <&dmac1 0x95>, <&dmac1 0x94>, 584 <&dmac2 0x95>, <&dmac2 0x94>; 585 dma-names = "tx", "rx", "tx", "rx"; 586 i2c-scl-internal-delay-ns = <6>; 587 status = "disabled"; 588 }; 589 590 i2c3: i2c@e66d0000 { 591 #address-cells = <1>; 592 #size-cells = <0>; 593 compatible = "renesas,i2c-r8a77995", 594 "renesas,rcar-gen3-i2c"; 595 reg = <0 0xe66d0000 0 0x40>; 596 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 597 clocks = <&cpg CPG_MOD 928>; 598 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 599 resets = <&cpg 928>; 600 dmas = <&dmac0 0x97>, <&dmac0 0x96>; 601 dma-names = "tx", "rx"; 602 i2c-scl-internal-delay-ns = <6>; 603 status = "disabled"; 604 }; 605 606 pwm0: pwm@e6e30000 { 607 compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar"; 608 reg = <0 0xe6e30000 0 0x8>; 609 #pwm-cells = <2>; 610 clocks = <&cpg CPG_MOD 523>; 611 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 612 resets = <&cpg 523>; 613 status = "disabled"; 614 }; 615 616 pwm1: pwm@e6e31000 { 617 compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar"; 618 reg = <0 0xe6e31000 0 0x8>; 619 #pwm-cells = <2>; 620 clocks = <&cpg CPG_MOD 523>; 621 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 622 resets = <&cpg 523>; 623 status = "disabled"; 624 }; 625 626 pwm2: pwm@e6e32000 { 627 compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar"; 628 reg = <0 0xe6e32000 0 0x8>; 629 #pwm-cells = <2>; 630 clocks = <&cpg CPG_MOD 523>; 631 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 632 resets = <&cpg 523>; 633 status = "disabled"; 634 }; 635 636 pwm3: pwm@e6e33000 { 637 compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar"; 638 reg = <0 0xe6e33000 0 0x8>; 639 #pwm-cells = <2>; 640 clocks = <&cpg CPG_MOD 523>; 641 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 642 resets = <&cpg 523>; 643 status = "disabled"; 644 }; 645 646 sdhi2: sd@ee140000 { 647 compatible = "renesas,sdhi-r8a77995", 648 "renesas,rcar-gen3-sdhi"; 649 reg = <0 0xee140000 0 0x2000>; 650 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 651 clocks = <&cpg CPG_MOD 312>; 652 max-frequency = <200000000>; 653 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 654 resets = <&cpg 312>; 655 status = "disabled"; 656 }; 657 658 ehci0: usb@ee080100 { 659 compatible = "generic-ehci"; 660 reg = <0 0xee080100 0 0x100>; 661 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 662 clocks = <&cpg CPG_MOD 703>; 663 phys = <&usb2_phy0>; 664 phy-names = "usb"; 665 companion = <&ohci0>; 666 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 667 resets = <&cpg 703>; 668 status = "disabled"; 669 }; 670 671 ohci0: usb@ee080000 { 672 compatible = "generic-ohci"; 673 reg = <0 0xee080000 0 0x100>; 674 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 675 clocks = <&cpg CPG_MOD 703>; 676 phys = <&usb2_phy0>; 677 phy-names = "usb"; 678 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 679 resets = <&cpg 703>; 680 status = "disabled"; 681 }; 682 683 usb2_phy0: usb-phy@ee080200 { 684 compatible = "renesas,usb2-phy-r8a77995", 685 "renesas,rcar-gen3-usb2-phy"; 686 reg = <0 0xee080200 0 0x700>; 687 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 688 clocks = <&cpg CPG_MOD 703>; 689 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 690 resets = <&cpg 703>; 691 #phy-cells = <0>; 692 status = "disabled"; 693 }; 694 695 vspbs: vsp@fe960000 { 696 compatible = "renesas,vsp2"; 697 reg = <0 0xfe960000 0 0x8000>; 698 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; 699 clocks = <&cpg CPG_MOD 627>; 700 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 701 resets = <&cpg 627>; 702 renesas,fcp = <&fcpvb0>; 703 }; 704 705 fcpvb0: fcp@fe96f000 { 706 compatible = "renesas,fcpv"; 707 reg = <0 0xfe96f000 0 0x200>; 708 clocks = <&cpg CPG_MOD 607>; 709 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 710 resets = <&cpg 607>; 711 iommus = <&ipmmu_vp0 5>; 712 }; 713 714 vspd0: vsp@fea20000 { 715 compatible = "renesas,vsp2"; 716 reg = <0 0xfea20000 0 0x8000>; 717 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 718 clocks = <&cpg CPG_MOD 623>; 719 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 720 resets = <&cpg 623>; 721 renesas,fcp = <&fcpvd0>; 722 }; 723 724 fcpvd0: fcp@fea27000 { 725 compatible = "renesas,fcpv"; 726 reg = <0 0xfea27000 0 0x200>; 727 clocks = <&cpg CPG_MOD 603>; 728 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 729 resets = <&cpg 603>; 730 iommus = <&ipmmu_vi0 8>; 731 }; 732 733 vspd1: vsp@fea28000 { 734 compatible = "renesas,vsp2"; 735 reg = <0 0xfea28000 0 0x8000>; 736 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 737 clocks = <&cpg CPG_MOD 622>; 738 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 739 resets = <&cpg 622>; 740 renesas,fcp = <&fcpvd1>; 741 }; 742 743 fcpvd1: fcp@fea2f000 { 744 compatible = "renesas,fcpv"; 745 reg = <0 0xfea2f000 0 0x200>; 746 clocks = <&cpg CPG_MOD 602>; 747 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 748 resets = <&cpg 602>; 749 iommus = <&ipmmu_vi0 9>; 750 }; 751 752 du: display@feb00000 { 753 compatible = "renesas,du-r8a77995"; 754 reg = <0 0xfeb00000 0 0x80000>; 755 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 756 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 757 clocks = <&cpg CPG_MOD 724>, 758 <&cpg CPG_MOD 723>; 759 clock-names = "du.0", "du.1"; 760 vsps = <&vspd0 0 &vspd1 0>; 761 status = "disabled"; 762 763 ports { 764 #address-cells = <1>; 765 #size-cells = <0>; 766 767 port@0 { 768 reg = <0>; 769 du_out_rgb: endpoint { 770 }; 771 }; 772 773 port@1 { 774 reg = <1>; 775 du_out_lvds0: endpoint { 776 }; 777 }; 778 779 port@2 { 780 reg = <2>; 781 du_out_lvds1: endpoint { 782 }; 783 }; 784 }; 785 }; 786 }; 787 788 timer { 789 compatible = "arm,armv8-timer"; 790 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 791 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 792 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 793 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 794 }; 795}; 796