1 /* 2 * Driver for Analog Devices ADV748X HDMI receiver and Component Processor (CP) 3 * 4 * Copyright (C) 2017 Renesas Electronics Corp. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/mutex.h> 14 15 #include <media/v4l2-ctrls.h> 16 #include <media/v4l2-device.h> 17 #include <media/v4l2-dv-timings.h> 18 #include <media/v4l2-ioctl.h> 19 20 #include <uapi/linux/v4l2-dv-timings.h> 21 22 #include "adv748x.h" 23 24 /* ----------------------------------------------------------------------------- 25 * HDMI and CP 26 */ 27 28 #define ADV748X_HDMI_MIN_WIDTH 640 29 #define ADV748X_HDMI_MAX_WIDTH 1920 30 #define ADV748X_HDMI_MIN_HEIGHT 480 31 #define ADV748X_HDMI_MAX_HEIGHT 1200 32 33 /* V4L2_DV_BT_CEA_720X480I59_94 - 0.5 MHz */ 34 #define ADV748X_HDMI_MIN_PIXELCLOCK 13000000 35 /* V4L2_DV_BT_DMT_1600X1200P60 */ 36 #define ADV748X_HDMI_MAX_PIXELCLOCK 162000000 37 38 static const struct v4l2_dv_timings_cap adv748x_hdmi_timings_cap = { 39 .type = V4L2_DV_BT_656_1120, 40 /* keep this initialization for compatibility with GCC < 4.4.6 */ 41 .reserved = { 0 }, 42 43 V4L2_INIT_BT_TIMINGS(ADV748X_HDMI_MIN_WIDTH, ADV748X_HDMI_MAX_WIDTH, 44 ADV748X_HDMI_MIN_HEIGHT, ADV748X_HDMI_MAX_HEIGHT, 45 ADV748X_HDMI_MIN_PIXELCLOCK, 46 ADV748X_HDMI_MAX_PIXELCLOCK, 47 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT, 48 V4L2_DV_BT_CAP_PROGRESSIVE) 49 }; 50 51 struct adv748x_hdmi_video_standards { 52 struct v4l2_dv_timings timings; 53 u8 vid_std; 54 u8 v_freq; 55 }; 56 57 static const struct adv748x_hdmi_video_standards 58 adv748x_hdmi_video_standards[] = { 59 { V4L2_DV_BT_CEA_720X480P59_94, 0x4a, 0x00 }, 60 { V4L2_DV_BT_CEA_720X576P50, 0x4b, 0x00 }, 61 { V4L2_DV_BT_CEA_1280X720P60, 0x53, 0x00 }, 62 { V4L2_DV_BT_CEA_1280X720P50, 0x53, 0x01 }, 63 { V4L2_DV_BT_CEA_1280X720P30, 0x53, 0x02 }, 64 { V4L2_DV_BT_CEA_1280X720P25, 0x53, 0x03 }, 65 { V4L2_DV_BT_CEA_1280X720P24, 0x53, 0x04 }, 66 { V4L2_DV_BT_CEA_1920X1080P60, 0x5e, 0x00 }, 67 { V4L2_DV_BT_CEA_1920X1080P50, 0x5e, 0x01 }, 68 { V4L2_DV_BT_CEA_1920X1080P30, 0x5e, 0x02 }, 69 { V4L2_DV_BT_CEA_1920X1080P25, 0x5e, 0x03 }, 70 { V4L2_DV_BT_CEA_1920X1080P24, 0x5e, 0x04 }, 71 /* SVGA */ 72 { V4L2_DV_BT_DMT_800X600P56, 0x80, 0x00 }, 73 { V4L2_DV_BT_DMT_800X600P60, 0x81, 0x00 }, 74 { V4L2_DV_BT_DMT_800X600P72, 0x82, 0x00 }, 75 { V4L2_DV_BT_DMT_800X600P75, 0x83, 0x00 }, 76 { V4L2_DV_BT_DMT_800X600P85, 0x84, 0x00 }, 77 /* SXGA */ 78 { V4L2_DV_BT_DMT_1280X1024P60, 0x85, 0x00 }, 79 { V4L2_DV_BT_DMT_1280X1024P75, 0x86, 0x00 }, 80 /* VGA */ 81 { V4L2_DV_BT_DMT_640X480P60, 0x88, 0x00 }, 82 { V4L2_DV_BT_DMT_640X480P72, 0x89, 0x00 }, 83 { V4L2_DV_BT_DMT_640X480P75, 0x8a, 0x00 }, 84 { V4L2_DV_BT_DMT_640X480P85, 0x8b, 0x00 }, 85 /* XGA */ 86 { V4L2_DV_BT_DMT_1024X768P60, 0x8c, 0x00 }, 87 { V4L2_DV_BT_DMT_1024X768P70, 0x8d, 0x00 }, 88 { V4L2_DV_BT_DMT_1024X768P75, 0x8e, 0x00 }, 89 { V4L2_DV_BT_DMT_1024X768P85, 0x8f, 0x00 }, 90 /* UXGA */ 91 { V4L2_DV_BT_DMT_1600X1200P60, 0x96, 0x00 }, 92 }; 93 94 static void adv748x_hdmi_fill_format(struct adv748x_hdmi *hdmi, 95 struct v4l2_mbus_framefmt *fmt) 96 { 97 memset(fmt, 0, sizeof(*fmt)); 98 99 fmt->code = MEDIA_BUS_FMT_RGB888_1X24; 100 fmt->field = hdmi->timings.bt.interlaced ? 101 V4L2_FIELD_ALTERNATE : V4L2_FIELD_NONE; 102 103 /* TODO: The colorspace depends on the AVI InfoFrame contents */ 104 fmt->colorspace = V4L2_COLORSPACE_SRGB; 105 106 fmt->width = hdmi->timings.bt.width; 107 fmt->height = hdmi->timings.bt.height; 108 109 if (fmt->field == V4L2_FIELD_ALTERNATE) 110 fmt->height /= 2; 111 } 112 113 static void adv748x_fill_optional_dv_timings(struct v4l2_dv_timings *timings) 114 { 115 v4l2_find_dv_timings_cap(timings, &adv748x_hdmi_timings_cap, 116 250000, NULL, NULL); 117 } 118 119 static bool adv748x_hdmi_has_signal(struct adv748x_state *state) 120 { 121 int val; 122 123 /* Check that VERT_FILTER and DE_REGEN is locked */ 124 val = hdmi_read(state, ADV748X_HDMI_LW1); 125 return (val & ADV748X_HDMI_LW1_VERT_FILTER) && 126 (val & ADV748X_HDMI_LW1_DE_REGEN); 127 } 128 129 static int adv748x_hdmi_read_pixelclock(struct adv748x_state *state) 130 { 131 int a, b; 132 133 a = hdmi_read(state, ADV748X_HDMI_TMDS_1); 134 b = hdmi_read(state, ADV748X_HDMI_TMDS_2); 135 if (a < 0 || b < 0) 136 return -ENODATA; 137 138 /* 139 * The high 9 bits store TMDS frequency measurement in MHz 140 * The low 7 bits of TMDS_2 store the 7-bit TMDS fractional frequency 141 * measurement in 1/128 MHz 142 */ 143 return ((a << 1) | (b >> 7)) * 1000000 + (b & 0x7f) * 1000000 / 128; 144 } 145 146 /* 147 * adv748x_hdmi_set_de_timings: Adjust horizontal picture offset through DE 148 * 149 * HDMI CP uses a Data Enable synchronisation timing reference 150 * 151 * Vary the leading and trailing edge position of the DE signal output by the CP 152 * core. Values are stored as signed-twos-complement in one-pixel-clock units 153 * 154 * The start and end are shifted equally by the 10-bit shift value. 155 */ 156 static void adv748x_hdmi_set_de_timings(struct adv748x_state *state, int shift) 157 { 158 u8 high, low; 159 160 /* POS_HIGH stores bits 8 and 9 of both the start and end */ 161 high = ADV748X_CP_DE_POS_HIGH_SET; 162 high |= (shift & 0x300) >> 8; 163 low = shift & 0xff; 164 165 /* The sequence of the writes is important and must be followed */ 166 cp_write(state, ADV748X_CP_DE_POS_HIGH, high); 167 cp_write(state, ADV748X_CP_DE_POS_END_LOW, low); 168 169 high |= (shift & 0x300) >> 6; 170 171 cp_write(state, ADV748X_CP_DE_POS_HIGH, high); 172 cp_write(state, ADV748X_CP_DE_POS_START_LOW, low); 173 } 174 175 static int adv748x_hdmi_set_video_timings(struct adv748x_state *state, 176 const struct v4l2_dv_timings *timings) 177 { 178 const struct adv748x_hdmi_video_standards *stds = 179 adv748x_hdmi_video_standards; 180 unsigned int i; 181 182 for (i = 0; i < ARRAY_SIZE(adv748x_hdmi_video_standards); i++) { 183 if (!v4l2_match_dv_timings(timings, &stds[i].timings, 250000, 184 false)) 185 continue; 186 } 187 188 if (i >= ARRAY_SIZE(adv748x_hdmi_video_standards)) 189 return -EINVAL; 190 191 /* 192 * When setting cp_vid_std to either 720p, 1080i, or 1080p, the video 193 * will get shifted horizontally to the left in active video mode. 194 * The de_h_start and de_h_end controls are used to centre the picture 195 * correctly 196 */ 197 switch (stds[i].vid_std) { 198 case 0x53: /* 720p */ 199 adv748x_hdmi_set_de_timings(state, -40); 200 break; 201 case 0x54: /* 1080i */ 202 case 0x5e: /* 1080p */ 203 adv748x_hdmi_set_de_timings(state, -44); 204 break; 205 default: 206 adv748x_hdmi_set_de_timings(state, 0); 207 break; 208 } 209 210 io_write(state, ADV748X_IO_VID_STD, stds[i].vid_std); 211 io_clrset(state, ADV748X_IO_DATAPATH, ADV748X_IO_DATAPATH_VFREQ_M, 212 stds[i].v_freq << ADV748X_IO_DATAPATH_VFREQ_SHIFT); 213 214 return 0; 215 } 216 217 /* ----------------------------------------------------------------------------- 218 * v4l2_subdev_video_ops 219 */ 220 221 static int adv748x_hdmi_s_dv_timings(struct v4l2_subdev *sd, 222 struct v4l2_dv_timings *timings) 223 { 224 struct adv748x_hdmi *hdmi = adv748x_sd_to_hdmi(sd); 225 struct adv748x_state *state = adv748x_hdmi_to_state(hdmi); 226 int ret; 227 228 if (!timings) 229 return -EINVAL; 230 231 if (v4l2_match_dv_timings(&hdmi->timings, timings, 0, false)) 232 return 0; 233 234 if (!v4l2_valid_dv_timings(timings, &adv748x_hdmi_timings_cap, 235 NULL, NULL)) 236 return -ERANGE; 237 238 adv748x_fill_optional_dv_timings(timings); 239 240 mutex_lock(&state->mutex); 241 242 ret = adv748x_hdmi_set_video_timings(state, timings); 243 if (ret) 244 goto error; 245 246 hdmi->timings = *timings; 247 248 cp_clrset(state, ADV748X_CP_VID_ADJ_2, ADV748X_CP_VID_ADJ_2_INTERLACED, 249 timings->bt.interlaced ? 250 ADV748X_CP_VID_ADJ_2_INTERLACED : 0); 251 252 mutex_unlock(&state->mutex); 253 254 return 0; 255 256 error: 257 mutex_unlock(&state->mutex); 258 return ret; 259 } 260 261 static int adv748x_hdmi_g_dv_timings(struct v4l2_subdev *sd, 262 struct v4l2_dv_timings *timings) 263 { 264 struct adv748x_hdmi *hdmi = adv748x_sd_to_hdmi(sd); 265 struct adv748x_state *state = adv748x_hdmi_to_state(hdmi); 266 267 mutex_lock(&state->mutex); 268 269 *timings = hdmi->timings; 270 271 mutex_unlock(&state->mutex); 272 273 return 0; 274 } 275 276 static int adv748x_hdmi_query_dv_timings(struct v4l2_subdev *sd, 277 struct v4l2_dv_timings *timings) 278 { 279 struct adv748x_hdmi *hdmi = adv748x_sd_to_hdmi(sd); 280 struct adv748x_state *state = adv748x_hdmi_to_state(hdmi); 281 struct v4l2_bt_timings *bt = &timings->bt; 282 int pixelclock; 283 int polarity; 284 285 if (!timings) 286 return -EINVAL; 287 288 memset(timings, 0, sizeof(struct v4l2_dv_timings)); 289 290 if (!adv748x_hdmi_has_signal(state)) 291 return -ENOLINK; 292 293 pixelclock = adv748x_hdmi_read_pixelclock(state); 294 if (pixelclock < 0) 295 return -ENODATA; 296 297 timings->type = V4L2_DV_BT_656_1120; 298 299 bt->pixelclock = pixelclock; 300 bt->interlaced = hdmi_read(state, ADV748X_HDMI_F1H1) & 301 ADV748X_HDMI_F1H1_INTERLACED ? 302 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE; 303 bt->width = hdmi_read16(state, ADV748X_HDMI_LW1, 304 ADV748X_HDMI_LW1_WIDTH_MASK); 305 bt->height = hdmi_read16(state, ADV748X_HDMI_F0H1, 306 ADV748X_HDMI_F0H1_HEIGHT_MASK); 307 bt->hfrontporch = hdmi_read16(state, ADV748X_HDMI_HFRONT_PORCH, 308 ADV748X_HDMI_HFRONT_PORCH_MASK); 309 bt->hsync = hdmi_read16(state, ADV748X_HDMI_HSYNC_WIDTH, 310 ADV748X_HDMI_HSYNC_WIDTH_MASK); 311 bt->hbackporch = hdmi_read16(state, ADV748X_HDMI_HBACK_PORCH, 312 ADV748X_HDMI_HBACK_PORCH_MASK); 313 bt->vfrontporch = hdmi_read16(state, ADV748X_HDMI_VFRONT_PORCH, 314 ADV748X_HDMI_VFRONT_PORCH_MASK) / 2; 315 bt->vsync = hdmi_read16(state, ADV748X_HDMI_VSYNC_WIDTH, 316 ADV748X_HDMI_VSYNC_WIDTH_MASK) / 2; 317 bt->vbackporch = hdmi_read16(state, ADV748X_HDMI_VBACK_PORCH, 318 ADV748X_HDMI_VBACK_PORCH_MASK) / 2; 319 320 polarity = hdmi_read(state, 0x05); 321 bt->polarities = (polarity & BIT(4) ? V4L2_DV_VSYNC_POS_POL : 0) | 322 (polarity & BIT(5) ? V4L2_DV_HSYNC_POS_POL : 0); 323 324 if (bt->interlaced == V4L2_DV_INTERLACED) { 325 bt->height += hdmi_read16(state, 0x0b, 0x1fff); 326 bt->il_vfrontporch = hdmi_read16(state, 0x2c, 0x3fff) / 2; 327 bt->il_vsync = hdmi_read16(state, 0x30, 0x3fff) / 2; 328 bt->il_vbackporch = hdmi_read16(state, 0x34, 0x3fff) / 2; 329 } 330 331 adv748x_fill_optional_dv_timings(timings); 332 333 /* 334 * No interrupt handling is implemented yet. 335 * There should be an IRQ when a cable is plugged and the new timings 336 * should be figured out and stored to state. 337 */ 338 hdmi->timings = *timings; 339 340 return 0; 341 } 342 343 static int adv748x_hdmi_g_input_status(struct v4l2_subdev *sd, u32 *status) 344 { 345 struct adv748x_hdmi *hdmi = adv748x_sd_to_hdmi(sd); 346 struct adv748x_state *state = adv748x_hdmi_to_state(hdmi); 347 348 mutex_lock(&state->mutex); 349 350 *status = adv748x_hdmi_has_signal(state) ? 0 : V4L2_IN_ST_NO_SIGNAL; 351 352 mutex_unlock(&state->mutex); 353 354 return 0; 355 } 356 357 static int adv748x_hdmi_s_stream(struct v4l2_subdev *sd, int enable) 358 { 359 struct adv748x_hdmi *hdmi = adv748x_sd_to_hdmi(sd); 360 struct adv748x_state *state = adv748x_hdmi_to_state(hdmi); 361 int ret; 362 363 mutex_lock(&state->mutex); 364 365 ret = adv748x_txa_power(state, enable); 366 if (ret) 367 goto done; 368 369 if (adv748x_hdmi_has_signal(state)) 370 adv_dbg(state, "Detected HDMI signal\n"); 371 else 372 adv_dbg(state, "Couldn't detect HDMI video signal\n"); 373 374 done: 375 mutex_unlock(&state->mutex); 376 return ret; 377 } 378 379 static int adv748x_hdmi_g_pixelaspect(struct v4l2_subdev *sd, 380 struct v4l2_fract *aspect) 381 { 382 aspect->numerator = 1; 383 aspect->denominator = 1; 384 385 return 0; 386 } 387 388 static const struct v4l2_subdev_video_ops adv748x_video_ops_hdmi = { 389 .s_dv_timings = adv748x_hdmi_s_dv_timings, 390 .g_dv_timings = adv748x_hdmi_g_dv_timings, 391 .query_dv_timings = adv748x_hdmi_query_dv_timings, 392 .g_input_status = adv748x_hdmi_g_input_status, 393 .s_stream = adv748x_hdmi_s_stream, 394 .g_pixelaspect = adv748x_hdmi_g_pixelaspect, 395 }; 396 397 /* ----------------------------------------------------------------------------- 398 * v4l2_subdev_pad_ops 399 */ 400 401 static int adv748x_hdmi_propagate_pixelrate(struct adv748x_hdmi *hdmi) 402 { 403 struct v4l2_subdev *tx; 404 struct v4l2_dv_timings timings; 405 struct v4l2_bt_timings *bt = &timings.bt; 406 unsigned int fps; 407 408 tx = adv748x_get_remote_sd(&hdmi->pads[ADV748X_HDMI_SOURCE]); 409 if (!tx) 410 return -ENOLINK; 411 412 adv748x_hdmi_query_dv_timings(&hdmi->sd, &timings); 413 414 fps = DIV_ROUND_CLOSEST_ULL(bt->pixelclock, 415 V4L2_DV_BT_FRAME_WIDTH(bt) * 416 V4L2_DV_BT_FRAME_HEIGHT(bt)); 417 418 return adv748x_csi2_set_pixelrate(tx, bt->width * bt->height * fps); 419 } 420 421 static int adv748x_hdmi_enum_mbus_code(struct v4l2_subdev *sd, 422 struct v4l2_subdev_pad_config *cfg, 423 struct v4l2_subdev_mbus_code_enum *code) 424 { 425 if (code->index != 0) 426 return -EINVAL; 427 428 code->code = MEDIA_BUS_FMT_RGB888_1X24; 429 430 return 0; 431 } 432 433 static int adv748x_hdmi_get_format(struct v4l2_subdev *sd, 434 struct v4l2_subdev_pad_config *cfg, 435 struct v4l2_subdev_format *sdformat) 436 { 437 struct adv748x_hdmi *hdmi = adv748x_sd_to_hdmi(sd); 438 struct v4l2_mbus_framefmt *mbusformat; 439 440 if (sdformat->pad != ADV748X_HDMI_SOURCE) 441 return -EINVAL; 442 443 if (sdformat->which == V4L2_SUBDEV_FORMAT_TRY) { 444 mbusformat = v4l2_subdev_get_try_format(sd, cfg, sdformat->pad); 445 sdformat->format = *mbusformat; 446 } else { 447 adv748x_hdmi_fill_format(hdmi, &sdformat->format); 448 adv748x_hdmi_propagate_pixelrate(hdmi); 449 } 450 451 return 0; 452 } 453 454 static int adv748x_hdmi_set_format(struct v4l2_subdev *sd, 455 struct v4l2_subdev_pad_config *cfg, 456 struct v4l2_subdev_format *sdformat) 457 { 458 struct v4l2_mbus_framefmt *mbusformat; 459 460 if (sdformat->pad != ADV748X_HDMI_SOURCE) 461 return -EINVAL; 462 463 if (sdformat->which == V4L2_SUBDEV_FORMAT_ACTIVE) 464 return adv748x_hdmi_get_format(sd, cfg, sdformat); 465 466 mbusformat = v4l2_subdev_get_try_format(sd, cfg, sdformat->pad); 467 *mbusformat = sdformat->format; 468 469 return 0; 470 } 471 472 static int adv748x_hdmi_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid) 473 { 474 struct adv748x_hdmi *hdmi = adv748x_sd_to_hdmi(sd); 475 476 memset(edid->reserved, 0, sizeof(edid->reserved)); 477 478 if (!hdmi->edid.present) 479 return -ENODATA; 480 481 if (edid->start_block == 0 && edid->blocks == 0) { 482 edid->blocks = hdmi->edid.blocks; 483 return 0; 484 } 485 486 if (edid->start_block >= hdmi->edid.blocks) 487 return -EINVAL; 488 489 if (edid->start_block + edid->blocks > hdmi->edid.blocks) 490 edid->blocks = hdmi->edid.blocks - edid->start_block; 491 492 memcpy(edid->edid, hdmi->edid.edid + edid->start_block * 128, 493 edid->blocks * 128); 494 495 return 0; 496 } 497 498 static inline int adv748x_hdmi_edid_write_block(struct adv748x_hdmi *hdmi, 499 unsigned int total_len, const u8 *val) 500 { 501 struct adv748x_state *state = adv748x_hdmi_to_state(hdmi); 502 int err = 0; 503 int i = 0; 504 int len = 0; 505 506 adv_dbg(state, "%s: write EDID block (%d byte)\n", 507 __func__, total_len); 508 509 while (!err && i < total_len) { 510 len = (total_len - i) > I2C_SMBUS_BLOCK_MAX ? 511 I2C_SMBUS_BLOCK_MAX : 512 (total_len - i); 513 514 err = adv748x_write_block(state, ADV748X_PAGE_EDID, 515 i, val + i, len); 516 i += len; 517 } 518 519 return err; 520 } 521 522 static int adv748x_hdmi_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid) 523 { 524 struct adv748x_hdmi *hdmi = adv748x_sd_to_hdmi(sd); 525 struct adv748x_state *state = adv748x_hdmi_to_state(hdmi); 526 int err; 527 528 memset(edid->reserved, 0, sizeof(edid->reserved)); 529 530 if (edid->start_block != 0) 531 return -EINVAL; 532 533 if (edid->blocks == 0) { 534 hdmi->edid.blocks = 0; 535 hdmi->edid.present = 0; 536 537 /* Fall back to a 16:9 aspect ratio */ 538 hdmi->aspect_ratio.numerator = 16; 539 hdmi->aspect_ratio.denominator = 9; 540 541 /* Disable the EDID */ 542 repeater_write(state, ADV748X_REPEATER_EDID_SZ, 543 edid->blocks << ADV748X_REPEATER_EDID_SZ_SHIFT); 544 545 repeater_write(state, ADV748X_REPEATER_EDID_CTL, 0); 546 547 return 0; 548 } 549 550 if (edid->blocks > 4) { 551 edid->blocks = 4; 552 return -E2BIG; 553 } 554 555 memcpy(hdmi->edid.edid, edid->edid, 128 * edid->blocks); 556 hdmi->edid.blocks = edid->blocks; 557 hdmi->edid.present = true; 558 559 hdmi->aspect_ratio = v4l2_calc_aspect_ratio(edid->edid[0x15], 560 edid->edid[0x16]); 561 562 err = adv748x_hdmi_edid_write_block(hdmi, 128 * edid->blocks, 563 hdmi->edid.edid); 564 if (err < 0) { 565 v4l2_err(sd, "error %d writing edid pad %d\n", err, edid->pad); 566 return err; 567 } 568 569 repeater_write(state, ADV748X_REPEATER_EDID_SZ, 570 edid->blocks << ADV748X_REPEATER_EDID_SZ_SHIFT); 571 572 repeater_write(state, ADV748X_REPEATER_EDID_CTL, 573 ADV748X_REPEATER_EDID_CTL_EN); 574 575 return 0; 576 } 577 578 static bool adv748x_hdmi_check_dv_timings(const struct v4l2_dv_timings *timings, 579 void *hdl) 580 { 581 const struct adv748x_hdmi_video_standards *stds = 582 adv748x_hdmi_video_standards; 583 unsigned int i; 584 585 for (i = 0; stds[i].timings.bt.width; i++) 586 if (v4l2_match_dv_timings(timings, &stds[i].timings, 0, false)) 587 return true; 588 589 return false; 590 } 591 592 static int adv748x_hdmi_enum_dv_timings(struct v4l2_subdev *sd, 593 struct v4l2_enum_dv_timings *timings) 594 { 595 return v4l2_enum_dv_timings_cap(timings, &adv748x_hdmi_timings_cap, 596 adv748x_hdmi_check_dv_timings, NULL); 597 } 598 599 static int adv748x_hdmi_dv_timings_cap(struct v4l2_subdev *sd, 600 struct v4l2_dv_timings_cap *cap) 601 { 602 *cap = adv748x_hdmi_timings_cap; 603 return 0; 604 } 605 606 static const struct v4l2_subdev_pad_ops adv748x_pad_ops_hdmi = { 607 .enum_mbus_code = adv748x_hdmi_enum_mbus_code, 608 .set_fmt = adv748x_hdmi_set_format, 609 .get_fmt = adv748x_hdmi_get_format, 610 .get_edid = adv748x_hdmi_get_edid, 611 .set_edid = adv748x_hdmi_set_edid, 612 .dv_timings_cap = adv748x_hdmi_dv_timings_cap, 613 .enum_dv_timings = adv748x_hdmi_enum_dv_timings, 614 }; 615 616 /* ----------------------------------------------------------------------------- 617 * v4l2_subdev_ops 618 */ 619 620 static const struct v4l2_subdev_ops adv748x_ops_hdmi = { 621 .video = &adv748x_video_ops_hdmi, 622 .pad = &adv748x_pad_ops_hdmi, 623 }; 624 625 /* ----------------------------------------------------------------------------- 626 * Controls 627 */ 628 629 static const char * const hdmi_ctrl_patgen_menu[] = { 630 "Disabled", 631 "Solid Color", 632 "Color Bars", 633 "Ramp Grey", 634 "Ramp Blue", 635 "Ramp Red", 636 "Checkered" 637 }; 638 639 static int adv748x_hdmi_s_ctrl(struct v4l2_ctrl *ctrl) 640 { 641 struct adv748x_hdmi *hdmi = adv748x_ctrl_to_hdmi(ctrl); 642 struct adv748x_state *state = adv748x_hdmi_to_state(hdmi); 643 int ret; 644 u8 pattern; 645 646 /* Enable video adjustment first */ 647 ret = cp_clrset(state, ADV748X_CP_VID_ADJ, 648 ADV748X_CP_VID_ADJ_ENABLE, 649 ADV748X_CP_VID_ADJ_ENABLE); 650 if (ret < 0) 651 return ret; 652 653 switch (ctrl->id) { 654 case V4L2_CID_BRIGHTNESS: 655 ret = cp_write(state, ADV748X_CP_BRI, ctrl->val); 656 break; 657 case V4L2_CID_HUE: 658 ret = cp_write(state, ADV748X_CP_HUE, ctrl->val); 659 break; 660 case V4L2_CID_CONTRAST: 661 ret = cp_write(state, ADV748X_CP_CON, ctrl->val); 662 break; 663 case V4L2_CID_SATURATION: 664 ret = cp_write(state, ADV748X_CP_SAT, ctrl->val); 665 break; 666 case V4L2_CID_TEST_PATTERN: 667 pattern = ctrl->val; 668 669 /* Pattern is 0-indexed. Ctrl Menu is 1-indexed */ 670 if (pattern) { 671 pattern--; 672 pattern |= ADV748X_CP_PAT_GEN_EN; 673 } 674 675 ret = cp_write(state, ADV748X_CP_PAT_GEN, pattern); 676 677 break; 678 default: 679 return -EINVAL; 680 } 681 682 return ret; 683 } 684 685 static const struct v4l2_ctrl_ops adv748x_hdmi_ctrl_ops = { 686 .s_ctrl = adv748x_hdmi_s_ctrl, 687 }; 688 689 static int adv748x_hdmi_init_controls(struct adv748x_hdmi *hdmi) 690 { 691 struct adv748x_state *state = adv748x_hdmi_to_state(hdmi); 692 693 v4l2_ctrl_handler_init(&hdmi->ctrl_hdl, 5); 694 695 /* Use our mutex for the controls */ 696 hdmi->ctrl_hdl.lock = &state->mutex; 697 698 v4l2_ctrl_new_std(&hdmi->ctrl_hdl, &adv748x_hdmi_ctrl_ops, 699 V4L2_CID_BRIGHTNESS, ADV748X_CP_BRI_MIN, 700 ADV748X_CP_BRI_MAX, 1, ADV748X_CP_BRI_DEF); 701 v4l2_ctrl_new_std(&hdmi->ctrl_hdl, &adv748x_hdmi_ctrl_ops, 702 V4L2_CID_CONTRAST, ADV748X_CP_CON_MIN, 703 ADV748X_CP_CON_MAX, 1, ADV748X_CP_CON_DEF); 704 v4l2_ctrl_new_std(&hdmi->ctrl_hdl, &adv748x_hdmi_ctrl_ops, 705 V4L2_CID_SATURATION, ADV748X_CP_SAT_MIN, 706 ADV748X_CP_SAT_MAX, 1, ADV748X_CP_SAT_DEF); 707 v4l2_ctrl_new_std(&hdmi->ctrl_hdl, &adv748x_hdmi_ctrl_ops, 708 V4L2_CID_HUE, ADV748X_CP_HUE_MIN, 709 ADV748X_CP_HUE_MAX, 1, ADV748X_CP_HUE_DEF); 710 711 /* 712 * Todo: V4L2_CID_DV_RX_POWER_PRESENT should also be supported when 713 * interrupts are handled correctly 714 */ 715 716 v4l2_ctrl_new_std_menu_items(&hdmi->ctrl_hdl, &adv748x_hdmi_ctrl_ops, 717 V4L2_CID_TEST_PATTERN, 718 ARRAY_SIZE(hdmi_ctrl_patgen_menu) - 1, 719 0, 0, hdmi_ctrl_patgen_menu); 720 721 hdmi->sd.ctrl_handler = &hdmi->ctrl_hdl; 722 if (hdmi->ctrl_hdl.error) { 723 v4l2_ctrl_handler_free(&hdmi->ctrl_hdl); 724 return hdmi->ctrl_hdl.error; 725 } 726 727 return v4l2_ctrl_handler_setup(&hdmi->ctrl_hdl); 728 } 729 730 int adv748x_hdmi_init(struct adv748x_hdmi *hdmi) 731 { 732 struct adv748x_state *state = adv748x_hdmi_to_state(hdmi); 733 static const struct v4l2_dv_timings cea1280x720 = 734 V4L2_DV_BT_CEA_1280X720P30; 735 int ret; 736 737 hdmi->timings = cea1280x720; 738 739 /* Initialise a default 16:9 aspect ratio */ 740 hdmi->aspect_ratio.numerator = 16; 741 hdmi->aspect_ratio.denominator = 9; 742 743 adv748x_subdev_init(&hdmi->sd, state, &adv748x_ops_hdmi, 744 MEDIA_ENT_F_IO_DTV, "hdmi"); 745 746 hdmi->pads[ADV748X_HDMI_SINK].flags = MEDIA_PAD_FL_SINK; 747 hdmi->pads[ADV748X_HDMI_SOURCE].flags = MEDIA_PAD_FL_SOURCE; 748 749 ret = media_entity_pads_init(&hdmi->sd.entity, 750 ADV748X_HDMI_NR_PADS, hdmi->pads); 751 if (ret) 752 return ret; 753 754 ret = adv748x_hdmi_init_controls(hdmi); 755 if (ret) 756 goto err_free_media; 757 758 return 0; 759 760 err_free_media: 761 media_entity_cleanup(&hdmi->sd.entity); 762 763 return ret; 764 } 765 766 void adv748x_hdmi_cleanup(struct adv748x_hdmi *hdmi) 767 { 768 v4l2_device_unregister_subdev(&hdmi->sd); 769 media_entity_cleanup(&hdmi->sd.entity); 770 v4l2_ctrl_handler_free(&hdmi->ctrl_hdl); 771 } 772