1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Intel PRO/1000 Linux driver 3 * Copyright(c) 1999 - 2015 Intel Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in 15 * the file called "COPYING". 16 * 17 * Contact Information: 18 * Linux NICS <linux.nics@intel.com> 19 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 20 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 21 */ 22 23 #ifndef _E1000E_80003ES2LAN_H_ 24 #define _E1000E_80003ES2LAN_H_ 25 26 #define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL 0x00 27 #define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL 0x02 28 #define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL 0x10 29 #define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE 0x1F 30 31 #define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS 0x0008 32 #define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS 0x0800 33 #define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING 0x0010 34 35 #define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004 36 #define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT 0x0000 37 #define E1000_KMRNCTRLSTA_OPMODE_E_IDLE 0x2000 38 39 #define E1000_KMRNCTRLSTA_OPMODE_MASK 0x000C 40 #define E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO 0x0004 41 42 #define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gig Carry Extend Padding */ 43 #define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN 0x00010000 44 45 #define DEFAULT_TIPG_IPGT_1000_80003ES2LAN 0x8 46 #define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN 0x9 47 48 /* GG82563 PHY Specific Status Register (Page 0, Register 16 */ 49 #define GG82563_PSCR_POLARITY_REVERSAL_DISABLE 0x0002 /* 1=Reversal Dis */ 50 #define GG82563_PSCR_CROSSOVER_MODE_MASK 0x0060 51 #define GG82563_PSCR_CROSSOVER_MODE_MDI 0x0000 /* 00=Manual MDI */ 52 #define GG82563_PSCR_CROSSOVER_MODE_MDIX 0x0020 /* 01=Manual MDIX */ 53 #define GG82563_PSCR_CROSSOVER_MODE_AUTO 0x0060 /* 11=Auto crossover */ 54 55 /* PHY Specific Control Register 2 (Page 0, Register 26) */ 56 #define GG82563_PSCR2_REVERSE_AUTO_NEG 0x2000 /* 1=Reverse Auto-Neg */ 57 58 /* MAC Specific Control Register (Page 2, Register 21) */ 59 /* Tx clock speed for Link Down and 1000BASE-T for the following speeds */ 60 #define GG82563_MSCR_TX_CLK_MASK 0x0007 61 #define GG82563_MSCR_TX_CLK_10MBPS_2_5 0x0004 62 #define GG82563_MSCR_TX_CLK_100MBPS_25 0x0005 63 #define GG82563_MSCR_TX_CLK_1000MBPS_25 0x0007 64 65 #define GG82563_MSCR_ASSERT_CRS_ON_TX 0x0010 /* 1=Assert */ 66 67 /* DSP Distance Register (Page 5, Register 26) 68 * 0 = <50M 69 * 1 = 50-80M 70 * 2 = 80-100M 71 * 3 = 110-140M 72 * 4 = >140M 73 */ 74 #define GG82563_DSPD_CABLE_LENGTH 0x0007 75 76 /* Kumeran Mode Control Register (Page 193, Register 16) */ 77 #define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800 78 79 /* Max number of times Kumeran read/write should be validated */ 80 #define GG82563_MAX_KMRN_RETRY 0x5 81 82 /* Power Management Control Register (Page 193, Register 20) */ 83 /* 1=Enable SERDES Electrical Idle */ 84 #define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE 0x0001 85 86 /* In-Band Control Register (Page 194, Register 18) */ 87 #define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding */ 88 89 #endif 90