1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2018, Intel Corporation. */ 3 4 #include "ice_common.h" 5 #include "ice_sched.h" 6 #include "ice_adminq_cmd.h" 7 8 #define ICE_PF_RESET_WAIT_COUNT 200 9 10 #define ICE_NIC_FLX_ENTRY(hw, mdid, idx) \ 11 wr32((hw), GLFLXP_RXDID_FLX_WRD_##idx(ICE_RXDID_FLEX_NIC), \ 12 ((ICE_RX_OPC_MDID << \ 13 GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_S) & \ 14 GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_M) | \ 15 (((mdid) << GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_S) & \ 16 GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_M)) 17 18 #define ICE_NIC_FLX_FLG_ENTRY(hw, flg_0, flg_1, flg_2, flg_3, idx) \ 19 wr32((hw), GLFLXP_RXDID_FLAGS(ICE_RXDID_FLEX_NIC, idx), \ 20 (((flg_0) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S) & \ 21 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_M) | \ 22 (((flg_1) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_S) & \ 23 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_M) | \ 24 (((flg_2) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_S) & \ 25 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_M) | \ 26 (((flg_3) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_S) & \ 27 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_M)) 28 29 /** 30 * ice_set_mac_type - Sets MAC type 31 * @hw: pointer to the HW structure 32 * 33 * This function sets the MAC type of the adapter based on the 34 * vendor ID and device ID stored in the hw structure. 35 */ 36 static enum ice_status ice_set_mac_type(struct ice_hw *hw) 37 { 38 if (hw->vendor_id != PCI_VENDOR_ID_INTEL) 39 return ICE_ERR_DEVICE_NOT_SUPPORTED; 40 41 hw->mac_type = ICE_MAC_GENERIC; 42 return 0; 43 } 44 45 /** 46 * ice_clear_pf_cfg - Clear PF configuration 47 * @hw: pointer to the hardware structure 48 */ 49 enum ice_status ice_clear_pf_cfg(struct ice_hw *hw) 50 { 51 struct ice_aq_desc desc; 52 53 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg); 54 55 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 56 } 57 58 /** 59 * ice_aq_manage_mac_read - manage MAC address read command 60 * @hw: pointer to the hw struct 61 * @buf: a virtual buffer to hold the manage MAC read response 62 * @buf_size: Size of the virtual buffer 63 * @cd: pointer to command details structure or NULL 64 * 65 * This function is used to return per PF station MAC address (0x0107). 66 * NOTE: Upon successful completion of this command, MAC address information 67 * is returned in user specified buffer. Please interpret user specified 68 * buffer as "manage_mac_read" response. 69 * Response such as various MAC addresses are stored in HW struct (port.mac) 70 * ice_aq_discover_caps is expected to be called before this function is called. 71 */ 72 static enum ice_status 73 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size, 74 struct ice_sq_cd *cd) 75 { 76 struct ice_aqc_manage_mac_read_resp *resp; 77 struct ice_aqc_manage_mac_read *cmd; 78 struct ice_aq_desc desc; 79 enum ice_status status; 80 u16 flags; 81 82 cmd = &desc.params.mac_read; 83 84 if (buf_size < sizeof(*resp)) 85 return ICE_ERR_BUF_TOO_SHORT; 86 87 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read); 88 89 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 90 if (status) 91 return status; 92 93 resp = (struct ice_aqc_manage_mac_read_resp *)buf; 94 flags = le16_to_cpu(cmd->flags) & ICE_AQC_MAN_MAC_READ_M; 95 96 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) { 97 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n"); 98 return ICE_ERR_CFG; 99 } 100 101 ether_addr_copy(hw->port_info->mac.lan_addr, resp->mac_addr); 102 ether_addr_copy(hw->port_info->mac.perm_addr, resp->mac_addr); 103 return 0; 104 } 105 106 /** 107 * ice_aq_get_phy_caps - returns PHY capabilities 108 * @pi: port information structure 109 * @qual_mods: report qualified modules 110 * @report_mode: report mode capabilities 111 * @pcaps: structure for PHY capabilities to be filled 112 * @cd: pointer to command details structure or NULL 113 * 114 * Returns the various PHY capabilities supported on the Port (0x0600) 115 */ 116 static enum ice_status 117 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, 118 struct ice_aqc_get_phy_caps_data *pcaps, 119 struct ice_sq_cd *cd) 120 { 121 struct ice_aqc_get_phy_caps *cmd; 122 u16 pcaps_size = sizeof(*pcaps); 123 struct ice_aq_desc desc; 124 enum ice_status status; 125 126 cmd = &desc.params.get_phy; 127 128 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi) 129 return ICE_ERR_PARAM; 130 131 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps); 132 133 if (qual_mods) 134 cmd->param0 |= cpu_to_le16(ICE_AQC_GET_PHY_RQM); 135 136 cmd->param0 |= cpu_to_le16(report_mode); 137 status = ice_aq_send_cmd(pi->hw, &desc, pcaps, pcaps_size, cd); 138 139 if (!status && report_mode == ICE_AQC_REPORT_TOPO_CAP) 140 pi->phy.phy_type_low = le64_to_cpu(pcaps->phy_type_low); 141 142 return status; 143 } 144 145 /** 146 * ice_get_media_type - Gets media type 147 * @pi: port information structure 148 */ 149 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi) 150 { 151 struct ice_link_status *hw_link_info; 152 153 if (!pi) 154 return ICE_MEDIA_UNKNOWN; 155 156 hw_link_info = &pi->phy.link_info; 157 158 if (hw_link_info->phy_type_low) { 159 switch (hw_link_info->phy_type_low) { 160 case ICE_PHY_TYPE_LOW_1000BASE_SX: 161 case ICE_PHY_TYPE_LOW_1000BASE_LX: 162 case ICE_PHY_TYPE_LOW_10GBASE_SR: 163 case ICE_PHY_TYPE_LOW_10GBASE_LR: 164 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 165 case ICE_PHY_TYPE_LOW_25GBASE_SR: 166 case ICE_PHY_TYPE_LOW_25GBASE_LR: 167 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 168 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 169 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 170 return ICE_MEDIA_FIBER; 171 case ICE_PHY_TYPE_LOW_100BASE_TX: 172 case ICE_PHY_TYPE_LOW_1000BASE_T: 173 case ICE_PHY_TYPE_LOW_2500BASE_T: 174 case ICE_PHY_TYPE_LOW_5GBASE_T: 175 case ICE_PHY_TYPE_LOW_10GBASE_T: 176 case ICE_PHY_TYPE_LOW_25GBASE_T: 177 return ICE_MEDIA_BASET; 178 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 179 case ICE_PHY_TYPE_LOW_25GBASE_CR: 180 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 181 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 182 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 183 return ICE_MEDIA_DA; 184 case ICE_PHY_TYPE_LOW_1000BASE_KX: 185 case ICE_PHY_TYPE_LOW_2500BASE_KX: 186 case ICE_PHY_TYPE_LOW_2500BASE_X: 187 case ICE_PHY_TYPE_LOW_5GBASE_KR: 188 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 189 case ICE_PHY_TYPE_LOW_25GBASE_KR: 190 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 191 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 192 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 193 return ICE_MEDIA_BACKPLANE; 194 } 195 } 196 197 return ICE_MEDIA_UNKNOWN; 198 } 199 200 /** 201 * ice_aq_get_link_info 202 * @pi: port information structure 203 * @ena_lse: enable/disable LinkStatusEvent reporting 204 * @link: pointer to link status structure - optional 205 * @cd: pointer to command details structure or NULL 206 * 207 * Get Link Status (0x607). Returns the link status of the adapter. 208 */ 209 enum ice_status 210 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse, 211 struct ice_link_status *link, struct ice_sq_cd *cd) 212 { 213 struct ice_link_status *hw_link_info_old, *hw_link_info; 214 struct ice_aqc_get_link_status_data link_data = { 0 }; 215 struct ice_aqc_get_link_status *resp; 216 enum ice_media_type *hw_media_type; 217 struct ice_fc_info *hw_fc_info; 218 bool tx_pause, rx_pause; 219 struct ice_aq_desc desc; 220 enum ice_status status; 221 u16 cmd_flags; 222 223 if (!pi) 224 return ICE_ERR_PARAM; 225 hw_link_info_old = &pi->phy.link_info_old; 226 hw_media_type = &pi->phy.media_type; 227 hw_link_info = &pi->phy.link_info; 228 hw_fc_info = &pi->fc; 229 230 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status); 231 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS; 232 resp = &desc.params.get_link_status; 233 resp->cmd_flags = cpu_to_le16(cmd_flags); 234 resp->lport_num = pi->lport; 235 236 status = ice_aq_send_cmd(pi->hw, &desc, &link_data, sizeof(link_data), 237 cd); 238 239 if (status) 240 return status; 241 242 /* save off old link status information */ 243 *hw_link_info_old = *hw_link_info; 244 245 /* update current link status information */ 246 hw_link_info->link_speed = le16_to_cpu(link_data.link_speed); 247 hw_link_info->phy_type_low = le64_to_cpu(link_data.phy_type_low); 248 *hw_media_type = ice_get_media_type(pi); 249 hw_link_info->link_info = link_data.link_info; 250 hw_link_info->an_info = link_data.an_info; 251 hw_link_info->ext_info = link_data.ext_info; 252 hw_link_info->max_frame_size = le16_to_cpu(link_data.max_frame_size); 253 hw_link_info->pacing = link_data.cfg & ICE_AQ_CFG_PACING_M; 254 255 /* update fc info */ 256 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX); 257 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX); 258 if (tx_pause && rx_pause) 259 hw_fc_info->current_mode = ICE_FC_FULL; 260 else if (tx_pause) 261 hw_fc_info->current_mode = ICE_FC_TX_PAUSE; 262 else if (rx_pause) 263 hw_fc_info->current_mode = ICE_FC_RX_PAUSE; 264 else 265 hw_fc_info->current_mode = ICE_FC_NONE; 266 267 hw_link_info->lse_ena = 268 !!(resp->cmd_flags & cpu_to_le16(ICE_AQ_LSE_IS_ENABLED)); 269 270 /* save link status information */ 271 if (link) 272 *link = *hw_link_info; 273 274 /* flag cleared so calling functions don't call AQ again */ 275 pi->phy.get_link_info = false; 276 277 return status; 278 } 279 280 /** 281 * ice_init_flex_parser - initialize rx flex parser 282 * @hw: pointer to the hardware structure 283 * 284 * Function to initialize flex descriptors 285 */ 286 static void ice_init_flex_parser(struct ice_hw *hw) 287 { 288 u8 idx = 0; 289 290 ICE_NIC_FLX_ENTRY(hw, ICE_RX_MDID_HASH_LOW, 0); 291 ICE_NIC_FLX_ENTRY(hw, ICE_RX_MDID_HASH_HIGH, 1); 292 ICE_NIC_FLX_ENTRY(hw, ICE_RX_MDID_FLOW_ID_LOWER, 2); 293 ICE_NIC_FLX_ENTRY(hw, ICE_RX_MDID_FLOW_ID_HIGH, 3); 294 ICE_NIC_FLX_FLG_ENTRY(hw, ICE_RXFLG_PKT_FRG, ICE_RXFLG_UDP_GRE, 295 ICE_RXFLG_PKT_DSI, ICE_RXFLG_FIN, idx++); 296 ICE_NIC_FLX_FLG_ENTRY(hw, ICE_RXFLG_SYN, ICE_RXFLG_RST, 297 ICE_RXFLG_PKT_DSI, ICE_RXFLG_PKT_DSI, idx++); 298 ICE_NIC_FLX_FLG_ENTRY(hw, ICE_RXFLG_PKT_DSI, ICE_RXFLG_PKT_DSI, 299 ICE_RXFLG_EVLAN_x8100, ICE_RXFLG_EVLAN_x9100, 300 idx++); 301 ICE_NIC_FLX_FLG_ENTRY(hw, ICE_RXFLG_VLAN_x8100, ICE_RXFLG_TNL_VLAN, 302 ICE_RXFLG_TNL_MAC, ICE_RXFLG_TNL0, idx++); 303 ICE_NIC_FLX_FLG_ENTRY(hw, ICE_RXFLG_TNL1, ICE_RXFLG_TNL2, 304 ICE_RXFLG_PKT_DSI, ICE_RXFLG_PKT_DSI, idx); 305 } 306 307 /** 308 * ice_init_fltr_mgmt_struct - initializes filter management list and locks 309 * @hw: pointer to the hw struct 310 */ 311 static enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw) 312 { 313 struct ice_switch_info *sw; 314 315 hw->switch_info = devm_kzalloc(ice_hw_to_dev(hw), 316 sizeof(*hw->switch_info), GFP_KERNEL); 317 sw = hw->switch_info; 318 319 if (!sw) 320 return ICE_ERR_NO_MEMORY; 321 322 INIT_LIST_HEAD(&sw->vsi_list_map_head); 323 324 mutex_init(&sw->mac_list_lock); 325 INIT_LIST_HEAD(&sw->mac_list_head); 326 327 mutex_init(&sw->vlan_list_lock); 328 INIT_LIST_HEAD(&sw->vlan_list_head); 329 330 mutex_init(&sw->eth_m_list_lock); 331 INIT_LIST_HEAD(&sw->eth_m_list_head); 332 333 mutex_init(&sw->promisc_list_lock); 334 INIT_LIST_HEAD(&sw->promisc_list_head); 335 336 mutex_init(&sw->mac_vlan_list_lock); 337 INIT_LIST_HEAD(&sw->mac_vlan_list_head); 338 339 return 0; 340 } 341 342 /** 343 * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks 344 * @hw: pointer to the hw struct 345 */ 346 static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw) 347 { 348 struct ice_switch_info *sw = hw->switch_info; 349 struct ice_vsi_list_map_info *v_pos_map; 350 struct ice_vsi_list_map_info *v_tmp_map; 351 352 list_for_each_entry_safe(v_pos_map, v_tmp_map, &sw->vsi_list_map_head, 353 list_entry) { 354 list_del(&v_pos_map->list_entry); 355 devm_kfree(ice_hw_to_dev(hw), v_pos_map); 356 } 357 358 mutex_destroy(&sw->mac_list_lock); 359 mutex_destroy(&sw->vlan_list_lock); 360 mutex_destroy(&sw->eth_m_list_lock); 361 mutex_destroy(&sw->promisc_list_lock); 362 mutex_destroy(&sw->mac_vlan_list_lock); 363 364 devm_kfree(ice_hw_to_dev(hw), sw); 365 } 366 367 /** 368 * ice_init_hw - main hardware initialization routine 369 * @hw: pointer to the hardware structure 370 */ 371 enum ice_status ice_init_hw(struct ice_hw *hw) 372 { 373 struct ice_aqc_get_phy_caps_data *pcaps; 374 enum ice_status status; 375 u16 mac_buf_len; 376 void *mac_buf; 377 378 /* Set MAC type based on DeviceID */ 379 status = ice_set_mac_type(hw); 380 if (status) 381 return status; 382 383 hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) & 384 PF_FUNC_RID_FUNC_NUM_M) >> 385 PF_FUNC_RID_FUNC_NUM_S; 386 387 status = ice_reset(hw, ICE_RESET_PFR); 388 if (status) 389 return status; 390 391 /* set these values to minimum allowed */ 392 hw->itr_gran_200 = ICE_ITR_GRAN_MIN_200; 393 hw->itr_gran_100 = ICE_ITR_GRAN_MIN_100; 394 hw->itr_gran_50 = ICE_ITR_GRAN_MIN_50; 395 hw->itr_gran_25 = ICE_ITR_GRAN_MIN_25; 396 397 status = ice_init_all_ctrlq(hw); 398 if (status) 399 goto err_unroll_cqinit; 400 401 status = ice_clear_pf_cfg(hw); 402 if (status) 403 goto err_unroll_cqinit; 404 405 ice_clear_pxe_mode(hw); 406 407 status = ice_init_nvm(hw); 408 if (status) 409 goto err_unroll_cqinit; 410 411 status = ice_get_caps(hw); 412 if (status) 413 goto err_unroll_cqinit; 414 415 hw->port_info = devm_kzalloc(ice_hw_to_dev(hw), 416 sizeof(*hw->port_info), GFP_KERNEL); 417 if (!hw->port_info) { 418 status = ICE_ERR_NO_MEMORY; 419 goto err_unroll_cqinit; 420 } 421 422 /* set the back pointer to hw */ 423 hw->port_info->hw = hw; 424 425 /* Initialize port_info struct with switch configuration data */ 426 status = ice_get_initial_sw_cfg(hw); 427 if (status) 428 goto err_unroll_alloc; 429 430 hw->evb_veb = true; 431 432 /* Query the allocated resources for tx scheduler */ 433 status = ice_sched_query_res_alloc(hw); 434 if (status) { 435 ice_debug(hw, ICE_DBG_SCHED, 436 "Failed to get scheduler allocated resources\n"); 437 goto err_unroll_alloc; 438 } 439 440 /* Initialize port_info struct with scheduler data */ 441 status = ice_sched_init_port(hw->port_info); 442 if (status) 443 goto err_unroll_sched; 444 445 pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), GFP_KERNEL); 446 if (!pcaps) { 447 status = ICE_ERR_NO_MEMORY; 448 goto err_unroll_sched; 449 } 450 451 /* Initialize port_info struct with PHY capabilities */ 452 status = ice_aq_get_phy_caps(hw->port_info, false, 453 ICE_AQC_REPORT_TOPO_CAP, pcaps, NULL); 454 devm_kfree(ice_hw_to_dev(hw), pcaps); 455 if (status) 456 goto err_unroll_sched; 457 458 /* Initialize port_info struct with link information */ 459 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL); 460 if (status) 461 goto err_unroll_sched; 462 463 status = ice_init_fltr_mgmt_struct(hw); 464 if (status) 465 goto err_unroll_sched; 466 467 /* Get port MAC information */ 468 mac_buf_len = sizeof(struct ice_aqc_manage_mac_read_resp); 469 mac_buf = devm_kzalloc(ice_hw_to_dev(hw), mac_buf_len, GFP_KERNEL); 470 471 if (!mac_buf) 472 goto err_unroll_fltr_mgmt_struct; 473 474 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL); 475 devm_kfree(ice_hw_to_dev(hw), mac_buf); 476 477 if (status) 478 goto err_unroll_fltr_mgmt_struct; 479 480 ice_init_flex_parser(hw); 481 482 return 0; 483 484 err_unroll_fltr_mgmt_struct: 485 ice_cleanup_fltr_mgmt_struct(hw); 486 err_unroll_sched: 487 ice_sched_cleanup_all(hw); 488 err_unroll_alloc: 489 devm_kfree(ice_hw_to_dev(hw), hw->port_info); 490 err_unroll_cqinit: 491 ice_shutdown_all_ctrlq(hw); 492 return status; 493 } 494 495 /** 496 * ice_deinit_hw - unroll initialization operations done by ice_init_hw 497 * @hw: pointer to the hardware structure 498 */ 499 void ice_deinit_hw(struct ice_hw *hw) 500 { 501 ice_sched_cleanup_all(hw); 502 ice_shutdown_all_ctrlq(hw); 503 504 if (hw->port_info) { 505 devm_kfree(ice_hw_to_dev(hw), hw->port_info); 506 hw->port_info = NULL; 507 } 508 509 ice_cleanup_fltr_mgmt_struct(hw); 510 } 511 512 /** 513 * ice_check_reset - Check to see if a global reset is complete 514 * @hw: pointer to the hardware structure 515 */ 516 enum ice_status ice_check_reset(struct ice_hw *hw) 517 { 518 u32 cnt, reg = 0, grst_delay; 519 520 /* Poll for Device Active state in case a recent CORER, GLOBR, 521 * or EMPR has occurred. The grst delay value is in 100ms units. 522 * Add 1sec for outstanding AQ commands that can take a long time. 523 */ 524 grst_delay = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >> 525 GLGEN_RSTCTL_GRSTDEL_S) + 10; 526 527 for (cnt = 0; cnt < grst_delay; cnt++) { 528 mdelay(100); 529 reg = rd32(hw, GLGEN_RSTAT); 530 if (!(reg & GLGEN_RSTAT_DEVSTATE_M)) 531 break; 532 } 533 534 if (cnt == grst_delay) { 535 ice_debug(hw, ICE_DBG_INIT, 536 "Global reset polling failed to complete.\n"); 537 return ICE_ERR_RESET_FAILED; 538 } 539 540 #define ICE_RESET_DONE_MASK (GLNVM_ULD_CORER_DONE_M | \ 541 GLNVM_ULD_GLOBR_DONE_M) 542 543 /* Device is Active; check Global Reset processes are done */ 544 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) { 545 reg = rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK; 546 if (reg == ICE_RESET_DONE_MASK) { 547 ice_debug(hw, ICE_DBG_INIT, 548 "Global reset processes done. %d\n", cnt); 549 break; 550 } 551 mdelay(10); 552 } 553 554 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 555 ice_debug(hw, ICE_DBG_INIT, 556 "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n", 557 reg); 558 return ICE_ERR_RESET_FAILED; 559 } 560 561 return 0; 562 } 563 564 /** 565 * ice_pf_reset - Reset the PF 566 * @hw: pointer to the hardware structure 567 * 568 * If a global reset has been triggered, this function checks 569 * for its completion and then issues the PF reset 570 */ 571 static enum ice_status ice_pf_reset(struct ice_hw *hw) 572 { 573 u32 cnt, reg; 574 575 /* If at function entry a global reset was already in progress, i.e. 576 * state is not 'device active' or any of the reset done bits are not 577 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the 578 * global reset is done. 579 */ 580 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) || 581 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) { 582 /* poll on global reset currently in progress until done */ 583 if (ice_check_reset(hw)) 584 return ICE_ERR_RESET_FAILED; 585 586 return 0; 587 } 588 589 /* Reset the PF */ 590 reg = rd32(hw, PFGEN_CTRL); 591 592 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M)); 593 594 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) { 595 reg = rd32(hw, PFGEN_CTRL); 596 if (!(reg & PFGEN_CTRL_PFSWR_M)) 597 break; 598 599 mdelay(1); 600 } 601 602 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 603 ice_debug(hw, ICE_DBG_INIT, 604 "PF reset polling failed to complete.\n"); 605 return ICE_ERR_RESET_FAILED; 606 } 607 608 return 0; 609 } 610 611 /** 612 * ice_reset - Perform different types of reset 613 * @hw: pointer to the hardware structure 614 * @req: reset request 615 * 616 * This function triggers a reset as specified by the req parameter. 617 * 618 * Note: 619 * If anything other than a PF reset is triggered, PXE mode is restored. 620 * This has to be cleared using ice_clear_pxe_mode again, once the AQ 621 * interface has been restored in the rebuild flow. 622 */ 623 enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req) 624 { 625 u32 val = 0; 626 627 switch (req) { 628 case ICE_RESET_PFR: 629 return ice_pf_reset(hw); 630 case ICE_RESET_CORER: 631 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n"); 632 val = GLGEN_RTRIG_CORER_M; 633 break; 634 case ICE_RESET_GLOBR: 635 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n"); 636 val = GLGEN_RTRIG_GLOBR_M; 637 break; 638 } 639 640 val |= rd32(hw, GLGEN_RTRIG); 641 wr32(hw, GLGEN_RTRIG, val); 642 ice_flush(hw); 643 644 /* wait for the FW to be ready */ 645 return ice_check_reset(hw); 646 } 647 648 /** 649 * ice_copy_rxq_ctx_to_hw 650 * @hw: pointer to the hardware structure 651 * @ice_rxq_ctx: pointer to the rxq context 652 * @rxq_index: the index of the rx queue 653 * 654 * Copies rxq context from dense structure to hw register space 655 */ 656 static enum ice_status 657 ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index) 658 { 659 u8 i; 660 661 if (!ice_rxq_ctx) 662 return ICE_ERR_BAD_PTR; 663 664 if (rxq_index > QRX_CTRL_MAX_INDEX) 665 return ICE_ERR_PARAM; 666 667 /* Copy each dword separately to hw */ 668 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) { 669 wr32(hw, QRX_CONTEXT(i, rxq_index), 670 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32))))); 671 672 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, 673 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32))))); 674 } 675 676 return 0; 677 } 678 679 /* LAN Rx Queue Context */ 680 static const struct ice_ctx_ele ice_rlan_ctx_info[] = { 681 /* Field Width LSB */ 682 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0), 683 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13), 684 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32), 685 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89), 686 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102), 687 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109), 688 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114), 689 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116), 690 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117), 691 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119), 692 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120), 693 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124), 694 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127), 695 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174), 696 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193), 697 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194), 698 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195), 699 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196), 700 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198), 701 { 0 } 702 }; 703 704 /** 705 * ice_write_rxq_ctx 706 * @hw: pointer to the hardware structure 707 * @rlan_ctx: pointer to the rxq context 708 * @rxq_index: the index of the rx queue 709 * 710 * Converts rxq context from sparse to dense structure and then writes 711 * it to hw register space 712 */ 713 enum ice_status 714 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 715 u32 rxq_index) 716 { 717 u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 }; 718 719 ice_set_ctx((u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info); 720 return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index); 721 } 722 723 /* LAN Tx Queue Context */ 724 const struct ice_ctx_ele ice_tlan_ctx_info[] = { 725 /* Field Width LSB */ 726 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0), 727 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57), 728 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60), 729 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65), 730 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68), 731 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78), 732 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80), 733 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90), 734 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92), 735 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93), 736 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101), 737 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102), 738 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103), 739 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104), 740 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105), 741 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114), 742 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128), 743 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129), 744 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135), 745 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148), 746 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152), 747 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153), 748 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164), 749 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165), 750 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166), 751 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168), 752 ICE_CTX_STORE(ice_tlan_ctx, int_q_state, 110, 171), 753 { 0 } 754 }; 755 756 /** 757 * ice_debug_cq 758 * @hw: pointer to the hardware structure 759 * @mask: debug mask 760 * @desc: pointer to control queue descriptor 761 * @buf: pointer to command buffer 762 * @buf_len: max length of buf 763 * 764 * Dumps debug log about control command with descriptor contents. 765 */ 766 void ice_debug_cq(struct ice_hw *hw, u32 __maybe_unused mask, void *desc, 767 void *buf, u16 buf_len) 768 { 769 struct ice_aq_desc *cq_desc = (struct ice_aq_desc *)desc; 770 u16 len; 771 772 #ifndef CONFIG_DYNAMIC_DEBUG 773 if (!(mask & hw->debug_mask)) 774 return; 775 #endif 776 777 if (!desc) 778 return; 779 780 len = le16_to_cpu(cq_desc->datalen); 781 782 ice_debug(hw, mask, 783 "CQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n", 784 le16_to_cpu(cq_desc->opcode), 785 le16_to_cpu(cq_desc->flags), 786 le16_to_cpu(cq_desc->datalen), le16_to_cpu(cq_desc->retval)); 787 ice_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n", 788 le32_to_cpu(cq_desc->cookie_high), 789 le32_to_cpu(cq_desc->cookie_low)); 790 ice_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n", 791 le32_to_cpu(cq_desc->params.generic.param0), 792 le32_to_cpu(cq_desc->params.generic.param1)); 793 ice_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n", 794 le32_to_cpu(cq_desc->params.generic.addr_high), 795 le32_to_cpu(cq_desc->params.generic.addr_low)); 796 if (buf && cq_desc->datalen != 0) { 797 ice_debug(hw, mask, "Buffer:\n"); 798 if (buf_len < len) 799 len = buf_len; 800 801 ice_debug_array(hw, mask, 16, 1, (u8 *)buf, len); 802 } 803 } 804 805 /* FW Admin Queue command wrappers */ 806 807 /** 808 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue 809 * @hw: pointer to the hw struct 810 * @desc: descriptor describing the command 811 * @buf: buffer to use for indirect commands (NULL for direct commands) 812 * @buf_size: size of buffer for indirect commands (0 for direct commands) 813 * @cd: pointer to command details structure 814 * 815 * Helper function to send FW Admin Queue commands to the FW Admin Queue. 816 */ 817 enum ice_status 818 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf, 819 u16 buf_size, struct ice_sq_cd *cd) 820 { 821 return ice_sq_send_cmd(hw, &hw->adminq, desc, buf, buf_size, cd); 822 } 823 824 /** 825 * ice_aq_get_fw_ver 826 * @hw: pointer to the hw struct 827 * @cd: pointer to command details structure or NULL 828 * 829 * Get the firmware version (0x0001) from the admin queue commands 830 */ 831 enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd) 832 { 833 struct ice_aqc_get_ver *resp; 834 struct ice_aq_desc desc; 835 enum ice_status status; 836 837 resp = &desc.params.get_ver; 838 839 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver); 840 841 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 842 843 if (!status) { 844 hw->fw_branch = resp->fw_branch; 845 hw->fw_maj_ver = resp->fw_major; 846 hw->fw_min_ver = resp->fw_minor; 847 hw->fw_patch = resp->fw_patch; 848 hw->fw_build = le32_to_cpu(resp->fw_build); 849 hw->api_branch = resp->api_branch; 850 hw->api_maj_ver = resp->api_major; 851 hw->api_min_ver = resp->api_minor; 852 hw->api_patch = resp->api_patch; 853 } 854 855 return status; 856 } 857 858 /** 859 * ice_aq_q_shutdown 860 * @hw: pointer to the hw struct 861 * @unloading: is the driver unloading itself 862 * 863 * Tell the Firmware that we're shutting down the AdminQ and whether 864 * or not the driver is unloading as well (0x0003). 865 */ 866 enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading) 867 { 868 struct ice_aqc_q_shutdown *cmd; 869 struct ice_aq_desc desc; 870 871 cmd = &desc.params.q_shutdown; 872 873 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown); 874 875 if (unloading) 876 cmd->driver_unloading = cpu_to_le32(ICE_AQC_DRIVER_UNLOADING); 877 878 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 879 } 880 881 /** 882 * ice_aq_req_res 883 * @hw: pointer to the hw struct 884 * @res: resource id 885 * @access: access type 886 * @sdp_number: resource number 887 * @timeout: the maximum time in ms that the driver may hold the resource 888 * @cd: pointer to command details structure or NULL 889 * 890 * requests common resource using the admin queue commands (0x0008) 891 */ 892 static enum ice_status 893 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res, 894 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout, 895 struct ice_sq_cd *cd) 896 { 897 struct ice_aqc_req_res *cmd_resp; 898 struct ice_aq_desc desc; 899 enum ice_status status; 900 901 cmd_resp = &desc.params.res_owner; 902 903 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res); 904 905 cmd_resp->res_id = cpu_to_le16(res); 906 cmd_resp->access_type = cpu_to_le16(access); 907 cmd_resp->res_number = cpu_to_le32(sdp_number); 908 909 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 910 /* The completion specifies the maximum time in ms that the driver 911 * may hold the resource in the Timeout field. 912 * If the resource is held by someone else, the command completes with 913 * busy return value and the timeout field indicates the maximum time 914 * the current owner of the resource has to free it. 915 */ 916 if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY) 917 *timeout = le32_to_cpu(cmd_resp->timeout); 918 919 return status; 920 } 921 922 /** 923 * ice_aq_release_res 924 * @hw: pointer to the hw struct 925 * @res: resource id 926 * @sdp_number: resource number 927 * @cd: pointer to command details structure or NULL 928 * 929 * release common resource using the admin queue commands (0x0009) 930 */ 931 static enum ice_status 932 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number, 933 struct ice_sq_cd *cd) 934 { 935 struct ice_aqc_req_res *cmd; 936 struct ice_aq_desc desc; 937 938 cmd = &desc.params.res_owner; 939 940 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res); 941 942 cmd->res_id = cpu_to_le16(res); 943 cmd->res_number = cpu_to_le32(sdp_number); 944 945 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 946 } 947 948 /** 949 * ice_acquire_res 950 * @hw: pointer to the HW structure 951 * @res: resource id 952 * @access: access type (read or write) 953 * 954 * This function will attempt to acquire the ownership of a resource. 955 */ 956 enum ice_status 957 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res, 958 enum ice_aq_res_access_type access) 959 { 960 #define ICE_RES_POLLING_DELAY_MS 10 961 u32 delay = ICE_RES_POLLING_DELAY_MS; 962 enum ice_status status; 963 u32 time_left = 0; 964 u32 timeout; 965 966 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 967 968 /* An admin queue return code of ICE_AQ_RC_EEXIST means that another 969 * driver has previously acquired the resource and performed any 970 * necessary updates; in this case the caller does not obtain the 971 * resource and has no further work to do. 972 */ 973 if (hw->adminq.sq_last_status == ICE_AQ_RC_EEXIST) { 974 status = ICE_ERR_AQ_NO_WORK; 975 goto ice_acquire_res_exit; 976 } 977 978 if (status) 979 ice_debug(hw, ICE_DBG_RES, 980 "resource %d acquire type %d failed.\n", res, access); 981 982 /* If necessary, poll until the current lock owner timeouts */ 983 timeout = time_left; 984 while (status && timeout && time_left) { 985 mdelay(delay); 986 timeout = (timeout > delay) ? timeout - delay : 0; 987 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 988 989 if (hw->adminq.sq_last_status == ICE_AQ_RC_EEXIST) { 990 /* lock free, but no work to do */ 991 status = ICE_ERR_AQ_NO_WORK; 992 break; 993 } 994 995 if (!status) 996 /* lock acquired */ 997 break; 998 } 999 if (status && status != ICE_ERR_AQ_NO_WORK) 1000 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n"); 1001 1002 ice_acquire_res_exit: 1003 if (status == ICE_ERR_AQ_NO_WORK) { 1004 if (access == ICE_RES_WRITE) 1005 ice_debug(hw, ICE_DBG_RES, 1006 "resource indicates no work to do.\n"); 1007 else 1008 ice_debug(hw, ICE_DBG_RES, 1009 "Warning: ICE_ERR_AQ_NO_WORK not expected\n"); 1010 } 1011 return status; 1012 } 1013 1014 /** 1015 * ice_release_res 1016 * @hw: pointer to the HW structure 1017 * @res: resource id 1018 * 1019 * This function will release a resource using the proper Admin Command. 1020 */ 1021 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res) 1022 { 1023 enum ice_status status; 1024 u32 total_delay = 0; 1025 1026 status = ice_aq_release_res(hw, res, 0, NULL); 1027 1028 /* there are some rare cases when trying to release the resource 1029 * results in an admin Q timeout, so handle them correctly 1030 */ 1031 while ((status == ICE_ERR_AQ_TIMEOUT) && 1032 (total_delay < hw->adminq.sq_cmd_timeout)) { 1033 mdelay(1); 1034 status = ice_aq_release_res(hw, res, 0, NULL); 1035 total_delay++; 1036 } 1037 } 1038 1039 /** 1040 * ice_parse_caps - parse function/device capabilities 1041 * @hw: pointer to the hw struct 1042 * @buf: pointer to a buffer containing function/device capability records 1043 * @cap_count: number of capability records in the list 1044 * @opc: type of capabilities list to parse 1045 * 1046 * Helper function to parse function(0x000a)/device(0x000b) capabilities list. 1047 */ 1048 static void 1049 ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count, 1050 enum ice_adminq_opc opc) 1051 { 1052 struct ice_aqc_list_caps_elem *cap_resp; 1053 struct ice_hw_func_caps *func_p = NULL; 1054 struct ice_hw_dev_caps *dev_p = NULL; 1055 struct ice_hw_common_caps *caps; 1056 u32 i; 1057 1058 if (!buf) 1059 return; 1060 1061 cap_resp = (struct ice_aqc_list_caps_elem *)buf; 1062 1063 if (opc == ice_aqc_opc_list_dev_caps) { 1064 dev_p = &hw->dev_caps; 1065 caps = &dev_p->common_cap; 1066 } else if (opc == ice_aqc_opc_list_func_caps) { 1067 func_p = &hw->func_caps; 1068 caps = &func_p->common_cap; 1069 } else { 1070 ice_debug(hw, ICE_DBG_INIT, "wrong opcode\n"); 1071 return; 1072 } 1073 1074 for (i = 0; caps && i < cap_count; i++, cap_resp++) { 1075 u32 logical_id = le32_to_cpu(cap_resp->logical_id); 1076 u32 phys_id = le32_to_cpu(cap_resp->phys_id); 1077 u32 number = le32_to_cpu(cap_resp->number); 1078 u16 cap = le16_to_cpu(cap_resp->cap); 1079 1080 switch (cap) { 1081 case ICE_AQC_CAPS_VSI: 1082 if (dev_p) { 1083 dev_p->num_vsi_allocd_to_host = number; 1084 ice_debug(hw, ICE_DBG_INIT, 1085 "HW caps: Dev.VSI cnt = %d\n", 1086 dev_p->num_vsi_allocd_to_host); 1087 } else if (func_p) { 1088 func_p->guaranteed_num_vsi = number; 1089 ice_debug(hw, ICE_DBG_INIT, 1090 "HW caps: Func.VSI cnt = %d\n", 1091 func_p->guaranteed_num_vsi); 1092 } 1093 break; 1094 case ICE_AQC_CAPS_RSS: 1095 caps->rss_table_size = number; 1096 caps->rss_table_entry_width = logical_id; 1097 ice_debug(hw, ICE_DBG_INIT, 1098 "HW caps: RSS table size = %d\n", 1099 caps->rss_table_size); 1100 ice_debug(hw, ICE_DBG_INIT, 1101 "HW caps: RSS table width = %d\n", 1102 caps->rss_table_entry_width); 1103 break; 1104 case ICE_AQC_CAPS_RXQS: 1105 caps->num_rxq = number; 1106 caps->rxq_first_id = phys_id; 1107 ice_debug(hw, ICE_DBG_INIT, 1108 "HW caps: Num Rx Qs = %d\n", caps->num_rxq); 1109 ice_debug(hw, ICE_DBG_INIT, 1110 "HW caps: Rx first queue ID = %d\n", 1111 caps->rxq_first_id); 1112 break; 1113 case ICE_AQC_CAPS_TXQS: 1114 caps->num_txq = number; 1115 caps->txq_first_id = phys_id; 1116 ice_debug(hw, ICE_DBG_INIT, 1117 "HW caps: Num Tx Qs = %d\n", caps->num_txq); 1118 ice_debug(hw, ICE_DBG_INIT, 1119 "HW caps: Tx first queue ID = %d\n", 1120 caps->txq_first_id); 1121 break; 1122 case ICE_AQC_CAPS_MSIX: 1123 caps->num_msix_vectors = number; 1124 caps->msix_vector_first_id = phys_id; 1125 ice_debug(hw, ICE_DBG_INIT, 1126 "HW caps: MSIX vector count = %d\n", 1127 caps->num_msix_vectors); 1128 ice_debug(hw, ICE_DBG_INIT, 1129 "HW caps: MSIX first vector index = %d\n", 1130 caps->msix_vector_first_id); 1131 break; 1132 case ICE_AQC_CAPS_MAX_MTU: 1133 caps->max_mtu = number; 1134 if (dev_p) 1135 ice_debug(hw, ICE_DBG_INIT, 1136 "HW caps: Dev.MaxMTU = %d\n", 1137 caps->max_mtu); 1138 else if (func_p) 1139 ice_debug(hw, ICE_DBG_INIT, 1140 "HW caps: func.MaxMTU = %d\n", 1141 caps->max_mtu); 1142 break; 1143 default: 1144 ice_debug(hw, ICE_DBG_INIT, 1145 "HW caps: Unknown capability[%d]: 0x%x\n", i, 1146 cap); 1147 break; 1148 } 1149 } 1150 } 1151 1152 /** 1153 * ice_aq_discover_caps - query function/device capabilities 1154 * @hw: pointer to the hw struct 1155 * @buf: a virtual buffer to hold the capabilities 1156 * @buf_size: Size of the virtual buffer 1157 * @data_size: Size of the returned data, or buf size needed if AQ err==ENOMEM 1158 * @opc: capabilities type to discover - pass in the command opcode 1159 * @cd: pointer to command details structure or NULL 1160 * 1161 * Get the function(0x000a)/device(0x000b) capabilities description from 1162 * the firmware. 1163 */ 1164 static enum ice_status 1165 ice_aq_discover_caps(struct ice_hw *hw, void *buf, u16 buf_size, u16 *data_size, 1166 enum ice_adminq_opc opc, struct ice_sq_cd *cd) 1167 { 1168 struct ice_aqc_list_caps *cmd; 1169 struct ice_aq_desc desc; 1170 enum ice_status status; 1171 1172 cmd = &desc.params.get_cap; 1173 1174 if (opc != ice_aqc_opc_list_func_caps && 1175 opc != ice_aqc_opc_list_dev_caps) 1176 return ICE_ERR_PARAM; 1177 1178 ice_fill_dflt_direct_cmd_desc(&desc, opc); 1179 1180 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 1181 if (!status) 1182 ice_parse_caps(hw, buf, le32_to_cpu(cmd->count), opc); 1183 *data_size = le16_to_cpu(desc.datalen); 1184 1185 return status; 1186 } 1187 1188 /** 1189 * ice_get_caps - get info about the HW 1190 * @hw: pointer to the hardware structure 1191 */ 1192 enum ice_status ice_get_caps(struct ice_hw *hw) 1193 { 1194 enum ice_status status; 1195 u16 data_size = 0; 1196 u16 cbuf_len; 1197 u8 retries; 1198 1199 /* The driver doesn't know how many capabilities the device will return 1200 * so the buffer size required isn't known ahead of time. The driver 1201 * starts with cbuf_len and if this turns out to be insufficient, the 1202 * device returns ICE_AQ_RC_ENOMEM and also the buffer size it needs. 1203 * The driver then allocates the buffer of this size and retries the 1204 * operation. So it follows that the retry count is 2. 1205 */ 1206 #define ICE_GET_CAP_BUF_COUNT 40 1207 #define ICE_GET_CAP_RETRY_COUNT 2 1208 1209 cbuf_len = ICE_GET_CAP_BUF_COUNT * 1210 sizeof(struct ice_aqc_list_caps_elem); 1211 1212 retries = ICE_GET_CAP_RETRY_COUNT; 1213 1214 do { 1215 void *cbuf; 1216 1217 cbuf = devm_kzalloc(ice_hw_to_dev(hw), cbuf_len, GFP_KERNEL); 1218 if (!cbuf) 1219 return ICE_ERR_NO_MEMORY; 1220 1221 status = ice_aq_discover_caps(hw, cbuf, cbuf_len, &data_size, 1222 ice_aqc_opc_list_func_caps, NULL); 1223 devm_kfree(ice_hw_to_dev(hw), cbuf); 1224 1225 if (!status || hw->adminq.sq_last_status != ICE_AQ_RC_ENOMEM) 1226 break; 1227 1228 /* If ENOMEM is returned, try again with bigger buffer */ 1229 cbuf_len = data_size; 1230 } while (--retries); 1231 1232 return status; 1233 } 1234 1235 /** 1236 * ice_aq_manage_mac_write - manage MAC address write command 1237 * @hw: pointer to the hw struct 1238 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address 1239 * @flags: flags to control write behavior 1240 * @cd: pointer to command details structure or NULL 1241 * 1242 * This function is used to write MAC address to the NVM (0x0108). 1243 */ 1244 enum ice_status 1245 ice_aq_manage_mac_write(struct ice_hw *hw, u8 *mac_addr, u8 flags, 1246 struct ice_sq_cd *cd) 1247 { 1248 struct ice_aqc_manage_mac_write *cmd; 1249 struct ice_aq_desc desc; 1250 1251 cmd = &desc.params.mac_write; 1252 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write); 1253 1254 cmd->flags = flags; 1255 1256 /* Prep values for flags, sah, sal */ 1257 cmd->sah = htons(*((u16 *)mac_addr)); 1258 cmd->sal = htonl(*((u32 *)(mac_addr + 2))); 1259 1260 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1261 } 1262 1263 /** 1264 * ice_aq_clear_pxe_mode 1265 * @hw: pointer to the hw struct 1266 * 1267 * Tell the firmware that the driver is taking over from PXE (0x0110). 1268 */ 1269 static enum ice_status ice_aq_clear_pxe_mode(struct ice_hw *hw) 1270 { 1271 struct ice_aq_desc desc; 1272 1273 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode); 1274 desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT; 1275 1276 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 1277 } 1278 1279 /** 1280 * ice_clear_pxe_mode - clear pxe operations mode 1281 * @hw: pointer to the hw struct 1282 * 1283 * Make sure all PXE mode settings are cleared, including things 1284 * like descriptor fetch/write-back mode. 1285 */ 1286 void ice_clear_pxe_mode(struct ice_hw *hw) 1287 { 1288 if (ice_check_sq_alive(hw, &hw->adminq)) 1289 ice_aq_clear_pxe_mode(hw); 1290 } 1291 1292 /** 1293 * ice_aq_set_phy_cfg 1294 * @hw: pointer to the hw struct 1295 * @lport: logical port number 1296 * @cfg: structure with PHY configuration data to be set 1297 * @cd: pointer to command details structure or NULL 1298 * 1299 * Set the various PHY configuration parameters supported on the Port. 1300 * One or more of the Set PHY config parameters may be ignored in an MFP 1301 * mode as the PF may not have the privilege to set some of the PHY Config 1302 * parameters. This status will be indicated by the command response (0x0601). 1303 */ 1304 static enum ice_status 1305 ice_aq_set_phy_cfg(struct ice_hw *hw, u8 lport, 1306 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd) 1307 { 1308 struct ice_aqc_set_phy_cfg *cmd; 1309 struct ice_aq_desc desc; 1310 1311 if (!cfg) 1312 return ICE_ERR_PARAM; 1313 1314 cmd = &desc.params.set_phy; 1315 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg); 1316 cmd->lport_num = lport; 1317 1318 return ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd); 1319 } 1320 1321 /** 1322 * ice_update_link_info - update status of the HW network link 1323 * @pi: port info structure of the interested logical port 1324 */ 1325 static enum ice_status 1326 ice_update_link_info(struct ice_port_info *pi) 1327 { 1328 struct ice_aqc_get_phy_caps_data *pcaps; 1329 struct ice_phy_info *phy_info; 1330 enum ice_status status; 1331 struct ice_hw *hw; 1332 1333 if (!pi) 1334 return ICE_ERR_PARAM; 1335 1336 hw = pi->hw; 1337 1338 pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), GFP_KERNEL); 1339 if (!pcaps) 1340 return ICE_ERR_NO_MEMORY; 1341 1342 phy_info = &pi->phy; 1343 status = ice_aq_get_link_info(pi, true, NULL, NULL); 1344 if (status) 1345 goto out; 1346 1347 if (phy_info->link_info.link_info & ICE_AQ_MEDIA_AVAILABLE) { 1348 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, 1349 pcaps, NULL); 1350 if (status) 1351 goto out; 1352 1353 memcpy(phy_info->link_info.module_type, &pcaps->module_type, 1354 sizeof(phy_info->link_info.module_type)); 1355 } 1356 out: 1357 devm_kfree(ice_hw_to_dev(hw), pcaps); 1358 return status; 1359 } 1360 1361 /** 1362 * ice_set_fc 1363 * @pi: port information structure 1364 * @aq_failures: pointer to status code, specific to ice_set_fc routine 1365 * @atomic_restart: enable automatic link update 1366 * 1367 * Set the requested flow control mode. 1368 */ 1369 enum ice_status 1370 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool atomic_restart) 1371 { 1372 struct ice_aqc_set_phy_cfg_data cfg = { 0 }; 1373 struct ice_aqc_get_phy_caps_data *pcaps; 1374 enum ice_status status; 1375 u8 pause_mask = 0x0; 1376 struct ice_hw *hw; 1377 1378 if (!pi) 1379 return ICE_ERR_PARAM; 1380 hw = pi->hw; 1381 *aq_failures = ICE_SET_FC_AQ_FAIL_NONE; 1382 1383 switch (pi->fc.req_mode) { 1384 case ICE_FC_FULL: 1385 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 1386 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 1387 break; 1388 case ICE_FC_RX_PAUSE: 1389 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 1390 break; 1391 case ICE_FC_TX_PAUSE: 1392 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 1393 break; 1394 default: 1395 break; 1396 } 1397 1398 pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), GFP_KERNEL); 1399 if (!pcaps) 1400 return ICE_ERR_NO_MEMORY; 1401 1402 /* Get the current phy config */ 1403 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps, 1404 NULL); 1405 if (status) { 1406 *aq_failures = ICE_SET_FC_AQ_FAIL_GET; 1407 goto out; 1408 } 1409 1410 /* clear the old pause settings */ 1411 cfg.caps = pcaps->caps & ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE | 1412 ICE_AQC_PHY_EN_RX_LINK_PAUSE); 1413 /* set the new capabilities */ 1414 cfg.caps |= pause_mask; 1415 /* If the capabilities have changed, then set the new config */ 1416 if (cfg.caps != pcaps->caps) { 1417 int retry_count, retry_max = 10; 1418 1419 /* Auto restart link so settings take effect */ 1420 if (atomic_restart) 1421 cfg.caps |= ICE_AQ_PHY_ENA_ATOMIC_LINK; 1422 /* Copy over all the old settings */ 1423 cfg.phy_type_low = pcaps->phy_type_low; 1424 cfg.low_power_ctrl = pcaps->low_power_ctrl; 1425 cfg.eee_cap = pcaps->eee_cap; 1426 cfg.eeer_value = pcaps->eeer_value; 1427 cfg.link_fec_opt = pcaps->link_fec_options; 1428 1429 status = ice_aq_set_phy_cfg(hw, pi->lport, &cfg, NULL); 1430 if (status) { 1431 *aq_failures = ICE_SET_FC_AQ_FAIL_SET; 1432 goto out; 1433 } 1434 1435 /* Update the link info 1436 * It sometimes takes a really long time for link to 1437 * come back from the atomic reset. Thus, we wait a 1438 * little bit. 1439 */ 1440 for (retry_count = 0; retry_count < retry_max; retry_count++) { 1441 status = ice_update_link_info(pi); 1442 1443 if (!status) 1444 break; 1445 1446 mdelay(100); 1447 } 1448 1449 if (status) 1450 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE; 1451 } 1452 1453 out: 1454 devm_kfree(ice_hw_to_dev(hw), pcaps); 1455 return status; 1456 } 1457 1458 /** 1459 * ice_get_link_status - get status of the HW network link 1460 * @pi: port information structure 1461 * @link_up: pointer to bool (true/false = linkup/linkdown) 1462 * 1463 * Variable link_up is true if link is up, false if link is down. 1464 * The variable link_up is invalid if status is non zero. As a 1465 * result of this call, link status reporting becomes enabled 1466 */ 1467 enum ice_status ice_get_link_status(struct ice_port_info *pi, bool *link_up) 1468 { 1469 struct ice_phy_info *phy_info; 1470 enum ice_status status = 0; 1471 1472 if (!pi) 1473 return ICE_ERR_PARAM; 1474 1475 phy_info = &pi->phy; 1476 1477 if (phy_info->get_link_info) { 1478 status = ice_update_link_info(pi); 1479 1480 if (status) 1481 ice_debug(pi->hw, ICE_DBG_LINK, 1482 "get link status error, status = %d\n", 1483 status); 1484 } 1485 1486 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP; 1487 1488 return status; 1489 } 1490 1491 /** 1492 * ice_aq_set_link_restart_an 1493 * @pi: pointer to the port information structure 1494 * @ena_link: if true: enable link, if false: disable link 1495 * @cd: pointer to command details structure or NULL 1496 * 1497 * Sets up the link and restarts the Auto-Negotiation over the link. 1498 */ 1499 enum ice_status 1500 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link, 1501 struct ice_sq_cd *cd) 1502 { 1503 struct ice_aqc_restart_an *cmd; 1504 struct ice_aq_desc desc; 1505 1506 cmd = &desc.params.restart_an; 1507 1508 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an); 1509 1510 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART; 1511 cmd->lport_num = pi->lport; 1512 if (ena_link) 1513 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE; 1514 else 1515 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE; 1516 1517 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 1518 } 1519 1520 /** 1521 * ice_aq_set_event_mask 1522 * @hw: pointer to the hw struct 1523 * @port_num: port number of the physical function 1524 * @mask: event mask to be set 1525 * @cd: pointer to command details structure or NULL 1526 * 1527 * Set event mask (0x0613) 1528 */ 1529 enum ice_status 1530 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask, 1531 struct ice_sq_cd *cd) 1532 { 1533 struct ice_aqc_set_event_mask *cmd; 1534 struct ice_aq_desc desc; 1535 1536 cmd = &desc.params.set_event_mask; 1537 1538 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask); 1539 1540 cmd->lport_num = port_num; 1541 1542 cmd->event_mask = cpu_to_le16(mask); 1543 1544 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1545 } 1546 1547 /** 1548 * __ice_aq_get_set_rss_lut 1549 * @hw: pointer to the hardware structure 1550 * @vsi_id: VSI FW index 1551 * @lut_type: LUT table type 1552 * @lut: pointer to the LUT buffer provided by the caller 1553 * @lut_size: size of the LUT buffer 1554 * @glob_lut_idx: global LUT index 1555 * @set: set true to set the table, false to get the table 1556 * 1557 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table 1558 */ 1559 static enum ice_status 1560 __ice_aq_get_set_rss_lut(struct ice_hw *hw, u16 vsi_id, u8 lut_type, u8 *lut, 1561 u16 lut_size, u8 glob_lut_idx, bool set) 1562 { 1563 struct ice_aqc_get_set_rss_lut *cmd_resp; 1564 struct ice_aq_desc desc; 1565 enum ice_status status; 1566 u16 flags = 0; 1567 1568 cmd_resp = &desc.params.get_set_rss_lut; 1569 1570 if (set) { 1571 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_lut); 1572 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 1573 } else { 1574 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_lut); 1575 } 1576 1577 cmd_resp->vsi_id = cpu_to_le16(((vsi_id << 1578 ICE_AQC_GSET_RSS_LUT_VSI_ID_S) & 1579 ICE_AQC_GSET_RSS_LUT_VSI_ID_M) | 1580 ICE_AQC_GSET_RSS_LUT_VSI_VALID); 1581 1582 switch (lut_type) { 1583 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI: 1584 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF: 1585 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL: 1586 flags |= ((lut_type << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) & 1587 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M); 1588 break; 1589 default: 1590 status = ICE_ERR_PARAM; 1591 goto ice_aq_get_set_rss_lut_exit; 1592 } 1593 1594 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL) { 1595 flags |= ((glob_lut_idx << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) & 1596 ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M); 1597 1598 if (!set) 1599 goto ice_aq_get_set_rss_lut_send; 1600 } else if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) { 1601 if (!set) 1602 goto ice_aq_get_set_rss_lut_send; 1603 } else { 1604 goto ice_aq_get_set_rss_lut_send; 1605 } 1606 1607 /* LUT size is only valid for Global and PF table types */ 1608 if (lut_size == ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128) { 1609 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG << 1610 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & 1611 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; 1612 } else if (lut_size == ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512) { 1613 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG << 1614 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & 1615 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; 1616 } else if ((lut_size == ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K) && 1617 (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF)) { 1618 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG << 1619 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & 1620 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; 1621 } else { 1622 status = ICE_ERR_PARAM; 1623 goto ice_aq_get_set_rss_lut_exit; 1624 } 1625 1626 ice_aq_get_set_rss_lut_send: 1627 cmd_resp->flags = cpu_to_le16(flags); 1628 status = ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL); 1629 1630 ice_aq_get_set_rss_lut_exit: 1631 return status; 1632 } 1633 1634 /** 1635 * ice_aq_get_rss_lut 1636 * @hw: pointer to the hardware structure 1637 * @vsi_id: VSI FW index 1638 * @lut_type: LUT table type 1639 * @lut: pointer to the LUT buffer provided by the caller 1640 * @lut_size: size of the LUT buffer 1641 * 1642 * get the RSS lookup table, PF or VSI type 1643 */ 1644 enum ice_status 1645 ice_aq_get_rss_lut(struct ice_hw *hw, u16 vsi_id, u8 lut_type, u8 *lut, 1646 u16 lut_size) 1647 { 1648 return __ice_aq_get_set_rss_lut(hw, vsi_id, lut_type, lut, lut_size, 0, 1649 false); 1650 } 1651 1652 /** 1653 * ice_aq_set_rss_lut 1654 * @hw: pointer to the hardware structure 1655 * @vsi_id: VSI FW index 1656 * @lut_type: LUT table type 1657 * @lut: pointer to the LUT buffer provided by the caller 1658 * @lut_size: size of the LUT buffer 1659 * 1660 * set the RSS lookup table, PF or VSI type 1661 */ 1662 enum ice_status 1663 ice_aq_set_rss_lut(struct ice_hw *hw, u16 vsi_id, u8 lut_type, u8 *lut, 1664 u16 lut_size) 1665 { 1666 return __ice_aq_get_set_rss_lut(hw, vsi_id, lut_type, lut, lut_size, 0, 1667 true); 1668 } 1669 1670 /** 1671 * __ice_aq_get_set_rss_key 1672 * @hw: pointer to the hw struct 1673 * @vsi_id: VSI FW index 1674 * @key: pointer to key info struct 1675 * @set: set true to set the key, false to get the key 1676 * 1677 * get (0x0B04) or set (0x0B02) the RSS key per VSI 1678 */ 1679 static enum 1680 ice_status __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id, 1681 struct ice_aqc_get_set_rss_keys *key, 1682 bool set) 1683 { 1684 struct ice_aqc_get_set_rss_key *cmd_resp; 1685 u16 key_size = sizeof(*key); 1686 struct ice_aq_desc desc; 1687 1688 cmd_resp = &desc.params.get_set_rss_key; 1689 1690 if (set) { 1691 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key); 1692 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 1693 } else { 1694 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key); 1695 } 1696 1697 cmd_resp->vsi_id = cpu_to_le16(((vsi_id << 1698 ICE_AQC_GSET_RSS_KEY_VSI_ID_S) & 1699 ICE_AQC_GSET_RSS_KEY_VSI_ID_M) | 1700 ICE_AQC_GSET_RSS_KEY_VSI_VALID); 1701 1702 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL); 1703 } 1704 1705 /** 1706 * ice_aq_get_rss_key 1707 * @hw: pointer to the hw struct 1708 * @vsi_id: VSI FW index 1709 * @key: pointer to key info struct 1710 * 1711 * get the RSS key per VSI 1712 */ 1713 enum ice_status 1714 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_id, 1715 struct ice_aqc_get_set_rss_keys *key) 1716 { 1717 return __ice_aq_get_set_rss_key(hw, vsi_id, key, false); 1718 } 1719 1720 /** 1721 * ice_aq_set_rss_key 1722 * @hw: pointer to the hw struct 1723 * @vsi_id: VSI FW index 1724 * @keys: pointer to key info struct 1725 * 1726 * set the RSS key per VSI 1727 */ 1728 enum ice_status 1729 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_id, 1730 struct ice_aqc_get_set_rss_keys *keys) 1731 { 1732 return __ice_aq_get_set_rss_key(hw, vsi_id, keys, true); 1733 } 1734 1735 /** 1736 * ice_aq_add_lan_txq 1737 * @hw: pointer to the hardware structure 1738 * @num_qgrps: Number of added queue groups 1739 * @qg_list: list of queue groups to be added 1740 * @buf_size: size of buffer for indirect command 1741 * @cd: pointer to command details structure or NULL 1742 * 1743 * Add Tx LAN queue (0x0C30) 1744 * 1745 * NOTE: 1746 * Prior to calling add Tx LAN queue: 1747 * Initialize the following as part of the Tx queue context: 1748 * Completion queue ID if the queue uses Completion queue, Quanta profile, 1749 * Cache profile and Packet shaper profile. 1750 * 1751 * After add Tx LAN queue AQ command is completed: 1752 * Interrupts should be associated with specific queues, 1753 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue 1754 * flow. 1755 */ 1756 static enum ice_status 1757 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps, 1758 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size, 1759 struct ice_sq_cd *cd) 1760 { 1761 u16 i, sum_header_size, sum_q_size = 0; 1762 struct ice_aqc_add_tx_qgrp *list; 1763 struct ice_aqc_add_txqs *cmd; 1764 struct ice_aq_desc desc; 1765 1766 cmd = &desc.params.add_txqs; 1767 1768 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs); 1769 1770 if (!qg_list) 1771 return ICE_ERR_PARAM; 1772 1773 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 1774 return ICE_ERR_PARAM; 1775 1776 sum_header_size = num_qgrps * 1777 (sizeof(*qg_list) - sizeof(*qg_list->txqs)); 1778 1779 list = qg_list; 1780 for (i = 0; i < num_qgrps; i++) { 1781 struct ice_aqc_add_txqs_perq *q = list->txqs; 1782 1783 sum_q_size += list->num_txqs * sizeof(*q); 1784 list = (struct ice_aqc_add_tx_qgrp *)(q + list->num_txqs); 1785 } 1786 1787 if (buf_size != (sum_header_size + sum_q_size)) 1788 return ICE_ERR_PARAM; 1789 1790 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 1791 1792 cmd->num_qgrps = num_qgrps; 1793 1794 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 1795 } 1796 1797 /** 1798 * ice_aq_dis_lan_txq 1799 * @hw: pointer to the hardware structure 1800 * @num_qgrps: number of groups in the list 1801 * @qg_list: the list of groups to disable 1802 * @buf_size: the total size of the qg_list buffer in bytes 1803 * @cd: pointer to command details structure or NULL 1804 * 1805 * Disable LAN Tx queue (0x0C31) 1806 */ 1807 static enum ice_status 1808 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps, 1809 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size, 1810 struct ice_sq_cd *cd) 1811 { 1812 struct ice_aqc_dis_txqs *cmd; 1813 struct ice_aq_desc desc; 1814 u16 i, sz = 0; 1815 1816 cmd = &desc.params.dis_txqs; 1817 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs); 1818 1819 if (!qg_list) 1820 return ICE_ERR_PARAM; 1821 1822 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 1823 return ICE_ERR_PARAM; 1824 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 1825 cmd->num_entries = num_qgrps; 1826 1827 for (i = 0; i < num_qgrps; ++i) { 1828 /* Calculate the size taken up by the queue IDs in this group */ 1829 sz += qg_list[i].num_qs * sizeof(qg_list[i].q_id); 1830 1831 /* Add the size of the group header */ 1832 sz += sizeof(qg_list[i]) - sizeof(qg_list[i].q_id); 1833 1834 /* If the num of queues is even, add 2 bytes of padding */ 1835 if ((qg_list[i].num_qs % 2) == 0) 1836 sz += 2; 1837 } 1838 1839 if (buf_size != sz) 1840 return ICE_ERR_PARAM; 1841 1842 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 1843 } 1844 1845 /* End of FW Admin Queue command wrappers */ 1846 1847 /** 1848 * ice_write_byte - write a byte to a packed context structure 1849 * @src_ctx: the context structure to read from 1850 * @dest_ctx: the context to be written to 1851 * @ce_info: a description of the struct to be filled 1852 */ 1853 static void ice_write_byte(u8 *src_ctx, u8 *dest_ctx, 1854 const struct ice_ctx_ele *ce_info) 1855 { 1856 u8 src_byte, dest_byte, mask; 1857 u8 *from, *dest; 1858 u16 shift_width; 1859 1860 /* copy from the next struct field */ 1861 from = src_ctx + ce_info->offset; 1862 1863 /* prepare the bits and mask */ 1864 shift_width = ce_info->lsb % 8; 1865 mask = (u8)(BIT(ce_info->width) - 1); 1866 1867 src_byte = *from; 1868 src_byte &= mask; 1869 1870 /* shift to correct alignment */ 1871 mask <<= shift_width; 1872 src_byte <<= shift_width; 1873 1874 /* get the current bits from the target bit string */ 1875 dest = dest_ctx + (ce_info->lsb / 8); 1876 1877 memcpy(&dest_byte, dest, sizeof(dest_byte)); 1878 1879 dest_byte &= ~mask; /* get the bits not changing */ 1880 dest_byte |= src_byte; /* add in the new bits */ 1881 1882 /* put it all back */ 1883 memcpy(dest, &dest_byte, sizeof(dest_byte)); 1884 } 1885 1886 /** 1887 * ice_write_word - write a word to a packed context structure 1888 * @src_ctx: the context structure to read from 1889 * @dest_ctx: the context to be written to 1890 * @ce_info: a description of the struct to be filled 1891 */ 1892 static void ice_write_word(u8 *src_ctx, u8 *dest_ctx, 1893 const struct ice_ctx_ele *ce_info) 1894 { 1895 u16 src_word, mask; 1896 __le16 dest_word; 1897 u8 *from, *dest; 1898 u16 shift_width; 1899 1900 /* copy from the next struct field */ 1901 from = src_ctx + ce_info->offset; 1902 1903 /* prepare the bits and mask */ 1904 shift_width = ce_info->lsb % 8; 1905 mask = BIT(ce_info->width) - 1; 1906 1907 /* don't swizzle the bits until after the mask because the mask bits 1908 * will be in a different bit position on big endian machines 1909 */ 1910 src_word = *(u16 *)from; 1911 src_word &= mask; 1912 1913 /* shift to correct alignment */ 1914 mask <<= shift_width; 1915 src_word <<= shift_width; 1916 1917 /* get the current bits from the target bit string */ 1918 dest = dest_ctx + (ce_info->lsb / 8); 1919 1920 memcpy(&dest_word, dest, sizeof(dest_word)); 1921 1922 dest_word &= ~(cpu_to_le16(mask)); /* get the bits not changing */ 1923 dest_word |= cpu_to_le16(src_word); /* add in the new bits */ 1924 1925 /* put it all back */ 1926 memcpy(dest, &dest_word, sizeof(dest_word)); 1927 } 1928 1929 /** 1930 * ice_write_dword - write a dword to a packed context structure 1931 * @src_ctx: the context structure to read from 1932 * @dest_ctx: the context to be written to 1933 * @ce_info: a description of the struct to be filled 1934 */ 1935 static void ice_write_dword(u8 *src_ctx, u8 *dest_ctx, 1936 const struct ice_ctx_ele *ce_info) 1937 { 1938 u32 src_dword, mask; 1939 __le32 dest_dword; 1940 u8 *from, *dest; 1941 u16 shift_width; 1942 1943 /* copy from the next struct field */ 1944 from = src_ctx + ce_info->offset; 1945 1946 /* prepare the bits and mask */ 1947 shift_width = ce_info->lsb % 8; 1948 1949 /* if the field width is exactly 32 on an x86 machine, then the shift 1950 * operation will not work because the SHL instructions count is masked 1951 * to 5 bits so the shift will do nothing 1952 */ 1953 if (ce_info->width < 32) 1954 mask = BIT(ce_info->width) - 1; 1955 else 1956 mask = (u32)~0; 1957 1958 /* don't swizzle the bits until after the mask because the mask bits 1959 * will be in a different bit position on big endian machines 1960 */ 1961 src_dword = *(u32 *)from; 1962 src_dword &= mask; 1963 1964 /* shift to correct alignment */ 1965 mask <<= shift_width; 1966 src_dword <<= shift_width; 1967 1968 /* get the current bits from the target bit string */ 1969 dest = dest_ctx + (ce_info->lsb / 8); 1970 1971 memcpy(&dest_dword, dest, sizeof(dest_dword)); 1972 1973 dest_dword &= ~(cpu_to_le32(mask)); /* get the bits not changing */ 1974 dest_dword |= cpu_to_le32(src_dword); /* add in the new bits */ 1975 1976 /* put it all back */ 1977 memcpy(dest, &dest_dword, sizeof(dest_dword)); 1978 } 1979 1980 /** 1981 * ice_write_qword - write a qword to a packed context structure 1982 * @src_ctx: the context structure to read from 1983 * @dest_ctx: the context to be written to 1984 * @ce_info: a description of the struct to be filled 1985 */ 1986 static void ice_write_qword(u8 *src_ctx, u8 *dest_ctx, 1987 const struct ice_ctx_ele *ce_info) 1988 { 1989 u64 src_qword, mask; 1990 __le64 dest_qword; 1991 u8 *from, *dest; 1992 u16 shift_width; 1993 1994 /* copy from the next struct field */ 1995 from = src_ctx + ce_info->offset; 1996 1997 /* prepare the bits and mask */ 1998 shift_width = ce_info->lsb % 8; 1999 2000 /* if the field width is exactly 64 on an x86 machine, then the shift 2001 * operation will not work because the SHL instructions count is masked 2002 * to 6 bits so the shift will do nothing 2003 */ 2004 if (ce_info->width < 64) 2005 mask = BIT_ULL(ce_info->width) - 1; 2006 else 2007 mask = (u64)~0; 2008 2009 /* don't swizzle the bits until after the mask because the mask bits 2010 * will be in a different bit position on big endian machines 2011 */ 2012 src_qword = *(u64 *)from; 2013 src_qword &= mask; 2014 2015 /* shift to correct alignment */ 2016 mask <<= shift_width; 2017 src_qword <<= shift_width; 2018 2019 /* get the current bits from the target bit string */ 2020 dest = dest_ctx + (ce_info->lsb / 8); 2021 2022 memcpy(&dest_qword, dest, sizeof(dest_qword)); 2023 2024 dest_qword &= ~(cpu_to_le64(mask)); /* get the bits not changing */ 2025 dest_qword |= cpu_to_le64(src_qword); /* add in the new bits */ 2026 2027 /* put it all back */ 2028 memcpy(dest, &dest_qword, sizeof(dest_qword)); 2029 } 2030 2031 /** 2032 * ice_set_ctx - set context bits in packed structure 2033 * @src_ctx: pointer to a generic non-packed context structure 2034 * @dest_ctx: pointer to memory for the packed structure 2035 * @ce_info: a description of the structure to be transformed 2036 */ 2037 enum ice_status 2038 ice_set_ctx(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 2039 { 2040 int f; 2041 2042 for (f = 0; ce_info[f].width; f++) { 2043 /* We have to deal with each element of the FW response 2044 * using the correct size so that we are correct regardless 2045 * of the endianness of the machine. 2046 */ 2047 switch (ce_info[f].size_of) { 2048 case sizeof(u8): 2049 ice_write_byte(src_ctx, dest_ctx, &ce_info[f]); 2050 break; 2051 case sizeof(u16): 2052 ice_write_word(src_ctx, dest_ctx, &ce_info[f]); 2053 break; 2054 case sizeof(u32): 2055 ice_write_dword(src_ctx, dest_ctx, &ce_info[f]); 2056 break; 2057 case sizeof(u64): 2058 ice_write_qword(src_ctx, dest_ctx, &ce_info[f]); 2059 break; 2060 default: 2061 return ICE_ERR_INVAL_SIZE; 2062 } 2063 } 2064 2065 return 0; 2066 } 2067 2068 /** 2069 * ice_ena_vsi_txq 2070 * @pi: port information structure 2071 * @vsi_id: VSI id 2072 * @tc: tc number 2073 * @num_qgrps: Number of added queue groups 2074 * @buf: list of queue groups to be added 2075 * @buf_size: size of buffer for indirect command 2076 * @cd: pointer to command details structure or NULL 2077 * 2078 * This function adds one lan q 2079 */ 2080 enum ice_status 2081 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_id, u8 tc, u8 num_qgrps, 2082 struct ice_aqc_add_tx_qgrp *buf, u16 buf_size, 2083 struct ice_sq_cd *cd) 2084 { 2085 struct ice_aqc_txsched_elem_data node = { 0 }; 2086 struct ice_sched_node *parent; 2087 enum ice_status status; 2088 struct ice_hw *hw; 2089 2090 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 2091 return ICE_ERR_CFG; 2092 2093 if (num_qgrps > 1 || buf->num_txqs > 1) 2094 return ICE_ERR_MAX_LIMIT; 2095 2096 hw = pi->hw; 2097 2098 mutex_lock(&pi->sched_lock); 2099 2100 /* find a parent node */ 2101 parent = ice_sched_get_free_qparent(pi, vsi_id, tc, 2102 ICE_SCHED_NODE_OWNER_LAN); 2103 if (!parent) { 2104 status = ICE_ERR_PARAM; 2105 goto ena_txq_exit; 2106 } 2107 buf->parent_teid = parent->info.node_teid; 2108 node.parent_teid = parent->info.node_teid; 2109 /* Mark that the values in the "generic" section as valid. The default 2110 * value in the "generic" section is zero. This means that : 2111 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0. 2112 * - 0 priority among siblings, indicated by Bit 1-3. 2113 * - WFQ, indicated by Bit 4. 2114 * - 0 Adjustment value is used in PSM credit update flow, indicated by 2115 * Bit 5-6. 2116 * - Bit 7 is reserved. 2117 * Without setting the generic section as valid in valid_sections, the 2118 * Admin Q command will fail with error code ICE_AQ_RC_EINVAL. 2119 */ 2120 buf->txqs[0].info.valid_sections = ICE_AQC_ELEM_VALID_GENERIC; 2121 2122 /* add the lan q */ 2123 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd); 2124 if (status) 2125 goto ena_txq_exit; 2126 2127 node.node_teid = buf->txqs[0].q_teid; 2128 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; 2129 2130 /* add a leaf node into schduler tree q layer */ 2131 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node); 2132 2133 ena_txq_exit: 2134 mutex_unlock(&pi->sched_lock); 2135 return status; 2136 } 2137 2138 /** 2139 * ice_dis_vsi_txq 2140 * @pi: port information structure 2141 * @num_queues: number of queues 2142 * @q_ids: pointer to the q_id array 2143 * @q_teids: pointer to queue node teids 2144 * @cd: pointer to command details structure or NULL 2145 * 2146 * This function removes queues and their corresponding nodes in SW DB 2147 */ 2148 enum ice_status 2149 ice_dis_vsi_txq(struct ice_port_info *pi, u8 num_queues, u16 *q_ids, 2150 u32 *q_teids, struct ice_sq_cd *cd) 2151 { 2152 enum ice_status status = ICE_ERR_DOES_NOT_EXIST; 2153 struct ice_aqc_dis_txq_item qg_list; 2154 u16 i; 2155 2156 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 2157 return ICE_ERR_CFG; 2158 2159 mutex_lock(&pi->sched_lock); 2160 2161 for (i = 0; i < num_queues; i++) { 2162 struct ice_sched_node *node; 2163 2164 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]); 2165 if (!node) 2166 continue; 2167 qg_list.parent_teid = node->info.parent_teid; 2168 qg_list.num_qs = 1; 2169 qg_list.q_id[0] = cpu_to_le16(q_ids[i]); 2170 status = ice_aq_dis_lan_txq(pi->hw, 1, &qg_list, 2171 sizeof(qg_list), cd); 2172 2173 if (status) 2174 break; 2175 ice_free_sched_node(pi, node); 2176 } 2177 mutex_unlock(&pi->sched_lock); 2178 return status; 2179 } 2180 2181 /** 2182 * ice_cfg_vsi_qs - configure the new/exisiting VSI queues 2183 * @pi: port information structure 2184 * @vsi_id: VSI Id 2185 * @tc_bitmap: TC bitmap 2186 * @maxqs: max queues array per TC 2187 * @owner: lan or rdma 2188 * 2189 * This function adds/updates the VSI queues per TC. 2190 */ 2191 static enum ice_status 2192 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_id, u8 tc_bitmap, 2193 u16 *maxqs, u8 owner) 2194 { 2195 enum ice_status status = 0; 2196 u8 i; 2197 2198 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 2199 return ICE_ERR_CFG; 2200 2201 mutex_lock(&pi->sched_lock); 2202 2203 for (i = 0; i < ICE_MAX_TRAFFIC_CLASS; i++) { 2204 /* configuration is possible only if TC node is present */ 2205 if (!ice_sched_get_tc_node(pi, i)) 2206 continue; 2207 2208 status = ice_sched_cfg_vsi(pi, vsi_id, i, maxqs[i], owner, 2209 ice_is_tc_ena(tc_bitmap, i)); 2210 if (status) 2211 break; 2212 } 2213 2214 mutex_unlock(&pi->sched_lock); 2215 return status; 2216 } 2217 2218 /** 2219 * ice_cfg_vsi_lan - configure VSI lan queues 2220 * @pi: port information structure 2221 * @vsi_id: VSI Id 2222 * @tc_bitmap: TC bitmap 2223 * @max_lanqs: max lan queues array per TC 2224 * 2225 * This function adds/updates the VSI lan queues per TC. 2226 */ 2227 enum ice_status 2228 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_id, u8 tc_bitmap, 2229 u16 *max_lanqs) 2230 { 2231 return ice_cfg_vsi_qs(pi, vsi_id, tc_bitmap, max_lanqs, 2232 ICE_SCHED_NODE_OWNER_LAN); 2233 } 2234