1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * This file contains work-arounds for many known PCI hardware 4 * bugs. Devices present only on certain architectures (host 5 * bridges et cetera) should be handled in arch-specific code. 6 * 7 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init. 8 * 9 * Copyright (c) 1999 Martin Mares <mj@ucw.cz> 10 * 11 * Init/reset quirks for USB host controllers should be in the 12 * USB quirks file, where their drivers can access reuse it. 13 */ 14 15 #include <linux/types.h> 16 #include <linux/kernel.h> 17 #include <linux/export.h> 18 #include <linux/pci.h> 19 #include <linux/init.h> 20 #include <linux/delay.h> 21 #include <linux/acpi.h> 22 #include <linux/dmi.h> 23 #include <linux/pci-aspm.h> 24 #include <linux/ioport.h> 25 #include <linux/sched.h> 26 #include <linux/ktime.h> 27 #include <linux/mm.h> 28 #include <linux/platform_data/x86/apple.h> 29 #include <linux/pm_runtime.h> 30 #include <asm/dma.h> /* isa_dma_bridge_buggy */ 31 #include "pci.h" 32 33 /* 34 * Decoding should be disabled for a PCI device during BAR sizing to avoid 35 * conflict. But doing so may cause problems on host bridge and perhaps other 36 * key system devices. For devices that need to have mmio decoding always-on, 37 * we need to set the dev->mmio_always_on bit. 38 */ 39 static void quirk_mmio_always_on(struct pci_dev *dev) 40 { 41 dev->mmio_always_on = 1; 42 } 43 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID, 44 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on); 45 46 /* The Mellanox Tavor device gives false positive parity errors 47 * Mark this device with a broken_parity_status, to allow 48 * PCI scanning code to "skip" this now blacklisted device. 49 */ 50 static void quirk_mellanox_tavor(struct pci_dev *dev) 51 { 52 dev->broken_parity_status = 1; /* This device gives false positives */ 53 } 54 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, quirk_mellanox_tavor); 55 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, quirk_mellanox_tavor); 56 57 /* Deal with broken BIOSes that neglect to enable passive release, 58 which can cause problems in combination with the 82441FX/PPro MTRRs */ 59 static void quirk_passive_release(struct pci_dev *dev) 60 { 61 struct pci_dev *d = NULL; 62 unsigned char dlc; 63 64 /* We have to make sure a particular bit is set in the PIIX3 65 ISA bridge, so we have to go out and find it. */ 66 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) { 67 pci_read_config_byte(d, 0x82, &dlc); 68 if (!(dlc & 1<<1)) { 69 pci_info(d, "PIIX3: Enabling Passive Release\n"); 70 dlc |= 1<<1; 71 pci_write_config_byte(d, 0x82, dlc); 72 } 73 } 74 } 75 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); 76 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); 77 78 /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround 79 but VIA don't answer queries. If you happen to have good contacts at VIA 80 ask them for me please -- Alan 81 82 This appears to be BIOS not version dependent. So presumably there is a 83 chipset level fix */ 84 85 static void quirk_isa_dma_hangs(struct pci_dev *dev) 86 { 87 if (!isa_dma_bridge_buggy) { 88 isa_dma_bridge_buggy = 1; 89 pci_info(dev, "Activating ISA DMA hang workarounds\n"); 90 } 91 } 92 /* 93 * Its not totally clear which chipsets are the problematic ones 94 * We know 82C586 and 82C596 variants are affected. 95 */ 96 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs); 97 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs); 98 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs); 99 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs); 100 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs); 101 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs); 102 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs); 103 104 /* 105 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear 106 * for some HT machines to use C4 w/o hanging. 107 */ 108 static void quirk_tigerpoint_bm_sts(struct pci_dev *dev) 109 { 110 u32 pmbase; 111 u16 pm1a; 112 113 pci_read_config_dword(dev, 0x40, &pmbase); 114 pmbase = pmbase & 0xff80; 115 pm1a = inw(pmbase); 116 117 if (pm1a & 0x10) { 118 pci_info(dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n"); 119 outw(0x10, pmbase); 120 } 121 } 122 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts); 123 124 /* 125 * Chipsets where PCI->PCI transfers vanish or hang 126 */ 127 static void quirk_nopcipci(struct pci_dev *dev) 128 { 129 if ((pci_pci_problems & PCIPCI_FAIL) == 0) { 130 pci_info(dev, "Disabling direct PCI/PCI transfers\n"); 131 pci_pci_problems |= PCIPCI_FAIL; 132 } 133 } 134 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci); 135 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci); 136 137 static void quirk_nopciamd(struct pci_dev *dev) 138 { 139 u8 rev; 140 pci_read_config_byte(dev, 0x08, &rev); 141 if (rev == 0x13) { 142 /* Erratum 24 */ 143 pci_info(dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n"); 144 pci_pci_problems |= PCIAGP_FAIL; 145 } 146 } 147 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd); 148 149 /* 150 * Triton requires workarounds to be used by the drivers 151 */ 152 static void quirk_triton(struct pci_dev *dev) 153 { 154 if ((pci_pci_problems&PCIPCI_TRITON) == 0) { 155 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 156 pci_pci_problems |= PCIPCI_TRITON; 157 } 158 } 159 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton); 160 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton); 161 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton); 162 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton); 163 164 /* 165 * VIA Apollo KT133 needs PCI latency patch 166 * Made according to a windows driver based patch by George E. Breese 167 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm 168 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for 169 * the info on which Mr Breese based his work. 170 * 171 * Updated based on further information from the site and also on 172 * information provided by VIA 173 */ 174 static void quirk_vialatency(struct pci_dev *dev) 175 { 176 struct pci_dev *p; 177 u8 busarb; 178 /* Ok we have a potential problem chipset here. Now see if we have 179 a buggy southbridge */ 180 181 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL); 182 if (p != NULL) { 183 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */ 184 /* Check for buggy part revisions */ 185 if (p->revision < 0x40 || p->revision > 0x42) 186 goto exit; 187 } else { 188 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL); 189 if (p == NULL) /* No problem parts */ 190 goto exit; 191 /* Check for buggy part revisions */ 192 if (p->revision < 0x10 || p->revision > 0x12) 193 goto exit; 194 } 195 196 /* 197 * Ok we have the problem. Now set the PCI master grant to 198 * occur every master grant. The apparent bug is that under high 199 * PCI load (quite common in Linux of course) you can get data 200 * loss when the CPU is held off the bus for 3 bus master requests 201 * This happens to include the IDE controllers.... 202 * 203 * VIA only apply this fix when an SB Live! is present but under 204 * both Linux and Windows this isn't enough, and we have seen 205 * corruption without SB Live! but with things like 3 UDMA IDE 206 * controllers. So we ignore that bit of the VIA recommendation.. 207 */ 208 209 pci_read_config_byte(dev, 0x76, &busarb); 210 /* Set bit 4 and bi 5 of byte 76 to 0x01 211 "Master priority rotation on every PCI master grant */ 212 busarb &= ~(1<<5); 213 busarb |= (1<<4); 214 pci_write_config_byte(dev, 0x76, busarb); 215 pci_info(dev, "Applying VIA southbridge workaround\n"); 216 exit: 217 pci_dev_put(p); 218 } 219 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); 220 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); 221 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); 222 /* Must restore this on a resume from RAM */ 223 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); 224 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); 225 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); 226 227 /* 228 * VIA Apollo VP3 needs ETBF on BT848/878 229 */ 230 static void quirk_viaetbf(struct pci_dev *dev) 231 { 232 if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) { 233 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 234 pci_pci_problems |= PCIPCI_VIAETBF; 235 } 236 } 237 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf); 238 239 static void quirk_vsfx(struct pci_dev *dev) 240 { 241 if ((pci_pci_problems&PCIPCI_VSFX) == 0) { 242 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 243 pci_pci_problems |= PCIPCI_VSFX; 244 } 245 } 246 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx); 247 248 /* 249 * Ali Magik requires workarounds to be used by the drivers 250 * that DMA to AGP space. Latency must be set to 0xA and triton 251 * workaround applied too 252 * [Info kindly provided by ALi] 253 */ 254 static void quirk_alimagik(struct pci_dev *dev) 255 { 256 if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) { 257 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 258 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON; 259 } 260 } 261 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik); 262 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik); 263 264 /* 265 * Natoma has some interesting boundary conditions with Zoran stuff 266 * at least 267 */ 268 static void quirk_natoma(struct pci_dev *dev) 269 { 270 if ((pci_pci_problems&PCIPCI_NATOMA) == 0) { 271 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 272 pci_pci_problems |= PCIPCI_NATOMA; 273 } 274 } 275 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma); 276 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma); 277 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma); 278 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma); 279 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma); 280 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma); 281 282 /* 283 * This chip can cause PCI parity errors if config register 0xA0 is read 284 * while DMAs are occurring. 285 */ 286 static void quirk_citrine(struct pci_dev *dev) 287 { 288 dev->cfg_size = 0xA0; 289 } 290 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine); 291 292 /* 293 * This chip can cause bus lockups if config addresses above 0x600 294 * are read or written. 295 */ 296 static void quirk_nfp6000(struct pci_dev *dev) 297 { 298 dev->cfg_size = 0x600; 299 } 300 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP4000, quirk_nfp6000); 301 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000, quirk_nfp6000); 302 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000_VF, quirk_nfp6000); 303 304 /* On IBM Crocodile ipr SAS adapters, expand BAR to system page size */ 305 static void quirk_extend_bar_to_page(struct pci_dev *dev) 306 { 307 int i; 308 309 for (i = 0; i <= PCI_STD_RESOURCE_END; i++) { 310 struct resource *r = &dev->resource[i]; 311 312 if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) { 313 r->end = PAGE_SIZE - 1; 314 r->start = 0; 315 r->flags |= IORESOURCE_UNSET; 316 pci_info(dev, "expanded BAR %d to page size: %pR\n", 317 i, r); 318 } 319 } 320 } 321 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page); 322 323 /* 324 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M. 325 * If it's needed, re-allocate the region. 326 */ 327 static void quirk_s3_64M(struct pci_dev *dev) 328 { 329 struct resource *r = &dev->resource[0]; 330 331 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) { 332 r->flags |= IORESOURCE_UNSET; 333 r->start = 0; 334 r->end = 0x3ffffff; 335 } 336 } 337 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M); 338 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M); 339 340 static void quirk_io(struct pci_dev *dev, int pos, unsigned size, 341 const char *name) 342 { 343 u32 region; 344 struct pci_bus_region bus_region; 345 struct resource *res = dev->resource + pos; 346 347 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), ®ion); 348 349 if (!region) 350 return; 351 352 res->name = pci_name(dev); 353 res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK; 354 res->flags |= 355 (IORESOURCE_IO | IORESOURCE_PCI_FIXED | IORESOURCE_SIZEALIGN); 356 region &= ~(size - 1); 357 358 /* Convert from PCI bus to resource space */ 359 bus_region.start = region; 360 bus_region.end = region + size - 1; 361 pcibios_bus_to_resource(dev->bus, res, &bus_region); 362 363 pci_info(dev, FW_BUG "%s quirk: reg 0x%x: %pR\n", 364 name, PCI_BASE_ADDRESS_0 + (pos << 2), res); 365 } 366 367 /* 368 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS 369 * ver. 1.33 20070103) don't set the correct ISA PCI region header info. 370 * BAR0 should be 8 bytes; instead, it may be set to something like 8k 371 * (which conflicts w/ BAR1's memory range). 372 * 373 * CS553x's ISA PCI BARs may also be read-only (ref: 374 * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward). 375 */ 376 static void quirk_cs5536_vsa(struct pci_dev *dev) 377 { 378 static char *name = "CS5536 ISA bridge"; 379 380 if (pci_resource_len(dev, 0) != 8) { 381 quirk_io(dev, 0, 8, name); /* SMB */ 382 quirk_io(dev, 1, 256, name); /* GPIO */ 383 quirk_io(dev, 2, 64, name); /* MFGPT */ 384 pci_info(dev, "%s bug detected (incorrect header); workaround applied\n", 385 name); 386 } 387 } 388 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa); 389 390 static void quirk_io_region(struct pci_dev *dev, int port, 391 unsigned size, int nr, const char *name) 392 { 393 u16 region; 394 struct pci_bus_region bus_region; 395 struct resource *res = dev->resource + nr; 396 397 pci_read_config_word(dev, port, ®ion); 398 region &= ~(size - 1); 399 400 if (!region) 401 return; 402 403 res->name = pci_name(dev); 404 res->flags = IORESOURCE_IO; 405 406 /* Convert from PCI bus to resource space */ 407 bus_region.start = region; 408 bus_region.end = region + size - 1; 409 pcibios_bus_to_resource(dev->bus, res, &bus_region); 410 411 if (!pci_claim_resource(dev, nr)) 412 pci_info(dev, "quirk: %pR claimed by %s\n", res, name); 413 } 414 415 /* 416 * ATI Northbridge setups MCE the processor if you even 417 * read somewhere between 0x3b0->0x3bb or read 0x3d3 418 */ 419 static void quirk_ati_exploding_mce(struct pci_dev *dev) 420 { 421 pci_info(dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n"); 422 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */ 423 request_region(0x3b0, 0x0C, "RadeonIGP"); 424 request_region(0x3d3, 0x01, "RadeonIGP"); 425 } 426 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce); 427 428 /* 429 * In the AMD NL platform, this device ([1022:7912]) has a class code of 430 * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will 431 * claim it. 432 * But the dwc3 driver is a more specific driver for this device, and we'd 433 * prefer to use it instead of xhci. To prevent xhci from claiming the 434 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec 435 * defines as "USB device (not host controller)". The dwc3 driver can then 436 * claim it based on its Vendor and Device ID. 437 */ 438 static void quirk_amd_nl_class(struct pci_dev *pdev) 439 { 440 u32 class = pdev->class; 441 442 /* Use "USB Device (not host controller)" class */ 443 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE; 444 pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n", 445 class, pdev->class); 446 } 447 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB, 448 quirk_amd_nl_class); 449 450 /* 451 * Let's make the southbridge information explicit instead 452 * of having to worry about people probing the ACPI areas, 453 * for example.. (Yes, it happens, and if you read the wrong 454 * ACPI register it will put the machine to sleep with no 455 * way of waking it up again. Bummer). 456 * 457 * ALI M7101: Two IO regions pointed to by words at 458 * 0xE0 (64 bytes of ACPI registers) 459 * 0xE2 (32 bytes of SMB registers) 460 */ 461 static void quirk_ali7101_acpi(struct pci_dev *dev) 462 { 463 quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI"); 464 quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB"); 465 } 466 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi); 467 468 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 469 { 470 u32 devres; 471 u32 mask, size, base; 472 473 pci_read_config_dword(dev, port, &devres); 474 if ((devres & enable) != enable) 475 return; 476 mask = (devres >> 16) & 15; 477 base = devres & 0xffff; 478 size = 16; 479 for (;;) { 480 unsigned bit = size >> 1; 481 if ((bit & mask) == bit) 482 break; 483 size = bit; 484 } 485 /* 486 * For now we only print it out. Eventually we'll want to 487 * reserve it (at least if it's in the 0x1000+ range), but 488 * let's get enough confirmation reports first. 489 */ 490 base &= -size; 491 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1); 492 } 493 494 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 495 { 496 u32 devres; 497 u32 mask, size, base; 498 499 pci_read_config_dword(dev, port, &devres); 500 if ((devres & enable) != enable) 501 return; 502 base = devres & 0xffff0000; 503 mask = (devres & 0x3f) << 16; 504 size = 128 << 16; 505 for (;;) { 506 unsigned bit = size >> 1; 507 if ((bit & mask) == bit) 508 break; 509 size = bit; 510 } 511 /* 512 * For now we only print it out. Eventually we'll want to 513 * reserve it, but let's get enough confirmation reports first. 514 */ 515 base &= -size; 516 pci_info(dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1); 517 } 518 519 /* 520 * PIIX4 ACPI: Two IO regions pointed to by longwords at 521 * 0x40 (64 bytes of ACPI registers) 522 * 0x90 (16 bytes of SMB registers) 523 * and a few strange programmable PIIX4 device resources. 524 */ 525 static void quirk_piix4_acpi(struct pci_dev *dev) 526 { 527 u32 res_a; 528 529 quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI"); 530 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB"); 531 532 /* Device resource A has enables for some of the other ones */ 533 pci_read_config_dword(dev, 0x5c, &res_a); 534 535 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21); 536 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21); 537 538 /* Device resource D is just bitfields for static resources */ 539 540 /* Device 12 enabled? */ 541 if (res_a & (1 << 29)) { 542 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20); 543 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7); 544 } 545 /* Device 13 enabled? */ 546 if (res_a & (1 << 30)) { 547 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20); 548 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7); 549 } 550 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20); 551 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20); 552 } 553 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi); 554 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi); 555 556 #define ICH_PMBASE 0x40 557 #define ICH_ACPI_CNTL 0x44 558 #define ICH4_ACPI_EN 0x10 559 #define ICH6_ACPI_EN 0x80 560 #define ICH4_GPIOBASE 0x58 561 #define ICH4_GPIO_CNTL 0x5c 562 #define ICH4_GPIO_EN 0x10 563 #define ICH6_GPIOBASE 0x48 564 #define ICH6_GPIO_CNTL 0x4c 565 #define ICH6_GPIO_EN 0x10 566 567 /* 568 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at 569 * 0x40 (128 bytes of ACPI, GPIO & TCO registers) 570 * 0x58 (64 bytes of GPIO I/O space) 571 */ 572 static void quirk_ich4_lpc_acpi(struct pci_dev *dev) 573 { 574 u8 enable; 575 576 /* 577 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict 578 * with low legacy (and fixed) ports. We don't know the decoding 579 * priority and can't tell whether the legacy device or the one created 580 * here is really at that address. This happens on boards with broken 581 * BIOSes. 582 */ 583 584 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); 585 if (enable & ICH4_ACPI_EN) 586 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES, 587 "ICH4 ACPI/GPIO/TCO"); 588 589 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable); 590 if (enable & ICH4_GPIO_EN) 591 quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1, 592 "ICH4 GPIO"); 593 } 594 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi); 595 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi); 596 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi); 597 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi); 598 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi); 599 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi); 600 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi); 601 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi); 602 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi); 603 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi); 604 605 static void ich6_lpc_acpi_gpio(struct pci_dev *dev) 606 { 607 u8 enable; 608 609 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); 610 if (enable & ICH6_ACPI_EN) 611 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES, 612 "ICH6 ACPI/GPIO/TCO"); 613 614 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable); 615 if (enable & ICH6_GPIO_EN) 616 quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1, 617 "ICH6 GPIO"); 618 } 619 620 static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize) 621 { 622 u32 val; 623 u32 size, base; 624 625 pci_read_config_dword(dev, reg, &val); 626 627 /* Enabled? */ 628 if (!(val & 1)) 629 return; 630 base = val & 0xfffc; 631 if (dynsize) { 632 /* 633 * This is not correct. It is 16, 32 or 64 bytes depending on 634 * register D31:F0:ADh bits 5:4. 635 * 636 * But this gets us at least _part_ of it. 637 */ 638 size = 16; 639 } else { 640 size = 128; 641 } 642 base &= ~(size-1); 643 644 /* Just print it out for now. We should reserve it after more debugging */ 645 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base+size-1); 646 } 647 648 static void quirk_ich6_lpc(struct pci_dev *dev) 649 { 650 /* Shared ACPI/GPIO decode with all ICH6+ */ 651 ich6_lpc_acpi_gpio(dev); 652 653 /* ICH6-specific generic IO decode */ 654 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0); 655 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1); 656 } 657 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc); 658 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc); 659 660 static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name) 661 { 662 u32 val; 663 u32 mask, base; 664 665 pci_read_config_dword(dev, reg, &val); 666 667 /* Enabled? */ 668 if (!(val & 1)) 669 return; 670 671 /* 672 * IO base in bits 15:2, mask in bits 23:18, both 673 * are dword-based 674 */ 675 base = val & 0xfffc; 676 mask = (val >> 16) & 0xfc; 677 mask |= 3; 678 679 /* Just print it out for now. We should reserve it after more debugging */ 680 pci_info(dev, "%s PIO at %04x (mask %04x)\n", name, base, mask); 681 } 682 683 /* ICH7-10 has the same common LPC generic IO decode registers */ 684 static void quirk_ich7_lpc(struct pci_dev *dev) 685 { 686 /* We share the common ACPI/GPIO decode with ICH6 */ 687 ich6_lpc_acpi_gpio(dev); 688 689 /* And have 4 ICH7+ generic decodes */ 690 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1"); 691 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2"); 692 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3"); 693 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4"); 694 } 695 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc); 696 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc); 697 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc); 698 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc); 699 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc); 700 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc); 701 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc); 702 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc); 703 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc); 704 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc); 705 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc); 706 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc); 707 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc); 708 709 /* 710 * VIA ACPI: One IO region pointed to by longword at 711 * 0x48 or 0x20 (256 bytes of ACPI registers) 712 */ 713 static void quirk_vt82c586_acpi(struct pci_dev *dev) 714 { 715 if (dev->revision & 0x10) 716 quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES, 717 "vt82c586 ACPI"); 718 } 719 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi); 720 721 /* 722 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at 723 * 0x48 (256 bytes of ACPI registers) 724 * 0x70 (128 bytes of hardware monitoring register) 725 * 0x90 (16 bytes of SMB registers) 726 */ 727 static void quirk_vt82c686_acpi(struct pci_dev *dev) 728 { 729 quirk_vt82c586_acpi(dev); 730 731 quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1, 732 "vt82c686 HW-mon"); 733 734 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB"); 735 } 736 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi); 737 738 /* 739 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at 740 * 0x88 (128 bytes of power management registers) 741 * 0xd0 (16 bytes of SMB registers) 742 */ 743 static void quirk_vt8235_acpi(struct pci_dev *dev) 744 { 745 quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM"); 746 quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB"); 747 } 748 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi); 749 750 /* 751 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast back-to-back: 752 * Disable fast back-to-back on the secondary bus segment 753 */ 754 static void quirk_xio2000a(struct pci_dev *dev) 755 { 756 struct pci_dev *pdev; 757 u16 command; 758 759 pci_warn(dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n"); 760 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) { 761 pci_read_config_word(pdev, PCI_COMMAND, &command); 762 if (command & PCI_COMMAND_FAST_BACK) 763 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK); 764 } 765 } 766 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A, 767 quirk_xio2000a); 768 769 #ifdef CONFIG_X86_IO_APIC 770 771 #include <asm/io_apic.h> 772 773 /* 774 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip 775 * devices to the external APIC. 776 * 777 * TODO: When we have device-specific interrupt routers, 778 * this code will go away from quirks. 779 */ 780 static void quirk_via_ioapic(struct pci_dev *dev) 781 { 782 u8 tmp; 783 784 if (nr_ioapics < 1) 785 tmp = 0; /* nothing routed to external APIC */ 786 else 787 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */ 788 789 pci_info(dev, "%sbling VIA external APIC routing\n", 790 tmp == 0 ? "Disa" : "Ena"); 791 792 /* Offset 0x58: External APIC IRQ output control */ 793 pci_write_config_byte(dev, 0x58, tmp); 794 } 795 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); 796 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); 797 798 /* 799 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit. 800 * This leads to doubled level interrupt rates. 801 * Set this bit to get rid of cycle wastage. 802 * Otherwise uncritical. 803 */ 804 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev) 805 { 806 u8 misc_control2; 807 #define BYPASS_APIC_DEASSERT 8 808 809 pci_read_config_byte(dev, 0x5B, &misc_control2); 810 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) { 811 pci_info(dev, "Bypassing VIA 8237 APIC De-Assert Message\n"); 812 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT); 813 } 814 } 815 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); 816 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); 817 818 /* 819 * The AMD io apic can hang the box when an apic irq is masked. 820 * We check all revs >= B0 (yet not in the pre production!) as the bug 821 * is currently marked NoFix 822 * 823 * We have multiple reports of hangs with this chipset that went away with 824 * noapic specified. For the moment we assume it's the erratum. We may be wrong 825 * of course. However the advice is demonstrably good even if so.. 826 */ 827 static void quirk_amd_ioapic(struct pci_dev *dev) 828 { 829 if (dev->revision >= 0x02) { 830 pci_warn(dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n"); 831 pci_warn(dev, " : booting with the \"noapic\" option\n"); 832 } 833 } 834 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic); 835 #endif /* CONFIG_X86_IO_APIC */ 836 837 #if defined(CONFIG_ARM64) && defined(CONFIG_PCI_ATS) 838 839 static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev) 840 { 841 /* Fix for improper SRIOV configuration on Cavium cn88xx RNM device */ 842 if (dev->subsystem_device == 0xa118) 843 dev->sriov->link = dev->devfn; 844 } 845 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link); 846 #endif 847 848 /* 849 * Some settings of MMRBC can lead to data corruption so block changes. 850 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide 851 */ 852 static void quirk_amd_8131_mmrbc(struct pci_dev *dev) 853 { 854 if (dev->subordinate && dev->revision <= 0x12) { 855 pci_info(dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n", 856 dev->revision); 857 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC; 858 } 859 } 860 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc); 861 862 /* 863 * FIXME: it is questionable that quirk_via_acpi 864 * is needed. It shows up as an ISA bridge, and does not 865 * support the PCI_INTERRUPT_LINE register at all. Therefore 866 * it seems like setting the pci_dev's 'irq' to the 867 * value of the ACPI SCI interrupt is only done for convenience. 868 * -jgarzik 869 */ 870 static void quirk_via_acpi(struct pci_dev *d) 871 { 872 /* 873 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42 874 */ 875 u8 irq; 876 pci_read_config_byte(d, 0x42, &irq); 877 irq &= 0xf; 878 if (irq && (irq != 2)) 879 d->irq = irq; 880 } 881 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi); 882 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi); 883 884 885 /* 886 * VIA bridges which have VLink 887 */ 888 889 static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18; 890 891 static void quirk_via_bridge(struct pci_dev *dev) 892 { 893 /* See what bridge we have and find the device ranges */ 894 switch (dev->device) { 895 case PCI_DEVICE_ID_VIA_82C686: 896 /* The VT82C686 is special, it attaches to PCI and can have 897 any device number. All its subdevices are functions of 898 that single device. */ 899 via_vlink_dev_lo = PCI_SLOT(dev->devfn); 900 via_vlink_dev_hi = PCI_SLOT(dev->devfn); 901 break; 902 case PCI_DEVICE_ID_VIA_8237: 903 case PCI_DEVICE_ID_VIA_8237A: 904 via_vlink_dev_lo = 15; 905 break; 906 case PCI_DEVICE_ID_VIA_8235: 907 via_vlink_dev_lo = 16; 908 break; 909 case PCI_DEVICE_ID_VIA_8231: 910 case PCI_DEVICE_ID_VIA_8233_0: 911 case PCI_DEVICE_ID_VIA_8233A: 912 case PCI_DEVICE_ID_VIA_8233C_0: 913 via_vlink_dev_lo = 17; 914 break; 915 } 916 } 917 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge); 918 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge); 919 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge); 920 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge); 921 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge); 922 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge); 923 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge); 924 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge); 925 926 /** 927 * quirk_via_vlink - VIA VLink IRQ number update 928 * @dev: PCI device 929 * 930 * If the device we are dealing with is on a PIC IRQ we need to 931 * ensure that the IRQ line register which usually is not relevant 932 * for PCI cards, is actually written so that interrupts get sent 933 * to the right place. 934 * We only do this on systems where a VIA south bridge was detected, 935 * and only for VIA devices on the motherboard (see quirk_via_bridge 936 * above). 937 */ 938 939 static void quirk_via_vlink(struct pci_dev *dev) 940 { 941 u8 irq, new_irq; 942 943 /* Check if we have VLink at all */ 944 if (via_vlink_dev_lo == -1) 945 return; 946 947 new_irq = dev->irq; 948 949 /* Don't quirk interrupts outside the legacy IRQ range */ 950 if (!new_irq || new_irq > 15) 951 return; 952 953 /* Internal device ? */ 954 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi || 955 PCI_SLOT(dev->devfn) < via_vlink_dev_lo) 956 return; 957 958 /* This is an internal VLink device on a PIC interrupt. The BIOS 959 ought to have set this but may not have, so we redo it */ 960 961 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); 962 if (new_irq != irq) { 963 pci_info(dev, "VIA VLink IRQ fixup, from %d to %d\n", 964 irq, new_irq); 965 udelay(15); /* unknown if delay really needed */ 966 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq); 967 } 968 } 969 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink); 970 971 /* 972 * VIA VT82C598 has its device ID settable and many BIOSes 973 * set it to the ID of VT82C597 for backward compatibility. 974 * We need to switch it off to be able to recognize the real 975 * type of the chip. 976 */ 977 static void quirk_vt82c598_id(struct pci_dev *dev) 978 { 979 pci_write_config_byte(dev, 0xfc, 0); 980 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device); 981 } 982 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id); 983 984 /* 985 * CardBus controllers have a legacy base address that enables them 986 * to respond as i82365 pcmcia controllers. We don't want them to 987 * do this even if the Linux CardBus driver is not loaded, because 988 * the Linux i82365 driver does not (and should not) handle CardBus. 989 */ 990 static void quirk_cardbus_legacy(struct pci_dev *dev) 991 { 992 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0); 993 } 994 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID, 995 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy); 996 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID, 997 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy); 998 999 /* 1000 * Following the PCI ordering rules is optional on the AMD762. I'm not 1001 * sure what the designers were smoking but let's not inhale... 1002 * 1003 * To be fair to AMD, it follows the spec by default, its BIOS people 1004 * who turn it off! 1005 */ 1006 static void quirk_amd_ordering(struct pci_dev *dev) 1007 { 1008 u32 pcic; 1009 pci_read_config_dword(dev, 0x4C, &pcic); 1010 if ((pcic & 6) != 6) { 1011 pcic |= 6; 1012 pci_warn(dev, "BIOS failed to enable PCI standards compliance; fixing this error\n"); 1013 pci_write_config_dword(dev, 0x4C, pcic); 1014 pci_read_config_dword(dev, 0x84, &pcic); 1015 pcic |= (1 << 23); /* Required in this mode */ 1016 pci_write_config_dword(dev, 0x84, pcic); 1017 } 1018 } 1019 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); 1020 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); 1021 1022 /* 1023 * DreamWorks provided workaround for Dunord I-3000 problem 1024 * 1025 * This card decodes and responds to addresses not apparently 1026 * assigned to it. We force a larger allocation to ensure that 1027 * nothing gets put too close to it. 1028 */ 1029 static void quirk_dunord(struct pci_dev *dev) 1030 { 1031 struct resource *r = &dev->resource[1]; 1032 1033 r->flags |= IORESOURCE_UNSET; 1034 r->start = 0; 1035 r->end = 0xffffff; 1036 } 1037 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord); 1038 1039 /* 1040 * i82380FB mobile docking controller: its PCI-to-PCI bridge 1041 * is subtractive decoding (transparent), and does indicate this 1042 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80 1043 * instead of 0x01. 1044 */ 1045 static void quirk_transparent_bridge(struct pci_dev *dev) 1046 { 1047 dev->transparent = 1; 1048 } 1049 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge); 1050 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge); 1051 1052 /* 1053 * Common misconfiguration of the MediaGX/Geode PCI master that will 1054 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 1055 * datasheets found at http://www.national.com/analog for info on what 1056 * these bits do. <christer@weinigel.se> 1057 */ 1058 static void quirk_mediagx_master(struct pci_dev *dev) 1059 { 1060 u8 reg; 1061 1062 pci_read_config_byte(dev, 0x41, ®); 1063 if (reg & 2) { 1064 reg &= ~2; 1065 pci_info(dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", 1066 reg); 1067 pci_write_config_byte(dev, 0x41, reg); 1068 } 1069 } 1070 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); 1071 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); 1072 1073 /* 1074 * Ensure C0 rev restreaming is off. This is normally done by 1075 * the BIOS but in the odd case it is not the results are corruption 1076 * hence the presence of a Linux check 1077 */ 1078 static void quirk_disable_pxb(struct pci_dev *pdev) 1079 { 1080 u16 config; 1081 1082 if (pdev->revision != 0x04) /* Only C0 requires this */ 1083 return; 1084 pci_read_config_word(pdev, 0x40, &config); 1085 if (config & (1<<6)) { 1086 config &= ~(1<<6); 1087 pci_write_config_word(pdev, 0x40, config); 1088 pci_info(pdev, "C0 revision 450NX. Disabling PCI restreaming\n"); 1089 } 1090 } 1091 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); 1092 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); 1093 1094 static void quirk_amd_ide_mode(struct pci_dev *pdev) 1095 { 1096 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */ 1097 u8 tmp; 1098 1099 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp); 1100 if (tmp == 0x01) { 1101 pci_read_config_byte(pdev, 0x40, &tmp); 1102 pci_write_config_byte(pdev, 0x40, tmp|1); 1103 pci_write_config_byte(pdev, 0x9, 1); 1104 pci_write_config_byte(pdev, 0xa, 6); 1105 pci_write_config_byte(pdev, 0x40, tmp); 1106 1107 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI; 1108 pci_info(pdev, "set SATA to AHCI mode\n"); 1109 } 1110 } 1111 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); 1112 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); 1113 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); 1114 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); 1115 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); 1116 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); 1117 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode); 1118 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode); 1119 1120 /* 1121 * Serverworks CSB5 IDE does not fully support native mode 1122 */ 1123 static void quirk_svwks_csb5ide(struct pci_dev *pdev) 1124 { 1125 u8 prog; 1126 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 1127 if (prog & 5) { 1128 prog &= ~5; 1129 pdev->class &= ~5; 1130 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 1131 /* PCI layer will sort out resources */ 1132 } 1133 } 1134 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide); 1135 1136 /* 1137 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same 1138 */ 1139 static void quirk_ide_samemode(struct pci_dev *pdev) 1140 { 1141 u8 prog; 1142 1143 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 1144 1145 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) { 1146 pci_info(pdev, "IDE mode mismatch; forcing legacy mode\n"); 1147 prog &= ~5; 1148 pdev->class &= ~5; 1149 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 1150 } 1151 } 1152 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode); 1153 1154 /* 1155 * Some ATA devices break if put into D3 1156 */ 1157 1158 static void quirk_no_ata_d3(struct pci_dev *pdev) 1159 { 1160 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3; 1161 } 1162 /* Quirk the legacy ATA devices only. The AHCI ones are ok */ 1163 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID, 1164 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1165 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 1166 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1167 /* ALi loses some register settings that we cannot then restore */ 1168 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, 1169 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1170 /* VIA comes back fine but we need to keep it alive or ACPI GTM failures 1171 occur when mode detecting */ 1172 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID, 1173 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1174 1175 /* This was originally an Alpha specific thing, but it really fits here. 1176 * The i82375 PCI/EISA bridge appears as non-classified. Fix that. 1177 */ 1178 static void quirk_eisa_bridge(struct pci_dev *dev) 1179 { 1180 dev->class = PCI_CLASS_BRIDGE_EISA << 8; 1181 } 1182 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge); 1183 1184 1185 /* 1186 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge 1187 * is not activated. The myth is that Asus said that they do not want the 1188 * users to be irritated by just another PCI Device in the Win98 device 1189 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors 1190 * package 2.7.0 for details) 1191 * 1192 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC 1193 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it 1194 * becomes necessary to do this tweak in two steps -- the chosen trigger 1195 * is either the Host bridge (preferred) or on-board VGA controller. 1196 * 1197 * Note that we used to unhide the SMBus that way on Toshiba laptops 1198 * (Satellite A40 and Tecra M2) but then found that the thermal management 1199 * was done by SMM code, which could cause unsynchronized concurrent 1200 * accesses to the SMBus registers, with potentially bad effects. Thus you 1201 * should be very careful when adding new entries: if SMM is accessing the 1202 * Intel SMBus, this is a very good reason to leave it hidden. 1203 * 1204 * Likewise, many recent laptops use ACPI for thermal management. If the 1205 * ACPI DSDT code accesses the SMBus, then Linux should not access it 1206 * natively, and keeping the SMBus hidden is the right thing to do. If you 1207 * are about to add an entry in the table below, please first disassemble 1208 * the DSDT and double-check that there is no code accessing the SMBus. 1209 */ 1210 static int asus_hides_smbus; 1211 1212 static void asus_hides_smbus_hostbridge(struct pci_dev *dev) 1213 { 1214 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 1215 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB) 1216 switch (dev->subsystem_device) { 1217 case 0x8025: /* P4B-LX */ 1218 case 0x8070: /* P4B */ 1219 case 0x8088: /* P4B533 */ 1220 case 0x1626: /* L3C notebook */ 1221 asus_hides_smbus = 1; 1222 } 1223 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) 1224 switch (dev->subsystem_device) { 1225 case 0x80b1: /* P4GE-V */ 1226 case 0x80b2: /* P4PE */ 1227 case 0x8093: /* P4B533-V */ 1228 asus_hides_smbus = 1; 1229 } 1230 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB) 1231 switch (dev->subsystem_device) { 1232 case 0x8030: /* P4T533 */ 1233 asus_hides_smbus = 1; 1234 } 1235 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0) 1236 switch (dev->subsystem_device) { 1237 case 0x8070: /* P4G8X Deluxe */ 1238 asus_hides_smbus = 1; 1239 } 1240 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH) 1241 switch (dev->subsystem_device) { 1242 case 0x80c9: /* PU-DLS */ 1243 asus_hides_smbus = 1; 1244 } 1245 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) 1246 switch (dev->subsystem_device) { 1247 case 0x1751: /* M2N notebook */ 1248 case 0x1821: /* M5N notebook */ 1249 case 0x1897: /* A6L notebook */ 1250 asus_hides_smbus = 1; 1251 } 1252 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1253 switch (dev->subsystem_device) { 1254 case 0x184b: /* W1N notebook */ 1255 case 0x186a: /* M6Ne notebook */ 1256 asus_hides_smbus = 1; 1257 } 1258 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) 1259 switch (dev->subsystem_device) { 1260 case 0x80f2: /* P4P800-X */ 1261 asus_hides_smbus = 1; 1262 } 1263 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) 1264 switch (dev->subsystem_device) { 1265 case 0x1882: /* M6V notebook */ 1266 case 0x1977: /* A6VA notebook */ 1267 asus_hides_smbus = 1; 1268 } 1269 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 1270 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1271 switch (dev->subsystem_device) { 1272 case 0x088C: /* HP Compaq nc8000 */ 1273 case 0x0890: /* HP Compaq nc6000 */ 1274 asus_hides_smbus = 1; 1275 } 1276 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) 1277 switch (dev->subsystem_device) { 1278 case 0x12bc: /* HP D330L */ 1279 case 0x12bd: /* HP D530 */ 1280 case 0x006a: /* HP Compaq nx9500 */ 1281 asus_hides_smbus = 1; 1282 } 1283 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB) 1284 switch (dev->subsystem_device) { 1285 case 0x12bf: /* HP xw4100 */ 1286 asus_hides_smbus = 1; 1287 } 1288 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) { 1289 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1290 switch (dev->subsystem_device) { 1291 case 0xC00C: /* Samsung P35 notebook */ 1292 asus_hides_smbus = 1; 1293 } 1294 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) { 1295 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1296 switch (dev->subsystem_device) { 1297 case 0x0058: /* Compaq Evo N620c */ 1298 asus_hides_smbus = 1; 1299 } 1300 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3) 1301 switch (dev->subsystem_device) { 1302 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */ 1303 /* Motherboard doesn't have Host bridge 1304 * subvendor/subdevice IDs, therefore checking 1305 * its on-board VGA controller */ 1306 asus_hides_smbus = 1; 1307 } 1308 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2) 1309 switch (dev->subsystem_device) { 1310 case 0x00b8: /* Compaq Evo D510 CMT */ 1311 case 0x00b9: /* Compaq Evo D510 SFF */ 1312 case 0x00ba: /* Compaq Evo D510 USDT */ 1313 /* Motherboard doesn't have Host bridge 1314 * subvendor/subdevice IDs and on-board VGA 1315 * controller is disabled if an AGP card is 1316 * inserted, therefore checking USB UHCI 1317 * Controller #1 */ 1318 asus_hides_smbus = 1; 1319 } 1320 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC) 1321 switch (dev->subsystem_device) { 1322 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */ 1323 /* Motherboard doesn't have host bridge 1324 * subvendor/subdevice IDs, therefore checking 1325 * its on-board VGA controller */ 1326 asus_hides_smbus = 1; 1327 } 1328 } 1329 } 1330 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge); 1331 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge); 1332 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge); 1333 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge); 1334 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge); 1335 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge); 1336 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge); 1337 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge); 1338 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge); 1339 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge); 1340 1341 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge); 1342 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge); 1343 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge); 1344 1345 static void asus_hides_smbus_lpc(struct pci_dev *dev) 1346 { 1347 u16 val; 1348 1349 if (likely(!asus_hides_smbus)) 1350 return; 1351 1352 pci_read_config_word(dev, 0xF2, &val); 1353 if (val & 0x8) { 1354 pci_write_config_word(dev, 0xF2, val & (~0x8)); 1355 pci_read_config_word(dev, 0xF2, &val); 1356 if (val & 0x8) 1357 pci_info(dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", 1358 val); 1359 else 1360 pci_info(dev, "Enabled i801 SMBus device\n"); 1361 } 1362 } 1363 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); 1364 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); 1365 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); 1366 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); 1367 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); 1368 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); 1369 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); 1370 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); 1371 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); 1372 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); 1373 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); 1374 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); 1375 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); 1376 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); 1377 1378 /* It appears we just have one such device. If not, we have a warning */ 1379 static void __iomem *asus_rcba_base; 1380 static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev) 1381 { 1382 u32 rcba; 1383 1384 if (likely(!asus_hides_smbus)) 1385 return; 1386 WARN_ON(asus_rcba_base); 1387 1388 pci_read_config_dword(dev, 0xF0, &rcba); 1389 /* use bits 31:14, 16 kB aligned */ 1390 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000); 1391 if (asus_rcba_base == NULL) 1392 return; 1393 } 1394 1395 static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev) 1396 { 1397 u32 val; 1398 1399 if (likely(!asus_hides_smbus || !asus_rcba_base)) 1400 return; 1401 /* read the Function Disable register, dword mode only */ 1402 val = readl(asus_rcba_base + 0x3418); 1403 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */ 1404 } 1405 1406 static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev) 1407 { 1408 if (likely(!asus_hides_smbus || !asus_rcba_base)) 1409 return; 1410 iounmap(asus_rcba_base); 1411 asus_rcba_base = NULL; 1412 pci_info(dev, "Enabled ICH6/i801 SMBus device\n"); 1413 } 1414 1415 static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev) 1416 { 1417 asus_hides_smbus_lpc_ich6_suspend(dev); 1418 asus_hides_smbus_lpc_ich6_resume_early(dev); 1419 asus_hides_smbus_lpc_ich6_resume(dev); 1420 } 1421 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6); 1422 DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend); 1423 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume); 1424 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early); 1425 1426 /* 1427 * SiS 96x south bridge: BIOS typically hides SMBus device... 1428 */ 1429 static void quirk_sis_96x_smbus(struct pci_dev *dev) 1430 { 1431 u8 val = 0; 1432 pci_read_config_byte(dev, 0x77, &val); 1433 if (val & 0x10) { 1434 pci_info(dev, "Enabling SiS 96x SMBus\n"); 1435 pci_write_config_byte(dev, 0x77, val & ~0x10); 1436 } 1437 } 1438 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); 1439 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); 1440 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); 1441 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); 1442 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); 1443 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); 1444 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); 1445 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); 1446 1447 /* 1448 * ... This is further complicated by the fact that some SiS96x south 1449 * bridges pretend to be 85C503/5513 instead. In that case see if we 1450 * spotted a compatible north bridge to make sure. 1451 * (pci_find_device doesn't work yet) 1452 * 1453 * We can also enable the sis96x bit in the discovery register.. 1454 */ 1455 #define SIS_DETECT_REGISTER 0x40 1456 1457 static void quirk_sis_503(struct pci_dev *dev) 1458 { 1459 u8 reg; 1460 u16 devid; 1461 1462 pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®); 1463 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6)); 1464 pci_read_config_word(dev, PCI_DEVICE_ID, &devid); 1465 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) { 1466 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg); 1467 return; 1468 } 1469 1470 /* 1471 * Ok, it now shows up as a 96x.. run the 96x quirk by 1472 * hand in case it has already been processed. 1473 * (depends on link order, which is apparently not guaranteed) 1474 */ 1475 dev->device = devid; 1476 quirk_sis_96x_smbus(dev); 1477 } 1478 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); 1479 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); 1480 1481 1482 /* 1483 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller 1484 * and MC97 modem controller are disabled when a second PCI soundcard is 1485 * present. This patch, tweaking the VT8237 ISA bridge, enables them. 1486 * -- bjd 1487 */ 1488 static void asus_hides_ac97_lpc(struct pci_dev *dev) 1489 { 1490 u8 val; 1491 int asus_hides_ac97 = 0; 1492 1493 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 1494 if (dev->device == PCI_DEVICE_ID_VIA_8237) 1495 asus_hides_ac97 = 1; 1496 } 1497 1498 if (!asus_hides_ac97) 1499 return; 1500 1501 pci_read_config_byte(dev, 0x50, &val); 1502 if (val & 0xc0) { 1503 pci_write_config_byte(dev, 0x50, val & (~0xc0)); 1504 pci_read_config_byte(dev, 0x50, &val); 1505 if (val & 0xc0) 1506 pci_info(dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", 1507 val); 1508 else 1509 pci_info(dev, "Enabled onboard AC97/MC97 devices\n"); 1510 } 1511 } 1512 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); 1513 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); 1514 1515 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE) 1516 1517 /* 1518 * If we are using libata we can drive this chip properly but must 1519 * do this early on to make the additional device appear during 1520 * the PCI scanning. 1521 */ 1522 static void quirk_jmicron_ata(struct pci_dev *pdev) 1523 { 1524 u32 conf1, conf5, class; 1525 u8 hdr; 1526 1527 /* Only poke fn 0 */ 1528 if (PCI_FUNC(pdev->devfn)) 1529 return; 1530 1531 pci_read_config_dword(pdev, 0x40, &conf1); 1532 pci_read_config_dword(pdev, 0x80, &conf5); 1533 1534 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */ 1535 conf5 &= ~(1 << 24); /* Clear bit 24 */ 1536 1537 switch (pdev->device) { 1538 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */ 1539 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */ 1540 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */ 1541 /* The controller should be in single function ahci mode */ 1542 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */ 1543 break; 1544 1545 case PCI_DEVICE_ID_JMICRON_JMB365: 1546 case PCI_DEVICE_ID_JMICRON_JMB366: 1547 /* Redirect IDE second PATA port to the right spot */ 1548 conf5 |= (1 << 24); 1549 /* Fall through */ 1550 case PCI_DEVICE_ID_JMICRON_JMB361: 1551 case PCI_DEVICE_ID_JMICRON_JMB363: 1552 case PCI_DEVICE_ID_JMICRON_JMB369: 1553 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */ 1554 /* Set the class codes correctly and then direct IDE 0 */ 1555 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */ 1556 break; 1557 1558 case PCI_DEVICE_ID_JMICRON_JMB368: 1559 /* The controller should be in single function IDE mode */ 1560 conf1 |= 0x00C00000; /* Set 22, 23 */ 1561 break; 1562 } 1563 1564 pci_write_config_dword(pdev, 0x40, conf1); 1565 pci_write_config_dword(pdev, 0x80, conf5); 1566 1567 /* Update pdev accordingly */ 1568 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr); 1569 pdev->hdr_type = hdr & 0x7f; 1570 pdev->multifunction = !!(hdr & 0x80); 1571 1572 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class); 1573 pdev->class = class >> 8; 1574 } 1575 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); 1576 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); 1577 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); 1578 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); 1579 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata); 1580 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); 1581 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); 1582 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); 1583 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata); 1584 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); 1585 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); 1586 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); 1587 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); 1588 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata); 1589 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); 1590 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); 1591 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); 1592 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata); 1593 1594 #endif 1595 1596 static void quirk_jmicron_async_suspend(struct pci_dev *dev) 1597 { 1598 if (dev->multifunction) { 1599 device_disable_async_suspend(&dev->dev); 1600 pci_info(dev, "async suspend disabled to avoid multi-function power-on ordering issue\n"); 1601 } 1602 } 1603 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend); 1604 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0, quirk_jmicron_async_suspend); 1605 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x2362, quirk_jmicron_async_suspend); 1606 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x236f, quirk_jmicron_async_suspend); 1607 1608 #ifdef CONFIG_X86_IO_APIC 1609 static void quirk_alder_ioapic(struct pci_dev *pdev) 1610 { 1611 int i; 1612 1613 if ((pdev->class >> 8) != 0xff00) 1614 return; 1615 1616 /* the first BAR is the location of the IO APIC...we must 1617 * not touch this (and it's already covered by the fixmap), so 1618 * forcibly insert it into the resource tree */ 1619 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0)) 1620 insert_resource(&iomem_resource, &pdev->resource[0]); 1621 1622 /* The next five BARs all seem to be rubbish, so just clean 1623 * them out */ 1624 for (i = 1; i < 6; i++) 1625 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i])); 1626 } 1627 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic); 1628 #endif 1629 1630 static void quirk_pcie_mch(struct pci_dev *pdev) 1631 { 1632 pdev->no_msi = 1; 1633 } 1634 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch); 1635 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch); 1636 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch); 1637 1638 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, PCI_CLASS_BRIDGE_PCI, 8, quirk_pcie_mch); 1639 1640 /* 1641 * It's possible for the MSI to get corrupted if shpc and acpi 1642 * are used together on certain PXH-based systems. 1643 */ 1644 static void quirk_pcie_pxh(struct pci_dev *dev) 1645 { 1646 dev->no_msi = 1; 1647 pci_warn(dev, "PXH quirk detected; SHPC device MSI disabled\n"); 1648 } 1649 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh); 1650 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh); 1651 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh); 1652 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh); 1653 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh); 1654 1655 /* 1656 * Some Intel PCI Express chipsets have trouble with downstream 1657 * device power management. 1658 */ 1659 static void quirk_intel_pcie_pm(struct pci_dev *dev) 1660 { 1661 pci_pm_d3_delay = 120; 1662 dev->no_d1d2 = 1; 1663 } 1664 1665 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm); 1666 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm); 1667 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm); 1668 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm); 1669 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm); 1670 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm); 1671 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm); 1672 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm); 1673 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm); 1674 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm); 1675 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm); 1676 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm); 1677 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm); 1678 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm); 1679 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm); 1680 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm); 1681 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm); 1682 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm); 1683 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm); 1684 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm); 1685 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm); 1686 1687 static void quirk_radeon_pm(struct pci_dev *dev) 1688 { 1689 if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE && 1690 dev->subsystem_device == 0x00e2) { 1691 if (dev->d3_delay < 20) { 1692 dev->d3_delay = 20; 1693 pci_info(dev, "extending delay after power-on from D3 to %d msec\n", 1694 dev->d3_delay); 1695 } 1696 } 1697 } 1698 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6741, quirk_radeon_pm); 1699 1700 #ifdef CONFIG_X86_IO_APIC 1701 static int dmi_disable_ioapicreroute(const struct dmi_system_id *d) 1702 { 1703 noioapicreroute = 1; 1704 pr_info("%s detected: disable boot interrupt reroute\n", d->ident); 1705 1706 return 0; 1707 } 1708 1709 static const struct dmi_system_id boot_interrupt_dmi_table[] = { 1710 /* 1711 * Systems to exclude from boot interrupt reroute quirks 1712 */ 1713 { 1714 .callback = dmi_disable_ioapicreroute, 1715 .ident = "ASUSTek Computer INC. M2N-LR", 1716 .matches = { 1717 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTek Computer INC."), 1718 DMI_MATCH(DMI_PRODUCT_NAME, "M2N-LR"), 1719 }, 1720 }, 1721 {} 1722 }; 1723 1724 /* 1725 * Boot interrupts on some chipsets cannot be turned off. For these chipsets, 1726 * remap the original interrupt in the linux kernel to the boot interrupt, so 1727 * that a PCI device's interrupt handler is installed on the boot interrupt 1728 * line instead. 1729 */ 1730 static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev) 1731 { 1732 dmi_check_system(boot_interrupt_dmi_table); 1733 if (noioapicquirk || noioapicreroute) 1734 return; 1735 1736 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT; 1737 pci_info(dev, "rerouting interrupts for [%04x:%04x]\n", 1738 dev->vendor, dev->device); 1739 } 1740 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); 1741 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); 1742 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); 1743 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); 1744 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); 1745 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); 1746 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); 1747 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); 1748 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); 1749 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); 1750 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); 1751 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); 1752 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); 1753 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); 1754 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); 1755 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); 1756 1757 /* 1758 * On some chipsets we can disable the generation of legacy INTx boot 1759 * interrupts. 1760 */ 1761 1762 /* 1763 * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no 1764 * 300641-004US, section 5.7.3. 1765 */ 1766 #define INTEL_6300_IOAPIC_ABAR 0x40 1767 #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14) 1768 1769 static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev) 1770 { 1771 u16 pci_config_word; 1772 1773 if (noioapicquirk) 1774 return; 1775 1776 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word); 1777 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ; 1778 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word); 1779 1780 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", 1781 dev->vendor, dev->device); 1782 } 1783 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt); 1784 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt); 1785 1786 /* 1787 * disable boot interrupts on HT-1000 1788 */ 1789 #define BC_HT1000_FEATURE_REG 0x64 1790 #define BC_HT1000_PIC_REGS_ENABLE (1<<0) 1791 #define BC_HT1000_MAP_IDX 0xC00 1792 #define BC_HT1000_MAP_DATA 0xC01 1793 1794 static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev) 1795 { 1796 u32 pci_config_dword; 1797 u8 irq; 1798 1799 if (noioapicquirk) 1800 return; 1801 1802 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword); 1803 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword | 1804 BC_HT1000_PIC_REGS_ENABLE); 1805 1806 for (irq = 0x10; irq < 0x10 + 32; irq++) { 1807 outb(irq, BC_HT1000_MAP_IDX); 1808 outb(0x00, BC_HT1000_MAP_DATA); 1809 } 1810 1811 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword); 1812 1813 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", 1814 dev->vendor, dev->device); 1815 } 1816 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); 1817 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); 1818 1819 /* 1820 * disable boot interrupts on AMD and ATI chipsets 1821 */ 1822 /* 1823 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131 1824 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode 1825 * (due to an erratum). 1826 */ 1827 #define AMD_813X_MISC 0x40 1828 #define AMD_813X_NOIOAMODE (1<<0) 1829 #define AMD_813X_REV_B1 0x12 1830 #define AMD_813X_REV_B2 0x13 1831 1832 static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev) 1833 { 1834 u32 pci_config_dword; 1835 1836 if (noioapicquirk) 1837 return; 1838 if ((dev->revision == AMD_813X_REV_B1) || 1839 (dev->revision == AMD_813X_REV_B2)) 1840 return; 1841 1842 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword); 1843 pci_config_dword &= ~AMD_813X_NOIOAMODE; 1844 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword); 1845 1846 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", 1847 dev->vendor, dev->device); 1848 } 1849 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 1850 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 1851 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 1852 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 1853 1854 #define AMD_8111_PCI_IRQ_ROUTING 0x56 1855 1856 static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev) 1857 { 1858 u16 pci_config_word; 1859 1860 if (noioapicquirk) 1861 return; 1862 1863 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word); 1864 if (!pci_config_word) { 1865 pci_info(dev, "boot interrupts on device [%04x:%04x] already disabled\n", 1866 dev->vendor, dev->device); 1867 return; 1868 } 1869 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0); 1870 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", 1871 dev->vendor, dev->device); 1872 } 1873 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); 1874 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); 1875 #endif /* CONFIG_X86_IO_APIC */ 1876 1877 /* 1878 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size 1879 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes. 1880 * Re-allocate the region if needed... 1881 */ 1882 static void quirk_tc86c001_ide(struct pci_dev *dev) 1883 { 1884 struct resource *r = &dev->resource[0]; 1885 1886 if (r->start & 0x8) { 1887 r->flags |= IORESOURCE_UNSET; 1888 r->start = 0; 1889 r->end = 0xf; 1890 } 1891 } 1892 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2, 1893 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE, 1894 quirk_tc86c001_ide); 1895 1896 /* 1897 * PLX PCI 9050 PCI Target bridge controller has an errata that prevents the 1898 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o) 1899 * being read correctly if bit 7 of the base address is set. 1900 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128). 1901 * Re-allocate the regions to a 256-byte boundary if necessary. 1902 */ 1903 static void quirk_plx_pci9050(struct pci_dev *dev) 1904 { 1905 unsigned int bar; 1906 1907 /* Fixed in revision 2 (PCI 9052). */ 1908 if (dev->revision >= 2) 1909 return; 1910 for (bar = 0; bar <= 1; bar++) 1911 if (pci_resource_len(dev, bar) == 0x80 && 1912 (pci_resource_start(dev, bar) & 0x80)) { 1913 struct resource *r = &dev->resource[bar]; 1914 pci_info(dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n", 1915 bar); 1916 r->flags |= IORESOURCE_UNSET; 1917 r->start = 0; 1918 r->end = 0xff; 1919 } 1920 } 1921 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 1922 quirk_plx_pci9050); 1923 /* 1924 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others) 1925 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b, 1926 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c, 1927 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b. 1928 * 1929 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq" 1930 * driver. 1931 */ 1932 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050); 1933 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050); 1934 1935 static void quirk_netmos(struct pci_dev *dev) 1936 { 1937 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; 1938 unsigned int num_serial = dev->subsystem_device & 0xf; 1939 1940 /* 1941 * These Netmos parts are multiport serial devices with optional 1942 * parallel ports. Even when parallel ports are present, they 1943 * are identified as class SERIAL, which means the serial driver 1944 * will claim them. To prevent this, mark them as class OTHER. 1945 * These combo devices should be claimed by parport_serial. 1946 * 1947 * The subdevice ID is of the form 0x00PS, where <P> is the number 1948 * of parallel ports and <S> is the number of serial ports. 1949 */ 1950 switch (dev->device) { 1951 case PCI_DEVICE_ID_NETMOS_9835: 1952 /* Well, this rule doesn't hold for the following 9835 device */ 1953 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && 1954 dev->subsystem_device == 0x0299) 1955 return; 1956 case PCI_DEVICE_ID_NETMOS_9735: 1957 case PCI_DEVICE_ID_NETMOS_9745: 1958 case PCI_DEVICE_ID_NETMOS_9845: 1959 case PCI_DEVICE_ID_NETMOS_9855: 1960 if (num_parallel) { 1961 pci_info(dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n", 1962 dev->device, num_parallel, num_serial); 1963 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) | 1964 (dev->class & 0xff); 1965 } 1966 } 1967 } 1968 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, 1969 PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos); 1970 1971 /* 1972 * Quirk non-zero PCI functions to route VPD access through function 0 for 1973 * devices that share VPD resources between functions. The functions are 1974 * expected to be identical devices. 1975 */ 1976 static void quirk_f0_vpd_link(struct pci_dev *dev) 1977 { 1978 struct pci_dev *f0; 1979 1980 if (!PCI_FUNC(dev->devfn)) 1981 return; 1982 1983 f0 = pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn), 0)); 1984 if (!f0) 1985 return; 1986 1987 if (f0->vpd && dev->class == f0->class && 1988 dev->vendor == f0->vendor && dev->device == f0->device) 1989 dev->dev_flags |= PCI_DEV_FLAGS_VPD_REF_F0; 1990 1991 pci_dev_put(f0); 1992 } 1993 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 1994 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_f0_vpd_link); 1995 1996 static void quirk_e100_interrupt(struct pci_dev *dev) 1997 { 1998 u16 command, pmcsr; 1999 u8 __iomem *csr; 2000 u8 cmd_hi; 2001 2002 switch (dev->device) { 2003 /* PCI IDs taken from drivers/net/e100.c */ 2004 case 0x1029: 2005 case 0x1030 ... 0x1034: 2006 case 0x1038 ... 0x103E: 2007 case 0x1050 ... 0x1057: 2008 case 0x1059: 2009 case 0x1064 ... 0x106B: 2010 case 0x1091 ... 0x1095: 2011 case 0x1209: 2012 case 0x1229: 2013 case 0x2449: 2014 case 0x2459: 2015 case 0x245D: 2016 case 0x27DC: 2017 break; 2018 default: 2019 return; 2020 } 2021 2022 /* 2023 * Some firmware hands off the e100 with interrupts enabled, 2024 * which can cause a flood of interrupts if packets are 2025 * received before the driver attaches to the device. So 2026 * disable all e100 interrupts here. The driver will 2027 * re-enable them when it's ready. 2028 */ 2029 pci_read_config_word(dev, PCI_COMMAND, &command); 2030 2031 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0)) 2032 return; 2033 2034 /* 2035 * Check that the device is in the D0 power state. If it's not, 2036 * there is no point to look any further. 2037 */ 2038 if (dev->pm_cap) { 2039 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); 2040 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0) 2041 return; 2042 } 2043 2044 /* Convert from PCI bus to resource space. */ 2045 csr = ioremap(pci_resource_start(dev, 0), 8); 2046 if (!csr) { 2047 pci_warn(dev, "Can't map e100 registers\n"); 2048 return; 2049 } 2050 2051 cmd_hi = readb(csr + 3); 2052 if (cmd_hi == 0) { 2053 pci_warn(dev, "Firmware left e100 interrupts enabled; disabling\n"); 2054 writeb(1, csr + 3); 2055 } 2056 2057 iounmap(csr); 2058 } 2059 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 2060 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt); 2061 2062 /* 2063 * The 82575 and 82598 may experience data corruption issues when transitioning 2064 * out of L0S. To prevent this we need to disable L0S on the PCIe link. 2065 */ 2066 static void quirk_disable_aspm_l0s(struct pci_dev *dev) 2067 { 2068 pci_info(dev, "Disabling L0s\n"); 2069 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S); 2070 } 2071 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s); 2072 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s); 2073 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s); 2074 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s); 2075 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s); 2076 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s); 2077 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s); 2078 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s); 2079 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s); 2080 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s); 2081 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s); 2082 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s); 2083 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s); 2084 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s); 2085 2086 static void fixup_rev1_53c810(struct pci_dev *dev) 2087 { 2088 u32 class = dev->class; 2089 2090 /* 2091 * rev 1 ncr53c810 chips don't set the class at all which means 2092 * they don't get their resources remapped. Fix that here. 2093 */ 2094 if (class) 2095 return; 2096 2097 dev->class = PCI_CLASS_STORAGE_SCSI << 8; 2098 pci_info(dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n", 2099 class, dev->class); 2100 } 2101 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810); 2102 2103 /* Enable 1k I/O space granularity on the Intel P64H2 */ 2104 static void quirk_p64h2_1k_io(struct pci_dev *dev) 2105 { 2106 u16 en1k; 2107 2108 pci_read_config_word(dev, 0x40, &en1k); 2109 2110 if (en1k & 0x200) { 2111 pci_info(dev, "Enable I/O Space to 1KB granularity\n"); 2112 dev->io_window_1k = 1; 2113 } 2114 } 2115 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io); 2116 2117 /* Under some circumstances, AER is not linked with extended capabilities. 2118 * Force it to be linked by setting the corresponding control bit in the 2119 * config space. 2120 */ 2121 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev) 2122 { 2123 uint8_t b; 2124 if (pci_read_config_byte(dev, 0xf41, &b) == 0) { 2125 if (!(b & 0x20)) { 2126 pci_write_config_byte(dev, 0xf41, b | 0x20); 2127 pci_info(dev, "Linking AER extended capability\n"); 2128 } 2129 } 2130 } 2131 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2132 quirk_nvidia_ck804_pcie_aer_ext_cap); 2133 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2134 quirk_nvidia_ck804_pcie_aer_ext_cap); 2135 2136 static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev) 2137 { 2138 /* 2139 * Disable PCI Bus Parking and PCI Master read caching on CX700 2140 * which causes unspecified timing errors with a VT6212L on the PCI 2141 * bus leading to USB2.0 packet loss. 2142 * 2143 * This quirk is only enabled if a second (on the external PCI bus) 2144 * VT6212L is found -- the CX700 core itself also contains a USB 2145 * host controller with the same PCI ID as the VT6212L. 2146 */ 2147 2148 /* Count VT6212L instances */ 2149 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA, 2150 PCI_DEVICE_ID_VIA_8235_USB_2, NULL); 2151 uint8_t b; 2152 2153 /* p should contain the first (internal) VT6212L -- see if we have 2154 an external one by searching again */ 2155 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p); 2156 if (!p) 2157 return; 2158 pci_dev_put(p); 2159 2160 if (pci_read_config_byte(dev, 0x76, &b) == 0) { 2161 if (b & 0x40) { 2162 /* Turn off PCI Bus Parking */ 2163 pci_write_config_byte(dev, 0x76, b ^ 0x40); 2164 2165 pci_info(dev, "Disabling VIA CX700 PCI parking\n"); 2166 } 2167 } 2168 2169 if (pci_read_config_byte(dev, 0x72, &b) == 0) { 2170 if (b != 0) { 2171 /* Turn off PCI Master read caching */ 2172 pci_write_config_byte(dev, 0x72, 0x0); 2173 2174 /* Set PCI Master Bus time-out to "1x16 PCLK" */ 2175 pci_write_config_byte(dev, 0x75, 0x1); 2176 2177 /* Disable "Read FIFO Timer" */ 2178 pci_write_config_byte(dev, 0x77, 0x0); 2179 2180 pci_info(dev, "Disabling VIA CX700 PCI caching\n"); 2181 } 2182 } 2183 } 2184 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching); 2185 2186 /* 2187 * If a device follows the VPD format spec, the PCI core will not read or 2188 * write past the VPD End Tag. But some vendors do not follow the VPD 2189 * format spec, so we can't tell how much data is safe to access. Devices 2190 * may behave unpredictably if we access too much. Blacklist these devices 2191 * so we don't touch VPD at all. 2192 */ 2193 static void quirk_blacklist_vpd(struct pci_dev *dev) 2194 { 2195 if (dev->vpd) { 2196 dev->vpd->len = 0; 2197 pci_warn(dev, FW_BUG "disabling VPD access (can't determine size of non-standard VPD format)\n"); 2198 } 2199 } 2200 2201 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0060, quirk_blacklist_vpd); 2202 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x007c, quirk_blacklist_vpd); 2203 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0413, quirk_blacklist_vpd); 2204 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0078, quirk_blacklist_vpd); 2205 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0079, quirk_blacklist_vpd); 2206 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0073, quirk_blacklist_vpd); 2207 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0071, quirk_blacklist_vpd); 2208 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x005b, quirk_blacklist_vpd); 2209 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x002f, quirk_blacklist_vpd); 2210 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x005d, quirk_blacklist_vpd); 2211 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x005f, quirk_blacklist_vpd); 2212 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, PCI_ANY_ID, 2213 quirk_blacklist_vpd); 2214 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_QLOGIC, 0x2261, quirk_blacklist_vpd); 2215 2216 /* 2217 * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the 2218 * VPD end tag will hang the device. This problem was initially 2219 * observed when a vpd entry was created in sysfs 2220 * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry 2221 * will dump 32k of data. Reading a full 32k will cause an access 2222 * beyond the VPD end tag causing the device to hang. Once the device 2223 * is hung, the bnx2 driver will not be able to reset the device. 2224 * We believe that it is legal to read beyond the end tag and 2225 * therefore the solution is to limit the read/write length. 2226 */ 2227 static void quirk_brcm_570x_limit_vpd(struct pci_dev *dev) 2228 { 2229 /* 2230 * Only disable the VPD capability for 5706, 5706S, 5708, 2231 * 5708S and 5709 rev. A 2232 */ 2233 if ((dev->device == PCI_DEVICE_ID_NX2_5706) || 2234 (dev->device == PCI_DEVICE_ID_NX2_5706S) || 2235 (dev->device == PCI_DEVICE_ID_NX2_5708) || 2236 (dev->device == PCI_DEVICE_ID_NX2_5708S) || 2237 ((dev->device == PCI_DEVICE_ID_NX2_5709) && 2238 (dev->revision & 0xf0) == 0x0)) { 2239 if (dev->vpd) 2240 dev->vpd->len = 0x80; 2241 } 2242 } 2243 2244 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2245 PCI_DEVICE_ID_NX2_5706, 2246 quirk_brcm_570x_limit_vpd); 2247 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2248 PCI_DEVICE_ID_NX2_5706S, 2249 quirk_brcm_570x_limit_vpd); 2250 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2251 PCI_DEVICE_ID_NX2_5708, 2252 quirk_brcm_570x_limit_vpd); 2253 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2254 PCI_DEVICE_ID_NX2_5708S, 2255 quirk_brcm_570x_limit_vpd); 2256 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2257 PCI_DEVICE_ID_NX2_5709, 2258 quirk_brcm_570x_limit_vpd); 2259 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2260 PCI_DEVICE_ID_NX2_5709S, 2261 quirk_brcm_570x_limit_vpd); 2262 2263 static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev) 2264 { 2265 u32 rev; 2266 2267 pci_read_config_dword(dev, 0xf4, &rev); 2268 2269 /* Only CAP the MRRS if the device is a 5719 A0 */ 2270 if (rev == 0x05719000) { 2271 int readrq = pcie_get_readrq(dev); 2272 if (readrq > 2048) 2273 pcie_set_readrq(dev, 2048); 2274 } 2275 } 2276 2277 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM, 2278 PCI_DEVICE_ID_TIGON3_5719, 2279 quirk_brcm_5719_limit_mrrs); 2280 2281 #ifdef CONFIG_PCIE_IPROC_PLATFORM 2282 static void quirk_paxc_bridge(struct pci_dev *pdev) 2283 { 2284 /* The PCI config space is shared with the PAXC root port and the first 2285 * Ethernet device. So, we need to workaround this by telling the PCI 2286 * code that the bridge is not an Ethernet device. 2287 */ 2288 if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE) 2289 pdev->class = PCI_CLASS_BRIDGE_PCI << 8; 2290 2291 /* MPSS is not being set properly (as it is currently 0). This is 2292 * because that area of the PCI config space is hard coded to zero, and 2293 * is not modifiable by firmware. Set this to 2 (e.g., 512 byte MPS) 2294 * so that the MPS can be set to the real max value. 2295 */ 2296 pdev->pcie_mpss = 2; 2297 } 2298 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16cd, quirk_paxc_bridge); 2299 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16f0, quirk_paxc_bridge); 2300 #endif 2301 2302 /* Originally in EDAC sources for i82875P: 2303 * Intel tells BIOS developers to hide device 6 which 2304 * configures the overflow device access containing 2305 * the DRBs - this is where we expose device 6. 2306 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm 2307 */ 2308 static void quirk_unhide_mch_dev6(struct pci_dev *dev) 2309 { 2310 u8 reg; 2311 2312 if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) { 2313 pci_info(dev, "Enabling MCH 'Overflow' Device\n"); 2314 pci_write_config_byte(dev, 0xF4, reg | 0x02); 2315 } 2316 } 2317 2318 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, 2319 quirk_unhide_mch_dev6); 2320 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, 2321 quirk_unhide_mch_dev6); 2322 2323 #ifdef CONFIG_PCI_MSI 2324 /* Some chipsets do not support MSI. We cannot easily rely on setting 2325 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually 2326 * some other buses controlled by the chipset even if Linux is not 2327 * aware of it. Instead of setting the flag on all buses in the 2328 * machine, simply disable MSI globally. 2329 */ 2330 static void quirk_disable_all_msi(struct pci_dev *dev) 2331 { 2332 pci_no_msi(); 2333 pci_warn(dev, "MSI quirk detected; MSI disabled\n"); 2334 } 2335 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi); 2336 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi); 2337 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi); 2338 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi); 2339 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi); 2340 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi); 2341 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi); 2342 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi); 2343 2344 /* Disable MSI on chipsets that are known to not support it */ 2345 static void quirk_disable_msi(struct pci_dev *dev) 2346 { 2347 if (dev->subordinate) { 2348 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n"); 2349 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 2350 } 2351 } 2352 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi); 2353 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi); 2354 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi); 2355 2356 /* 2357 * The APC bridge device in AMD 780 family northbridges has some random 2358 * OEM subsystem ID in its vendor ID register (erratum 18), so instead 2359 * we use the possible vendor/device IDs of the host bridge for the 2360 * declared quirk, and search for the APC bridge by slot number. 2361 */ 2362 static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge) 2363 { 2364 struct pci_dev *apc_bridge; 2365 2366 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0)); 2367 if (apc_bridge) { 2368 if (apc_bridge->device == 0x9602) 2369 quirk_disable_msi(apc_bridge); 2370 pci_dev_put(apc_bridge); 2371 } 2372 } 2373 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi); 2374 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi); 2375 2376 /* Go through the list of Hypertransport capabilities and 2377 * return 1 if a HT MSI capability is found and enabled */ 2378 static int msi_ht_cap_enabled(struct pci_dev *dev) 2379 { 2380 int pos, ttl = PCI_FIND_CAP_TTL; 2381 2382 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2383 while (pos && ttl--) { 2384 u8 flags; 2385 2386 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2387 &flags) == 0) { 2388 pci_info(dev, "Found %s HT MSI Mapping\n", 2389 flags & HT_MSI_FLAGS_ENABLE ? 2390 "enabled" : "disabled"); 2391 return (flags & HT_MSI_FLAGS_ENABLE) != 0; 2392 } 2393 2394 pos = pci_find_next_ht_capability(dev, pos, 2395 HT_CAPTYPE_MSI_MAPPING); 2396 } 2397 return 0; 2398 } 2399 2400 /* Check the hypertransport MSI mapping to know whether MSI is enabled or not */ 2401 static void quirk_msi_ht_cap(struct pci_dev *dev) 2402 { 2403 if (dev->subordinate && !msi_ht_cap_enabled(dev)) { 2404 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n"); 2405 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 2406 } 2407 } 2408 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE, 2409 quirk_msi_ht_cap); 2410 2411 /* The nVidia CK804 chipset may have 2 HT MSI mappings. 2412 * MSI are supported if the MSI capability set in any of these mappings. 2413 */ 2414 static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev) 2415 { 2416 struct pci_dev *pdev; 2417 2418 if (!dev->subordinate) 2419 return; 2420 2421 /* check HT MSI cap on this chipset and the root one. 2422 * a single one having MSI is enough to be sure that MSI are supported. 2423 */ 2424 pdev = pci_get_slot(dev->bus, 0); 2425 if (!pdev) 2426 return; 2427 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) { 2428 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n"); 2429 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 2430 } 2431 pci_dev_put(pdev); 2432 } 2433 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2434 quirk_nvidia_ck804_msi_ht_cap); 2435 2436 /* Force enable MSI mapping capability on HT bridges */ 2437 static void ht_enable_msi_mapping(struct pci_dev *dev) 2438 { 2439 int pos, ttl = PCI_FIND_CAP_TTL; 2440 2441 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2442 while (pos && ttl--) { 2443 u8 flags; 2444 2445 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2446 &flags) == 0) { 2447 pci_info(dev, "Enabling HT MSI Mapping\n"); 2448 2449 pci_write_config_byte(dev, pos + HT_MSI_FLAGS, 2450 flags | HT_MSI_FLAGS_ENABLE); 2451 } 2452 pos = pci_find_next_ht_capability(dev, pos, 2453 HT_CAPTYPE_MSI_MAPPING); 2454 } 2455 } 2456 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, 2457 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB, 2458 ht_enable_msi_mapping); 2459 2460 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, 2461 ht_enable_msi_mapping); 2462 2463 /* The P5N32-SLI motherboards from Asus have a problem with msi 2464 * for the MCP55 NIC. It is not yet determined whether the msi problem 2465 * also affects other devices. As for now, turn off msi for this device. 2466 */ 2467 static void nvenet_msi_disable(struct pci_dev *dev) 2468 { 2469 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME); 2470 2471 if (board_name && 2472 (strstr(board_name, "P5N32-SLI PREMIUM") || 2473 strstr(board_name, "P5N32-E SLI"))) { 2474 pci_info(dev, "Disabling MSI for MCP55 NIC on P5N32-SLI\n"); 2475 dev->no_msi = 1; 2476 } 2477 } 2478 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2479 PCI_DEVICE_ID_NVIDIA_NVENET_15, 2480 nvenet_msi_disable); 2481 2482 /* 2483 * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing 2484 * config register. This register controls the routing of legacy 2485 * interrupts from devices that route through the MCP55. If this register 2486 * is misprogrammed, interrupts are only sent to the BSP, unlike 2487 * conventional systems where the IRQ is broadcast to all online CPUs. Not 2488 * having this register set properly prevents kdump from booting up 2489 * properly, so let's make sure that we have it set correctly. 2490 * Note that this is an undocumented register. 2491 */ 2492 static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev) 2493 { 2494 u32 cfg; 2495 2496 if (!pci_find_capability(dev, PCI_CAP_ID_HT)) 2497 return; 2498 2499 pci_read_config_dword(dev, 0x74, &cfg); 2500 2501 if (cfg & ((1 << 2) | (1 << 15))) { 2502 printk(KERN_INFO "Rewriting irq routing register on MCP55\n"); 2503 cfg &= ~((1 << 2) | (1 << 15)); 2504 pci_write_config_dword(dev, 0x74, cfg); 2505 } 2506 } 2507 2508 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2509 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0, 2510 nvbridge_check_legacy_irq_routing); 2511 2512 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2513 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4, 2514 nvbridge_check_legacy_irq_routing); 2515 2516 static int ht_check_msi_mapping(struct pci_dev *dev) 2517 { 2518 int pos, ttl = PCI_FIND_CAP_TTL; 2519 int found = 0; 2520 2521 /* check if there is HT MSI cap or enabled on this device */ 2522 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2523 while (pos && ttl--) { 2524 u8 flags; 2525 2526 if (found < 1) 2527 found = 1; 2528 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2529 &flags) == 0) { 2530 if (flags & HT_MSI_FLAGS_ENABLE) { 2531 if (found < 2) { 2532 found = 2; 2533 break; 2534 } 2535 } 2536 } 2537 pos = pci_find_next_ht_capability(dev, pos, 2538 HT_CAPTYPE_MSI_MAPPING); 2539 } 2540 2541 return found; 2542 } 2543 2544 static int host_bridge_with_leaf(struct pci_dev *host_bridge) 2545 { 2546 struct pci_dev *dev; 2547 int pos; 2548 int i, dev_no; 2549 int found = 0; 2550 2551 dev_no = host_bridge->devfn >> 3; 2552 for (i = dev_no + 1; i < 0x20; i++) { 2553 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0)); 2554 if (!dev) 2555 continue; 2556 2557 /* found next host bridge ?*/ 2558 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); 2559 if (pos != 0) { 2560 pci_dev_put(dev); 2561 break; 2562 } 2563 2564 if (ht_check_msi_mapping(dev)) { 2565 found = 1; 2566 pci_dev_put(dev); 2567 break; 2568 } 2569 pci_dev_put(dev); 2570 } 2571 2572 return found; 2573 } 2574 2575 #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */ 2576 #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */ 2577 2578 static int is_end_of_ht_chain(struct pci_dev *dev) 2579 { 2580 int pos, ctrl_off; 2581 int end = 0; 2582 u16 flags, ctrl; 2583 2584 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); 2585 2586 if (!pos) 2587 goto out; 2588 2589 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags); 2590 2591 ctrl_off = ((flags >> 10) & 1) ? 2592 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1; 2593 pci_read_config_word(dev, pos + ctrl_off, &ctrl); 2594 2595 if (ctrl & (1 << 6)) 2596 end = 1; 2597 2598 out: 2599 return end; 2600 } 2601 2602 static void nv_ht_enable_msi_mapping(struct pci_dev *dev) 2603 { 2604 struct pci_dev *host_bridge; 2605 int pos; 2606 int i, dev_no; 2607 int found = 0; 2608 2609 dev_no = dev->devfn >> 3; 2610 for (i = dev_no; i >= 0; i--) { 2611 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0)); 2612 if (!host_bridge) 2613 continue; 2614 2615 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); 2616 if (pos != 0) { 2617 found = 1; 2618 break; 2619 } 2620 pci_dev_put(host_bridge); 2621 } 2622 2623 if (!found) 2624 return; 2625 2626 /* don't enable end_device/host_bridge with leaf directly here */ 2627 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) && 2628 host_bridge_with_leaf(host_bridge)) 2629 goto out; 2630 2631 /* root did that ! */ 2632 if (msi_ht_cap_enabled(host_bridge)) 2633 goto out; 2634 2635 ht_enable_msi_mapping(dev); 2636 2637 out: 2638 pci_dev_put(host_bridge); 2639 } 2640 2641 static void ht_disable_msi_mapping(struct pci_dev *dev) 2642 { 2643 int pos, ttl = PCI_FIND_CAP_TTL; 2644 2645 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2646 while (pos && ttl--) { 2647 u8 flags; 2648 2649 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2650 &flags) == 0) { 2651 pci_info(dev, "Disabling HT MSI Mapping\n"); 2652 2653 pci_write_config_byte(dev, pos + HT_MSI_FLAGS, 2654 flags & ~HT_MSI_FLAGS_ENABLE); 2655 } 2656 pos = pci_find_next_ht_capability(dev, pos, 2657 HT_CAPTYPE_MSI_MAPPING); 2658 } 2659 } 2660 2661 static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all) 2662 { 2663 struct pci_dev *host_bridge; 2664 int pos; 2665 int found; 2666 2667 if (!pci_msi_enabled()) 2668 return; 2669 2670 /* check if there is HT MSI cap or enabled on this device */ 2671 found = ht_check_msi_mapping(dev); 2672 2673 /* no HT MSI CAP */ 2674 if (found == 0) 2675 return; 2676 2677 /* 2678 * HT MSI mapping should be disabled on devices that are below 2679 * a non-Hypertransport host bridge. Locate the host bridge... 2680 */ 2681 host_bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus), 0, 2682 PCI_DEVFN(0, 0)); 2683 if (host_bridge == NULL) { 2684 pci_warn(dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n"); 2685 return; 2686 } 2687 2688 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); 2689 if (pos != 0) { 2690 /* Host bridge is to HT */ 2691 if (found == 1) { 2692 /* it is not enabled, try to enable it */ 2693 if (all) 2694 ht_enable_msi_mapping(dev); 2695 else 2696 nv_ht_enable_msi_mapping(dev); 2697 } 2698 goto out; 2699 } 2700 2701 /* HT MSI is not enabled */ 2702 if (found == 1) 2703 goto out; 2704 2705 /* Host bridge is not to HT, disable HT MSI mapping on this device */ 2706 ht_disable_msi_mapping(dev); 2707 2708 out: 2709 pci_dev_put(host_bridge); 2710 } 2711 2712 static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev) 2713 { 2714 return __nv_msi_ht_cap_quirk(dev, 1); 2715 } 2716 2717 static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev) 2718 { 2719 return __nv_msi_ht_cap_quirk(dev, 0); 2720 } 2721 2722 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); 2723 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); 2724 2725 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); 2726 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); 2727 2728 static void quirk_msi_intx_disable_bug(struct pci_dev *dev) 2729 { 2730 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 2731 } 2732 static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev) 2733 { 2734 struct pci_dev *p; 2735 2736 /* SB700 MSI issue will be fixed at HW level from revision A21, 2737 * we need check PCI REVISION ID of SMBus controller to get SB700 2738 * revision. 2739 */ 2740 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, 2741 NULL); 2742 if (!p) 2743 return; 2744 2745 if ((p->revision < 0x3B) && (p->revision >= 0x30)) 2746 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 2747 pci_dev_put(p); 2748 } 2749 static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev) 2750 { 2751 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */ 2752 if (dev->revision < 0x18) { 2753 pci_info(dev, "set MSI_INTX_DISABLE_BUG flag\n"); 2754 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 2755 } 2756 } 2757 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2758 PCI_DEVICE_ID_TIGON3_5780, 2759 quirk_msi_intx_disable_bug); 2760 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2761 PCI_DEVICE_ID_TIGON3_5780S, 2762 quirk_msi_intx_disable_bug); 2763 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2764 PCI_DEVICE_ID_TIGON3_5714, 2765 quirk_msi_intx_disable_bug); 2766 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2767 PCI_DEVICE_ID_TIGON3_5714S, 2768 quirk_msi_intx_disable_bug); 2769 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2770 PCI_DEVICE_ID_TIGON3_5715, 2771 quirk_msi_intx_disable_bug); 2772 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2773 PCI_DEVICE_ID_TIGON3_5715S, 2774 quirk_msi_intx_disable_bug); 2775 2776 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390, 2777 quirk_msi_intx_disable_ati_bug); 2778 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391, 2779 quirk_msi_intx_disable_ati_bug); 2780 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392, 2781 quirk_msi_intx_disable_ati_bug); 2782 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393, 2783 quirk_msi_intx_disable_ati_bug); 2784 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394, 2785 quirk_msi_intx_disable_ati_bug); 2786 2787 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373, 2788 quirk_msi_intx_disable_bug); 2789 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374, 2790 quirk_msi_intx_disable_bug); 2791 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375, 2792 quirk_msi_intx_disable_bug); 2793 2794 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062, 2795 quirk_msi_intx_disable_bug); 2796 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063, 2797 quirk_msi_intx_disable_bug); 2798 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060, 2799 quirk_msi_intx_disable_bug); 2800 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062, 2801 quirk_msi_intx_disable_bug); 2802 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073, 2803 quirk_msi_intx_disable_bug); 2804 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083, 2805 quirk_msi_intx_disable_bug); 2806 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090, 2807 quirk_msi_intx_disable_qca_bug); 2808 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091, 2809 quirk_msi_intx_disable_qca_bug); 2810 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0, 2811 quirk_msi_intx_disable_qca_bug); 2812 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1, 2813 quirk_msi_intx_disable_qca_bug); 2814 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091, 2815 quirk_msi_intx_disable_qca_bug); 2816 #endif /* CONFIG_PCI_MSI */ 2817 2818 /* Allow manual resource allocation for PCI hotplug bridges 2819 * via pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For 2820 * some PCI-PCI hotplug bridges, like PLX 6254 (former HINT HB6), 2821 * kernel fails to allocate resources when hotplug device is 2822 * inserted and PCI bus is rescanned. 2823 */ 2824 static void quirk_hotplug_bridge(struct pci_dev *dev) 2825 { 2826 dev->is_hotplug_bridge = 1; 2827 } 2828 2829 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge); 2830 2831 /* 2832 * This is a quirk for the Ricoh MMC controller found as a part of 2833 * some mulifunction chips. 2834 2835 * This is very similar and based on the ricoh_mmc driver written by 2836 * Philip Langdale. Thank you for these magic sequences. 2837 * 2838 * These chips implement the four main memory card controllers (SD, MMC, MS, xD) 2839 * and one or both of cardbus or firewire. 2840 * 2841 * It happens that they implement SD and MMC 2842 * support as separate controllers (and PCI functions). The linux SDHCI 2843 * driver supports MMC cards but the chip detects MMC cards in hardware 2844 * and directs them to the MMC controller - so the SDHCI driver never sees 2845 * them. 2846 * 2847 * To get around this, we must disable the useless MMC controller. 2848 * At that point, the SDHCI controller will start seeing them 2849 * It seems to be the case that the relevant PCI registers to deactivate the 2850 * MMC controller live on PCI function 0, which might be the cardbus controller 2851 * or the firewire controller, depending on the particular chip in question 2852 * 2853 * This has to be done early, because as soon as we disable the MMC controller 2854 * other pci functions shift up one level, e.g. function #2 becomes function 2855 * #1, and this will confuse the pci core. 2856 */ 2857 2858 #ifdef CONFIG_MMC_RICOH_MMC 2859 static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev) 2860 { 2861 /* disable via cardbus interface */ 2862 u8 write_enable; 2863 u8 write_target; 2864 u8 disable; 2865 2866 /* disable must be done via function #0 */ 2867 if (PCI_FUNC(dev->devfn)) 2868 return; 2869 2870 pci_read_config_byte(dev, 0xB7, &disable); 2871 if (disable & 0x02) 2872 return; 2873 2874 pci_read_config_byte(dev, 0x8E, &write_enable); 2875 pci_write_config_byte(dev, 0x8E, 0xAA); 2876 pci_read_config_byte(dev, 0x8D, &write_target); 2877 pci_write_config_byte(dev, 0x8D, 0xB7); 2878 pci_write_config_byte(dev, 0xB7, disable | 0x02); 2879 pci_write_config_byte(dev, 0x8E, write_enable); 2880 pci_write_config_byte(dev, 0x8D, write_target); 2881 2882 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via cardbus function)\n"); 2883 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n"); 2884 } 2885 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); 2886 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); 2887 2888 static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev) 2889 { 2890 /* disable via firewire interface */ 2891 u8 write_enable; 2892 u8 disable; 2893 2894 /* disable must be done via function #0 */ 2895 if (PCI_FUNC(dev->devfn)) 2896 return; 2897 /* 2898 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize 2899 * certain types of SD/MMC cards. Lowering the SD base 2900 * clock frequency from 200Mhz to 50Mhz fixes this issue. 2901 * 2902 * 0x150 - SD2.0 mode enable for changing base clock 2903 * frequency to 50Mhz 2904 * 0xe1 - Base clock frequency 2905 * 0x32 - 50Mhz new clock frequency 2906 * 0xf9 - Key register for 0x150 2907 * 0xfc - key register for 0xe1 2908 */ 2909 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 || 2910 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) { 2911 pci_write_config_byte(dev, 0xf9, 0xfc); 2912 pci_write_config_byte(dev, 0x150, 0x10); 2913 pci_write_config_byte(dev, 0xf9, 0x00); 2914 pci_write_config_byte(dev, 0xfc, 0x01); 2915 pci_write_config_byte(dev, 0xe1, 0x32); 2916 pci_write_config_byte(dev, 0xfc, 0x00); 2917 2918 pci_notice(dev, "MMC controller base frequency changed to 50Mhz.\n"); 2919 } 2920 2921 pci_read_config_byte(dev, 0xCB, &disable); 2922 2923 if (disable & 0x02) 2924 return; 2925 2926 pci_read_config_byte(dev, 0xCA, &write_enable); 2927 pci_write_config_byte(dev, 0xCA, 0x57); 2928 pci_write_config_byte(dev, 0xCB, disable | 0x02); 2929 pci_write_config_byte(dev, 0xCA, write_enable); 2930 2931 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via firewire function)\n"); 2932 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n"); 2933 2934 } 2935 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); 2936 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); 2937 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832); 2938 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832); 2939 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832); 2940 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832); 2941 #endif /*CONFIG_MMC_RICOH_MMC*/ 2942 2943 #ifdef CONFIG_DMAR_TABLE 2944 #define VTUNCERRMSK_REG 0x1ac 2945 #define VTD_MSK_SPEC_ERRORS (1 << 31) 2946 /* 2947 * This is a quirk for masking vt-d spec defined errors to platform error 2948 * handling logic. With out this, platforms using Intel 7500, 5500 chipsets 2949 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based 2950 * on the RAS config settings of the platform) when a vt-d fault happens. 2951 * The resulting SMI caused the system to hang. 2952 * 2953 * VT-d spec related errors are already handled by the VT-d OS code, so no 2954 * need to report the same error through other channels. 2955 */ 2956 static void vtd_mask_spec_errors(struct pci_dev *dev) 2957 { 2958 u32 word; 2959 2960 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word); 2961 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS); 2962 } 2963 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors); 2964 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors); 2965 #endif 2966 2967 static void fixup_ti816x_class(struct pci_dev *dev) 2968 { 2969 u32 class = dev->class; 2970 2971 /* TI 816x devices do not have class code set when in PCIe boot mode */ 2972 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8; 2973 pci_info(dev, "PCI class overridden (%#08x -> %#08x)\n", 2974 class, dev->class); 2975 } 2976 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800, 2977 PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class); 2978 2979 /* Some PCIe devices do not work reliably with the claimed maximum 2980 * payload size supported. 2981 */ 2982 static void fixup_mpss_256(struct pci_dev *dev) 2983 { 2984 dev->pcie_mpss = 1; /* 256 bytes */ 2985 } 2986 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE, 2987 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256); 2988 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE, 2989 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256); 2990 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE, 2991 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256); 2992 2993 /* Intel 5000 and 5100 Memory controllers have an errata with read completion 2994 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B. 2995 * Since there is no way of knowing what the PCIE MPS on each fabric will be 2996 * until all of the devices are discovered and buses walked, read completion 2997 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because 2998 * it is possible to hotplug a device with MPS of 256B. 2999 */ 3000 static void quirk_intel_mc_errata(struct pci_dev *dev) 3001 { 3002 int err; 3003 u16 rcc; 3004 3005 if (pcie_bus_config == PCIE_BUS_TUNE_OFF || 3006 pcie_bus_config == PCIE_BUS_DEFAULT) 3007 return; 3008 3009 /* Intel errata specifies bits to change but does not say what they are. 3010 * Keeping them magical until such time as the registers and values can 3011 * be explained. 3012 */ 3013 err = pci_read_config_word(dev, 0x48, &rcc); 3014 if (err) { 3015 pci_err(dev, "Error attempting to read the read completion coalescing register\n"); 3016 return; 3017 } 3018 3019 if (!(rcc & (1 << 10))) 3020 return; 3021 3022 rcc &= ~(1 << 10); 3023 3024 err = pci_write_config_word(dev, 0x48, rcc); 3025 if (err) { 3026 pci_err(dev, "Error attempting to write the read completion coalescing register\n"); 3027 return; 3028 } 3029 3030 pr_info_once("Read completion coalescing disabled due to hardware errata relating to 256B MPS\n"); 3031 } 3032 /* Intel 5000 series memory controllers and ports 2-7 */ 3033 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata); 3034 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata); 3035 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata); 3036 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata); 3037 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata); 3038 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata); 3039 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata); 3040 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata); 3041 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata); 3042 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata); 3043 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata); 3044 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata); 3045 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata); 3046 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata); 3047 /* Intel 5100 series memory controllers and ports 2-7 */ 3048 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata); 3049 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata); 3050 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata); 3051 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata); 3052 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata); 3053 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata); 3054 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata); 3055 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata); 3056 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata); 3057 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata); 3058 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata); 3059 3060 3061 /* 3062 * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum. To 3063 * work around this, query the size it should be configured to by the device and 3064 * modify the resource end to correspond to this new size. 3065 */ 3066 static void quirk_intel_ntb(struct pci_dev *dev) 3067 { 3068 int rc; 3069 u8 val; 3070 3071 rc = pci_read_config_byte(dev, 0x00D0, &val); 3072 if (rc) 3073 return; 3074 3075 dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1; 3076 3077 rc = pci_read_config_byte(dev, 0x00D1, &val); 3078 if (rc) 3079 return; 3080 3081 dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1; 3082 } 3083 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb); 3084 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb); 3085 3086 static ktime_t fixup_debug_start(struct pci_dev *dev, 3087 void (*fn)(struct pci_dev *dev)) 3088 { 3089 ktime_t calltime = 0; 3090 3091 pci_dbg(dev, "calling %pF\n", fn); 3092 if (initcall_debug) { 3093 pr_debug("calling %pF @ %i for %s\n", 3094 fn, task_pid_nr(current), dev_name(&dev->dev)); 3095 calltime = ktime_get(); 3096 } 3097 3098 return calltime; 3099 } 3100 3101 static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime, 3102 void (*fn)(struct pci_dev *dev)) 3103 { 3104 ktime_t delta, rettime; 3105 unsigned long long duration; 3106 3107 if (initcall_debug) { 3108 rettime = ktime_get(); 3109 delta = ktime_sub(rettime, calltime); 3110 duration = (unsigned long long) ktime_to_ns(delta) >> 10; 3111 pr_debug("pci fixup %pF returned after %lld usecs for %s\n", 3112 fn, duration, dev_name(&dev->dev)); 3113 } 3114 } 3115 3116 /* 3117 * Some BIOS implementations leave the Intel GPU interrupts enabled, 3118 * even though no one is handling them (f.e. i915 driver is never loaded). 3119 * Additionally the interrupt destination is not set up properly 3120 * and the interrupt ends up -somewhere-. 3121 * 3122 * These spurious interrupts are "sticky" and the kernel disables 3123 * the (shared) interrupt line after 100.000+ generated interrupts. 3124 * 3125 * Fix it by disabling the still enabled interrupts. 3126 * This resolves crashes often seen on monitor unplug. 3127 */ 3128 #define I915_DEIER_REG 0x4400c 3129 static void disable_igfx_irq(struct pci_dev *dev) 3130 { 3131 void __iomem *regs = pci_iomap(dev, 0, 0); 3132 if (regs == NULL) { 3133 pci_warn(dev, "igfx quirk: Can't iomap PCI device\n"); 3134 return; 3135 } 3136 3137 /* Check if any interrupt line is still enabled */ 3138 if (readl(regs + I915_DEIER_REG) != 0) { 3139 pci_warn(dev, "BIOS left Intel GPU interrupts enabled; disabling\n"); 3140 3141 writel(0, regs + I915_DEIER_REG); 3142 } 3143 3144 pci_iounmap(dev, regs); 3145 } 3146 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq); 3147 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq); 3148 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq); 3149 3150 /* 3151 * PCI devices which are on Intel chips can skip the 10ms delay 3152 * before entering D3 mode. 3153 */ 3154 static void quirk_remove_d3_delay(struct pci_dev *dev) 3155 { 3156 dev->d3_delay = 0; 3157 } 3158 /* C600 Series devices do not need 10ms d3_delay */ 3159 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3_delay); 3160 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3_delay); 3161 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3_delay); 3162 /* Lynxpoint-H PCH devices do not need 10ms d3_delay */ 3163 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3_delay); 3164 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3_delay); 3165 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3_delay); 3166 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3_delay); 3167 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3_delay); 3168 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3_delay); 3169 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3_delay); 3170 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3_delay); 3171 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3_delay); 3172 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3_delay); 3173 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3_delay); 3174 /* Intel Cherrytrail devices do not need 10ms d3_delay */ 3175 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3_delay); 3176 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3_delay); 3177 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3_delay); 3178 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3_delay); 3179 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3_delay); 3180 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3_delay); 3181 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3_delay); 3182 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3_delay); 3183 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3_delay); 3184 3185 /* 3186 * Some devices may pass our check in pci_intx_mask_supported() if 3187 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly 3188 * support this feature. 3189 */ 3190 static void quirk_broken_intx_masking(struct pci_dev *dev) 3191 { 3192 dev->broken_intx_masking = 1; 3193 } 3194 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x0030, 3195 quirk_broken_intx_masking); 3196 DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */ 3197 quirk_broken_intx_masking); 3198 DECLARE_PCI_FIXUP_FINAL(0x1b7c, 0x0004, /* Ceton InfiniTV4 */ 3199 quirk_broken_intx_masking); 3200 3201 /* 3202 * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10) 3203 * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC 3204 * 3205 * RTL8110SC - Fails under PCI device assignment using DisINTx masking. 3206 */ 3207 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REALTEK, 0x8169, 3208 quirk_broken_intx_masking); 3209 3210 /* 3211 * Intel i40e (XL710/X710) 10/20/40GbE NICs all have broken INTx masking, 3212 * DisINTx can be set but the interrupt status bit is non-functional. 3213 */ 3214 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1572, 3215 quirk_broken_intx_masking); 3216 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1574, 3217 quirk_broken_intx_masking); 3218 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1580, 3219 quirk_broken_intx_masking); 3220 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1581, 3221 quirk_broken_intx_masking); 3222 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1583, 3223 quirk_broken_intx_masking); 3224 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1584, 3225 quirk_broken_intx_masking); 3226 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1585, 3227 quirk_broken_intx_masking); 3228 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1586, 3229 quirk_broken_intx_masking); 3230 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1587, 3231 quirk_broken_intx_masking); 3232 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1588, 3233 quirk_broken_intx_masking); 3234 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1589, 3235 quirk_broken_intx_masking); 3236 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158a, 3237 quirk_broken_intx_masking); 3238 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158b, 3239 quirk_broken_intx_masking); 3240 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d0, 3241 quirk_broken_intx_masking); 3242 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d1, 3243 quirk_broken_intx_masking); 3244 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d2, 3245 quirk_broken_intx_masking); 3246 3247 static u16 mellanox_broken_intx_devs[] = { 3248 PCI_DEVICE_ID_MELLANOX_HERMON_SDR, 3249 PCI_DEVICE_ID_MELLANOX_HERMON_DDR, 3250 PCI_DEVICE_ID_MELLANOX_HERMON_QDR, 3251 PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2, 3252 PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2, 3253 PCI_DEVICE_ID_MELLANOX_HERMON_EN, 3254 PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2, 3255 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN, 3256 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2, 3257 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2, 3258 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2, 3259 PCI_DEVICE_ID_MELLANOX_CONNECTX2, 3260 PCI_DEVICE_ID_MELLANOX_CONNECTX3, 3261 PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO, 3262 }; 3263 3264 #define CONNECTX_4_CURR_MAX_MINOR 99 3265 #define CONNECTX_4_INTX_SUPPORT_MINOR 14 3266 3267 /* 3268 * Check ConnectX-4/LX FW version to see if it supports legacy interrupts. 3269 * If so, don't mark it as broken. 3270 * FW minor > 99 means older FW version format and no INTx masking support. 3271 * FW minor < 14 means new FW version format and no INTx masking support. 3272 */ 3273 static void mellanox_check_broken_intx_masking(struct pci_dev *pdev) 3274 { 3275 __be32 __iomem *fw_ver; 3276 u16 fw_major; 3277 u16 fw_minor; 3278 u16 fw_subminor; 3279 u32 fw_maj_min; 3280 u32 fw_sub_min; 3281 int i; 3282 3283 for (i = 0; i < ARRAY_SIZE(mellanox_broken_intx_devs); i++) { 3284 if (pdev->device == mellanox_broken_intx_devs[i]) { 3285 pdev->broken_intx_masking = 1; 3286 return; 3287 } 3288 } 3289 3290 /* Getting here means Connect-IB cards and up. Connect-IB has no INTx 3291 * support so shouldn't be checked further 3292 */ 3293 if (pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTIB) 3294 return; 3295 3296 if (pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4 && 3297 pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) 3298 return; 3299 3300 /* For ConnectX-4 and ConnectX-4LX, need to check FW support */ 3301 if (pci_enable_device_mem(pdev)) { 3302 pci_warn(pdev, "Can't enable device memory\n"); 3303 return; 3304 } 3305 3306 fw_ver = ioremap(pci_resource_start(pdev, 0), 4); 3307 if (!fw_ver) { 3308 pci_warn(pdev, "Can't map ConnectX-4 initialization segment\n"); 3309 goto out; 3310 } 3311 3312 /* Reading from resource space should be 32b aligned */ 3313 fw_maj_min = ioread32be(fw_ver); 3314 fw_sub_min = ioread32be(fw_ver + 1); 3315 fw_major = fw_maj_min & 0xffff; 3316 fw_minor = fw_maj_min >> 16; 3317 fw_subminor = fw_sub_min & 0xffff; 3318 if (fw_minor > CONNECTX_4_CURR_MAX_MINOR || 3319 fw_minor < CONNECTX_4_INTX_SUPPORT_MINOR) { 3320 pci_warn(pdev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW to %d.14.1100 and up for INTx support\n", 3321 fw_major, fw_minor, fw_subminor, pdev->device == 3322 PCI_DEVICE_ID_MELLANOX_CONNECTX4 ? 12 : 14); 3323 pdev->broken_intx_masking = 1; 3324 } 3325 3326 iounmap(fw_ver); 3327 3328 out: 3329 pci_disable_device(pdev); 3330 } 3331 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_ANY_ID, 3332 mellanox_check_broken_intx_masking); 3333 3334 static void quirk_no_bus_reset(struct pci_dev *dev) 3335 { 3336 dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET; 3337 } 3338 3339 /* 3340 * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset. 3341 * The device will throw a Link Down error on AER-capable systems and 3342 * regardless of AER, config space of the device is never accessible again 3343 * and typically causes the system to hang or reset when access is attempted. 3344 * http://www.spinics.net/lists/linux-pci/msg34797.html 3345 */ 3346 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset); 3347 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset); 3348 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset); 3349 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset); 3350 3351 /* 3352 * Root port on some Cavium CN8xxx chips do not successfully complete a bus 3353 * reset when used with certain child devices. After the reset, config 3354 * accesses to the child may fail. 3355 */ 3356 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_no_bus_reset); 3357 3358 static void quirk_no_pm_reset(struct pci_dev *dev) 3359 { 3360 /* 3361 * We can't do a bus reset on root bus devices, but an ineffective 3362 * PM reset may be better than nothing. 3363 */ 3364 if (!pci_is_root_bus(dev->bus)) 3365 dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET; 3366 } 3367 3368 /* 3369 * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition 3370 * causes a reset (i.e., they advertise NoSoftRst-). This transition seems 3371 * to have no effect on the device: it retains the framebuffer contents and 3372 * monitor sync. Advertising this support makes other layers, like VFIO, 3373 * assume pci_reset_function() is viable for this device. Mark it as 3374 * unavailable to skip it when testing reset methods. 3375 */ 3376 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 3377 PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset); 3378 3379 /* 3380 * Thunderbolt controllers with broken MSI hotplug signaling: 3381 * Entire 1st generation (Light Ridge, Eagle Ridge, Light Peak) and part 3382 * of the 2nd generation (Cactus Ridge 4C up to revision 1, Port Ridge). 3383 */ 3384 static void quirk_thunderbolt_hotplug_msi(struct pci_dev *pdev) 3385 { 3386 if (pdev->is_hotplug_bridge && 3387 (pdev->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C || 3388 pdev->revision <= 1)) 3389 pdev->no_msi = 1; 3390 } 3391 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_RIDGE, 3392 quirk_thunderbolt_hotplug_msi); 3393 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EAGLE_RIDGE, 3394 quirk_thunderbolt_hotplug_msi); 3395 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_PEAK, 3396 quirk_thunderbolt_hotplug_msi); 3397 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C, 3398 quirk_thunderbolt_hotplug_msi); 3399 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PORT_RIDGE, 3400 quirk_thunderbolt_hotplug_msi); 3401 3402 static void quirk_chelsio_extend_vpd(struct pci_dev *dev) 3403 { 3404 int chip = (dev->device & 0xf000) >> 12; 3405 int func = (dev->device & 0x0f00) >> 8; 3406 int prod = (dev->device & 0x00ff) >> 0; 3407 3408 /* 3409 * If this is a T3-based adapter, there's a 1KB VPD area at offset 3410 * 0xc00 which contains the preferred VPD values. If this is a T4 or 3411 * later based adapter, the special VPD is at offset 0x400 for the 3412 * Physical Functions (the SR-IOV Virtual Functions have no VPD 3413 * Capabilities). The PCI VPD Access core routines will normally 3414 * compute the size of the VPD by parsing the VPD Data Structure at 3415 * offset 0x000. This will result in silent failures when attempting 3416 * to accesses these other VPD areas which are beyond those computed 3417 * limits. 3418 */ 3419 if (chip == 0x0 && prod >= 0x20) 3420 pci_set_vpd_size(dev, 8192); 3421 else if (chip >= 0x4 && func < 0x8) 3422 pci_set_vpd_size(dev, 2048); 3423 } 3424 3425 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID, 3426 quirk_chelsio_extend_vpd); 3427 3428 #ifdef CONFIG_ACPI 3429 /* 3430 * Apple: Shutdown Cactus Ridge Thunderbolt controller. 3431 * 3432 * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be 3433 * shutdown before suspend. Otherwise the native host interface (NHI) will not 3434 * be present after resume if a device was plugged in before suspend. 3435 * 3436 * The thunderbolt controller consists of a pcie switch with downstream 3437 * bridges leading to the NHI and to the tunnel pci bridges. 3438 * 3439 * This quirk cuts power to the whole chip. Therefore we have to apply it 3440 * during suspend_noirq of the upstream bridge. 3441 * 3442 * Power is automagically restored before resume. No action is needed. 3443 */ 3444 static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev) 3445 { 3446 acpi_handle bridge, SXIO, SXFP, SXLV; 3447 3448 if (!x86_apple_machine) 3449 return; 3450 if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM) 3451 return; 3452 bridge = ACPI_HANDLE(&dev->dev); 3453 if (!bridge) 3454 return; 3455 /* 3456 * SXIO and SXLV are present only on machines requiring this quirk. 3457 * TB bridges in external devices might have the same device id as those 3458 * on the host, but they will not have the associated ACPI methods. This 3459 * implicitly checks that we are at the right bridge. 3460 */ 3461 if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO)) 3462 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP)) 3463 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV))) 3464 return; 3465 pci_info(dev, "quirk: cutting power to thunderbolt controller...\n"); 3466 3467 /* magic sequence */ 3468 acpi_execute_simple_method(SXIO, NULL, 1); 3469 acpi_execute_simple_method(SXFP, NULL, 0); 3470 msleep(300); 3471 acpi_execute_simple_method(SXLV, NULL, 0); 3472 acpi_execute_simple_method(SXIO, NULL, 0); 3473 acpi_execute_simple_method(SXLV, NULL, 0); 3474 } 3475 DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL, 3476 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C, 3477 quirk_apple_poweroff_thunderbolt); 3478 3479 /* 3480 * Apple: Wait for the thunderbolt controller to reestablish pci tunnels. 3481 * 3482 * During suspend the thunderbolt controller is reset and all pci 3483 * tunnels are lost. The NHI driver will try to reestablish all tunnels 3484 * during resume. We have to manually wait for the NHI since there is 3485 * no parent child relationship between the NHI and the tunneled 3486 * bridges. 3487 */ 3488 static void quirk_apple_wait_for_thunderbolt(struct pci_dev *dev) 3489 { 3490 struct pci_dev *sibling = NULL; 3491 struct pci_dev *nhi = NULL; 3492 3493 if (!x86_apple_machine) 3494 return; 3495 if (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM) 3496 return; 3497 /* 3498 * Find the NHI and confirm that we are a bridge on the tb host 3499 * controller and not on a tb endpoint. 3500 */ 3501 sibling = pci_get_slot(dev->bus, 0x0); 3502 if (sibling == dev) 3503 goto out; /* we are the downstream bridge to the NHI */ 3504 if (!sibling || !sibling->subordinate) 3505 goto out; 3506 nhi = pci_get_slot(sibling->subordinate, 0x0); 3507 if (!nhi) 3508 goto out; 3509 if (nhi->vendor != PCI_VENDOR_ID_INTEL 3510 || (nhi->device != PCI_DEVICE_ID_INTEL_LIGHT_RIDGE && 3511 nhi->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C && 3512 nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI && 3513 nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI) 3514 || nhi->class != PCI_CLASS_SYSTEM_OTHER << 8) 3515 goto out; 3516 pci_info(dev, "quirk: waiting for thunderbolt to reestablish PCI tunnels...\n"); 3517 device_pm_wait_for_dev(&dev->dev, &nhi->dev); 3518 out: 3519 pci_dev_put(nhi); 3520 pci_dev_put(sibling); 3521 } 3522 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, 3523 PCI_DEVICE_ID_INTEL_LIGHT_RIDGE, 3524 quirk_apple_wait_for_thunderbolt); 3525 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, 3526 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C, 3527 quirk_apple_wait_for_thunderbolt); 3528 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, 3529 PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_BRIDGE, 3530 quirk_apple_wait_for_thunderbolt); 3531 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, 3532 PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_BRIDGE, 3533 quirk_apple_wait_for_thunderbolt); 3534 #endif 3535 3536 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, 3537 struct pci_fixup *end) 3538 { 3539 ktime_t calltime; 3540 3541 for (; f < end; f++) 3542 if ((f->class == (u32) (dev->class >> f->class_shift) || 3543 f->class == (u32) PCI_ANY_ID) && 3544 (f->vendor == dev->vendor || 3545 f->vendor == (u16) PCI_ANY_ID) && 3546 (f->device == dev->device || 3547 f->device == (u16) PCI_ANY_ID)) { 3548 calltime = fixup_debug_start(dev, f->hook); 3549 f->hook(dev); 3550 fixup_debug_report(dev, calltime, f->hook); 3551 } 3552 } 3553 3554 extern struct pci_fixup __start_pci_fixups_early[]; 3555 extern struct pci_fixup __end_pci_fixups_early[]; 3556 extern struct pci_fixup __start_pci_fixups_header[]; 3557 extern struct pci_fixup __end_pci_fixups_header[]; 3558 extern struct pci_fixup __start_pci_fixups_final[]; 3559 extern struct pci_fixup __end_pci_fixups_final[]; 3560 extern struct pci_fixup __start_pci_fixups_enable[]; 3561 extern struct pci_fixup __end_pci_fixups_enable[]; 3562 extern struct pci_fixup __start_pci_fixups_resume[]; 3563 extern struct pci_fixup __end_pci_fixups_resume[]; 3564 extern struct pci_fixup __start_pci_fixups_resume_early[]; 3565 extern struct pci_fixup __end_pci_fixups_resume_early[]; 3566 extern struct pci_fixup __start_pci_fixups_suspend[]; 3567 extern struct pci_fixup __end_pci_fixups_suspend[]; 3568 extern struct pci_fixup __start_pci_fixups_suspend_late[]; 3569 extern struct pci_fixup __end_pci_fixups_suspend_late[]; 3570 3571 static bool pci_apply_fixup_final_quirks; 3572 3573 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) 3574 { 3575 struct pci_fixup *start, *end; 3576 3577 switch (pass) { 3578 case pci_fixup_early: 3579 start = __start_pci_fixups_early; 3580 end = __end_pci_fixups_early; 3581 break; 3582 3583 case pci_fixup_header: 3584 start = __start_pci_fixups_header; 3585 end = __end_pci_fixups_header; 3586 break; 3587 3588 case pci_fixup_final: 3589 if (!pci_apply_fixup_final_quirks) 3590 return; 3591 start = __start_pci_fixups_final; 3592 end = __end_pci_fixups_final; 3593 break; 3594 3595 case pci_fixup_enable: 3596 start = __start_pci_fixups_enable; 3597 end = __end_pci_fixups_enable; 3598 break; 3599 3600 case pci_fixup_resume: 3601 start = __start_pci_fixups_resume; 3602 end = __end_pci_fixups_resume; 3603 break; 3604 3605 case pci_fixup_resume_early: 3606 start = __start_pci_fixups_resume_early; 3607 end = __end_pci_fixups_resume_early; 3608 break; 3609 3610 case pci_fixup_suspend: 3611 start = __start_pci_fixups_suspend; 3612 end = __end_pci_fixups_suspend; 3613 break; 3614 3615 case pci_fixup_suspend_late: 3616 start = __start_pci_fixups_suspend_late; 3617 end = __end_pci_fixups_suspend_late; 3618 break; 3619 3620 default: 3621 /* stupid compiler warning, you would think with an enum... */ 3622 return; 3623 } 3624 pci_do_fixups(dev, start, end); 3625 } 3626 EXPORT_SYMBOL(pci_fixup_device); 3627 3628 3629 static int __init pci_apply_final_quirks(void) 3630 { 3631 struct pci_dev *dev = NULL; 3632 u8 cls = 0; 3633 u8 tmp; 3634 3635 if (pci_cache_line_size) 3636 printk(KERN_DEBUG "PCI: CLS %u bytes\n", 3637 pci_cache_line_size << 2); 3638 3639 pci_apply_fixup_final_quirks = true; 3640 for_each_pci_dev(dev) { 3641 pci_fixup_device(pci_fixup_final, dev); 3642 /* 3643 * If arch hasn't set it explicitly yet, use the CLS 3644 * value shared by all PCI devices. If there's a 3645 * mismatch, fall back to the default value. 3646 */ 3647 if (!pci_cache_line_size) { 3648 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp); 3649 if (!cls) 3650 cls = tmp; 3651 if (!tmp || cls == tmp) 3652 continue; 3653 3654 printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), using %u bytes\n", 3655 cls << 2, tmp << 2, 3656 pci_dfl_cache_line_size << 2); 3657 pci_cache_line_size = pci_dfl_cache_line_size; 3658 } 3659 } 3660 3661 if (!pci_cache_line_size) { 3662 printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n", 3663 cls << 2, pci_dfl_cache_line_size << 2); 3664 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size; 3665 } 3666 3667 return 0; 3668 } 3669 3670 fs_initcall_sync(pci_apply_final_quirks); 3671 3672 /* 3673 * Following are device-specific reset methods which can be used to 3674 * reset a single function if other methods (e.g. FLR, PM D0->D3) are 3675 * not available. 3676 */ 3677 static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe) 3678 { 3679 /* 3680 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf 3681 * 3682 * The 82599 supports FLR on VFs, but FLR support is reported only 3683 * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5). 3684 * Thus we must call pcie_flr() directly without first checking if it is 3685 * supported. 3686 */ 3687 if (!probe) 3688 pcie_flr(dev); 3689 return 0; 3690 } 3691 3692 #define SOUTH_CHICKEN2 0xc2004 3693 #define PCH_PP_STATUS 0xc7200 3694 #define PCH_PP_CONTROL 0xc7204 3695 #define MSG_CTL 0x45010 3696 #define NSDE_PWR_STATE 0xd0100 3697 #define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */ 3698 3699 static int reset_ivb_igd(struct pci_dev *dev, int probe) 3700 { 3701 void __iomem *mmio_base; 3702 unsigned long timeout; 3703 u32 val; 3704 3705 if (probe) 3706 return 0; 3707 3708 mmio_base = pci_iomap(dev, 0, 0); 3709 if (!mmio_base) 3710 return -ENOMEM; 3711 3712 iowrite32(0x00000002, mmio_base + MSG_CTL); 3713 3714 /* 3715 * Clobbering SOUTH_CHICKEN2 register is fine only if the next 3716 * driver loaded sets the right bits. However, this's a reset and 3717 * the bits have been set by i915 previously, so we clobber 3718 * SOUTH_CHICKEN2 register directly here. 3719 */ 3720 iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2); 3721 3722 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe; 3723 iowrite32(val, mmio_base + PCH_PP_CONTROL); 3724 3725 timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT); 3726 do { 3727 val = ioread32(mmio_base + PCH_PP_STATUS); 3728 if ((val & 0xb0000000) == 0) 3729 goto reset_complete; 3730 msleep(10); 3731 } while (time_before(jiffies, timeout)); 3732 pci_warn(dev, "timeout during reset\n"); 3733 3734 reset_complete: 3735 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE); 3736 3737 pci_iounmap(dev, mmio_base); 3738 return 0; 3739 } 3740 3741 /* 3742 * Device-specific reset method for Chelsio T4-based adapters. 3743 */ 3744 static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe) 3745 { 3746 u16 old_command; 3747 u16 msix_flags; 3748 3749 /* 3750 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating 3751 * that we have no device-specific reset method. 3752 */ 3753 if ((dev->device & 0xf000) != 0x4000) 3754 return -ENOTTY; 3755 3756 /* 3757 * If this is the "probe" phase, return 0 indicating that we can 3758 * reset this device. 3759 */ 3760 if (probe) 3761 return 0; 3762 3763 /* 3764 * T4 can wedge if there are DMAs in flight within the chip and Bus 3765 * Master has been disabled. We need to have it on till the Function 3766 * Level Reset completes. (BUS_MASTER is disabled in 3767 * pci_reset_function()). 3768 */ 3769 pci_read_config_word(dev, PCI_COMMAND, &old_command); 3770 pci_write_config_word(dev, PCI_COMMAND, 3771 old_command | PCI_COMMAND_MASTER); 3772 3773 /* 3774 * Perform the actual device function reset, saving and restoring 3775 * configuration information around the reset. 3776 */ 3777 pci_save_state(dev); 3778 3779 /* 3780 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts 3781 * are disabled when an MSI-X interrupt message needs to be delivered. 3782 * So we briefly re-enable MSI-X interrupts for the duration of the 3783 * FLR. The pci_restore_state() below will restore the original 3784 * MSI-X state. 3785 */ 3786 pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags); 3787 if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0) 3788 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, 3789 msix_flags | 3790 PCI_MSIX_FLAGS_ENABLE | 3791 PCI_MSIX_FLAGS_MASKALL); 3792 3793 pcie_flr(dev); 3794 3795 /* 3796 * Restore the configuration information (BAR values, etc.) including 3797 * the original PCI Configuration Space Command word, and return 3798 * success. 3799 */ 3800 pci_restore_state(dev); 3801 pci_write_config_word(dev, PCI_COMMAND, old_command); 3802 return 0; 3803 } 3804 3805 #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed 3806 #define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156 3807 #define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166 3808 3809 static const struct pci_dev_reset_methods pci_dev_reset_methods[] = { 3810 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF, 3811 reset_intel_82599_sfp_virtfn }, 3812 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA, 3813 reset_ivb_igd }, 3814 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA, 3815 reset_ivb_igd }, 3816 { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID, 3817 reset_chelsio_generic_dev }, 3818 { 0 } 3819 }; 3820 3821 /* 3822 * These device-specific reset methods are here rather than in a driver 3823 * because when a host assigns a device to a guest VM, the host may need 3824 * to reset the device but probably doesn't have a driver for it. 3825 */ 3826 int pci_dev_specific_reset(struct pci_dev *dev, int probe) 3827 { 3828 const struct pci_dev_reset_methods *i; 3829 3830 for (i = pci_dev_reset_methods; i->reset; i++) { 3831 if ((i->vendor == dev->vendor || 3832 i->vendor == (u16)PCI_ANY_ID) && 3833 (i->device == dev->device || 3834 i->device == (u16)PCI_ANY_ID)) 3835 return i->reset(dev, probe); 3836 } 3837 3838 return -ENOTTY; 3839 } 3840 3841 static void quirk_dma_func0_alias(struct pci_dev *dev) 3842 { 3843 if (PCI_FUNC(dev->devfn) != 0) 3844 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0)); 3845 } 3846 3847 /* 3848 * https://bugzilla.redhat.com/show_bug.cgi?id=605888 3849 * 3850 * Some Ricoh devices use function 0 as the PCIe requester ID for DMA. 3851 */ 3852 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias); 3853 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias); 3854 3855 static void quirk_dma_func1_alias(struct pci_dev *dev) 3856 { 3857 if (PCI_FUNC(dev->devfn) != 1) 3858 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1)); 3859 } 3860 3861 /* 3862 * Marvell 88SE9123 uses function 1 as the requester ID for DMA. In some 3863 * SKUs function 1 is present and is a legacy IDE controller, in other 3864 * SKUs this function is not present, making this a ghost requester. 3865 * https://bugzilla.kernel.org/show_bug.cgi?id=42679 3866 */ 3867 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120, 3868 quirk_dma_func1_alias); 3869 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123, 3870 quirk_dma_func1_alias); 3871 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9128, 3872 quirk_dma_func1_alias); 3873 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */ 3874 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130, 3875 quirk_dma_func1_alias); 3876 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */ 3877 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172, 3878 quirk_dma_func1_alias); 3879 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */ 3880 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a, 3881 quirk_dma_func1_alias); 3882 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c78 */ 3883 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9182, 3884 quirk_dma_func1_alias); 3885 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */ 3886 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0, 3887 quirk_dma_func1_alias); 3888 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */ 3889 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230, 3890 quirk_dma_func1_alias); 3891 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642, 3892 quirk_dma_func1_alias); 3893 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0645, 3894 quirk_dma_func1_alias); 3895 /* https://bugs.gentoo.org/show_bug.cgi?id=497630 */ 3896 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON, 3897 PCI_DEVICE_ID_JMICRON_JMB388_ESD, 3898 quirk_dma_func1_alias); 3899 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c117 */ 3900 DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */ 3901 0x0122, /* Plextor M6E (Marvell 88SS9183)*/ 3902 quirk_dma_func1_alias); 3903 3904 /* 3905 * Some devices DMA with the wrong devfn, not just the wrong function. 3906 * quirk_fixed_dma_alias() uses this table to create fixed aliases, where 3907 * the alias is "fixed" and independent of the device devfn. 3908 * 3909 * For example, the Adaptec 3405 is a PCIe card with an Intel 80333 I/O 3910 * processor. To software, this appears as a PCIe-to-PCI/X bridge with a 3911 * single device on the secondary bus. In reality, the single exposed 3912 * device at 0e.0 is the Address Translation Unit (ATU) of the controller 3913 * that provides a bridge to the internal bus of the I/O processor. The 3914 * controller supports private devices, which can be hidden from PCI config 3915 * space. In the case of the Adaptec 3405, a private device at 01.0 3916 * appears to be the DMA engine, which therefore needs to become a DMA 3917 * alias for the device. 3918 */ 3919 static const struct pci_device_id fixed_dma_alias_tbl[] = { 3920 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285, 3921 PCI_VENDOR_ID_ADAPTEC2, 0x02bb), /* Adaptec 3405 */ 3922 .driver_data = PCI_DEVFN(1, 0) }, 3923 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285, 3924 PCI_VENDOR_ID_ADAPTEC2, 0x02bc), /* Adaptec 3805 */ 3925 .driver_data = PCI_DEVFN(1, 0) }, 3926 { 0 } 3927 }; 3928 3929 static void quirk_fixed_dma_alias(struct pci_dev *dev) 3930 { 3931 const struct pci_device_id *id; 3932 3933 id = pci_match_id(fixed_dma_alias_tbl, dev); 3934 if (id) 3935 pci_add_dma_alias(dev, id->driver_data); 3936 } 3937 3938 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias); 3939 3940 /* 3941 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in 3942 * using the wrong DMA alias for the device. Some of these devices can be 3943 * used as either forward or reverse bridges, so we need to test whether the 3944 * device is operating in the correct mode. We could probably apply this 3945 * quirk to PCI_ANY_ID, but for now we'll just use known offenders. The test 3946 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and 3947 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge. 3948 */ 3949 static void quirk_use_pcie_bridge_dma_alias(struct pci_dev *pdev) 3950 { 3951 if (!pci_is_root_bus(pdev->bus) && 3952 pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE && 3953 !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) && 3954 pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE) 3955 pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS; 3956 } 3957 /* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */ 3958 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080, 3959 quirk_use_pcie_bridge_dma_alias); 3960 /* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */ 3961 DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias); 3962 /* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */ 3963 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias); 3964 /* ITE 8893 has the same problem as the 8892 */ 3965 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8893, quirk_use_pcie_bridge_dma_alias); 3966 /* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */ 3967 DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias); 3968 3969 /* 3970 * MIC x200 NTB forwards PCIe traffic using multiple alien RIDs. They have to 3971 * be added as aliases to the DMA device in order to allow buffer access 3972 * when IOMMU is enabled. Following devfns have to match RIT-LUT table 3973 * programmed in the EEPROM. 3974 */ 3975 static void quirk_mic_x200_dma_alias(struct pci_dev *pdev) 3976 { 3977 pci_add_dma_alias(pdev, PCI_DEVFN(0x10, 0x0)); 3978 pci_add_dma_alias(pdev, PCI_DEVFN(0x11, 0x0)); 3979 pci_add_dma_alias(pdev, PCI_DEVFN(0x12, 0x3)); 3980 } 3981 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2260, quirk_mic_x200_dma_alias); 3982 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2264, quirk_mic_x200_dma_alias); 3983 3984 /* 3985 * The IOMMU and interrupt controller on Broadcom Vulcan/Cavium ThunderX2 are 3986 * associated not at the root bus, but at a bridge below. This quirk avoids 3987 * generating invalid DMA aliases. 3988 */ 3989 static void quirk_bridge_cavm_thrx2_pcie_root(struct pci_dev *pdev) 3990 { 3991 pdev->dev_flags |= PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT; 3992 } 3993 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9000, 3994 quirk_bridge_cavm_thrx2_pcie_root); 3995 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9084, 3996 quirk_bridge_cavm_thrx2_pcie_root); 3997 3998 /* 3999 * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero) 4000 * class code. Fix it. 4001 */ 4002 static void quirk_tw686x_class(struct pci_dev *pdev) 4003 { 4004 u32 class = pdev->class; 4005 4006 /* Use "Multimedia controller" class */ 4007 pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01; 4008 pci_info(pdev, "TW686x PCI class overridden (%#08x -> %#08x)\n", 4009 class, pdev->class); 4010 } 4011 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8, 4012 quirk_tw686x_class); 4013 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED, 8, 4014 quirk_tw686x_class); 4015 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED, 8, 4016 quirk_tw686x_class); 4017 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8, 4018 quirk_tw686x_class); 4019 4020 /* 4021 * Some devices have problems with Transaction Layer Packets with the Relaxed 4022 * Ordering Attribute set. Such devices should mark themselves and other 4023 * Device Drivers should check before sending TLPs with RO set. 4024 */ 4025 static void quirk_relaxedordering_disable(struct pci_dev *dev) 4026 { 4027 dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING; 4028 pci_info(dev, "Disable Relaxed Ordering Attributes to avoid PCIe Completion erratum\n"); 4029 } 4030 4031 /* 4032 * Intel Xeon processors based on Broadwell/Haswell microarchitecture Root 4033 * Complex has a Flow Control Credit issue which can cause performance 4034 * problems with Upstream Transaction Layer Packets with Relaxed Ordering set. 4035 */ 4036 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f01, PCI_CLASS_NOT_DEFINED, 8, 4037 quirk_relaxedordering_disable); 4038 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f02, PCI_CLASS_NOT_DEFINED, 8, 4039 quirk_relaxedordering_disable); 4040 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f03, PCI_CLASS_NOT_DEFINED, 8, 4041 quirk_relaxedordering_disable); 4042 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f04, PCI_CLASS_NOT_DEFINED, 8, 4043 quirk_relaxedordering_disable); 4044 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f05, PCI_CLASS_NOT_DEFINED, 8, 4045 quirk_relaxedordering_disable); 4046 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f06, PCI_CLASS_NOT_DEFINED, 8, 4047 quirk_relaxedordering_disable); 4048 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f07, PCI_CLASS_NOT_DEFINED, 8, 4049 quirk_relaxedordering_disable); 4050 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f08, PCI_CLASS_NOT_DEFINED, 8, 4051 quirk_relaxedordering_disable); 4052 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f09, PCI_CLASS_NOT_DEFINED, 8, 4053 quirk_relaxedordering_disable); 4054 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0a, PCI_CLASS_NOT_DEFINED, 8, 4055 quirk_relaxedordering_disable); 4056 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0b, PCI_CLASS_NOT_DEFINED, 8, 4057 quirk_relaxedordering_disable); 4058 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0c, PCI_CLASS_NOT_DEFINED, 8, 4059 quirk_relaxedordering_disable); 4060 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0d, PCI_CLASS_NOT_DEFINED, 8, 4061 quirk_relaxedordering_disable); 4062 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0e, PCI_CLASS_NOT_DEFINED, 8, 4063 quirk_relaxedordering_disable); 4064 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f01, PCI_CLASS_NOT_DEFINED, 8, 4065 quirk_relaxedordering_disable); 4066 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f02, PCI_CLASS_NOT_DEFINED, 8, 4067 quirk_relaxedordering_disable); 4068 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f03, PCI_CLASS_NOT_DEFINED, 8, 4069 quirk_relaxedordering_disable); 4070 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f04, PCI_CLASS_NOT_DEFINED, 8, 4071 quirk_relaxedordering_disable); 4072 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f05, PCI_CLASS_NOT_DEFINED, 8, 4073 quirk_relaxedordering_disable); 4074 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f06, PCI_CLASS_NOT_DEFINED, 8, 4075 quirk_relaxedordering_disable); 4076 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f07, PCI_CLASS_NOT_DEFINED, 8, 4077 quirk_relaxedordering_disable); 4078 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f08, PCI_CLASS_NOT_DEFINED, 8, 4079 quirk_relaxedordering_disable); 4080 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f09, PCI_CLASS_NOT_DEFINED, 8, 4081 quirk_relaxedordering_disable); 4082 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0a, PCI_CLASS_NOT_DEFINED, 8, 4083 quirk_relaxedordering_disable); 4084 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0b, PCI_CLASS_NOT_DEFINED, 8, 4085 quirk_relaxedordering_disable); 4086 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0c, PCI_CLASS_NOT_DEFINED, 8, 4087 quirk_relaxedordering_disable); 4088 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0d, PCI_CLASS_NOT_DEFINED, 8, 4089 quirk_relaxedordering_disable); 4090 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0e, PCI_CLASS_NOT_DEFINED, 8, 4091 quirk_relaxedordering_disable); 4092 4093 /* 4094 * The AMD ARM A1100 (AKA "SEATTLE") SoC has a bug in its PCIe Root Complex 4095 * where Upstream Transaction Layer Packets with the Relaxed Ordering 4096 * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering 4097 * set. This is a violation of the PCIe 3.0 Transaction Ordering Rules 4098 * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0 4099 * November 10, 2010). As a result, on this platform we can't use Relaxed 4100 * Ordering for Upstream TLPs. 4101 */ 4102 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a00, PCI_CLASS_NOT_DEFINED, 8, 4103 quirk_relaxedordering_disable); 4104 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a01, PCI_CLASS_NOT_DEFINED, 8, 4105 quirk_relaxedordering_disable); 4106 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a02, PCI_CLASS_NOT_DEFINED, 8, 4107 quirk_relaxedordering_disable); 4108 4109 /* 4110 * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same 4111 * values for the Attribute as were supplied in the header of the 4112 * corresponding Request, except as explicitly allowed when IDO is used." 4113 * 4114 * If a non-compliant device generates a completion with a different 4115 * attribute than the request, the receiver may accept it (which itself 4116 * seems non-compliant based on sec 2.3.2), or it may handle it as a 4117 * Malformed TLP or an Unexpected Completion, which will probably lead to a 4118 * device access timeout. 4119 * 4120 * If the non-compliant device generates completions with zero attributes 4121 * (instead of copying the attributes from the request), we can work around 4122 * this by disabling the "Relaxed Ordering" and "No Snoop" attributes in 4123 * upstream devices so they always generate requests with zero attributes. 4124 * 4125 * This affects other devices under the same Root Port, but since these 4126 * attributes are performance hints, there should be no functional problem. 4127 * 4128 * Note that Configuration Space accesses are never supposed to have TLP 4129 * Attributes, so we're safe waiting till after any Configuration Space 4130 * accesses to do the Root Port fixup. 4131 */ 4132 static void quirk_disable_root_port_attributes(struct pci_dev *pdev) 4133 { 4134 struct pci_dev *root_port = pci_find_pcie_root_port(pdev); 4135 4136 if (!root_port) { 4137 pci_warn(pdev, "PCIe Completion erratum may cause device errors\n"); 4138 return; 4139 } 4140 4141 pci_info(root_port, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n", 4142 dev_name(&pdev->dev)); 4143 pcie_capability_clear_and_set_word(root_port, PCI_EXP_DEVCTL, 4144 PCI_EXP_DEVCTL_RELAX_EN | 4145 PCI_EXP_DEVCTL_NOSNOOP_EN, 0); 4146 } 4147 4148 /* 4149 * The Chelsio T5 chip fails to copy TLP Attributes from a Request to the 4150 * Completion it generates. 4151 */ 4152 static void quirk_chelsio_T5_disable_root_port_attributes(struct pci_dev *pdev) 4153 { 4154 /* 4155 * This mask/compare operation selects for Physical Function 4 on a 4156 * T5. We only need to fix up the Root Port once for any of the 4157 * PFs. PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely 4158 * 0x54xx so we use that one, 4159 */ 4160 if ((pdev->device & 0xff00) == 0x5400) 4161 quirk_disable_root_port_attributes(pdev); 4162 } 4163 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID, 4164 quirk_chelsio_T5_disable_root_port_attributes); 4165 4166 /* 4167 * AMD has indicated that the devices below do not support peer-to-peer 4168 * in any system where they are found in the southbridge with an AMD 4169 * IOMMU in the system. Multifunction devices that do not support 4170 * peer-to-peer between functions can claim to support a subset of ACS. 4171 * Such devices effectively enable request redirect (RR) and completion 4172 * redirect (CR) since all transactions are redirected to the upstream 4173 * root complex. 4174 * 4175 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94086 4176 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94102 4177 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/99402 4178 * 4179 * 1002:4385 SBx00 SMBus Controller 4180 * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller 4181 * 1002:4383 SBx00 Azalia (Intel HDA) 4182 * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller 4183 * 1002:4384 SBx00 PCI to PCI Bridge 4184 * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller 4185 * 4186 * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15 4187 * 4188 * 1022:780f [AMD] FCH PCI Bridge 4189 * 1022:7809 [AMD] FCH USB OHCI Controller 4190 */ 4191 static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags) 4192 { 4193 #ifdef CONFIG_ACPI 4194 struct acpi_table_header *header = NULL; 4195 acpi_status status; 4196 4197 /* Targeting multifunction devices on the SB (appears on root bus) */ 4198 if (!dev->multifunction || !pci_is_root_bus(dev->bus)) 4199 return -ENODEV; 4200 4201 /* The IVRS table describes the AMD IOMMU */ 4202 status = acpi_get_table("IVRS", 0, &header); 4203 if (ACPI_FAILURE(status)) 4204 return -ENODEV; 4205 4206 /* Filter out flags not applicable to multifunction */ 4207 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT); 4208 4209 return acs_flags & ~(PCI_ACS_RR | PCI_ACS_CR) ? 0 : 1; 4210 #else 4211 return -ENODEV; 4212 #endif 4213 } 4214 4215 static bool pci_quirk_cavium_acs_match(struct pci_dev *dev) 4216 { 4217 /* 4218 * Effectively selects all downstream ports for whole ThunderX 1 4219 * family by 0xf800 mask (which represents 8 SoCs), while the lower 4220 * bits of device ID are used to indicate which subdevice is used 4221 * within the SoC. 4222 */ 4223 return (pci_is_pcie(dev) && 4224 (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) && 4225 ((dev->device & 0xf800) == 0xa000)); 4226 } 4227 4228 static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags) 4229 { 4230 /* 4231 * Cavium root ports don't advertise an ACS capability. However, 4232 * the RTL internally implements similar protection as if ACS had 4233 * Request Redirection, Completion Redirection, Source Validation, 4234 * and Upstream Forwarding features enabled. Assert that the 4235 * hardware implements and enables equivalent ACS functionality for 4236 * these flags. 4237 */ 4238 acs_flags &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_SV | PCI_ACS_UF); 4239 4240 if (!pci_quirk_cavium_acs_match(dev)) 4241 return -ENOTTY; 4242 4243 return acs_flags ? 0 : 1; 4244 } 4245 4246 static int pci_quirk_xgene_acs(struct pci_dev *dev, u16 acs_flags) 4247 { 4248 /* 4249 * X-Gene root matching this quirk do not allow peer-to-peer 4250 * transactions with others, allowing masking out these bits as if they 4251 * were unimplemented in the ACS capability. 4252 */ 4253 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4254 4255 return acs_flags ? 0 : 1; 4256 } 4257 4258 /* 4259 * Many Intel PCH root ports do provide ACS-like features to disable peer 4260 * transactions and validate bus numbers in requests, but do not provide an 4261 * actual PCIe ACS capability. This is the list of device IDs known to fall 4262 * into that category as provided by Intel in Red Hat bugzilla 1037684. 4263 */ 4264 static const u16 pci_quirk_intel_pch_acs_ids[] = { 4265 /* Ibexpeak PCH */ 4266 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49, 4267 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51, 4268 /* Cougarpoint PCH */ 4269 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17, 4270 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f, 4271 /* Pantherpoint PCH */ 4272 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17, 4273 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f, 4274 /* Lynxpoint-H PCH */ 4275 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17, 4276 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f, 4277 /* Lynxpoint-LP PCH */ 4278 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17, 4279 0x9c18, 0x9c19, 0x9c1a, 0x9c1b, 4280 /* Wildcat PCH */ 4281 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97, 4282 0x9c98, 0x9c99, 0x9c9a, 0x9c9b, 4283 /* Patsburg (X79) PCH */ 4284 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e, 4285 /* Wellsburg (X99) PCH */ 4286 0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17, 4287 0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e, 4288 /* Lynx Point (9 series) PCH */ 4289 0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e, 4290 }; 4291 4292 static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev) 4293 { 4294 int i; 4295 4296 /* Filter out a few obvious non-matches first */ 4297 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 4298 return false; 4299 4300 for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++) 4301 if (pci_quirk_intel_pch_acs_ids[i] == dev->device) 4302 return true; 4303 4304 return false; 4305 } 4306 4307 #define INTEL_PCH_ACS_FLAGS (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV) 4308 4309 static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags) 4310 { 4311 u16 flags = dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK ? 4312 INTEL_PCH_ACS_FLAGS : 0; 4313 4314 if (!pci_quirk_intel_pch_acs_match(dev)) 4315 return -ENOTTY; 4316 4317 return acs_flags & ~flags ? 0 : 1; 4318 } 4319 4320 /* 4321 * These QCOM root ports do provide ACS-like features to disable peer 4322 * transactions and validate bus numbers in requests, but do not provide an 4323 * actual PCIe ACS capability. Hardware supports source validation but it 4324 * will report the issue as Completer Abort instead of ACS Violation. 4325 * Hardware doesn't support peer-to-peer and each root port is a root 4326 * complex with unique segment numbers. It is not possible for one root 4327 * port to pass traffic to another root port. All PCIe transactions are 4328 * terminated inside the root port. 4329 */ 4330 static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags) 4331 { 4332 u16 flags = (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV); 4333 int ret = acs_flags & ~flags ? 0 : 1; 4334 4335 pci_info(dev, "Using QCOM ACS Quirk (%d)\n", ret); 4336 4337 return ret; 4338 } 4339 4340 /* 4341 * Sunrise Point PCH root ports implement ACS, but unfortunately as shown in 4342 * the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2, 4343 * 12.1.46, 12.1.47)[1] this chipset uses dwords for the ACS capability and 4344 * control registers whereas the PCIe spec packs them into words (Rev 3.0, 4345 * 7.16 ACS Extended Capability). The bit definitions are correct, but the 4346 * control register is at offset 8 instead of 6 and we should probably use 4347 * dword accesses to them. This applies to the following PCI Device IDs, as 4348 * found in volume 1 of the datasheet[2]: 4349 * 4350 * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16} 4351 * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20} 4352 * 4353 * N.B. This doesn't fix what lspci shows. 4354 * 4355 * The 100 series chipset specification update includes this as errata #23[3]. 4356 * 4357 * The 200 series chipset (Union Point) has the same bug according to the 4358 * specification update (Intel 200 Series Chipset Family Platform Controller 4359 * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001, 4360 * Errata 22)[4]. Per the datasheet[5], root port PCI Device IDs for this 4361 * chipset include: 4362 * 4363 * 0xa290-0xa29f PCI Express Root port #{0-16} 4364 * 0xa2e7-0xa2ee PCI Express Root port #{17-24} 4365 * 4366 * [1] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html 4367 * [2] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html 4368 * [3] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html 4369 * [4] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html 4370 * [5] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html 4371 */ 4372 static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev *dev) 4373 { 4374 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 4375 return false; 4376 4377 switch (dev->device) { 4378 case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */ 4379 case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */ 4380 return true; 4381 } 4382 4383 return false; 4384 } 4385 4386 #define INTEL_SPT_ACS_CTRL (PCI_ACS_CAP + 4) 4387 4388 static int pci_quirk_intel_spt_pch_acs(struct pci_dev *dev, u16 acs_flags) 4389 { 4390 int pos; 4391 u32 cap, ctrl; 4392 4393 if (!pci_quirk_intel_spt_pch_acs_match(dev)) 4394 return -ENOTTY; 4395 4396 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS); 4397 if (!pos) 4398 return -ENOTTY; 4399 4400 /* see pci_acs_flags_enabled() */ 4401 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap); 4402 acs_flags &= (cap | PCI_ACS_EC); 4403 4404 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl); 4405 4406 return acs_flags & ~ctrl ? 0 : 1; 4407 } 4408 4409 static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags) 4410 { 4411 /* 4412 * SV, TB, and UF are not relevant to multifunction endpoints. 4413 * 4414 * Multifunction devices are only required to implement RR, CR, and DT 4415 * in their ACS capability if they support peer-to-peer transactions. 4416 * Devices matching this quirk have been verified by the vendor to not 4417 * perform peer-to-peer with other functions, allowing us to mask out 4418 * these bits as if they were unimplemented in the ACS capability. 4419 */ 4420 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR | 4421 PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT); 4422 4423 return acs_flags ? 0 : 1; 4424 } 4425 4426 static const struct pci_dev_acs_enabled { 4427 u16 vendor; 4428 u16 device; 4429 int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags); 4430 } pci_dev_acs_enabled[] = { 4431 { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs }, 4432 { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs }, 4433 { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs }, 4434 { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs }, 4435 { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs }, 4436 { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs }, 4437 { PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs }, 4438 { PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs }, 4439 { PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs }, 4440 { PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs }, 4441 { PCI_VENDOR_ID_SOLARFLARE, 0x0A03, pci_quirk_mf_endpoint_acs }, 4442 { PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs }, 4443 { PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs }, 4444 { PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs }, 4445 { PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs }, 4446 { PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs }, 4447 { PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs }, 4448 { PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs }, 4449 { PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs }, 4450 { PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs }, 4451 { PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs }, 4452 { PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs }, 4453 { PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs }, 4454 { PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs }, 4455 { PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs }, 4456 { PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs }, 4457 { PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs }, 4458 { PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs }, 4459 { PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs }, 4460 { PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs }, 4461 { PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs }, 4462 /* 82580 */ 4463 { PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs }, 4464 { PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs }, 4465 { PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs }, 4466 { PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs }, 4467 { PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs }, 4468 { PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs }, 4469 { PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs }, 4470 /* 82576 */ 4471 { PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs }, 4472 { PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs }, 4473 { PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs }, 4474 { PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs }, 4475 { PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs }, 4476 { PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs }, 4477 { PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs }, 4478 { PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs }, 4479 /* 82575 */ 4480 { PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs }, 4481 { PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs }, 4482 { PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs }, 4483 /* I350 */ 4484 { PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs }, 4485 { PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs }, 4486 { PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs }, 4487 { PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs }, 4488 /* 82571 (Quads omitted due to non-ACS switch) */ 4489 { PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs }, 4490 { PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs }, 4491 { PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs }, 4492 { PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs }, 4493 /* I219 */ 4494 { PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs }, 4495 { PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs }, 4496 /* QCOM QDF2xxx root ports */ 4497 { 0x17cb, 0x400, pci_quirk_qcom_rp_acs }, 4498 { 0x17cb, 0x401, pci_quirk_qcom_rp_acs }, 4499 /* Intel PCH root ports */ 4500 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs }, 4501 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_spt_pch_acs }, 4502 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */ 4503 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */ 4504 /* Cavium ThunderX */ 4505 { PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs }, 4506 /* APM X-Gene */ 4507 { PCI_VENDOR_ID_AMCC, 0xE004, pci_quirk_xgene_acs }, 4508 { 0 } 4509 }; 4510 4511 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags) 4512 { 4513 const struct pci_dev_acs_enabled *i; 4514 int ret; 4515 4516 /* 4517 * Allow devices that do not expose standard PCIe ACS capabilities 4518 * or control to indicate their support here. Multi-function express 4519 * devices which do not allow internal peer-to-peer between functions, 4520 * but do not implement PCIe ACS may wish to return true here. 4521 */ 4522 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) { 4523 if ((i->vendor == dev->vendor || 4524 i->vendor == (u16)PCI_ANY_ID) && 4525 (i->device == dev->device || 4526 i->device == (u16)PCI_ANY_ID)) { 4527 ret = i->acs_enabled(dev, acs_flags); 4528 if (ret >= 0) 4529 return ret; 4530 } 4531 } 4532 4533 return -ENOTTY; 4534 } 4535 4536 /* Config space offset of Root Complex Base Address register */ 4537 #define INTEL_LPC_RCBA_REG 0xf0 4538 /* 31:14 RCBA address */ 4539 #define INTEL_LPC_RCBA_MASK 0xffffc000 4540 /* RCBA Enable */ 4541 #define INTEL_LPC_RCBA_ENABLE (1 << 0) 4542 4543 /* Backbone Scratch Pad Register */ 4544 #define INTEL_BSPR_REG 0x1104 4545 /* Backbone Peer Non-Posted Disable */ 4546 #define INTEL_BSPR_REG_BPNPD (1 << 8) 4547 /* Backbone Peer Posted Disable */ 4548 #define INTEL_BSPR_REG_BPPD (1 << 9) 4549 4550 /* Upstream Peer Decode Configuration Register */ 4551 #define INTEL_UPDCR_REG 0x1114 4552 /* 5:0 Peer Decode Enable bits */ 4553 #define INTEL_UPDCR_REG_MASK 0x3f 4554 4555 static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev) 4556 { 4557 u32 rcba, bspr, updcr; 4558 void __iomem *rcba_mem; 4559 4560 /* 4561 * Read the RCBA register from the LPC (D31:F0). PCH root ports 4562 * are D28:F* and therefore get probed before LPC, thus we can't 4563 * use pci_get_slot/pci_read_config_dword here. 4564 */ 4565 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0), 4566 INTEL_LPC_RCBA_REG, &rcba); 4567 if (!(rcba & INTEL_LPC_RCBA_ENABLE)) 4568 return -EINVAL; 4569 4570 rcba_mem = ioremap_nocache(rcba & INTEL_LPC_RCBA_MASK, 4571 PAGE_ALIGN(INTEL_UPDCR_REG)); 4572 if (!rcba_mem) 4573 return -ENOMEM; 4574 4575 /* 4576 * The BSPR can disallow peer cycles, but it's set by soft strap and 4577 * therefore read-only. If both posted and non-posted peer cycles are 4578 * disallowed, we're ok. If either are allowed, then we need to use 4579 * the UPDCR to disable peer decodes for each port. This provides the 4580 * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF 4581 */ 4582 bspr = readl(rcba_mem + INTEL_BSPR_REG); 4583 bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD; 4584 if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) { 4585 updcr = readl(rcba_mem + INTEL_UPDCR_REG); 4586 if (updcr & INTEL_UPDCR_REG_MASK) { 4587 pci_info(dev, "Disabling UPDCR peer decodes\n"); 4588 updcr &= ~INTEL_UPDCR_REG_MASK; 4589 writel(updcr, rcba_mem + INTEL_UPDCR_REG); 4590 } 4591 } 4592 4593 iounmap(rcba_mem); 4594 return 0; 4595 } 4596 4597 /* Miscellaneous Port Configuration register */ 4598 #define INTEL_MPC_REG 0xd8 4599 /* MPC: Invalid Receive Bus Number Check Enable */ 4600 #define INTEL_MPC_REG_IRBNCE (1 << 26) 4601 4602 static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev) 4603 { 4604 u32 mpc; 4605 4606 /* 4607 * When enabled, the IRBNCE bit of the MPC register enables the 4608 * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which 4609 * ensures that requester IDs fall within the bus number range 4610 * of the bridge. Enable if not already. 4611 */ 4612 pci_read_config_dword(dev, INTEL_MPC_REG, &mpc); 4613 if (!(mpc & INTEL_MPC_REG_IRBNCE)) { 4614 pci_info(dev, "Enabling MPC IRBNCE\n"); 4615 mpc |= INTEL_MPC_REG_IRBNCE; 4616 pci_write_config_word(dev, INTEL_MPC_REG, mpc); 4617 } 4618 } 4619 4620 static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev) 4621 { 4622 if (!pci_quirk_intel_pch_acs_match(dev)) 4623 return -ENOTTY; 4624 4625 if (pci_quirk_enable_intel_lpc_acs(dev)) { 4626 pci_warn(dev, "Failed to enable Intel PCH ACS quirk\n"); 4627 return 0; 4628 } 4629 4630 pci_quirk_enable_intel_rp_mpc_acs(dev); 4631 4632 dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK; 4633 4634 pci_info(dev, "Intel PCH root port ACS workaround enabled\n"); 4635 4636 return 0; 4637 } 4638 4639 static int pci_quirk_enable_intel_spt_pch_acs(struct pci_dev *dev) 4640 { 4641 int pos; 4642 u32 cap, ctrl; 4643 4644 if (!pci_quirk_intel_spt_pch_acs_match(dev)) 4645 return -ENOTTY; 4646 4647 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS); 4648 if (!pos) 4649 return -ENOTTY; 4650 4651 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap); 4652 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl); 4653 4654 ctrl |= (cap & PCI_ACS_SV); 4655 ctrl |= (cap & PCI_ACS_RR); 4656 ctrl |= (cap & PCI_ACS_CR); 4657 ctrl |= (cap & PCI_ACS_UF); 4658 4659 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl); 4660 4661 pci_info(dev, "Intel SPT PCH root port ACS workaround enabled\n"); 4662 4663 return 0; 4664 } 4665 4666 static const struct pci_dev_enable_acs { 4667 u16 vendor; 4668 u16 device; 4669 int (*enable_acs)(struct pci_dev *dev); 4670 } pci_dev_enable_acs[] = { 4671 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_enable_intel_pch_acs }, 4672 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_enable_intel_spt_pch_acs }, 4673 { 0 } 4674 }; 4675 4676 int pci_dev_specific_enable_acs(struct pci_dev *dev) 4677 { 4678 const struct pci_dev_enable_acs *i; 4679 int ret; 4680 4681 for (i = pci_dev_enable_acs; i->enable_acs; i++) { 4682 if ((i->vendor == dev->vendor || 4683 i->vendor == (u16)PCI_ANY_ID) && 4684 (i->device == dev->device || 4685 i->device == (u16)PCI_ANY_ID)) { 4686 ret = i->enable_acs(dev); 4687 if (ret >= 0) 4688 return ret; 4689 } 4690 } 4691 4692 return -ENOTTY; 4693 } 4694 4695 /* 4696 * The PCI capabilities list for Intel DH895xCC VFs (device id 0x0443) with 4697 * QuickAssist Technology (QAT) is prematurely terminated in hardware. The 4698 * Next Capability pointer in the MSI Capability Structure should point to 4699 * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating 4700 * the list. 4701 */ 4702 static void quirk_intel_qat_vf_cap(struct pci_dev *pdev) 4703 { 4704 int pos, i = 0; 4705 u8 next_cap; 4706 u16 reg16, *cap; 4707 struct pci_cap_saved_state *state; 4708 4709 /* Bail if the hardware bug is fixed */ 4710 if (pdev->pcie_cap || pci_find_capability(pdev, PCI_CAP_ID_EXP)) 4711 return; 4712 4713 /* Bail if MSI Capability Structure is not found for some reason */ 4714 pos = pci_find_capability(pdev, PCI_CAP_ID_MSI); 4715 if (!pos) 4716 return; 4717 4718 /* 4719 * Bail if Next Capability pointer in the MSI Capability Structure 4720 * is not the expected incorrect 0x00. 4721 */ 4722 pci_read_config_byte(pdev, pos + 1, &next_cap); 4723 if (next_cap) 4724 return; 4725 4726 /* 4727 * PCIe Capability Structure is expected to be at 0x50 and should 4728 * terminate the list (Next Capability pointer is 0x00). Verify 4729 * Capability Id and Next Capability pointer is as expected. 4730 * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext() 4731 * to correctly set kernel data structures which have already been 4732 * set incorrectly due to the hardware bug. 4733 */ 4734 pos = 0x50; 4735 pci_read_config_word(pdev, pos, ®16); 4736 if (reg16 == (0x0000 | PCI_CAP_ID_EXP)) { 4737 u32 status; 4738 #ifndef PCI_EXP_SAVE_REGS 4739 #define PCI_EXP_SAVE_REGS 7 4740 #endif 4741 int size = PCI_EXP_SAVE_REGS * sizeof(u16); 4742 4743 pdev->pcie_cap = pos; 4744 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); 4745 pdev->pcie_flags_reg = reg16; 4746 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16); 4747 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD; 4748 4749 pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE; 4750 if (pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &status) != 4751 PCIBIOS_SUCCESSFUL || (status == 0xffffffff)) 4752 pdev->cfg_size = PCI_CFG_SPACE_SIZE; 4753 4754 if (pci_find_saved_cap(pdev, PCI_CAP_ID_EXP)) 4755 return; 4756 4757 /* 4758 * Save PCIE cap 4759 */ 4760 state = kzalloc(sizeof(*state) + size, GFP_KERNEL); 4761 if (!state) 4762 return; 4763 4764 state->cap.cap_nr = PCI_CAP_ID_EXP; 4765 state->cap.cap_extended = 0; 4766 state->cap.size = size; 4767 cap = (u16 *)&state->cap.data[0]; 4768 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap[i++]); 4769 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &cap[i++]); 4770 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &cap[i++]); 4771 pcie_capability_read_word(pdev, PCI_EXP_RTCTL, &cap[i++]); 4772 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &cap[i++]); 4773 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL2, &cap[i++]); 4774 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL2, &cap[i++]); 4775 hlist_add_head(&state->next, &pdev->saved_cap_space); 4776 } 4777 } 4778 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap); 4779 4780 /* FLR may cause some 82579 devices to hang. */ 4781 static void quirk_intel_no_flr(struct pci_dev *dev) 4782 { 4783 dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET; 4784 } 4785 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_intel_no_flr); 4786 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_intel_no_flr); 4787 4788 static void quirk_no_ext_tags(struct pci_dev *pdev) 4789 { 4790 struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus); 4791 4792 if (!bridge) 4793 return; 4794 4795 bridge->no_ext_tags = 1; 4796 pci_info(pdev, "disabling Extended Tags (this device can't handle them)\n"); 4797 4798 pci_walk_bus(bridge->bus, pci_configure_extended_tags, NULL); 4799 } 4800 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0140, quirk_no_ext_tags); 4801 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0142, quirk_no_ext_tags); 4802 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0144, quirk_no_ext_tags); 4803 4804 #ifdef CONFIG_PCI_ATS 4805 /* 4806 * Some devices have a broken ATS implementation causing IOMMU stalls. 4807 * Don't use ATS for those devices. 4808 */ 4809 static void quirk_no_ats(struct pci_dev *pdev) 4810 { 4811 pci_info(pdev, "disabling ATS (broken on this device)\n"); 4812 pdev->ats_cap = 0; 4813 } 4814 4815 /* AMD Stoney platform GPU */ 4816 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_no_ats); 4817 #endif /* CONFIG_PCI_ATS */ 4818 4819 /* Freescale PCIe doesn't support MSI in RC mode */ 4820 static void quirk_fsl_no_msi(struct pci_dev *pdev) 4821 { 4822 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT) 4823 pdev->no_msi = 1; 4824 } 4825 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_no_msi); 4826 4827 /* 4828 * GPUs with integrated HDA controller for streaming audio to attached displays 4829 * need a device link from the HDA controller (consumer) to the GPU (supplier) 4830 * so that the GPU is powered up whenever the HDA controller is accessed. 4831 * The GPU and HDA controller are functions 0 and 1 of the same PCI device. 4832 * The device link stays in place until shutdown (or removal of the PCI device 4833 * if it's hotplugged). Runtime PM is allowed by default on the HDA controller 4834 * to prevent it from permanently keeping the GPU awake. 4835 */ 4836 static void quirk_gpu_hda(struct pci_dev *hda) 4837 { 4838 struct pci_dev *gpu; 4839 4840 if (PCI_FUNC(hda->devfn) != 1) 4841 return; 4842 4843 gpu = pci_get_domain_bus_and_slot(pci_domain_nr(hda->bus), 4844 hda->bus->number, 4845 PCI_DEVFN(PCI_SLOT(hda->devfn), 0)); 4846 if (!gpu || (gpu->class >> 16) != PCI_BASE_CLASS_DISPLAY) { 4847 pci_dev_put(gpu); 4848 return; 4849 } 4850 4851 if (!device_link_add(&hda->dev, &gpu->dev, 4852 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME)) 4853 pci_err(hda, "cannot link HDA to GPU %s\n", pci_name(gpu)); 4854 4855 pm_runtime_allow(&hda->dev); 4856 pci_dev_put(gpu); 4857 } 4858 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 4859 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda); 4860 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMD, PCI_ANY_ID, 4861 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda); 4862 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 4863 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda); 4864